1/* tc-m68k.c -- Assemble for the m68k family 2 Copyright (C) 1987-2022 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21#include "as.h" 22#include "safe-ctype.h" 23#include "obstack.h" 24#include "subsegs.h" 25#include "dwarf2dbg.h" 26#include "dw2gencfi.h" 27 28#include "opcode/m68k.h" 29#include "m68k-parse.h" 30#include "elf/m68k.h" 31 32static void m68k_elf_cons (int); 33static void m68k_elf_gnu_attribute (int); 34 35/* This string holds the chars that always start a comment. If the 36 pre-processor is disabled, these aren't very useful. The macro 37 tc_comment_chars points to this. We use this, rather than the 38 usual comment_chars, so that the --bitwise-or option will work. */ 39#if defined (TE_SVR4) || defined (TE_DELTA) 40const char *m68k_comment_chars = "|#"; 41#else 42const char *m68k_comment_chars = "|"; 43#endif 44 45/* This array holds the chars that only start a comment at the beginning of 46 a line. If the line seems to have the form '# 123 filename' 47 .line and .file directives will appear in the pre-processed output */ 48/* Note that input_file.c hand checks for '#' at the beginning of the 49 first line of the input file. This is because the compiler outputs 50 #NO_APP at the beginning of its output. */ 51/* Also note that comments like this one will always work. */ 52const char line_comment_chars[] = "#*"; 53 54const char line_separator_chars[] = ";"; 55 56/* Chars that can be used to separate mant from exp in floating point nums. */ 57const char EXP_CHARS[] = "eE"; 58 59/* Chars that mean this number is a floating point constant, as 60 in "0f12.456" or "0d1.2345e12". */ 61 62const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 63 64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 65 changed in read.c . Ideally it shouldn't have to know about it at all, 66 but nothing is ideal around here. */ 67 68/* Are we trying to generate PIC code? If so, absolute references 69 ought to be made into linkage table references or pc-relative 70 references. Not implemented. For ELF there are other means 71 to denote pic relocations. */ 72int flag_want_pic; 73 74static int flag_short_refs; /* -l option. */ 75static int flag_long_jumps; /* -S option. */ 76static int flag_keep_pcrel; /* --pcrel option. */ 77 78#ifdef REGISTER_PREFIX_OPTIONAL 79int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 80#else 81int flag_reg_prefix_optional; 82#endif 83 84/* Whether --register-prefix-optional was used on the command line. */ 85static int reg_prefix_optional_seen; 86 87/* The floating point coprocessor to use by default. */ 88static enum m68k_register m68k_float_copnum = COP1; 89 90/* If this is non-zero, then references to number(%pc) will be taken 91 to refer to number, rather than to %pc + number. */ 92static int m68k_abspcadd; 93 94/* If this is non-zero, then the quick forms of the move, add, and sub 95 instructions are used when possible. */ 96static int m68k_quick = 1; 97 98/* If this is non-zero, then if the size is not specified for a base 99 or outer displacement, the assembler assumes that the size should 100 be 32 bits. */ 101static int m68k_rel32 = 1; 102 103/* This is non-zero if m68k_rel32 was set from the command line. */ 104static int m68k_rel32_from_cmdline; 105 106/* The default width to use for an index register when using a base 107 displacement. */ 108static enum m68k_size m68k_index_width_default = SIZE_LONG; 109 110/* The current label. */ 111 112static struct m68k_tc_sy *current_label; 113 114/* Pointer to list holding the opcodes sorted by name. */ 115static struct m68k_opcode const ** m68k_sorted_opcodes; 116 117/* It's an arbitrary name: This means I don't approve of it. 118 See flames below. */ 119static struct obstack robyn; 120 121struct m68k_incant 122 { 123 const char *m_operands; 124 unsigned long m_opcode; 125 short m_opnum; 126 short m_codenum; 127 int m_arch; 128 struct m68k_incant *m_next; 129 }; 130 131#define getone(x) ((((x)->m_opcode)>>16)&0xffff) 132#define gettwo(x) (((x)->m_opcode)&0xffff) 133 134static const enum m68k_register m68000_ctrl[] = { 0 }; 135static const enum m68k_register m68010_ctrl[] = { 136 SFC, DFC, USP, VBR, 137 0 138}; 139static const enum m68k_register m68020_ctrl[] = { 140 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, 141 0 142}; 143static const enum m68k_register m68040_ctrl[] = { 144 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, 145 USP, VBR, MSP, ISP, MMUSR, URP, SRP, 146 0 147}; 148static const enum m68k_register m68060_ctrl[] = { 149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, 150 USP, VBR, URP, SRP, PCR, 151 0 152}; 153static const enum m68k_register mcf_ctrl[] = { 154 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, 155 RAMBAR0, RAMBAR1, RAMBAR, MBAR, 156 0 157}; 158static const enum m68k_register mcf51_ctrl[] = { 159 VBR, CPUCR, 160 0 161}; 162static const enum m68k_register mcf5206_ctrl[] = { 163 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, 164 0 165}; 166static const enum m68k_register mcf5208_ctrl[] = { 167 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, 168 0 169}; 170static const enum m68k_register mcf5210a_ctrl[] = { 171 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, 172 0 173}; 174static const enum m68k_register mcf5213_ctrl[] = { 175 VBR, RAMBAR, RAMBAR1, FLASHBAR, 176 0 177}; 178static const enum m68k_register mcf5216_ctrl[] = { 179 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 180 0 181}; 182static const enum m68k_register mcf5221x_ctrl[] = { 183 VBR, FLASHBAR, RAMBAR, RAMBAR1, 184 0 185}; 186static const enum m68k_register mcf52223_ctrl[] = { 187 VBR, FLASHBAR, RAMBAR, RAMBAR1, 188 0 189}; 190static const enum m68k_register mcf52235_ctrl[] = { 191 VBR, FLASHBAR, RAMBAR, RAMBAR1, 192 0 193}; 194static const enum m68k_register mcf5225_ctrl[] = { 195 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, 196 0 197}; 198static const enum m68k_register mcf52259_ctrl[] = { 199 VBR, FLASHBAR, RAMBAR, RAMBAR1, 200 0 201}; 202static const enum m68k_register mcf52277_ctrl[] = { 203 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 204 0 205}; 206static const enum m68k_register mcf5235_ctrl[] = { 207 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 208 0 209}; 210static const enum m68k_register mcf5249_ctrl[] = { 211 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 212 0 213}; 214static const enum m68k_register mcf5250_ctrl[] = { 215 VBR, 216 0 217}; 218static const enum m68k_register mcf5253_ctrl[] = { 219 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 220 0 221}; 222static const enum m68k_register mcf5271_ctrl[] = { 223 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 224 0 225}; 226static const enum m68k_register mcf5272_ctrl[] = { 227 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, 228 0 229}; 230static const enum m68k_register mcf5275_ctrl[] = { 231 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 232 0 233}; 234static const enum m68k_register mcf5282_ctrl[] = { 235 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 236 0 237}; 238static const enum m68k_register mcf53017_ctrl[] = { 239 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 240 0 241}; 242static const enum m68k_register mcf5307_ctrl[] = { 243 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, 244 0 245}; 246static const enum m68k_register mcf5329_ctrl[] = { 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 248 0 249}; 250static const enum m68k_register mcf5373_ctrl[] = { 251 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 252 0 253}; 254static const enum m68k_register mcfv4e_ctrl[] = { 255 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 256 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, 257 MBAR, SECMBAR, 258 MPCR /* Multiprocessor Control register */, 259 EDRAMBAR /* Embedded DRAM Base Address Register */, 260 /* Permutation control registers. */ 261 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, 262 PCR3U0, PCR3L0, PCR3U1, PCR3L1, 263 /* Legacy names */ 264 TC /* ASID */, BUSCR /* MMUBAR */, 265 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 266 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, 267 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 268 0 269}; 270static const enum m68k_register mcf5407_ctrl[] = { 271 CACR, ASID, ACR0, ACR1, ACR2, ACR3, 272 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 273 /* Legacy names */ 274 TC /* ASID */, 275 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 276 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 277 0 278}; 279static const enum m68k_register mcf54418_ctrl[] = { 280 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, 281 VBR, PC, RAMBAR1, 282 /* Legacy names */ 283 TC /* ASID */, BUSCR /* MMUBAR */, 284 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 285 RAMBAR /* RAMBAR1 */, 286 0 287}; 288static const enum m68k_register mcf54455_ctrl[] = { 289 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 290 VBR, PC, RAMBAR1, 291 /* Legacy names */ 292 TC /* ASID */, BUSCR /* MMUBAR */, 293 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 294 RAMBAR /* RAMBAR1 */, 295 0 296}; 297static const enum m68k_register mcf5475_ctrl[] = { 298 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 299 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 300 /* Legacy names */ 301 TC /* ASID */, BUSCR /* MMUBAR */, 302 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 303 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 304 0 305}; 306static const enum m68k_register mcf5485_ctrl[] = { 307 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 308 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 309 /* Legacy names */ 310 TC /* ASID */, BUSCR /* MMUBAR */, 311 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 312 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 313 0 314}; 315static const enum m68k_register fido_ctrl[] = { 316 SFC, DFC, USP, VBR, CAC, MBO, 317 0 318}; 319#define cpu32_ctrl m68010_ctrl 320 321static const enum m68k_register *control_regs; 322 323/* Internal form of a 68020 instruction. */ 324struct m68k_it 325{ 326 const char *error; 327 const char *args; /* List of opcode info. */ 328 int numargs; 329 330 int numo; /* Number of shorts in opcode. */ 331 short opcode[11]; 332 333 struct m68k_op operands[6]; 334 335 int nexp; /* Number of exprs in use. */ 336 struct m68k_exp exprs[4]; 337 338 int nfrag; /* Number of frags we have to produce. */ 339 struct 340 { 341 int fragoff; /* Where in the current opcode the frag ends. */ 342 symbolS *fadd; 343 offsetT foff; 344 int fragty; 345 } 346 fragb[4]; 347 348 int nrel; /* Num of reloc structs in use. */ 349 struct 350 { 351 int n; 352 expressionS exp; 353 char wid; 354 char pcrel; 355 /* In a pc relative address the difference between the address 356 of the offset and the address that the offset is relative 357 to. This depends on the addressing mode. Basically this 358 is the value to put in the offset field to address the 359 first byte of the offset, without regarding the special 360 significance of some values (in the branch instruction, for 361 example). */ 362 int pcrel_fix; 363 /* Whether this expression needs special pic relocation, and if 364 so, which. */ 365 enum pic_relocation pic_reloc; 366 } 367 reloc[5]; /* Five is enough??? */ 368}; 369 370#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) 371#define float_of_arch(x) ((x) & mfloat) 372#define mmu_of_arch(x) ((x) & mmmu) 373#define arch_coldfire_p(x) ((x) & mcfisa_a) 374#define arch_coldfire_fpu(x) ((x) & cfloat) 375 376/* Macros for determining if cpu supports a specific addressing mode. */ 377#define HAVE_LONG_DISP(x) \ 378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 379#define HAVE_LONG_CALL(x) \ 380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 381#define HAVE_LONG_COND(x) \ 382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 383#define HAVE_LONG_BRANCH(x) \ 384 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) 385#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) 386 387static struct m68k_it the_ins; /* The instruction being assembled. */ 388 389#define op(ex) ((ex)->exp.X_op) 390#define adds(ex) ((ex)->exp.X_add_symbol) 391#define subs(ex) ((ex)->exp.X_op_symbol) 392#define offs(ex) ((ex)->exp.X_add_number) 393 394/* Macros for adding things to the m68k_it struct. */ 395#define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) 396 397/* Like addword, but goes BEFORE general operands. */ 398 399static void 400insop (int w, const struct m68k_incant *opcode) 401{ 402 int z; 403 for (z = the_ins.numo; z > opcode->m_codenum; --z) 404 the_ins.opcode[z] = the_ins.opcode[z - 1]; 405 for (z = 0; z < the_ins.nrel; z++) 406 the_ins.reloc[z].n += 2; 407 for (z = 0; z < the_ins.nfrag; z++) 408 the_ins.fragb[z].fragoff++; 409 the_ins.opcode[opcode->m_codenum] = w; 410 the_ins.numo++; 411} 412 413/* The numo+1 kludge is so we can hit the low order byte of the prev word. 414 Blecch. */ 415static void 416add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) 417{ 418 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' 419 ? the_ins.numo * 2 - 1 420 : (width == 'b' 421 ? the_ins.numo * 2 + 1 422 : the_ins.numo * 2)); 423 the_ins.reloc[the_ins.nrel].exp = exp->exp; 424 the_ins.reloc[the_ins.nrel].wid = width; 425 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; 426 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; 427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; 428} 429 430/* Cause an extra frag to be generated here, inserting up to 10 bytes 431 (that value is chosen in the frag_var call in md_assemble). TYPE 432 is the subtype of the frag to be generated; its primary type is 433 rs_machine_dependent. 434 435 The TYPE parameter is also used by md_convert_frag_1 and 436 md_estimate_size_before_relax. The appropriate type of fixup will 437 be emitted by md_convert_frag_1. 438 439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 440static void 441add_frag (symbolS *add, offsetT off, int type) 442{ 443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; 444 the_ins.fragb[the_ins.nfrag].fadd = add; 445 the_ins.fragb[the_ins.nfrag].foff = off; 446 the_ins.fragb[the_ins.nfrag++].fragty = type; 447} 448 449#define isvar(ex) \ 450 (op (ex) != O_constant && op (ex) != O_big) 451 452static char *crack_operand (char *str, struct m68k_op *opP); 453static int get_num (struct m68k_exp *exp, int ok); 454static int reverse_16_bits (int in); 455static int reverse_8_bits (int in); 456static void install_gen_operand (int mode, int val); 457static void install_operand (int mode, int val); 458static void s_bss (int); 459static void s_data1 (int); 460static void s_data2 (int); 461static void s_even (int); 462static void s_proc (int); 463static void s_chip (int); 464static void s_fopt (int); 465static void s_opt (int); 466static void s_reg (int); 467static void s_restore (int); 468static void s_save (int); 469static void s_mri_if (int); 470static void s_mri_else (int); 471static void s_mri_endi (int); 472static void s_mri_break (int); 473static void s_mri_next (int); 474static void s_mri_for (int); 475static void s_mri_endf (int); 476static void s_mri_repeat (int); 477static void s_mri_until (int); 478static void s_mri_while (int); 479static void s_mri_endw (int); 480static void s_m68k_cpu (int); 481static void s_m68k_arch (int); 482 483struct m68k_cpu 484{ 485 unsigned long arch; /* Architecture features. */ 486 const enum m68k_register *control_regs; /* Control regs on chip */ 487 const char *name; /* Name */ 488 int alias; /* Alias for a canonical name. If 1, then 489 succeeds canonical name, if -1 then 490 succeeds canonical name, if <-1 ||>1 this is a 491 deprecated name, and the next/previous name 492 should be used. */ 493}; 494 495/* We hold flags for features explicitly enabled and explicitly 496 disabled. */ 497static int current_architecture; 498static int not_current_architecture; 499static const struct m68k_cpu *selected_arch; 500static const struct m68k_cpu *selected_cpu; 501static int initialized; 502 503/* Architecture models. */ 504static const struct m68k_cpu m68k_archs[] = 505{ 506 {m68000, m68000_ctrl, "68000", 0}, 507 {m68010, m68010_ctrl, "68010", 0}, 508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 510 {m68040, m68040_ctrl, "68040", 0}, 511 {m68060, m68060_ctrl, "68060", 0}, 512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 513 {fido_a, fido_ctrl, "fidoa", 0}, 514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, 515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, 516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, 517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, 518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, 519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, 520 {0,0,NULL, 0} 521}; 522 523/* For -mno-mac we want to turn off all types of mac. */ 524static const unsigned no_mac = mcfmac | mcfemac; 525 526/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 527 for either. */ 528static const struct m68k_cpu m68k_extensions[] = 529{ 530 {m68851, NULL, "68851", -1}, 531 {m68881, NULL, "68881", -1}, 532 {m68881, NULL, "68882", -1}, 533 534 {cfloat|m68881, NULL, "float", 0}, 535 536 {mcfhwdiv, NULL, "div", 1}, 537 {mcfusp, NULL, "usp", 1}, 538 {mcfmac, (void *)&no_mac, "mac", 1}, 539 {mcfemac, NULL, "emac", 1}, 540 541 {0,NULL,NULL, 0} 542}; 543 544/* Processor list */ 545static const struct m68k_cpu m68k_cpus[] = 546{ 547 {m68000, m68000_ctrl, "68000", 0}, 548 {m68000, m68000_ctrl, "68ec000", 1}, 549 {m68000, m68000_ctrl, "68hc000", 1}, 550 {m68000, m68000_ctrl, "68hc001", 1}, 551 {m68000, m68000_ctrl, "68008", 1}, 552 {m68000, m68000_ctrl, "68302", 1}, 553 {m68000, m68000_ctrl, "68306", 1}, 554 {m68000, m68000_ctrl, "68307", 1}, 555 {m68000, m68000_ctrl, "68322", 1}, 556 {m68000, m68000_ctrl, "68356", 1}, 557 {m68010, m68010_ctrl, "68010", 0}, 558 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 559 {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, 560 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, 561 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 562 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, 563 {m68040, m68040_ctrl, "68040", 0}, 564 {m68040, m68040_ctrl, "68ec040", 1}, 565 {m68060, m68060_ctrl, "68060", 0}, 566 {m68060, m68060_ctrl, "68ec060", 1}, 567 568 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 569 {cpu32|m68881, cpu32_ctrl, "68330", 1}, 570 {cpu32|m68881, cpu32_ctrl, "68331", 1}, 571 {cpu32|m68881, cpu32_ctrl, "68332", 1}, 572 {cpu32|m68881, cpu32_ctrl, "68333", 1}, 573 {cpu32|m68881, cpu32_ctrl, "68334", 1}, 574 {cpu32|m68881, cpu32_ctrl, "68336", 1}, 575 {cpu32|m68881, cpu32_ctrl, "68340", 1}, 576 {cpu32|m68881, cpu32_ctrl, "68341", 1}, 577 {cpu32|m68881, cpu32_ctrl, "68349", 1}, 578 {cpu32|m68881, cpu32_ctrl, "68360", 1}, 579 580 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, 581 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, 582 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, 583 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, 584 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, 585 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, 586 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, 587 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, 588 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, 589 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, 590 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, 591 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, 592 593 {mcfisa_a, mcf_ctrl, "5200", 0}, 594 {mcfisa_a, mcf_ctrl, "5202", 1}, 595 {mcfisa_a, mcf_ctrl, "5204", 1}, 596 {mcfisa_a, mcf5206_ctrl, "5206", 1}, 597 598 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, 599 600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, 601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, 602 603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, 604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, 605 606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, 607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, 608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, 609 610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, 611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, 612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, 613 614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, 615 616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, 617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, 618 619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, 620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, 621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, 622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, 623 624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, 625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, 626 627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, 628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, 629 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, 632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, 633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, 635 636 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, 637 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, 638 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, 639 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, 641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, 643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, 645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, 646 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, 648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, 649 650 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, 651 652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, 653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, 654 655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, 656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, 657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, 659 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, 661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, 663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, 664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, 665 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, 666 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, 667 668 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, 669 670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, 672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, 673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, 674 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, 676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, 677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, 678 679 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, 680 681 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, 682 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, 683 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, 684 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, 685 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, 686 687 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, 688 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, 689 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, 690 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, 691 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, 692 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, 693 694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, 695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, 696 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, 697 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, 698 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, 699 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, 700 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, 701 702 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, 703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, 704 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, 705 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, 706 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, 707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, 708 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, 709 710 {fido_a, fido_ctrl, "fidoa", 0}, 711 {fido_a, fido_ctrl, "fido", 1}, 712 713 {0,NULL,NULL, 0} 714 }; 715 716static const struct m68k_cpu *m68k_lookup_cpu 717(const char *, const struct m68k_cpu *, int, int *); 718static int m68k_set_arch (const char *, int, int); 719static int m68k_set_cpu (const char *, int, int); 720static int m68k_set_extension (const char *, int, int); 721static void m68k_init_arch (void); 722 723/* This is the assembler relaxation table for m68k. m68k is a rich CISC 724 architecture and we have a lot of relaxation modes. */ 725 726/* Macros used in the relaxation code. */ 727#define TAB(x,y) (((x) << 2) + (y)) 728#define TABTYPE(x) ((x) >> 2) 729 730/* Relaxation states. */ 731#define BYTE 0 732#define SHORT 1 733#define LONG 2 734#define SZ_UNDEF 3 735 736/* Here are all the relaxation modes we support. First we can relax ordinary 737 branches. On 68020 and higher and on CPU32 all branch instructions take 738 three forms, so on these CPUs all branches always remain as such. When we 739 have to expand to the LONG form on a 68000, though, we substitute an 740 absolute jump instead. This is a direct replacement for unconditional 741 branches and a branch over a jump for conditional branches. However, if the 742 user requires PIC and disables this with --pcrel, we can only relax between 743 BYTE and SHORT forms, punting if that isn't enough. This gives us four 744 different relaxation modes for branches: */ 745 746#define BRANCHBWL 0 /* Branch byte, word, or long. */ 747#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ 748#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ 749#define BRANCHBW 3 /* Branch byte or word. */ 750 751/* We also relax coprocessor branches and DBcc's. All CPUs that support 752 coprocessor branches support them in word and long forms, so we have only 753 one relaxation mode for them. DBcc's are word only on all CPUs. We can 754 relax them to the LONG form with a branch-around sequence. This sequence 755 can use a long branch (if available) or an absolute jump (if acceptable). 756 This gives us two relaxation modes. If long branches are not available and 757 absolute jumps are not acceptable, we don't relax DBcc's. */ 758 759#define FBRANCH 4 /* Coprocessor branch. */ 760#define DBCCLBR 5 /* DBcc relaxable with a long branch. */ 761#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ 762 763/* That's all for instruction relaxation. However, we also relax PC-relative 764 operands. Specifically, we have three operand relaxation modes. On the 765 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and 766 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the 767 two. Also PC+displacement+index operands in their simple form (with a non- 768 suppressed index without memory indirection) are supported on all CPUs, but 769 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher 770 and on CPU32 we relax it to SHORT and LONG forms as well using the extended 771 form of the PC+displacement+index operand. Finally, some absolute operands 772 can be relaxed down to 16-bit PC-relative. */ 773 774#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ 775#define PCINDEX 8 /* PC + displacement + index. */ 776#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ 777 778/* This relaxation is required for branches where there is no long 779 branch and we are in pcrel mode. We generate a bne/beq pair. */ 780#define BRANCHBWPL 10 /* Branch byte, word or pair of longs 781 */ 782 783/* Note that calls to frag_var need to specify the maximum expansion 784 needed; this is currently 12 bytes for bne/beq pair. */ 785#define FRAG_VAR_SIZE 12 786 787/* The fields are: 788 How far Forward this mode will reach: 789 How far Backward this mode will reach: 790 How many bytes this mode will add to the size of the frag 791 Which mode to go to if the offset won't fit in this one 792 793 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ 794relax_typeS md_relax_table[] = 795{ 796 { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, 797 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, 798 { 0, 0, 4, 0 }, 799 { 1, 1, 0, 0 }, 800 801 { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, 802 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, 803 { 0, 0, 4, 0 }, 804 { 1, 1, 0, 0 }, 805 806 { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, 807 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, 808 { 0, 0, 6, 0 }, 809 { 1, 1, 0, 0 }, 810 811 { 127, -128, 0, TAB (BRANCHBW, SHORT) }, 812 { 0, 0, 2, 0 }, 813 { 1, 1, 0, 0 }, 814 { 1, 1, 0, 0 }, 815 816 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ 817 { 32767, -32768, 2, TAB (FBRANCH, LONG) }, 818 { 0, 0, 4, 0 }, 819 { 1, 1, 0, 0 }, 820 821 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 822 { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, 823 { 0, 0, 10, 0 }, 824 { 1, 1, 0, 0 }, 825 826 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 827 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, 828 { 0, 0, 10, 0 }, 829 { 1, 1, 0, 0 }, 830 831 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ 832 { 32767, -32768, 2, TAB (PCREL1632, LONG) }, 833 { 0, 0, 6, 0 }, 834 { 1, 1, 0, 0 }, 835 836 { 125, -130, 0, TAB (PCINDEX, SHORT) }, 837 { 32765, -32770, 2, TAB (PCINDEX, LONG) }, 838 { 0, 0, 4, 0 }, 839 { 1, 1, 0, 0 }, 840 841 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ 842 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, 843 { 0, 0, 4, 0 }, 844 { 1, 1, 0, 0 }, 845 846 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, 847 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, 848 { 0, 0, 10, 0 }, 849 { 1, 1, 0, 0 }, 850}; 851 852/* These are the machine dependent pseudo-ops. These are included so 853 the assembler can work on the output from the SUN C compiler, which 854 generates these. */ 855 856/* This table describes all the machine specific pseudo-ops the assembler 857 has to support. The fields are: 858 pseudo-op name without dot 859 function to call to execute this pseudo-op 860 Integer arg to pass to the function. */ 861const pseudo_typeS md_pseudo_table[] = 862{ 863 {"data1", s_data1, 0}, 864 {"data2", s_data2, 0}, 865 {"bss", s_bss, 0}, 866 {"even", s_even, 0}, 867 {"skip", s_space, 0}, 868 {"proc", s_proc, 0}, 869 {"align", s_align_bytes, 0}, 870 {"swbeg", s_ignore, 0}, 871 {"long", m68k_elf_cons, 4}, 872 {"extend", float_cons, 'x'}, 873 {"ldouble", float_cons, 'x'}, 874 875 {"arch", s_m68k_arch, 0}, 876 {"cpu", s_m68k_cpu, 0}, 877 {"gnu_attribute", m68k_elf_gnu_attribute, 0}, 878 879 /* The following pseudo-ops are supported for MRI compatibility. */ 880 {"chip", s_chip, 0}, 881 {"comline", s_space, 1}, 882 {"fopt", s_fopt, 0}, 883 {"mask2", s_ignore, 0}, 884 {"opt", s_opt, 0}, 885 {"reg", s_reg, 0}, 886 {"restore", s_restore, 0}, 887 {"save", s_save, 0}, 888 889 {"if", s_mri_if, 0}, 890 {"if.b", s_mri_if, 'b'}, 891 {"if.w", s_mri_if, 'w'}, 892 {"if.l", s_mri_if, 'l'}, 893 {"else", s_mri_else, 0}, 894 {"else.s", s_mri_else, 's'}, 895 {"else.l", s_mri_else, 'l'}, 896 {"endi", s_mri_endi, 0}, 897 {"break", s_mri_break, 0}, 898 {"break.s", s_mri_break, 's'}, 899 {"break.l", s_mri_break, 'l'}, 900 {"next", s_mri_next, 0}, 901 {"next.s", s_mri_next, 's'}, 902 {"next.l", s_mri_next, 'l'}, 903 {"for", s_mri_for, 0}, 904 {"for.b", s_mri_for, 'b'}, 905 {"for.w", s_mri_for, 'w'}, 906 {"for.l", s_mri_for, 'l'}, 907 {"endf", s_mri_endf, 0}, 908 {"repeat", s_mri_repeat, 0}, 909 {"until", s_mri_until, 0}, 910 {"until.b", s_mri_until, 'b'}, 911 {"until.w", s_mri_until, 'w'}, 912 {"until.l", s_mri_until, 'l'}, 913 {"while", s_mri_while, 0}, 914 {"while.b", s_mri_while, 'b'}, 915 {"while.w", s_mri_while, 'w'}, 916 {"while.l", s_mri_while, 'l'}, 917 {"endw", s_mri_endw, 0}, 918 919 {0, 0, 0} 920}; 921 922/* The mote pseudo ops are put into the opcode table, since they 923 don't start with a . they look like opcodes to gas. */ 924 925const pseudo_typeS mote_pseudo_table[] = 926{ 927 928 {"dcl", cons, 4}, 929 {"dc", cons, 2}, 930 {"dcw", cons, 2}, 931 {"dcb", cons, 1}, 932 933 {"dsl", s_space, 4}, 934 {"ds", s_space, 2}, 935 {"dsw", s_space, 2}, 936 {"dsb", s_space, 1}, 937 938 {"xdef", s_globl, 0}, 939 {"align", s_align_bytes, 0}, 940 {0, 0, 0} 941}; 942 943/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host 944 gives identical results to a 32-bit host. */ 945#define TRUNC(X) ((valueT) (X) & 0xffffffff) 946#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) 947 948#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) 949#define isubyte(x) ((valueT) TRUNC (x) < 0x100) 950#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) 951#define isuword(x) ((valueT) TRUNC (x) < 0x10000) 952 953#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) 954#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) 955#define islong(x) (1) 956 957static char notend_table[256]; 958static char alt_notend_table[256]; 959#define notend(s) \ 960 (! (notend_table[(unsigned char) *s] \ 961 || (*s == ':' \ 962 && alt_notend_table[(unsigned char) s[1]]))) 963 964 965/* Return zero if the reference to SYMBOL from within the same segment may 966 be relaxed. */ 967 968/* On an ELF system, we can't relax an externally visible symbol, 969 because it may be overridden by a shared library. However, if 970 TARGET_OS is "elf", then we presume that we are assembling for an 971 embedded system, in which case we don't have to worry about shared 972 libraries, and we can relax any external sym. */ 973 974#define relaxable_symbol(symbol) \ 975 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ 976 || S_IS_WEAK (symbol))) 977 978/* Compute the relocation code for a fixup of SIZE bytes, using pc 979 relative relocation if PCREL is non-zero. PIC says whether a special 980 pic relocation was requested. */ 981 982static bfd_reloc_code_real_type 983get_reloc_code (int size, int pcrel, enum pic_relocation pic) 984{ 985 switch (pic) 986 { 987 case pic_got_pcrel: 988 switch (size) 989 { 990 case 1: 991 return BFD_RELOC_8_GOT_PCREL; 992 case 2: 993 return BFD_RELOC_16_GOT_PCREL; 994 case 4: 995 return BFD_RELOC_32_GOT_PCREL; 996 } 997 break; 998 999 case pic_got_off: 1000 switch (size) 1001 { 1002 case 1: 1003 return BFD_RELOC_8_GOTOFF; 1004 case 2: 1005 return BFD_RELOC_16_GOTOFF; 1006 case 4: 1007 return BFD_RELOC_32_GOTOFF; 1008 } 1009 break; 1010 1011 case pic_plt_pcrel: 1012 switch (size) 1013 { 1014 case 1: 1015 return BFD_RELOC_8_PLT_PCREL; 1016 case 2: 1017 return BFD_RELOC_16_PLT_PCREL; 1018 case 4: 1019 return BFD_RELOC_32_PLT_PCREL; 1020 } 1021 break; 1022 1023 case pic_plt_off: 1024 switch (size) 1025 { 1026 case 1: 1027 return BFD_RELOC_8_PLTOFF; 1028 case 2: 1029 return BFD_RELOC_16_PLTOFF; 1030 case 4: 1031 return BFD_RELOC_32_PLTOFF; 1032 } 1033 break; 1034 1035 case pic_tls_gd: 1036 switch (size) 1037 { 1038 case 1: 1039 return BFD_RELOC_68K_TLS_GD8; 1040 case 2: 1041 return BFD_RELOC_68K_TLS_GD16; 1042 case 4: 1043 return BFD_RELOC_68K_TLS_GD32; 1044 } 1045 break; 1046 1047 case pic_tls_ldm: 1048 switch (size) 1049 { 1050 case 1: 1051 return BFD_RELOC_68K_TLS_LDM8; 1052 case 2: 1053 return BFD_RELOC_68K_TLS_LDM16; 1054 case 4: 1055 return BFD_RELOC_68K_TLS_LDM32; 1056 } 1057 break; 1058 1059 case pic_tls_ldo: 1060 switch (size) 1061 { 1062 case 1: 1063 return BFD_RELOC_68K_TLS_LDO8; 1064 case 2: 1065 return BFD_RELOC_68K_TLS_LDO16; 1066 case 4: 1067 return BFD_RELOC_68K_TLS_LDO32; 1068 } 1069 break; 1070 1071 case pic_tls_ie: 1072 switch (size) 1073 { 1074 case 1: 1075 return BFD_RELOC_68K_TLS_IE8; 1076 case 2: 1077 return BFD_RELOC_68K_TLS_IE16; 1078 case 4: 1079 return BFD_RELOC_68K_TLS_IE32; 1080 } 1081 break; 1082 1083 case pic_tls_le: 1084 switch (size) 1085 { 1086 case 1: 1087 return BFD_RELOC_68K_TLS_LE8; 1088 case 2: 1089 return BFD_RELOC_68K_TLS_LE16; 1090 case 4: 1091 return BFD_RELOC_68K_TLS_LE32; 1092 } 1093 break; 1094 1095 case pic_none: 1096 if (pcrel) 1097 { 1098 switch (size) 1099 { 1100 case 1: 1101 return BFD_RELOC_8_PCREL; 1102 case 2: 1103 return BFD_RELOC_16_PCREL; 1104 case 4: 1105 return BFD_RELOC_32_PCREL; 1106 } 1107 } 1108 else 1109 { 1110 switch (size) 1111 { 1112 case 1: 1113 return BFD_RELOC_8; 1114 case 2: 1115 return BFD_RELOC_16; 1116 case 4: 1117 return BFD_RELOC_32; 1118 } 1119 } 1120 } 1121 1122 if (pcrel) 1123 { 1124 if (pic == pic_none) 1125 as_bad (_("Can not do %d byte pc-relative relocation"), size); 1126 else 1127 as_bad (_("Can not do %d byte pc-relative pic relocation"), size); 1128 } 1129 else 1130 { 1131 if (pic == pic_none) 1132 as_bad (_("Can not do %d byte relocation"), size); 1133 else 1134 as_bad (_("Can not do %d byte pic relocation"), size); 1135 } 1136 1137 return BFD_RELOC_NONE; 1138} 1139 1140/* Here we decide which fixups can be adjusted to make them relative 1141 to the beginning of the section instead of the symbol. Basically 1142 we need to make sure that the dynamic relocations are done 1143 correctly, so in some cases we force the original symbol to be 1144 used. */ 1145int 1146tc_m68k_fix_adjustable (fixS *fixP) 1147{ 1148 /* Adjust_reloc_syms doesn't know about the GOT. */ 1149 switch (fixP->fx_r_type) 1150 { 1151 case BFD_RELOC_8_GOT_PCREL: 1152 case BFD_RELOC_16_GOT_PCREL: 1153 case BFD_RELOC_32_GOT_PCREL: 1154 case BFD_RELOC_8_GOTOFF: 1155 case BFD_RELOC_16_GOTOFF: 1156 case BFD_RELOC_32_GOTOFF: 1157 case BFD_RELOC_8_PLT_PCREL: 1158 case BFD_RELOC_16_PLT_PCREL: 1159 case BFD_RELOC_32_PLT_PCREL: 1160 case BFD_RELOC_8_PLTOFF: 1161 case BFD_RELOC_16_PLTOFF: 1162 case BFD_RELOC_32_PLTOFF: 1163 case BFD_RELOC_68K_TLS_GD32: 1164 case BFD_RELOC_68K_TLS_GD16: 1165 case BFD_RELOC_68K_TLS_GD8: 1166 case BFD_RELOC_68K_TLS_LDM32: 1167 case BFD_RELOC_68K_TLS_LDM16: 1168 case BFD_RELOC_68K_TLS_LDM8: 1169 case BFD_RELOC_68K_TLS_LDO32: 1170 case BFD_RELOC_68K_TLS_LDO16: 1171 case BFD_RELOC_68K_TLS_LDO8: 1172 case BFD_RELOC_68K_TLS_IE32: 1173 case BFD_RELOC_68K_TLS_IE16: 1174 case BFD_RELOC_68K_TLS_IE8: 1175 case BFD_RELOC_68K_TLS_LE32: 1176 case BFD_RELOC_68K_TLS_LE16: 1177 case BFD_RELOC_68K_TLS_LE8: 1178 return 0; 1179 1180 case BFD_RELOC_VTABLE_INHERIT: 1181 case BFD_RELOC_VTABLE_ENTRY: 1182 return 0; 1183 1184 default: 1185 return 1; 1186 } 1187} 1188 1189arelent * 1190tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 1191{ 1192 arelent *reloc; 1193 bfd_reloc_code_real_type code; 1194 1195 /* If the tcbit is set, then this was a fixup of a negative value 1196 that was never resolved. We do not have a reloc to handle this, 1197 so just return. We assume that other code will have detected this 1198 situation and produced a helpful error message, so we just tell the 1199 user that the reloc cannot be produced. */ 1200 if (fixp->fx_tcbit) 1201 { 1202 if (fixp->fx_addsy) 1203 as_bad_where (fixp->fx_file, fixp->fx_line, 1204 _("Unable to produce reloc against symbol '%s'"), 1205 S_GET_NAME (fixp->fx_addsy)); 1206 return NULL; 1207 } 1208 1209 if (fixp->fx_r_type != BFD_RELOC_NONE) 1210 { 1211 code = fixp->fx_r_type; 1212 1213 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible 1214 that fixup_segment converted a non-PC relative reloc into a 1215 PC relative reloc. In such a case, we need to convert the 1216 reloc code. */ 1217 if (fixp->fx_pcrel) 1218 { 1219 switch (code) 1220 { 1221 case BFD_RELOC_8: 1222 code = BFD_RELOC_8_PCREL; 1223 break; 1224 case BFD_RELOC_16: 1225 code = BFD_RELOC_16_PCREL; 1226 break; 1227 case BFD_RELOC_32: 1228 code = BFD_RELOC_32_PCREL; 1229 break; 1230 case BFD_RELOC_8_PCREL: 1231 case BFD_RELOC_16_PCREL: 1232 case BFD_RELOC_32_PCREL: 1233 case BFD_RELOC_8_GOT_PCREL: 1234 case BFD_RELOC_16_GOT_PCREL: 1235 case BFD_RELOC_32_GOT_PCREL: 1236 case BFD_RELOC_8_GOTOFF: 1237 case BFD_RELOC_16_GOTOFF: 1238 case BFD_RELOC_32_GOTOFF: 1239 case BFD_RELOC_8_PLT_PCREL: 1240 case BFD_RELOC_16_PLT_PCREL: 1241 case BFD_RELOC_32_PLT_PCREL: 1242 case BFD_RELOC_8_PLTOFF: 1243 case BFD_RELOC_16_PLTOFF: 1244 case BFD_RELOC_32_PLTOFF: 1245 case BFD_RELOC_68K_TLS_GD32: 1246 case BFD_RELOC_68K_TLS_GD16: 1247 case BFD_RELOC_68K_TLS_GD8: 1248 case BFD_RELOC_68K_TLS_LDM32: 1249 case BFD_RELOC_68K_TLS_LDM16: 1250 case BFD_RELOC_68K_TLS_LDM8: 1251 case BFD_RELOC_68K_TLS_LDO32: 1252 case BFD_RELOC_68K_TLS_LDO16: 1253 case BFD_RELOC_68K_TLS_LDO8: 1254 case BFD_RELOC_68K_TLS_IE32: 1255 case BFD_RELOC_68K_TLS_IE16: 1256 case BFD_RELOC_68K_TLS_IE8: 1257 case BFD_RELOC_68K_TLS_LE32: 1258 case BFD_RELOC_68K_TLS_LE16: 1259 case BFD_RELOC_68K_TLS_LE8: 1260 break; 1261 default: 1262 as_bad_where (fixp->fx_file, fixp->fx_line, 1263 _("Cannot make %s relocation PC relative"), 1264 bfd_get_reloc_code_name (code)); 1265 } 1266 } 1267 } 1268 else 1269 { 1270#define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) 1271 switch (F (fixp->fx_size, fixp->fx_pcrel)) 1272 { 1273#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break 1274 MAP (1, 0, BFD_RELOC_8); 1275 MAP (2, 0, BFD_RELOC_16); 1276 MAP (4, 0, BFD_RELOC_32); 1277 MAP (1, 1, BFD_RELOC_8_PCREL); 1278 MAP (2, 1, BFD_RELOC_16_PCREL); 1279 MAP (4, 1, BFD_RELOC_32_PCREL); 1280 default: 1281 abort (); 1282 } 1283 } 1284#undef F 1285#undef MAP 1286 1287 reloc = XNEW (arelent); 1288 reloc->sym_ptr_ptr = XNEW (asymbol *); 1289 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1290 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1291 if (!fixp->fx_pcrel) 1292 reloc->addend = fixp->fx_addnumber; 1293 else 1294 reloc->addend = (section->vma 1295 + fixp->fx_pcrel_adjust 1296 + fixp->fx_addnumber 1297 + md_pcrel_from (fixp)); 1298 1299 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 1300 gas_assert (reloc->howto != 0); 1301 1302 return reloc; 1303} 1304 1305/* Handle of the OPCODE hash table. NULL means any use before 1306 m68k_ip_begin() will crash. */ 1307static htab_t op_hash; 1308 1309/* Assemble an m68k instruction. */ 1310 1311static void 1312m68k_ip (char *instring) 1313{ 1314 char *p; 1315 struct m68k_op *opP; 1316 const struct m68k_incant *opcode; 1317 const char *s; 1318 int tmpreg = 0, baseo = 0, outro = 0, nextword; 1319 char *pdot, *pdotmove; 1320 enum m68k_size siz1, siz2; 1321 char c; 1322 int losing; 1323 int opsfound; 1324 struct m68k_op operands_backup[6]; 1325 LITTLENUM_TYPE words[6]; 1326 LITTLENUM_TYPE *wordp; 1327 unsigned long ok_arch = 0; 1328 1329 if (*instring == ' ') 1330 instring++; /* Skip leading whitespace. */ 1331 1332 /* Scan up to end of operation-code, which MUST end in end-of-string 1333 or exactly 1 space. */ 1334 pdot = 0; 1335 for (p = instring; *p != '\0'; p++) 1336 { 1337 if (*p == ' ') 1338 break; 1339 if (*p == '.') 1340 pdot = p; 1341 } 1342 1343 if (p == instring) 1344 { 1345 the_ins.error = _("No operator"); 1346 return; 1347 } 1348 1349 /* p now points to the end of the opcode name, probably whitespace. 1350 Make sure the name is null terminated by clobbering the 1351 whitespace, look it up in the hash table, then fix it back. 1352 Remove a dot, first, since the opcode tables have none. */ 1353 if (pdot != NULL) 1354 { 1355 for (pdotmove = pdot; pdotmove < p; pdotmove++) 1356 *pdotmove = pdotmove[1]; 1357 p--; 1358 } 1359 1360 c = *p; 1361 *p = '\0'; 1362 opcode = (const struct m68k_incant *) str_hash_find (op_hash, instring); 1363 *p = c; 1364 1365 if (pdot != NULL) 1366 { 1367 for (pdotmove = p; pdotmove > pdot; pdotmove--) 1368 *pdotmove = pdotmove[-1]; 1369 *pdot = '.'; 1370 ++p; 1371 } 1372 1373 if (opcode == NULL) 1374 { 1375 the_ins.error = _("Unknown operator"); 1376 return; 1377 } 1378 1379 /* Found a legitimate opcode, start matching operands. */ 1380 while (*p == ' ') 1381 ++p; 1382 1383 if (opcode->m_operands == 0) 1384 { 1385 char *old = input_line_pointer; 1386 *old = '\n'; 1387 input_line_pointer = p; 1388 /* Ahh - it's a motorola style pseudo op. */ 1389 mote_pseudo_table[opcode->m_opnum].poc_handler 1390 (mote_pseudo_table[opcode->m_opnum].poc_val); 1391 input_line_pointer = old; 1392 *old = 0; 1393 1394 return; 1395 } 1396 1397 if (flag_mri && opcode->m_opnum == 0) 1398 { 1399 /* In MRI mode, random garbage is allowed after an instruction 1400 which accepts no operands. */ 1401 the_ins.args = opcode->m_operands; 1402 the_ins.numargs = opcode->m_opnum; 1403 the_ins.numo = opcode->m_codenum; 1404 the_ins.opcode[0] = getone (opcode); 1405 the_ins.opcode[1] = gettwo (opcode); 1406 return; 1407 } 1408 1409 for (opP = &the_ins.operands[0]; *p; opP++) 1410 { 1411 p = crack_operand (p, opP); 1412 1413 if (opP->error) 1414 { 1415 the_ins.error = opP->error; 1416 return; 1417 } 1418 } 1419 1420 opsfound = opP - &the_ins.operands[0]; 1421 1422 /* This ugly hack is to support the floating pt opcodes in their 1423 standard form. Essentially, we fake a first entry of type COP#1 */ 1424 if (opcode->m_operands[0] == 'I') 1425 { 1426 int n; 1427 1428 for (n = opsfound; n > 0; --n) 1429 the_ins.operands[n] = the_ins.operands[n - 1]; 1430 1431 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); 1432 the_ins.operands[0].mode = CONTROL; 1433 the_ins.operands[0].reg = m68k_float_copnum; 1434 opsfound++; 1435 } 1436 1437 /* We've got the operands. Find an opcode that'll accept them. */ 1438 for (losing = 0;;) 1439 { 1440 /* If we didn't get the right number of ops, or we have no 1441 common model with this pattern then reject this pattern. */ 1442 1443 ok_arch |= opcode->m_arch; 1444 if (opsfound != opcode->m_opnum 1445 || ((opcode->m_arch & current_architecture) == 0)) 1446 ++losing; 1447 else 1448 { 1449 int i; 1450 1451 /* Make a copy of the operands of this insn so that 1452 we can modify them safely, should we want to. */ 1453 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); 1454 for (i = 0; i < opsfound; i++) 1455 operands_backup[i] = the_ins.operands[i]; 1456 1457 for (s = opcode->m_operands, opP = &operands_backup[0]; 1458 *s && !losing; 1459 s += 2, opP++) 1460 { 1461 /* Warning: this switch is huge! */ 1462 /* I've tried to organize the cases into this order: 1463 non-alpha first, then alpha by letter. Lower-case 1464 goes directly before uppercase counterpart. */ 1465 /* Code with multiple case ...: gets sorted by the lowest 1466 case ... it belongs to. I hope this makes sense. */ 1467 switch (*s) 1468 { 1469 case '!': 1470 switch (opP->mode) 1471 { 1472 case IMMED: 1473 case DREG: 1474 case AREG: 1475 case FPREG: 1476 case CONTROL: 1477 case AINC: 1478 case ADEC: 1479 case REGLST: 1480 losing++; 1481 break; 1482 default: 1483 break; 1484 } 1485 break; 1486 1487 case '<': 1488 switch (opP->mode) 1489 { 1490 case DREG: 1491 case AREG: 1492 case FPREG: 1493 case CONTROL: 1494 case IMMED: 1495 case ADEC: 1496 case REGLST: 1497 losing++; 1498 break; 1499 default: 1500 break; 1501 } 1502 break; 1503 1504 case '>': 1505 switch (opP->mode) 1506 { 1507 case DREG: 1508 case AREG: 1509 case FPREG: 1510 case CONTROL: 1511 case IMMED: 1512 case AINC: 1513 case REGLST: 1514 losing++; 1515 break; 1516 case ABSL: 1517 break; 1518 default: 1519 if (opP->reg == PC 1520 || opP->reg == ZPC) 1521 losing++; 1522 break; 1523 } 1524 break; 1525 1526 case 'm': 1527 switch (opP->mode) 1528 { 1529 case DREG: 1530 case AREG: 1531 case AINDR: 1532 case AINC: 1533 case ADEC: 1534 break; 1535 default: 1536 losing++; 1537 } 1538 break; 1539 1540 case 'n': 1541 switch (opP->mode) 1542 { 1543 case DISP: 1544 break; 1545 default: 1546 losing++; 1547 } 1548 break; 1549 1550 case 'o': 1551 switch (opP->mode) 1552 { 1553 case BASE: 1554 case ABSL: 1555 case IMMED: 1556 break; 1557 default: 1558 losing++; 1559 } 1560 break; 1561 1562 case 'p': 1563 switch (opP->mode) 1564 { 1565 case DREG: 1566 case AREG: 1567 case AINDR: 1568 case AINC: 1569 case ADEC: 1570 break; 1571 case DISP: 1572 if (opP->reg == PC || opP->reg == ZPC) 1573 losing++; 1574 break; 1575 default: 1576 losing++; 1577 } 1578 break; 1579 1580 case 'q': 1581 switch (opP->mode) 1582 { 1583 case DREG: 1584 case AINDR: 1585 case AINC: 1586 case ADEC: 1587 break; 1588 case DISP: 1589 if (opP->reg == PC || opP->reg == ZPC) 1590 losing++; 1591 break; 1592 default: 1593 losing++; 1594 break; 1595 } 1596 break; 1597 1598 case 'v': 1599 switch (opP->mode) 1600 { 1601 case DREG: 1602 case AINDR: 1603 case AINC: 1604 case ADEC: 1605 case ABSL: 1606 break; 1607 case DISP: 1608 if (opP->reg == PC || opP->reg == ZPC) 1609 losing++; 1610 break; 1611 default: 1612 losing++; 1613 break; 1614 } 1615 break; 1616 1617 case '#': 1618 if (opP->mode != IMMED) 1619 losing++; 1620 else if (s[1] == 'b' 1621 && ! isvar (&opP->disp) 1622 && (opP->disp.exp.X_op != O_constant 1623 || ! isbyte (opP->disp.exp.X_add_number))) 1624 losing++; 1625 else if (s[1] == 'B' 1626 && ! isvar (&opP->disp) 1627 && (opP->disp.exp.X_op != O_constant 1628 || ! issbyte (opP->disp.exp.X_add_number))) 1629 losing++; 1630 else if (s[1] == 'w' 1631 && ! isvar (&opP->disp) 1632 && (opP->disp.exp.X_op != O_constant 1633 || ! isword (opP->disp.exp.X_add_number))) 1634 losing++; 1635 else if (s[1] == 'W' 1636 && ! isvar (&opP->disp) 1637 && (opP->disp.exp.X_op != O_constant 1638 || ! issword (opP->disp.exp.X_add_number))) 1639 losing++; 1640 break; 1641 1642 case '^': 1643 case 'T': 1644 if (opP->mode != IMMED) 1645 losing++; 1646 break; 1647 1648 case '$': 1649 if (opP->mode == AREG 1650 || opP->mode == CONTROL 1651 || opP->mode == FPREG 1652 || opP->mode == IMMED 1653 || opP->mode == REGLST 1654 || (opP->mode != ABSL 1655 && (opP->reg == PC 1656 || opP->reg == ZPC))) 1657 losing++; 1658 break; 1659 1660 case '%': 1661 if (opP->mode == CONTROL 1662 || opP->mode == FPREG 1663 || opP->mode == REGLST 1664 || opP->mode == IMMED 1665 || (opP->mode != ABSL 1666 && (opP->reg == PC 1667 || opP->reg == ZPC))) 1668 losing++; 1669 break; 1670 1671 case '&': 1672 switch (opP->mode) 1673 { 1674 case DREG: 1675 case AREG: 1676 case FPREG: 1677 case CONTROL: 1678 case IMMED: 1679 case AINC: 1680 case ADEC: 1681 case REGLST: 1682 losing++; 1683 break; 1684 case ABSL: 1685 break; 1686 default: 1687 if (opP->reg == PC 1688 || opP->reg == ZPC) 1689 losing++; 1690 break; 1691 } 1692 break; 1693 1694 case '*': 1695 if (opP->mode == CONTROL 1696 || opP->mode == FPREG 1697 || opP->mode == REGLST) 1698 losing++; 1699 break; 1700 1701 case '+': 1702 if (opP->mode != AINC) 1703 losing++; 1704 break; 1705 1706 case '-': 1707 if (opP->mode != ADEC) 1708 losing++; 1709 break; 1710 1711 case '/': 1712 switch (opP->mode) 1713 { 1714 case AREG: 1715 case CONTROL: 1716 case FPREG: 1717 case AINC: 1718 case ADEC: 1719 case IMMED: 1720 case REGLST: 1721 losing++; 1722 break; 1723 default: 1724 break; 1725 } 1726 break; 1727 1728 case ';': 1729 switch (opP->mode) 1730 { 1731 case AREG: 1732 case CONTROL: 1733 case FPREG: 1734 case REGLST: 1735 losing++; 1736 break; 1737 default: 1738 break; 1739 } 1740 break; 1741 1742 case '?': 1743 switch (opP->mode) 1744 { 1745 case AREG: 1746 case CONTROL: 1747 case FPREG: 1748 case AINC: 1749 case ADEC: 1750 case IMMED: 1751 case REGLST: 1752 losing++; 1753 break; 1754 case ABSL: 1755 break; 1756 default: 1757 if (opP->reg == PC || opP->reg == ZPC) 1758 losing++; 1759 break; 1760 } 1761 break; 1762 1763 case '@': 1764 switch (opP->mode) 1765 { 1766 case AREG: 1767 case CONTROL: 1768 case FPREG: 1769 case IMMED: 1770 case REGLST: 1771 losing++; 1772 break; 1773 default: 1774 break; 1775 } 1776 break; 1777 1778 case '~': /* For now! (JF FOO is this right?) */ 1779 switch (opP->mode) 1780 { 1781 case DREG: 1782 case AREG: 1783 case CONTROL: 1784 case FPREG: 1785 case IMMED: 1786 case REGLST: 1787 losing++; 1788 break; 1789 case ABSL: 1790 break; 1791 default: 1792 if (opP->reg == PC 1793 || opP->reg == ZPC) 1794 losing++; 1795 break; 1796 } 1797 break; 1798 1799 case '3': 1800 if (opP->mode != CONTROL 1801 || (opP->reg != TT0 && opP->reg != TT1)) 1802 losing++; 1803 break; 1804 1805 case 'A': 1806 if (opP->mode != AREG) 1807 losing++; 1808 break; 1809 1810 case 'a': 1811 if (opP->mode != AINDR) 1812 ++losing; 1813 break; 1814 1815 case '4': 1816 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC 1817 && (opP->mode != DISP 1818 || opP->reg < ADDR0 1819 || opP->reg > ADDR7)) 1820 ++losing; 1821 break; 1822 1823 case 'B': /* FOO */ 1824 if (opP->mode != ABSL 1825 || (flag_long_jumps 1826 && startswith (instring, "jbsr"))) 1827 losing++; 1828 break; 1829 1830 case 'b': 1831 switch (opP->mode) 1832 { 1833 case IMMED: 1834 case ABSL: 1835 case AREG: 1836 case FPREG: 1837 case CONTROL: 1838 case POST: 1839 case PRE: 1840 case REGLST: 1841 losing++; 1842 break; 1843 default: 1844 break; 1845 } 1846 break; 1847 1848 case 'C': 1849 if (opP->mode != CONTROL || opP->reg != CCR) 1850 losing++; 1851 break; 1852 1853 case 'd': 1854 if (opP->mode != DISP 1855 || opP->reg < ADDR0 1856 || opP->reg > ADDR7) 1857 losing++; 1858 break; 1859 1860 case 'D': 1861 if (opP->mode != DREG) 1862 losing++; 1863 break; 1864 1865 case 'E': 1866 if (opP->reg != ACC) 1867 losing++; 1868 break; 1869 1870 case 'e': 1871 if (opP->reg != ACC && opP->reg != ACC1 1872 && opP->reg != ACC2 && opP->reg != ACC3) 1873 losing++; 1874 break; 1875 1876 case 'F': 1877 if (opP->mode != FPREG) 1878 losing++; 1879 break; 1880 1881 case 'G': 1882 if (opP->reg != MACSR) 1883 losing++; 1884 break; 1885 1886 case 'g': 1887 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) 1888 losing++; 1889 break; 1890 1891 case 'H': 1892 if (opP->reg != MASK) 1893 losing++; 1894 break; 1895 1896 case 'I': 1897 if (opP->mode != CONTROL 1898 || opP->reg < COP0 1899 || opP->reg > COP7) 1900 losing++; 1901 break; 1902 1903 case 'i': 1904 if (opP->mode != LSH && opP->mode != RSH) 1905 losing++; 1906 break; 1907 1908 case 'J': 1909 if (opP->mode != CONTROL 1910 || opP->reg < USP 1911 || opP->reg > last_movec_reg 1912 || !control_regs) 1913 losing++; 1914 else 1915 { 1916 const enum m68k_register *rp; 1917 1918 for (rp = control_regs; *rp; rp++) 1919 { 1920 if (*rp == opP->reg) 1921 break; 1922 /* In most CPUs RAMBAR refers to control reg 1923 c05 (RAMBAR1), but a few CPUs have it 1924 refer to c04 (RAMBAR0). */ 1925 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) 1926 { 1927 opP->reg = RAMBAR_ALT; 1928 break; 1929 } 1930 } 1931 if (*rp == 0) 1932 losing++; 1933 } 1934 break; 1935 1936 case 'k': 1937 if (opP->mode != IMMED) 1938 losing++; 1939 break; 1940 1941 case 'l': 1942 case 'L': 1943 if (opP->mode == DREG 1944 || opP->mode == AREG 1945 || opP->mode == FPREG) 1946 { 1947 if (s[1] == '8') 1948 losing++; 1949 else 1950 { 1951 switch (opP->mode) 1952 { 1953 case DREG: 1954 opP->mask = 1 << (opP->reg - DATA0); 1955 break; 1956 case AREG: 1957 opP->mask = 1 << (opP->reg - ADDR0 + 8); 1958 break; 1959 case FPREG: 1960 opP->mask = 1 << (opP->reg - FP0 + 16); 1961 break; 1962 default: 1963 abort (); 1964 } 1965 opP->mode = REGLST; 1966 } 1967 } 1968 else if (opP->mode == CONTROL) 1969 { 1970 if (s[1] != '8') 1971 losing++; 1972 else 1973 { 1974 switch (opP->reg) 1975 { 1976 case FPI: 1977 opP->mask = 1 << 24; 1978 break; 1979 case FPS: 1980 opP->mask = 1 << 25; 1981 break; 1982 case FPC: 1983 opP->mask = 1 << 26; 1984 break; 1985 default: 1986 losing++; 1987 break; 1988 } 1989 opP->mode = REGLST; 1990 } 1991 } 1992 else if (opP->mode != REGLST) 1993 losing++; 1994 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) 1995 losing++; 1996 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) 1997 losing++; 1998 break; 1999 2000 case 'M': 2001 if (opP->mode != IMMED) 2002 losing++; 2003 else if (opP->disp.exp.X_op != O_constant 2004 || ! issbyte (opP->disp.exp.X_add_number)) 2005 losing++; 2006 else if (! m68k_quick 2007 && instring[3] != 'q' 2008 && instring[4] != 'q') 2009 losing++; 2010 break; 2011 2012 case 'O': 2013 if (opP->mode != DREG 2014 && opP->mode != IMMED 2015 && opP->mode != ABSL) 2016 losing++; 2017 break; 2018 2019 case 'Q': 2020 if (opP->mode != IMMED) 2021 losing++; 2022 else if (opP->disp.exp.X_op != O_constant 2023 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2024 losing++; 2025 else if (! m68k_quick 2026 && (startswith (instring, "add") 2027 || startswith (instring, "sub")) 2028 && instring[3] != 'q') 2029 losing++; 2030 break; 2031 2032 case 'R': 2033 if (opP->mode != DREG && opP->mode != AREG) 2034 losing++; 2035 break; 2036 2037 case 'r': 2038 if (opP->mode != AINDR 2039 && (opP->mode != BASE 2040 || (opP->reg != 0 2041 && opP->reg != ZADDR0) 2042 || opP->disp.exp.X_op != O_absent 2043 || ((opP->index.reg < DATA0 2044 || opP->index.reg > DATA7) 2045 && (opP->index.reg < ADDR0 2046 || opP->index.reg > ADDR7)) 2047 || opP->index.size != SIZE_UNSPEC 2048 || opP->index.scale != 1)) 2049 losing++; 2050 break; 2051 2052 case 's': 2053 if (opP->mode != CONTROL 2054 || ! (opP->reg == FPI 2055 || opP->reg == FPS 2056 || opP->reg == FPC)) 2057 losing++; 2058 break; 2059 2060 case 'S': 2061 if (opP->mode != CONTROL || opP->reg != SR) 2062 losing++; 2063 break; 2064 2065 case 't': 2066 if (opP->mode != IMMED) 2067 losing++; 2068 else if (opP->disp.exp.X_op != O_constant 2069 || TRUNC (opP->disp.exp.X_add_number) > 7) 2070 losing++; 2071 break; 2072 2073 case 'U': 2074 if (opP->mode != CONTROL || opP->reg != USP) 2075 losing++; 2076 break; 2077 2078 case 'x': 2079 if (opP->mode != IMMED) 2080 losing++; 2081 else if (opP->disp.exp.X_op != O_constant 2082 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff 2083 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) 2084 losing++; 2085 break; 2086 2087 case 'j': 2088 if (opP->mode != IMMED) 2089 losing++; 2090 else if (opP->disp.exp.X_op != O_constant 2091 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2092 losing++; 2093 break; 2094 2095 case 'K': 2096 if (opP->mode != IMMED) 2097 losing++; 2098 else if (opP->disp.exp.X_op != O_constant 2099 || TRUNC (opP->disp.exp.X_add_number) > 511) 2100 losing++; 2101 break; 2102 2103 /* JF these are out of order. We could put them 2104 in order if we were willing to put up with 2105 bunches of #ifdef m68851s in the code. 2106 2107 Don't forget that you need these operands 2108 to use 68030 MMU instructions. */ 2109#ifndef NO_68851 2110 /* Memory addressing mode used by pflushr. */ 2111 case '|': 2112 if (opP->mode == CONTROL 2113 || opP->mode == FPREG 2114 || opP->mode == DREG 2115 || opP->mode == AREG 2116 || opP->mode == REGLST) 2117 losing++; 2118 /* We should accept immediate operands, but they 2119 supposedly have to be quad word, and we don't 2120 handle that. I would like to see what a Motorola 2121 assembler does before doing something here. */ 2122 if (opP->mode == IMMED) 2123 losing++; 2124 break; 2125 2126 case 'f': 2127 if (opP->mode != CONTROL 2128 || (opP->reg != SFC && opP->reg != DFC)) 2129 losing++; 2130 break; 2131 2132 case '0': 2133 if (opP->mode != CONTROL || opP->reg != TC) 2134 losing++; 2135 break; 2136 2137 case '1': 2138 if (opP->mode != CONTROL || opP->reg != AC) 2139 losing++; 2140 break; 2141 2142 case '2': 2143 if (opP->mode != CONTROL 2144 || (opP->reg != CAL 2145 && opP->reg != VAL 2146 && opP->reg != SCC)) 2147 losing++; 2148 break; 2149 2150 case 'V': 2151 if (opP->mode != CONTROL 2152 || opP->reg != VAL) 2153 losing++; 2154 break; 2155 2156 case 'W': 2157 if (opP->mode != CONTROL 2158 || (opP->reg != DRP 2159 && opP->reg != SRP 2160 && opP->reg != CRP)) 2161 losing++; 2162 break; 2163 2164 case 'w': 2165 switch (opP->mode) 2166 { 2167 case IMMED: 2168 case ABSL: 2169 case AREG: 2170 case DREG: 2171 case FPREG: 2172 case CONTROL: 2173 case POST: 2174 case PRE: 2175 case REGLST: 2176 losing++; 2177 break; 2178 default: 2179 break; 2180 } 2181 break; 2182 2183 case 'X': 2184 if (opP->mode != CONTROL 2185 || (!(opP->reg >= BAD && opP->reg <= BAD + 7) 2186 && !(opP->reg >= BAC && opP->reg <= BAC + 7))) 2187 losing++; 2188 break; 2189 2190 case 'Y': 2191 if (opP->mode != CONTROL || opP->reg != PSR) 2192 losing++; 2193 break; 2194 2195 case 'Z': 2196 if (opP->mode != CONTROL || opP->reg != PCSR) 2197 losing++; 2198 break; 2199#endif 2200 case 'c': 2201 if (opP->mode != CONTROL 2202 || (opP->reg != NC 2203 && opP->reg != IC 2204 && opP->reg != DC 2205 && opP->reg != BC)) 2206 losing++; 2207 break; 2208 2209 case '_': 2210 if (opP->mode != ABSL) 2211 ++losing; 2212 break; 2213 2214 case 'u': 2215 if (opP->reg < DATA0L || opP->reg > ADDR7U) 2216 losing++; 2217 /* FIXME: kludge instead of fixing parser: 2218 upper/lower registers are *not* CONTROL 2219 registers, but ordinary ones. */ 2220 if ((opP->reg >= DATA0L && opP->reg <= DATA7L) 2221 || (opP->reg >= DATA0U && opP->reg <= DATA7U)) 2222 opP->mode = DREG; 2223 else 2224 opP->mode = AREG; 2225 break; 2226 2227 case 'y': 2228 if (!(opP->mode == AINDR 2229 || (opP->mode == DISP 2230 && !(opP->reg == PC || opP->reg == ZPC)))) 2231 losing++; 2232 break; 2233 2234 case 'z': 2235 if (!(opP->mode == AINDR || opP->mode == DISP)) 2236 losing++; 2237 break; 2238 2239 default: 2240 abort (); 2241 } 2242 2243 if (losing) 2244 break; 2245 } 2246 2247 /* Since we have found the correct instruction, copy 2248 in the modifications that we may have made. */ 2249 if (!losing) 2250 for (i = 0; i < opsfound; i++) 2251 the_ins.operands[i] = operands_backup[i]; 2252 } 2253 2254 if (!losing) 2255 break; 2256 2257 opcode = opcode->m_next; 2258 2259 if (!opcode) 2260 { 2261 if (ok_arch 2262 && !(ok_arch & current_architecture)) 2263 { 2264 const struct m68k_cpu *cpu; 2265 int any = 0; 2266 size_t space = 400; 2267 char *buf = XNEWVEC (char, space + 1); 2268 size_t len; 2269 int paren = 1; 2270 2271 the_ins.error = buf; 2272 /* Make sure there's a NUL at the end of the buffer -- strncpy 2273 won't write one when it runs out of buffer. */ 2274 buf[space] = 0; 2275#define APPEND(STRING) \ 2276 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) 2277 2278 APPEND (_("invalid instruction for this architecture; needs ")); 2279 switch (ok_arch) 2280 { 2281 case mcfisa_a: 2282 APPEND ("ColdFire ISA_A"); 2283 break; 2284 case mcfhwdiv: 2285 APPEND ("ColdFire "); 2286 APPEND (_("hardware divide")); 2287 break; 2288 case mcfisa_aa: 2289 APPEND ("ColdFire ISA_A+"); 2290 break; 2291 case mcfisa_b: 2292 APPEND ("ColdFire ISA_B"); 2293 break; 2294 case mcfisa_c: 2295 APPEND ("ColdFire ISA_C"); 2296 break; 2297 case cfloat: 2298 APPEND ("ColdFire fpu"); 2299 break; 2300 case mfloat: 2301 APPEND ("M68K fpu"); 2302 break; 2303 case mmmu: 2304 APPEND ("M68K mmu"); 2305 break; 2306 case m68020up: 2307 APPEND ("68020 "); 2308 APPEND (_("or higher")); 2309 break; 2310 case m68000up: 2311 APPEND ("68000 "); 2312 APPEND (_("or higher")); 2313 break; 2314 case m68010up: 2315 APPEND ("68010 "); 2316 APPEND (_("or higher")); 2317 break; 2318 default: 2319 paren = 0; 2320 } 2321 if (paren) 2322 APPEND (" ("); 2323 2324 for (cpu = m68k_cpus; cpu->name; cpu++) 2325 if (!cpu->alias && (cpu->arch & ok_arch)) 2326 { 2327 const struct m68k_cpu *alias; 2328 int seen_master = 0; 2329 2330 if (any) 2331 APPEND (", "); 2332 any = 0; 2333 APPEND (cpu->name); 2334 for (alias = cpu; alias != m68k_cpus; alias--) 2335 if (alias[-1].alias >= 0) 2336 break; 2337 for (; !seen_master || alias->alias > 0; alias++) 2338 { 2339 if (!alias->alias) 2340 seen_master = 1; 2341 else 2342 { 2343 if (any) 2344 APPEND (", "); 2345 else 2346 APPEND (" ["); 2347 APPEND (alias->name); 2348 any = 1; 2349 } 2350 } 2351 if (any) 2352 APPEND ("]"); 2353 any = 1; 2354 } 2355 if (paren) 2356 APPEND (")"); 2357#undef APPEND 2358 if (!space) 2359 { 2360 /* We ran out of space, so replace the end of the list 2361 with ellipsis. */ 2362 buf -= 4; 2363 while (*buf != ' ') 2364 buf--; 2365 strcpy (buf, " ..."); 2366 } 2367 } 2368 else 2369 the_ins.error = _("operands mismatch"); 2370 return; 2371 } 2372 2373 losing = 0; 2374 } 2375 2376 /* Now assemble it. */ 2377 the_ins.args = opcode->m_operands; 2378 the_ins.numargs = opcode->m_opnum; 2379 the_ins.numo = opcode->m_codenum; 2380 the_ins.opcode[0] = getone (opcode); 2381 the_ins.opcode[1] = gettwo (opcode); 2382 2383 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) 2384 { 2385 int have_disp = 0; 2386 int use_pl = 0; 2387 2388 /* This switch is a doozy. 2389 Watch the first step; it's a big one! */ 2390 switch (s[0]) 2391 { 2392 2393 case '*': 2394 case '~': 2395 case '%': 2396 case ';': 2397 case '@': 2398 case '!': 2399 case '&': 2400 case '$': 2401 case '?': 2402 case '/': 2403 case '<': 2404 case '>': 2405 case 'b': 2406 case 'm': 2407 case 'n': 2408 case 'o': 2409 case 'p': 2410 case 'q': 2411 case 'v': 2412 case 'w': 2413 case 'y': 2414 case 'z': 2415 case '4': 2416#ifndef NO_68851 2417 case '|': 2418#endif 2419 switch (opP->mode) 2420 { 2421 case IMMED: 2422 tmpreg = 0x3c; /* 7.4 */ 2423 if (strchr ("bwl", s[1])) 2424 nextword = get_num (&opP->disp, 90); 2425 else 2426 nextword = get_num (&opP->disp, 0); 2427 if (isvar (&opP->disp)) 2428 add_fix (s[1], &opP->disp, 0, 0); 2429 switch (s[1]) 2430 { 2431 case 'b': 2432 if (!isbyte (nextword)) 2433 opP->error = _("operand out of range"); 2434 addword (nextword); 2435 baseo = 0; 2436 break; 2437 case 'w': 2438 if (!isword (nextword)) 2439 opP->error = _("operand out of range"); 2440 addword (nextword); 2441 baseo = 0; 2442 break; 2443 case 'W': 2444 if (!issword (nextword)) 2445 opP->error = _("operand out of range"); 2446 addword (nextword); 2447 baseo = 0; 2448 break; 2449 case 'l': 2450 addword (nextword >> 16); 2451 addword (nextword); 2452 baseo = 0; 2453 break; 2454 2455 case 'f': 2456 baseo = 2; 2457 outro = 8; 2458 break; 2459 case 'F': 2460 baseo = 4; 2461 outro = 11; 2462 break; 2463 case 'x': 2464 baseo = 6; 2465 outro = 15; 2466 break; 2467 case 'p': 2468 baseo = 6; 2469 outro = -1; 2470 break; 2471 default: 2472 abort (); 2473 } 2474 if (!baseo) 2475 break; 2476 2477 /* We gotta put out some float. */ 2478 if (op (&opP->disp) != O_big) 2479 { 2480 valueT val; 2481 int gencnt; 2482 2483 /* Can other cases happen here? */ 2484 if (op (&opP->disp) != O_constant) 2485 abort (); 2486 2487 val = (valueT) offs (&opP->disp); 2488 gencnt = 0; 2489 do 2490 { 2491 generic_bignum[gencnt] = (LITTLENUM_TYPE) val; 2492 val >>= LITTLENUM_NUMBER_OF_BITS; 2493 ++gencnt; 2494 } 2495 while (val != 0); 2496 offs (&opP->disp) = gencnt; 2497 } 2498 if (offs (&opP->disp) > 0) 2499 { 2500 if (offs (&opP->disp) > baseo) 2501 { 2502 as_warn (_("Bignum too big for %c format; truncated"), 2503 s[1]); 2504 offs (&opP->disp) = baseo; 2505 } 2506 baseo -= offs (&opP->disp); 2507 while (baseo--) 2508 addword (0); 2509 for (wordp = generic_bignum + offs (&opP->disp) - 1; 2510 offs (&opP->disp)--; 2511 --wordp) 2512 addword (*wordp); 2513 break; 2514 } 2515 gen_to_words (words, baseo, (long) outro); 2516 for (wordp = words; baseo--; wordp++) 2517 addword (*wordp); 2518 break; 2519 case DREG: 2520 tmpreg = opP->reg - DATA; /* 0.dreg */ 2521 break; 2522 case AREG: 2523 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ 2524 break; 2525 case AINDR: 2526 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2527 break; 2528 case ADEC: 2529 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ 2530 break; 2531 case AINC: 2532 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ 2533 break; 2534 case DISP: 2535 2536 nextword = get_num (&opP->disp, 90); 2537 2538 /* Convert mode 5 addressing with a zero offset into 2539 mode 2 addressing to reduce the instruction size by a 2540 word. */ 2541 if (! isvar (&opP->disp) 2542 && (nextword == 0) 2543 && (opP->disp.size == SIZE_UNSPEC) 2544 && (opP->reg >= ADDR0) 2545 && (opP->reg <= ADDR7)) 2546 { 2547 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2548 break; 2549 } 2550 2551 if (opP->reg == PC 2552 && ! isvar (&opP->disp) 2553 && m68k_abspcadd) 2554 { 2555 opP->disp.exp.X_op = O_symbol; 2556 opP->disp.exp.X_add_symbol = 2557 section_symbol (absolute_section); 2558 } 2559 2560 /* Force into index mode. Hope this works. */ 2561 2562 /* We do the first bit for 32-bit displacements, and the 2563 second bit for 16 bit ones. It is possible that we 2564 should make the default be WORD instead of LONG, but 2565 I think that'd break GCC, so we put up with a little 2566 inefficiency for the sake of working output. */ 2567 2568 if (!issword (nextword) 2569 || (isvar (&opP->disp) 2570 && ((opP->disp.size == SIZE_UNSPEC 2571 && flag_short_refs == 0 2572 && cpu_of_arch (current_architecture) >= m68020 2573 && ! arch_coldfire_p (current_architecture)) 2574 || opP->disp.size == SIZE_LONG))) 2575 { 2576 if (cpu_of_arch (current_architecture) < m68020 2577 || arch_coldfire_p (current_architecture)) 2578 opP->error = 2579 _("displacement too large for this architecture; needs 68020 or higher"); 2580 if (opP->reg == PC) 2581 tmpreg = 0x3B; /* 7.3 */ 2582 else 2583 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2584 if (isvar (&opP->disp)) 2585 { 2586 if (opP->reg == PC) 2587 { 2588 if (opP->disp.size == SIZE_LONG 2589 /* If the displacement needs pic 2590 relocation it cannot be relaxed. */ 2591 || opP->disp.pic_reloc != pic_none) 2592 { 2593 addword (0x0170); 2594 add_fix ('l', &opP->disp, 1, 2); 2595 } 2596 else 2597 { 2598 add_frag (adds (&opP->disp), 2599 SEXT (offs (&opP->disp)), 2600 TAB (PCREL1632, SZ_UNDEF)); 2601 break; 2602 } 2603 } 2604 else 2605 { 2606 addword (0x0170); 2607 add_fix ('l', &opP->disp, 0, 0); 2608 } 2609 } 2610 else 2611 addword (0x0170); 2612 addword (nextword >> 16); 2613 } 2614 else 2615 { 2616 if (opP->reg == PC) 2617 tmpreg = 0x3A; /* 7.2 */ 2618 else 2619 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ 2620 2621 if (isvar (&opP->disp)) 2622 { 2623 if (opP->reg == PC) 2624 { 2625 add_fix ('w', &opP->disp, 1, 0); 2626 } 2627 else 2628 add_fix ('w', &opP->disp, 0, 0); 2629 } 2630 } 2631 addword (nextword); 2632 break; 2633 2634 case POST: 2635 case PRE: 2636 case BASE: 2637 nextword = 0; 2638 baseo = get_num (&opP->disp, 90); 2639 if (opP->mode == POST || opP->mode == PRE) 2640 outro = get_num (&opP->odisp, 90); 2641 /* Figure out the `addressing mode'. 2642 Also turn on the BASE_DISABLE bit, if needed. */ 2643 if (opP->reg == PC || opP->reg == ZPC) 2644 { 2645 tmpreg = 0x3b; /* 7.3 */ 2646 if (opP->reg == ZPC) 2647 nextword |= 0x80; 2648 } 2649 else if (opP->reg == 0) 2650 { 2651 nextword |= 0x80; 2652 tmpreg = 0x30; /* 6.garbage */ 2653 } 2654 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) 2655 { 2656 nextword |= 0x80; 2657 tmpreg = 0x30 + opP->reg - ZADDR0; 2658 } 2659 else 2660 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2661 2662 siz1 = opP->disp.size; 2663 if (opP->mode == POST || opP->mode == PRE) 2664 siz2 = opP->odisp.size; 2665 else 2666 siz2 = SIZE_UNSPEC; 2667 2668 /* Index register stuff. */ 2669 if (opP->index.reg != 0 2670 && opP->index.reg >= DATA 2671 && opP->index.reg <= ADDR7) 2672 { 2673 nextword |= (opP->index.reg - DATA) << 12; 2674 2675 if (opP->index.size == SIZE_LONG 2676 || (opP->index.size == SIZE_UNSPEC 2677 && m68k_index_width_default == SIZE_LONG)) 2678 nextword |= 0x800; 2679 2680 if ((opP->index.scale != 1 2681 && cpu_of_arch (current_architecture) < m68020) 2682 || (opP->index.scale == 8 2683 && (arch_coldfire_p (current_architecture) 2684 && !arch_coldfire_fpu (current_architecture)))) 2685 { 2686 opP->error = 2687 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); 2688 } 2689 2690 if (arch_coldfire_p (current_architecture) 2691 && opP->index.size == SIZE_WORD) 2692 opP->error = _("invalid index size for coldfire"); 2693 2694 switch (opP->index.scale) 2695 { 2696 case 1: 2697 break; 2698 case 2: 2699 nextword |= 0x200; 2700 break; 2701 case 4: 2702 nextword |= 0x400; 2703 break; 2704 case 8: 2705 nextword |= 0x600; 2706 break; 2707 default: 2708 abort (); 2709 } 2710 /* IF it's simple, 2711 GET US OUT OF HERE! */ 2712 2713 /* Must be INDEX, with an index register. Address 2714 register cannot be ZERO-PC, and either :b was 2715 forced, or we know it will fit. For a 68000 or 2716 68010, force this mode anyways, because the 2717 larger modes aren't supported. */ 2718 if (opP->mode == BASE 2719 && ((opP->reg >= ADDR0 2720 && opP->reg <= ADDR7) 2721 || opP->reg == PC)) 2722 { 2723 if (siz1 == SIZE_BYTE 2724 || cpu_of_arch (current_architecture) < m68020 2725 || arch_coldfire_p (current_architecture) 2726 || (siz1 == SIZE_UNSPEC 2727 && ! isvar (&opP->disp) 2728 && issbyte (baseo))) 2729 { 2730 nextword += baseo & 0xff; 2731 addword (nextword); 2732 if (isvar (&opP->disp)) 2733 { 2734 /* Do a byte relocation. If it doesn't 2735 fit (possible on m68000) let the 2736 fixup processing complain later. */ 2737 if (opP->reg == PC) 2738 add_fix ('B', &opP->disp, 1, 1); 2739 else 2740 add_fix ('B', &opP->disp, 0, 0); 2741 } 2742 else if (siz1 != SIZE_BYTE) 2743 { 2744 if (siz1 != SIZE_UNSPEC) 2745 as_warn (_("Forcing byte displacement")); 2746 if (! issbyte (baseo)) 2747 opP->error = _("byte displacement out of range"); 2748 } 2749 2750 break; 2751 } 2752 else if (siz1 == SIZE_UNSPEC 2753 && opP->reg == PC 2754 && isvar (&opP->disp) 2755 && subs (&opP->disp) == NULL 2756 /* If the displacement needs pic 2757 relocation it cannot be relaxed. */ 2758 && opP->disp.pic_reloc == pic_none) 2759 { 2760 /* The code in md_convert_frag_1 needs to be 2761 able to adjust nextword. Call frag_grow 2762 to ensure that we have enough space in 2763 the frag obstack to make all the bytes 2764 contiguous. */ 2765 frag_grow (14); 2766 nextword += baseo & 0xff; 2767 addword (nextword); 2768 add_frag (adds (&opP->disp), 2769 SEXT (offs (&opP->disp)), 2770 TAB (PCINDEX, SZ_UNDEF)); 2771 2772 break; 2773 } 2774 } 2775 } 2776 else 2777 { 2778 nextword |= 0x40; /* No index reg. */ 2779 if (opP->index.reg >= ZDATA0 2780 && opP->index.reg <= ZDATA7) 2781 nextword |= (opP->index.reg - ZDATA0) << 12; 2782 else if (opP->index.reg >= ZADDR0 2783 && opP->index.reg <= ZADDR7) 2784 nextword |= (opP->index.reg - ZADDR0 + 8) << 12; 2785 } 2786 2787 /* It isn't simple. */ 2788 2789 if (cpu_of_arch (current_architecture) < m68020 2790 || arch_coldfire_p (current_architecture)) 2791 opP->error = 2792 _("invalid operand mode for this architecture; needs 68020 or higher"); 2793 2794 nextword |= 0x100; 2795 /* If the guy specified a width, we assume that it is 2796 wide enough. Maybe it isn't. If so, we lose. */ 2797 switch (siz1) 2798 { 2799 case SIZE_UNSPEC: 2800 if (isvar (&opP->disp) 2801 ? m68k_rel32 2802 : ! issword (baseo)) 2803 { 2804 siz1 = SIZE_LONG; 2805 nextword |= 0x30; 2806 } 2807 else if (! isvar (&opP->disp) && baseo == 0) 2808 nextword |= 0x10; 2809 else 2810 { 2811 nextword |= 0x20; 2812 siz1 = SIZE_WORD; 2813 } 2814 break; 2815 case SIZE_BYTE: 2816 as_warn (_(":b not permitted; defaulting to :w")); 2817 /* Fall through. */ 2818 case SIZE_WORD: 2819 nextword |= 0x20; 2820 break; 2821 case SIZE_LONG: 2822 nextword |= 0x30; 2823 break; 2824 } 2825 2826 /* Figure out inner displacement stuff. */ 2827 if (opP->mode == POST || opP->mode == PRE) 2828 { 2829 if (cpu_of_arch (current_architecture) & cpu32) 2830 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); 2831 switch (siz2) 2832 { 2833 case SIZE_UNSPEC: 2834 if (isvar (&opP->odisp) 2835 ? m68k_rel32 2836 : ! issword (outro)) 2837 { 2838 siz2 = SIZE_LONG; 2839 nextword |= 0x3; 2840 } 2841 else if (! isvar (&opP->odisp) && outro == 0) 2842 nextword |= 0x1; 2843 else 2844 { 2845 nextword |= 0x2; 2846 siz2 = SIZE_WORD; 2847 } 2848 break; 2849 case 1: 2850 as_warn (_(":b not permitted; defaulting to :w")); 2851 /* Fall through. */ 2852 case 2: 2853 nextword |= 0x2; 2854 break; 2855 case 3: 2856 nextword |= 0x3; 2857 break; 2858 } 2859 if (opP->mode == POST 2860 && (nextword & 0x40) == 0) 2861 nextword |= 0x04; 2862 } 2863 addword (nextword); 2864 2865 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) 2866 { 2867 if (opP->reg == PC || opP->reg == ZPC) 2868 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); 2869 else 2870 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); 2871 } 2872 if (siz1 == SIZE_LONG) 2873 addword (baseo >> 16); 2874 if (siz1 != SIZE_UNSPEC) 2875 addword (baseo); 2876 2877 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) 2878 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); 2879 if (siz2 == SIZE_LONG) 2880 addword (outro >> 16); 2881 if (siz2 != SIZE_UNSPEC) 2882 addword (outro); 2883 2884 break; 2885 2886 case ABSL: 2887 nextword = get_num (&opP->disp, 90); 2888 switch (opP->disp.size) 2889 { 2890 default: 2891 abort (); 2892 case SIZE_UNSPEC: 2893 if (!isvar (&opP->disp) && issword (offs (&opP->disp))) 2894 { 2895 tmpreg = 0x38; /* 7.0 */ 2896 addword (nextword); 2897 break; 2898 } 2899 if (isvar (&opP->disp) 2900 && !subs (&opP->disp) 2901 && adds (&opP->disp) 2902 /* If the displacement needs pic relocation it 2903 cannot be relaxed. */ 2904 && opP->disp.pic_reloc == pic_none 2905 && !flag_long_jumps 2906 && !strchr ("~%&$?", s[0])) 2907 { 2908 tmpreg = 0x3A; /* 7.2 */ 2909 add_frag (adds (&opP->disp), 2910 SEXT (offs (&opP->disp)), 2911 TAB (ABSTOPCREL, SZ_UNDEF)); 2912 break; 2913 } 2914 /* Fall through. */ 2915 case SIZE_LONG: 2916 if (isvar (&opP->disp)) 2917 add_fix ('l', &opP->disp, 0, 0); 2918 2919 tmpreg = 0x39;/* 7.1 mode */ 2920 addword (nextword >> 16); 2921 addword (nextword); 2922 break; 2923 2924 case SIZE_BYTE: 2925 as_bad (_("unsupported byte value; use a different suffix")); 2926 /* Fall through. */ 2927 2928 case SIZE_WORD: 2929 if (isvar (&opP->disp)) 2930 add_fix ('w', &opP->disp, 0, 0); 2931 2932 tmpreg = 0x38;/* 7.0 mode */ 2933 addword (nextword); 2934 break; 2935 } 2936 break; 2937 case CONTROL: 2938 case FPREG: 2939 default: 2940 as_bad (_("unknown/incorrect operand")); 2941 /* abort (); */ 2942 } 2943 2944 /* If s[0] is '4', then this is for the mac instructions 2945 that can have a trailing_ampersand set. If so, set 0x100 2946 bit on tmpreg so install_gen_operand can check for it and 2947 set the appropriate bit (word2, bit 5). */ 2948 if (s[0] == '4') 2949 { 2950 if (opP->trailing_ampersand) 2951 tmpreg |= 0x100; 2952 } 2953 install_gen_operand (s[1], tmpreg); 2954 break; 2955 2956 case '#': 2957 case '^': 2958 switch (s[1]) 2959 { /* JF: I hate floating point! */ 2960 case 'j': 2961 tmpreg = 70; 2962 break; 2963 case '8': 2964 tmpreg = 20; 2965 break; 2966 case 'C': 2967 tmpreg = 50; 2968 break; 2969 case '3': 2970 default: 2971 tmpreg = 90; 2972 break; 2973 } 2974 tmpreg = get_num (&opP->disp, tmpreg); 2975 if (isvar (&opP->disp)) 2976 add_fix (s[1], &opP->disp, 0, 0); 2977 switch (s[1]) 2978 { 2979 case 'b': /* Danger: These do no check for 2980 certain types of overflow. 2981 user beware! */ 2982 if (!isbyte (tmpreg)) 2983 opP->error = _("out of range"); 2984 insop (tmpreg, opcode); 2985 if (isvar (&opP->disp)) 2986 the_ins.reloc[the_ins.nrel - 1].n = 2987 (opcode->m_codenum) * 2 + 1; 2988 break; 2989 case 'B': 2990 if (!issbyte (tmpreg)) 2991 opP->error = _("out of range"); 2992 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; 2993 if (isvar (&opP->disp)) 2994 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; 2995 break; 2996 case 'w': 2997 if (!isword (tmpreg)) 2998 opP->error = _("out of range"); 2999 insop (tmpreg, opcode); 3000 if (isvar (&opP->disp)) 3001 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3002 break; 3003 case 'W': 3004 if (!issword (tmpreg)) 3005 opP->error = _("out of range"); 3006 insop (tmpreg, opcode); 3007 if (isvar (&opP->disp)) 3008 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3009 break; 3010 case 'l': 3011 /* Because of the way insop works, we put these two out 3012 backwards. */ 3013 insop (tmpreg, opcode); 3014 insop (tmpreg >> 16, opcode); 3015 if (isvar (&opP->disp)) 3016 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3017 break; 3018 case '3': 3019 tmpreg &= 0xFF; 3020 /* Fall through. */ 3021 case '8': 3022 case 'C': 3023 case 'j': 3024 install_operand (s[1], tmpreg); 3025 break; 3026 default: 3027 abort (); 3028 } 3029 break; 3030 3031 case '+': 3032 case '-': 3033 case 'A': 3034 case 'a': 3035 install_operand (s[1], opP->reg - ADDR); 3036 break; 3037 3038 case 'B': 3039 tmpreg = get_num (&opP->disp, 90); 3040 3041 switch (s[1]) 3042 { 3043 case 'B': 3044 add_fix ('B', &opP->disp, 1, -1); 3045 break; 3046 case 'W': 3047 add_fix ('w', &opP->disp, 1, 0); 3048 addword (0); 3049 break; 3050 case 'L': 3051 long_branch: 3052 the_ins.opcode[0] |= 0xff; 3053 add_fix ('l', &opP->disp, 1, 0); 3054 addword (0); 3055 addword (0); 3056 break; 3057 case 'g': /* Conditional branch */ 3058 have_disp = HAVE_LONG_CALL (current_architecture); 3059 goto var_branch; 3060 3061 case 'b': /* Unconditional branch */ 3062 have_disp = HAVE_LONG_BRANCH (current_architecture); 3063 use_pl = LONG_BRANCH_VIA_COND (current_architecture); 3064 goto var_branch; 3065 3066 case 's': /* Unconditional subroutine */ 3067 have_disp = HAVE_LONG_CALL (current_architecture); 3068 3069 var_branch: 3070 if (subs (&opP->disp) /* We can't relax it. */ 3071 /* If the displacement needs pic relocation it cannot be 3072 relaxed. */ 3073 || opP->disp.pic_reloc != pic_none) 3074 { 3075 if (!have_disp) 3076 as_warn (_("Can't use long branches on this architecture")); 3077 goto long_branch; 3078 } 3079 3080 /* This could either be a symbol, or an absolute 3081 address. If it's an absolute address, turn it into 3082 an absolute jump right here and keep it out of the 3083 relaxer. */ 3084 if (adds (&opP->disp) == 0) 3085 { 3086 if (the_ins.opcode[0] == 0x6000) /* jbra */ 3087 the_ins.opcode[0] = 0x4EF9; 3088 else if (the_ins.opcode[0] == 0x6100) /* jbsr */ 3089 the_ins.opcode[0] = 0x4EB9; 3090 else /* jCC */ 3091 { 3092 the_ins.opcode[0] ^= 0x0100; 3093 the_ins.opcode[0] |= 0x0006; 3094 addword (0x4EF9); 3095 } 3096 add_fix ('l', &opP->disp, 0, 0); 3097 addword (0); 3098 addword (0); 3099 break; 3100 } 3101 3102 /* Now we know it's going into the relaxer. Now figure 3103 out which mode. We try in this order of preference: 3104 long branch, absolute jump, byte/word branches only. */ 3105 if (have_disp) 3106 add_frag (adds (&opP->disp), 3107 SEXT (offs (&opP->disp)), 3108 TAB (BRANCHBWL, SZ_UNDEF)); 3109 else if (! flag_keep_pcrel) 3110 { 3111 if ((the_ins.opcode[0] == 0x6000) 3112 || (the_ins.opcode[0] == 0x6100)) 3113 add_frag (adds (&opP->disp), 3114 SEXT (offs (&opP->disp)), 3115 TAB (BRABSJUNC, SZ_UNDEF)); 3116 else 3117 add_frag (adds (&opP->disp), 3118 SEXT (offs (&opP->disp)), 3119 TAB (BRABSJCOND, SZ_UNDEF)); 3120 } 3121 else 3122 add_frag (adds (&opP->disp), 3123 SEXT (offs (&opP->disp)), 3124 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) 3125 : TAB (BRANCHBW, SZ_UNDEF))); 3126 break; 3127 case 'w': 3128 if (isvar (&opP->disp)) 3129 { 3130 /* Check for DBcc instructions. We can relax them, 3131 but only if we have long branches and/or absolute 3132 jumps. */ 3133 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) 3134 && (HAVE_LONG_BRANCH (current_architecture) 3135 || ! flag_keep_pcrel)) 3136 { 3137 if (HAVE_LONG_BRANCH (current_architecture)) 3138 add_frag (adds (&opP->disp), 3139 SEXT (offs (&opP->disp)), 3140 TAB (DBCCLBR, SZ_UNDEF)); 3141 else 3142 add_frag (adds (&opP->disp), 3143 SEXT (offs (&opP->disp)), 3144 TAB (DBCCABSJ, SZ_UNDEF)); 3145 break; 3146 } 3147 add_fix ('w', &opP->disp, 1, 0); 3148 } 3149 addword (0); 3150 break; 3151 case 'C': /* Fixed size LONG coproc branches. */ 3152 add_fix ('l', &opP->disp, 1, 0); 3153 addword (0); 3154 addword (0); 3155 break; 3156 case 'c': /* Var size Coprocesssor branches. */ 3157 if (subs (&opP->disp) || (adds (&opP->disp) == 0)) 3158 { 3159 the_ins.opcode[the_ins.numo - 1] |= 0x40; 3160 add_fix ('l', &opP->disp, 1, 0); 3161 addword (0); 3162 addword (0); 3163 } 3164 else 3165 add_frag (adds (&opP->disp), 3166 SEXT (offs (&opP->disp)), 3167 TAB (FBRANCH, SZ_UNDEF)); 3168 break; 3169 default: 3170 abort (); 3171 } 3172 break; 3173 3174 case 'C': /* Ignore it. */ 3175 break; 3176 3177 case 'd': /* JF this is a kludge. */ 3178 install_operand ('s', opP->reg - ADDR); 3179 tmpreg = get_num (&opP->disp, 90); 3180 if (!issword (tmpreg)) 3181 { 3182 as_warn (_("Expression out of range, using 0")); 3183 tmpreg = 0; 3184 } 3185 addword (tmpreg); 3186 break; 3187 3188 case 'D': 3189 install_operand (s[1], opP->reg - DATA); 3190 break; 3191 3192 case 'e': /* EMAC ACCx, reg/reg. */ 3193 install_operand (s[1], opP->reg - ACC); 3194 break; 3195 3196 case 'E': /* Ignore it. */ 3197 break; 3198 3199 case 'F': 3200 install_operand (s[1], opP->reg - FP0); 3201 break; 3202 3203 case 'g': /* EMAC ACCEXTx. */ 3204 install_operand (s[1], opP->reg - ACCEXT01); 3205 break; 3206 3207 case 'G': /* Ignore it. */ 3208 case 'H': 3209 break; 3210 3211 case 'I': 3212 tmpreg = opP->reg - COP0; 3213 install_operand (s[1], tmpreg); 3214 break; 3215 3216 case 'i': /* MAC/EMAC scale factor. */ 3217 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); 3218 break; 3219 3220 case 'J': /* JF foo. */ 3221 switch (opP->reg) 3222 { 3223 case SFC: 3224 tmpreg = 0x000; 3225 break; 3226 case DFC: 3227 tmpreg = 0x001; 3228 break; 3229 case CACR: 3230 tmpreg = 0x002; 3231 break; 3232 case TC: 3233 case ASID: 3234 tmpreg = 0x003; 3235 break; 3236 case ACR0: 3237 case ITT0: 3238 tmpreg = 0x004; 3239 break; 3240 case ACR1: 3241 case ITT1: 3242 tmpreg = 0x005; 3243 break; 3244 case ACR2: 3245 case DTT0: 3246 tmpreg = 0x006; 3247 break; 3248 case ACR3: 3249 case DTT1: 3250 tmpreg = 0x007; 3251 break; 3252 case BUSCR: 3253 case MMUBAR: 3254 tmpreg = 0x008; 3255 break; 3256 case RGPIOBAR: 3257 tmpreg = 0x009; 3258 break; 3259 case ACR4: 3260 case ACR5: 3261 case ACR6: 3262 case ACR7: 3263 tmpreg = 0x00c + (opP->reg - ACR4); 3264 break; 3265 3266 case USP: 3267 tmpreg = 0x800; 3268 break; 3269 case VBR: 3270 tmpreg = 0x801; 3271 break; 3272 case CAAR: 3273 case CPUCR: 3274 tmpreg = 0x802; 3275 break; 3276 case MSP: 3277 tmpreg = 0x803; 3278 break; 3279 case ISP: 3280 tmpreg = 0x804; 3281 break; 3282 case MMUSR: 3283 tmpreg = 0x805; 3284 break; 3285 case URP: 3286 tmpreg = 0x806; 3287 break; 3288 case SRP: 3289 tmpreg = 0x807; 3290 break; 3291 case PCR: 3292 tmpreg = 0x808; 3293 break; 3294 case ROMBAR: 3295 case ROMBAR0: 3296 tmpreg = 0xC00; 3297 break; 3298 case ROMBAR1: 3299 tmpreg = 0xC01; 3300 break; 3301 case FLASHBAR: 3302 case RAMBAR0: 3303 case RAMBAR_ALT: 3304 tmpreg = 0xC04; 3305 break; 3306 case RAMBAR: 3307 case RAMBAR1: 3308 tmpreg = 0xC05; 3309 break; 3310 case MPCR: 3311 tmpreg = 0xC0C; 3312 break; 3313 case EDRAMBAR: 3314 tmpreg = 0xC0D; 3315 break; 3316 case MBAR0: 3317 case MBAR2: 3318 case SECMBAR: 3319 tmpreg = 0xC0E; 3320 break; 3321 case MBAR1: 3322 case MBAR: 3323 tmpreg = 0xC0F; 3324 break; 3325 case PCR1U0: 3326 tmpreg = 0xD02; 3327 break; 3328 case PCR1L0: 3329 tmpreg = 0xD03; 3330 break; 3331 case PCR2U0: 3332 tmpreg = 0xD04; 3333 break; 3334 case PCR2L0: 3335 tmpreg = 0xD05; 3336 break; 3337 case PCR3U0: 3338 tmpreg = 0xD06; 3339 break; 3340 case PCR3L0: 3341 tmpreg = 0xD07; 3342 break; 3343 case PCR1L1: 3344 tmpreg = 0xD0A; 3345 break; 3346 case PCR1U1: 3347 tmpreg = 0xD0B; 3348 break; 3349 case PCR2L1: 3350 tmpreg = 0xD0C; 3351 break; 3352 case PCR2U1: 3353 tmpreg = 0xD0D; 3354 break; 3355 case PCR3L1: 3356 tmpreg = 0xD0E; 3357 break; 3358 case PCR3U1: 3359 tmpreg = 0xD0F; 3360 break; 3361 case CAC: 3362 tmpreg = 0xFFE; 3363 break; 3364 case MBO: 3365 tmpreg = 0xFFF; 3366 break; 3367 default: 3368 abort (); 3369 } 3370 install_operand (s[1], tmpreg); 3371 break; 3372 3373 case 'k': 3374 tmpreg = get_num (&opP->disp, 55); 3375 install_operand (s[1], tmpreg & 0x7f); 3376 break; 3377 3378 case 'l': 3379 tmpreg = opP->mask; 3380 if (s[1] == 'w') 3381 { 3382 if (tmpreg & 0x7FF0000) 3383 as_bad (_("Floating point register in register list")); 3384 insop (reverse_16_bits (tmpreg), opcode); 3385 } 3386 else 3387 { 3388 if (tmpreg & 0x700FFFF) 3389 as_bad (_("Wrong register in floating-point reglist")); 3390 install_operand (s[1], reverse_8_bits (tmpreg >> 16)); 3391 } 3392 break; 3393 3394 case 'L': 3395 tmpreg = opP->mask; 3396 if (s[1] == 'w') 3397 { 3398 if (tmpreg & 0x7FF0000) 3399 as_bad (_("Floating point register in register list")); 3400 insop (tmpreg, opcode); 3401 } 3402 else if (s[1] == '8') 3403 { 3404 if (tmpreg & 0x0FFFFFF) 3405 as_bad (_("incorrect register in reglist")); 3406 install_operand (s[1], tmpreg >> 24); 3407 } 3408 else 3409 { 3410 if (tmpreg & 0x700FFFF) 3411 as_bad (_("wrong register in floating-point reglist")); 3412 else 3413 install_operand (s[1], tmpreg >> 16); 3414 } 3415 break; 3416 3417 case 'M': 3418 install_operand (s[1], get_num (&opP->disp, 60)); 3419 break; 3420 3421 case 'O': 3422 tmpreg = ((opP->mode == DREG) 3423 ? 0x20 + (int) (opP->reg - DATA) 3424 : (get_num (&opP->disp, 40) & 0x1F)); 3425 install_operand (s[1], tmpreg); 3426 break; 3427 3428 case 'Q': 3429 tmpreg = get_num (&opP->disp, 10); 3430 if (tmpreg == 8) 3431 tmpreg = 0; 3432 install_operand (s[1], tmpreg); 3433 break; 3434 3435 case 'R': 3436 /* This depends on the fact that ADDR registers are eight 3437 more than their corresponding DATA regs, so the result 3438 will have the ADDR_REG bit set. */ 3439 install_operand (s[1], opP->reg - DATA); 3440 break; 3441 3442 case 'r': 3443 if (opP->mode == AINDR) 3444 install_operand (s[1], opP->reg - DATA); 3445 else 3446 install_operand (s[1], opP->index.reg - DATA); 3447 break; 3448 3449 case 's': 3450 if (opP->reg == FPI) 3451 tmpreg = 0x1; 3452 else if (opP->reg == FPS) 3453 tmpreg = 0x2; 3454 else if (opP->reg == FPC) 3455 tmpreg = 0x4; 3456 else 3457 abort (); 3458 install_operand (s[1], tmpreg); 3459 break; 3460 3461 case 'S': /* Ignore it. */ 3462 break; 3463 3464 case 'T': 3465 install_operand (s[1], get_num (&opP->disp, 30)); 3466 break; 3467 3468 case 'U': /* Ignore it. */ 3469 break; 3470 3471 case 'c': 3472 switch (opP->reg) 3473 { 3474 case NC: 3475 tmpreg = 0; 3476 break; 3477 case DC: 3478 tmpreg = 1; 3479 break; 3480 case IC: 3481 tmpreg = 2; 3482 break; 3483 case BC: 3484 tmpreg = 3; 3485 break; 3486 default: 3487 as_fatal (_("failed sanity check")); 3488 } /* switch on cache token. */ 3489 install_operand (s[1], tmpreg); 3490 break; 3491#ifndef NO_68851 3492 /* JF: These are out of order, I fear. */ 3493 case 'f': 3494 switch (opP->reg) 3495 { 3496 case SFC: 3497 tmpreg = 0; 3498 break; 3499 case DFC: 3500 tmpreg = 1; 3501 break; 3502 default: 3503 abort (); 3504 } 3505 install_operand (s[1], tmpreg); 3506 break; 3507 3508 case '0': 3509 case '1': 3510 case '2': 3511 switch (opP->reg) 3512 { 3513 case TC: 3514 tmpreg = 0; 3515 break; 3516 case CAL: 3517 tmpreg = 4; 3518 break; 3519 case VAL: 3520 tmpreg = 5; 3521 break; 3522 case SCC: 3523 tmpreg = 6; 3524 break; 3525 case AC: 3526 tmpreg = 7; 3527 break; 3528 default: 3529 abort (); 3530 } 3531 install_operand (s[1], tmpreg); 3532 break; 3533 3534 case 'V': 3535 if (opP->reg == VAL) 3536 break; 3537 abort (); 3538 3539 case 'W': 3540 switch (opP->reg) 3541 { 3542 case DRP: 3543 tmpreg = 1; 3544 break; 3545 case SRP: 3546 tmpreg = 2; 3547 break; 3548 case CRP: 3549 tmpreg = 3; 3550 break; 3551 default: 3552 abort (); 3553 } 3554 install_operand (s[1], tmpreg); 3555 break; 3556 3557 case 'X': 3558 switch (opP->reg) 3559 { 3560 case BAD: 3561 case BAD + 1: 3562 case BAD + 2: 3563 case BAD + 3: 3564 case BAD + 4: 3565 case BAD + 5: 3566 case BAD + 6: 3567 case BAD + 7: 3568 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 3569 break; 3570 3571 case BAC: 3572 case BAC + 1: 3573 case BAC + 2: 3574 case BAC + 3: 3575 case BAC + 4: 3576 case BAC + 5: 3577 case BAC + 6: 3578 case BAC + 7: 3579 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 3580 break; 3581 3582 default: 3583 abort (); 3584 } 3585 install_operand (s[1], tmpreg); 3586 break; 3587 case 'Y': 3588 know (opP->reg == PSR); 3589 break; 3590 case 'Z': 3591 know (opP->reg == PCSR); 3592 break; 3593#endif /* m68851 */ 3594 case '3': 3595 switch (opP->reg) 3596 { 3597 case TT0: 3598 tmpreg = 2; 3599 break; 3600 case TT1: 3601 tmpreg = 3; 3602 break; 3603 default: 3604 abort (); 3605 } 3606 install_operand (s[1], tmpreg); 3607 break; 3608 case 't': 3609 tmpreg = get_num (&opP->disp, 20); 3610 install_operand (s[1], tmpreg); 3611 break; 3612 case '_': /* used only for move16 absolute 32-bit address. */ 3613 if (isvar (&opP->disp)) 3614 add_fix ('l', &opP->disp, 0, 0); 3615 tmpreg = get_num (&opP->disp, 90); 3616 addword (tmpreg >> 16); 3617 addword (tmpreg & 0xFFFF); 3618 break; 3619 case 'u': 3620 install_operand (s[1], opP->reg - DATA0L); 3621 opP->reg -= (DATA0L); 3622 opP->reg &= 0x0F; /* remove upper/lower bit. */ 3623 break; 3624 case 'x': 3625 tmpreg = get_num (&opP->disp, 80); 3626 if (tmpreg == -1) 3627 tmpreg = 0; 3628 install_operand (s[1], tmpreg); 3629 break; 3630 case 'j': 3631 tmpreg = get_num (&opP->disp, 10); 3632 install_operand (s[1], tmpreg - 1); 3633 break; 3634 case 'K': 3635 tmpreg = get_num (&opP->disp, 65); 3636 install_operand (s[1], tmpreg); 3637 break; 3638 default: 3639 abort (); 3640 } 3641 } 3642 3643 /* By the time when get here (FINALLY) the_ins contains the complete 3644 instruction, ready to be emitted. . . */ 3645} 3646 3647static int 3648reverse_16_bits (int in) 3649{ 3650 int out = 0; 3651 int n; 3652 3653 static int mask[16] = 3654 { 3655 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3656 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 3657 }; 3658 for (n = 0; n < 16; n++) 3659 { 3660 if (in & mask[n]) 3661 out |= mask[15 - n]; 3662 } 3663 return out; 3664} /* reverse_16_bits() */ 3665 3666static int 3667reverse_8_bits (int in) 3668{ 3669 int out = 0; 3670 int n; 3671 3672 static int mask[8] = 3673 { 3674 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3675 }; 3676 3677 for (n = 0; n < 8; n++) 3678 { 3679 if (in & mask[n]) 3680 out |= mask[7 - n]; 3681 } 3682 return out; 3683} /* reverse_8_bits() */ 3684 3685/* Cause an extra frag to be generated here, inserting up to 3686 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be 3687 generated; its primary type is rs_machine_dependent. 3688 3689 The TYPE parameter is also used by md_convert_frag_1 and 3690 md_estimate_size_before_relax. The appropriate type of fixup will 3691 be emitted by md_convert_frag_1. 3692 3693 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 3694static void 3695install_operand (int mode, int val) 3696{ 3697 switch (mode) 3698 { 3699 case 's': 3700 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ 3701 break; 3702 case 'd': 3703 the_ins.opcode[0] |= val << 9; 3704 break; 3705 case 'E': 3706 the_ins.opcode[1] |= val << 9; 3707 break; 3708 case '1': 3709 the_ins.opcode[1] |= val << 12; 3710 break; 3711 case '2': 3712 the_ins.opcode[1] |= val << 6; 3713 break; 3714 case '3': 3715 the_ins.opcode[1] |= val; 3716 break; 3717 case '4': 3718 the_ins.opcode[2] |= val << 12; 3719 break; 3720 case '5': 3721 the_ins.opcode[2] |= val << 6; 3722 break; 3723 case '6': 3724 /* DANGER! This is a hack to force cas2l and cas2w cmds to be 3725 three words long! */ 3726 the_ins.numo++; 3727 the_ins.opcode[2] |= val; 3728 break; 3729 case '7': 3730 the_ins.opcode[1] |= val << 7; 3731 break; 3732 case '8': 3733 the_ins.opcode[1] |= val << 10; 3734 break; 3735#ifndef NO_68851 3736 case '9': 3737 the_ins.opcode[1] |= val << 5; 3738 break; 3739#endif 3740 3741 case 't': 3742 the_ins.opcode[1] |= (val << 10) | (val << 7); 3743 break; 3744 case 'D': 3745 the_ins.opcode[1] |= (val << 12) | val; 3746 break; 3747 case 'g': 3748 the_ins.opcode[0] |= val = 0xff; 3749 break; 3750 case 'i': 3751 the_ins.opcode[0] |= val << 9; 3752 break; 3753 case 'C': 3754 the_ins.opcode[1] |= val; 3755 break; 3756 case 'j': 3757 the_ins.opcode[1] |= val; 3758 the_ins.numo++; /* What a hack. */ 3759 break; 3760 case 'k': 3761 the_ins.opcode[1] |= val << 4; 3762 break; 3763 case 'b': 3764 case 'w': 3765 case 'W': 3766 case 'l': 3767 break; 3768 case 'e': 3769 the_ins.opcode[0] |= (val << 6); 3770 break; 3771 case 'L': 3772 the_ins.opcode[1] = (val >> 16); 3773 the_ins.opcode[2] = val & 0xffff; 3774 break; 3775 case 'm': 3776 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3777 the_ins.opcode[0] |= ((val & 0x7) << 9); 3778 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3779 break; 3780 case 'n': /* MAC/EMAC Rx on !load. */ 3781 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3782 the_ins.opcode[0] |= ((val & 0x7) << 9); 3783 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3784 break; 3785 case 'o': /* MAC/EMAC Rx on load. */ 3786 the_ins.opcode[1] |= val << 12; 3787 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3788 break; 3789 case 'M': /* MAC/EMAC Ry on !load. */ 3790 the_ins.opcode[0] |= (val & 0xF); 3791 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3792 break; 3793 case 'N': /* MAC/EMAC Ry on load. */ 3794 the_ins.opcode[1] |= (val & 0xF); 3795 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3796 break; 3797 case 'h': 3798 the_ins.opcode[1] |= ((val != 1) << 10); 3799 break; 3800 case 'F': 3801 the_ins.opcode[0] |= ((val & 0x3) << 9); 3802 break; 3803 case 'f': 3804 the_ins.opcode[0] |= ((val & 0x3) << 0); 3805 break; 3806 case 'G': /* EMAC accumulator in a EMAC load instruction. */ 3807 the_ins.opcode[0] |= ((~val & 0x1) << 7); 3808 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3809 break; 3810 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ 3811 the_ins.opcode[0] |= ((val & 0x1) << 7); 3812 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3813 break; 3814 case 'I': 3815 the_ins.opcode[1] |= ((val & 0x3) << 9); 3816 break; 3817 case ']': 3818 the_ins.opcode[0] |= (val & 0x1) <<10; 3819 break; 3820 case 'c': 3821 default: 3822 as_fatal (_("failed sanity check.")); 3823 } 3824} 3825 3826static void 3827install_gen_operand (int mode, int val) 3828{ 3829 switch (mode) 3830 { 3831 case '/': /* Special for mask loads for mac/msac insns with 3832 possible mask; trailing_ampersand set in bit 8. */ 3833 the_ins.opcode[0] |= (val & 0x3f); 3834 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); 3835 break; 3836 case 's': 3837 the_ins.opcode[0] |= val; 3838 break; 3839 case 'd': 3840 /* This is a kludge!!! */ 3841 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; 3842 break; 3843 case 'b': 3844 case 'w': 3845 case 'l': 3846 case 'f': 3847 case 'F': 3848 case 'x': 3849 case 'p': 3850 the_ins.opcode[0] |= val; 3851 break; 3852 /* more stuff goes here. */ 3853 default: 3854 as_fatal (_("failed sanity check.")); 3855 } 3856} 3857 3858/* Verify that we have some number of paren pairs, do m68k_ip_op(), and 3859 then deal with the bitfield hack. */ 3860 3861static char * 3862crack_operand (char *str, struct m68k_op *opP) 3863{ 3864 int parens; 3865 int c; 3866 char *beg_str; 3867 int inquote = 0; 3868 3869 if (!str) 3870 { 3871 return str; 3872 } 3873 beg_str = str; 3874 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) 3875 { 3876 if (! inquote) 3877 { 3878 if (*str == '(') 3879 parens++; 3880 else if (*str == ')') 3881 { 3882 if (!parens) 3883 { /* ERROR. */ 3884 opP->error = _("Extra )"); 3885 return str; 3886 } 3887 --parens; 3888 } 3889 } 3890 if (flag_mri && *str == '\'') 3891 inquote = ! inquote; 3892 } 3893 if (!*str && parens) 3894 { /* ERROR. */ 3895 opP->error = _("Missing )"); 3896 return str; 3897 } 3898 c = *str; 3899 *str = '\0'; 3900 if (m68k_ip_op (beg_str, opP) != 0) 3901 { 3902 *str = c; 3903 return str; 3904 } 3905 *str = c; 3906 if (c == '}') 3907 c = *++str; /* JF bitfield hack. */ 3908 if (c) 3909 { 3910 c = *++str; 3911 if (!c) 3912 as_bad (_("Missing operand")); 3913 } 3914 3915 /* Detect MRI REG symbols and convert them to REGLSTs. */ 3916 if (opP->mode == CONTROL && (int)opP->reg < 0) 3917 { 3918 opP->mode = REGLST; 3919 opP->mask = ~(int)opP->reg; 3920 opP->reg = 0; 3921 } 3922 3923 return str; 3924} 3925 3926/* This is the guts of the machine-dependent assembler. STR points to a 3927 machine dependent instruction. This function is supposed to emit 3928 the frags/bytes it assembles to. 3929 */ 3930 3931static void 3932insert_reg (const char *regname, int regnum) 3933{ 3934 char buf[100]; 3935 int i; 3936 3937#ifdef REGISTER_PREFIX 3938 if (!flag_reg_prefix_optional) 3939 { 3940 buf[0] = REGISTER_PREFIX; 3941 strcpy (buf + 1, regname); 3942 regname = buf; 3943 } 3944#endif 3945 3946 symbol_table_insert (symbol_new (regname, reg_section, 3947 &zero_address_frag, regnum)); 3948 3949 for (i = 0; regname[i]; i++) 3950 buf[i] = TOUPPER (regname[i]); 3951 buf[i] = '\0'; 3952 3953 symbol_table_insert (symbol_new (buf, reg_section, 3954 &zero_address_frag, regnum)); 3955} 3956 3957struct init_entry 3958 { 3959 const char *name; 3960 int number; 3961 }; 3962 3963static const struct init_entry init_table[] = 3964{ 3965 { "d0", DATA0 }, 3966 { "d1", DATA1 }, 3967 { "d2", DATA2 }, 3968 { "d3", DATA3 }, 3969 { "d4", DATA4 }, 3970 { "d5", DATA5 }, 3971 { "d6", DATA6 }, 3972 { "d7", DATA7 }, 3973 { "a0", ADDR0 }, 3974 { "a1", ADDR1 }, 3975 { "a2", ADDR2 }, 3976 { "a3", ADDR3 }, 3977 { "a4", ADDR4 }, 3978 { "a5", ADDR5 }, 3979 { "a6", ADDR6 }, 3980 { "fp", ADDR6 }, 3981 { "a7", ADDR7 }, 3982 { "sp", ADDR7 }, 3983 { "ssp", ADDR7 }, 3984 { "fp0", FP0 }, 3985 { "fp1", FP1 }, 3986 { "fp2", FP2 }, 3987 { "fp3", FP3 }, 3988 { "fp4", FP4 }, 3989 { "fp5", FP5 }, 3990 { "fp6", FP6 }, 3991 { "fp7", FP7 }, 3992 { "fpi", FPI }, 3993 { "fpiar", FPI }, 3994 { "fpc", FPI }, 3995 { "fps", FPS }, 3996 { "fpsr", FPS }, 3997 { "fpc", FPC }, 3998 { "fpcr", FPC }, 3999 { "control", FPC }, 4000 { "status", FPS }, 4001 { "iaddr", FPI }, 4002 4003 { "cop0", COP0 }, 4004 { "cop1", COP1 }, 4005 { "cop2", COP2 }, 4006 { "cop3", COP3 }, 4007 { "cop4", COP4 }, 4008 { "cop5", COP5 }, 4009 { "cop6", COP6 }, 4010 { "cop7", COP7 }, 4011 { "pc", PC }, 4012 { "zpc", ZPC }, 4013 { "sr", SR }, 4014 4015 { "ccr", CCR }, 4016 { "cc", CCR }, 4017 4018 { "acc", ACC }, 4019 { "acc0", ACC }, 4020 { "acc1", ACC1 }, 4021 { "acc2", ACC2 }, 4022 { "acc3", ACC3 }, 4023 { "accext01", ACCEXT01 }, 4024 { "accext23", ACCEXT23 }, 4025 { "macsr", MACSR }, 4026 { "mask", MASK }, 4027 4028 /* Control registers. */ 4029 { "sfc", SFC }, /* Source Function Code. */ 4030 { "sfcr", SFC }, 4031 { "dfc", DFC }, /* Destination Function Code. */ 4032 { "dfcr", DFC }, 4033 { "cacr", CACR }, /* Cache Control Register. */ 4034 { "caar", CAAR }, /* Cache Address Register. */ 4035 { "cpucr", CPUCR }, /* CPU Control Register. */ 4036 4037 { "usp", USP }, /* User Stack Pointer. */ 4038 { "vbr", VBR }, /* Vector Base Register. */ 4039 { "msp", MSP }, /* Master Stack Pointer. */ 4040 { "isp", ISP }, /* Interrupt Stack Pointer. */ 4041 4042 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ 4043 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ 4044 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ 4045 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ 4046 4047 /* 68ec040 versions of same */ 4048 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ 4049 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ 4050 { "dacr0", DTT0 }, /* Data Access Control Register 0. */ 4051 { "dacr1", DTT1 }, /* Data Access Control Register 0. */ 4052 4053 /* Coldfire versions of same. The ColdFire programmer's reference 4054 manual indicated that the order is 2,3,0,1, but Ken Rose 4055 <rose@netcom.com> says that 0,1,2,3 is the correct order. */ 4056 { "acr0", ACR0 }, /* Access Control Unit 0. */ 4057 { "acr1", ACR1 }, /* Access Control Unit 1. */ 4058 { "acr2", ACR2 }, /* Access Control Unit 2. */ 4059 { "acr3", ACR3 }, /* Access Control Unit 3. */ 4060 { "acr4", ACR4 }, /* Access Control Unit 4. */ 4061 { "acr5", ACR5 }, /* Access Control Unit 5. */ 4062 { "acr6", ACR6 }, /* Access Control Unit 6. */ 4063 { "acr7", ACR7 }, /* Access Control Unit 7. */ 4064 4065 { "tc", TC }, /* MMU Translation Control Register. */ 4066 { "tcr", TC }, 4067 { "asid", ASID }, 4068 4069 { "mmusr", MMUSR }, /* MMU Status Register. */ 4070 { "srp", SRP }, /* User Root Pointer. */ 4071 { "urp", URP }, /* Supervisor Root Pointer. */ 4072 4073 { "buscr", BUSCR }, 4074 { "mmubar", MMUBAR }, 4075 { "pcr", PCR }, 4076 4077 { "rombar", ROMBAR }, /* ROM Base Address Register. */ 4078 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ 4079 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ 4080 { "mbar", MBAR }, /* Module Base Address Register. */ 4081 4082 { "mbar0", MBAR0 }, /* mcfv4e registers. */ 4083 { "mbar1", MBAR1 }, /* mcfv4e registers. */ 4084 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ 4085 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ 4086 { "mpcr", MPCR }, /* mcfv4e registers. */ 4087 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ 4088 { "secmbar", SECMBAR }, /* mcfv4e registers. */ 4089 { "asid", TC }, /* mcfv4e registers. */ 4090 { "mmubar", BUSCR }, /* mcfv4e registers. */ 4091 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ 4092 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ 4093 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ 4094 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ 4095 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ 4096 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ 4097 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ 4098 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ 4099 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ 4100 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ 4101 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ 4102 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ 4103 4104 { "flashbar", FLASHBAR }, /* mcf528x registers. */ 4105 { "rambar", RAMBAR }, /* mcf528x registers. */ 4106 4107 { "mbar2", MBAR2 }, /* mcf5249 registers. */ 4108 4109 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ 4110 4111 { "cac", CAC }, /* fido registers. */ 4112 { "mbb", MBO }, /* fido registers (obsolete). */ 4113 { "mbo", MBO }, /* fido registers. */ 4114 /* End of control registers. */ 4115 4116 { "ac", AC }, 4117 { "bc", BC }, 4118 { "cal", CAL }, 4119 { "crp", CRP }, 4120 { "drp", DRP }, 4121 { "pcsr", PCSR }, 4122 { "psr", PSR }, 4123 { "scc", SCC }, 4124 { "val", VAL }, 4125 { "bad0", BAD0 }, 4126 { "bad1", BAD1 }, 4127 { "bad2", BAD2 }, 4128 { "bad3", BAD3 }, 4129 { "bad4", BAD4 }, 4130 { "bad5", BAD5 }, 4131 { "bad6", BAD6 }, 4132 { "bad7", BAD7 }, 4133 { "bac0", BAC0 }, 4134 { "bac1", BAC1 }, 4135 { "bac2", BAC2 }, 4136 { "bac3", BAC3 }, 4137 { "bac4", BAC4 }, 4138 { "bac5", BAC5 }, 4139 { "bac6", BAC6 }, 4140 { "bac7", BAC7 }, 4141 4142 { "ic", IC }, 4143 { "dc", DC }, 4144 { "nc", NC }, 4145 4146 { "tt0", TT0 }, 4147 { "tt1", TT1 }, 4148 /* 68ec030 versions of same. */ 4149 { "ac0", TT0 }, 4150 { "ac1", TT1 }, 4151 /* 68ec030 access control unit, identical to 030 MMU status reg. */ 4152 { "acusr", PSR }, 4153 4154 /* Suppressed data and address registers. */ 4155 { "zd0", ZDATA0 }, 4156 { "zd1", ZDATA1 }, 4157 { "zd2", ZDATA2 }, 4158 { "zd3", ZDATA3 }, 4159 { "zd4", ZDATA4 }, 4160 { "zd5", ZDATA5 }, 4161 { "zd6", ZDATA6 }, 4162 { "zd7", ZDATA7 }, 4163 { "za0", ZADDR0 }, 4164 { "za1", ZADDR1 }, 4165 { "za2", ZADDR2 }, 4166 { "za3", ZADDR3 }, 4167 { "za4", ZADDR4 }, 4168 { "za5", ZADDR5 }, 4169 { "za6", ZADDR6 }, 4170 { "za7", ZADDR7 }, 4171 4172 /* Upper and lower data and address registers, used by macw and msacw. */ 4173 { "d0l", DATA0L }, 4174 { "d1l", DATA1L }, 4175 { "d2l", DATA2L }, 4176 { "d3l", DATA3L }, 4177 { "d4l", DATA4L }, 4178 { "d5l", DATA5L }, 4179 { "d6l", DATA6L }, 4180 { "d7l", DATA7L }, 4181 4182 { "a0l", ADDR0L }, 4183 { "a1l", ADDR1L }, 4184 { "a2l", ADDR2L }, 4185 { "a3l", ADDR3L }, 4186 { "a4l", ADDR4L }, 4187 { "a5l", ADDR5L }, 4188 { "a6l", ADDR6L }, 4189 { "a7l", ADDR7L }, 4190 4191 { "d0u", DATA0U }, 4192 { "d1u", DATA1U }, 4193 { "d2u", DATA2U }, 4194 { "d3u", DATA3U }, 4195 { "d4u", DATA4U }, 4196 { "d5u", DATA5U }, 4197 { "d6u", DATA6U }, 4198 { "d7u", DATA7U }, 4199 4200 { "a0u", ADDR0U }, 4201 { "a1u", ADDR1U }, 4202 { "a2u", ADDR2U }, 4203 { "a3u", ADDR3U }, 4204 { "a4u", ADDR4U }, 4205 { "a5u", ADDR5U }, 4206 { "a6u", ADDR6U }, 4207 { "a7u", ADDR7U }, 4208 4209 { 0, 0 } 4210}; 4211 4212static void 4213init_regtable (void) 4214{ 4215 int i; 4216 for (i = 0; init_table[i].name; i++) 4217 insert_reg (init_table[i].name, init_table[i].number); 4218} 4219 4220void 4221md_assemble (char *str) 4222{ 4223 const char *er; 4224 short *fromP; 4225 char *toP = NULL; 4226 int m, n = 0; 4227 char *to_beg_P; 4228 int shorts_this_frag; 4229 fixS *fixP; 4230 4231 if (!selected_cpu && !selected_arch) 4232 { 4233 /* We've not selected an architecture yet. Set the default 4234 now. We do this lazily so that an initial .cpu or .arch directive 4235 can specify. */ 4236 if (!m68k_set_cpu (TARGET_CPU, 1, 1)) 4237 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); 4238 } 4239 if (!initialized) 4240 m68k_init_arch (); 4241 4242 /* In MRI mode, the instruction and operands are separated by a 4243 space. Anything following the operands is a comment. The label 4244 has already been removed. */ 4245 if (flag_mri) 4246 { 4247 char *s; 4248 int fields = 0; 4249 int infield = 0; 4250 int inquote = 0; 4251 4252 for (s = str; *s != '\0'; s++) 4253 { 4254 if ((*s == ' ' || *s == '\t') && ! inquote) 4255 { 4256 if (infield) 4257 { 4258 ++fields; 4259 if (fields >= 2) 4260 { 4261 *s = '\0'; 4262 break; 4263 } 4264 infield = 0; 4265 } 4266 } 4267 else 4268 { 4269 if (! infield) 4270 infield = 1; 4271 if (*s == '\'') 4272 inquote = ! inquote; 4273 } 4274 } 4275 } 4276 4277 memset (&the_ins, '\0', sizeof (the_ins)); 4278 m68k_ip (str); 4279 er = the_ins.error; 4280 if (!er) 4281 { 4282 for (n = 0; n < the_ins.numargs; n++) 4283 if (the_ins.operands[n].error) 4284 { 4285 er = the_ins.operands[n].error; 4286 break; 4287 } 4288 } 4289 if (er) 4290 { 4291 as_bad (_("%s -- statement `%s' ignored"), er, str); 4292 return; 4293 } 4294 4295 /* If there is a current label, record that it marks an instruction. */ 4296 if (current_label != NULL) 4297 { 4298 current_label->text = 1; 4299 current_label = NULL; 4300 } 4301 4302 /* Tie dwarf2 debug info to the address at the start of the insn. */ 4303 dwarf2_emit_insn (0); 4304 4305 if (the_ins.nfrag == 0) 4306 { 4307 /* No frag hacking involved; just put it out. */ 4308 toP = frag_more (2 * the_ins.numo); 4309 fromP = &the_ins.opcode[0]; 4310 for (m = the_ins.numo; m; --m) 4311 { 4312 md_number_to_chars (toP, (long) (*fromP), 2); 4313 toP += 2; 4314 fromP++; 4315 } 4316 /* Put out symbol-dependent info. */ 4317 for (m = 0; m < the_ins.nrel; m++) 4318 { 4319 switch (the_ins.reloc[m].wid) 4320 { 4321 case 'B': 4322 n = 1; 4323 break; 4324 case 'b': 4325 n = 1; 4326 break; 4327 case '3': 4328 n = 1; 4329 break; 4330 case 'w': 4331 case 'W': 4332 n = 2; 4333 break; 4334 case 'l': 4335 n = 4; 4336 break; 4337 default: 4338 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"), 4339 the_ins.reloc[m].wid); 4340 } 4341 4342 fixP = fix_new_exp (frag_now, 4343 ((toP - frag_now->fr_literal) 4344 - the_ins.numo * 2 + the_ins.reloc[m].n), 4345 n, 4346 &the_ins.reloc[m].exp, 4347 the_ins.reloc[m].pcrel, 4348 get_reloc_code (n, the_ins.reloc[m].pcrel, 4349 the_ins.reloc[m].pic_reloc)); 4350 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4351 if (the_ins.reloc[m].wid == 'B') 4352 fixP->fx_signed = 1; 4353 } 4354 return; 4355 } 4356 4357 /* There's some frag hacking. */ 4358 { 4359 /* Calculate the max frag size. */ 4360 int wid; 4361 4362 wid = 2 * the_ins.fragb[0].fragoff; 4363 for (n = 1; n < the_ins.nfrag; n++) 4364 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4365 /* frag_var part. */ 4366 wid += FRAG_VAR_SIZE; 4367 /* Make sure the whole insn fits in one chunk, in particular that 4368 the var part is attached, as we access one byte before the 4369 variable frag for byte branches. */ 4370 frag_grow (wid); 4371 } 4372 4373 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) 4374 { 4375 int wid; 4376 4377 if (n == 0) 4378 wid = 2 * the_ins.fragb[n].fragoff; 4379 else 4380 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4381 toP = frag_more (wid); 4382 to_beg_P = toP; 4383 shorts_this_frag = 0; 4384 for (m = wid / 2; m; --m) 4385 { 4386 md_number_to_chars (toP, (long) (*fromP), 2); 4387 toP += 2; 4388 fromP++; 4389 shorts_this_frag++; 4390 } 4391 for (m = 0; m < the_ins.nrel; m++) 4392 { 4393 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) 4394 { 4395 the_ins.reloc[m].n -= 2 * shorts_this_frag; 4396 break; 4397 } 4398 wid = the_ins.reloc[m].wid; 4399 if (wid == 0) 4400 continue; 4401 the_ins.reloc[m].wid = 0; 4402 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4403 4404 fixP = fix_new_exp (frag_now, 4405 ((toP - frag_now->fr_literal) 4406 - the_ins.numo * 2 + the_ins.reloc[m].n), 4407 wid, 4408 &the_ins.reloc[m].exp, 4409 the_ins.reloc[m].pcrel, 4410 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4411 the_ins.reloc[m].pic_reloc)); 4412 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4413 } 4414 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, 4415 (relax_substateT) (the_ins.fragb[n].fragty), 4416 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); 4417 } 4418 gas_assert (the_ins.nfrag >= 1); 4419 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff; 4420 shorts_this_frag = 0; 4421 if (n) 4422 { 4423 toP = frag_more (n * 2); 4424 while (n--) 4425 { 4426 md_number_to_chars (toP, (long) (*fromP), 2); 4427 toP += 2; 4428 fromP++; 4429 shorts_this_frag++; 4430 } 4431 } 4432 for (m = 0; m < the_ins.nrel; m++) 4433 { 4434 int wid; 4435 4436 wid = the_ins.reloc[m].wid; 4437 if (wid == 0) 4438 continue; 4439 the_ins.reloc[m].wid = 0; 4440 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4441 4442 fixP = fix_new_exp (frag_now, 4443 ((the_ins.reloc[m].n + toP - frag_now->fr_literal) 4444 - shorts_this_frag * 2), 4445 wid, 4446 &the_ins.reloc[m].exp, 4447 the_ins.reloc[m].pcrel, 4448 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4449 the_ins.reloc[m].pic_reloc)); 4450 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4451 } 4452} 4453 4454/* Comparison function used by qsort to rank the opcode entries by name. */ 4455 4456static int 4457m68k_compare_opcode (const void * v1, const void * v2) 4458{ 4459 struct m68k_opcode * op1, * op2; 4460 int ret; 4461 4462 if (v1 == v2) 4463 return 0; 4464 4465 op1 = *(struct m68k_opcode **) v1; 4466 op2 = *(struct m68k_opcode **) v2; 4467 4468 /* Compare the two names. If different, return the comparison. 4469 If the same, return the order they are in the opcode table. */ 4470 ret = strcmp (op1->name, op2->name); 4471 if (ret) 4472 return ret; 4473 if (op1 < op2) 4474 return -1; 4475 return 1; 4476} 4477 4478void 4479md_begin (void) 4480{ 4481 const struct m68k_opcode *ins; 4482 struct m68k_incant *hack, *slak; 4483 int i; 4484 4485 /* Set up hash tables with 68000 instructions. 4486 similar to what the vax assembler does. */ 4487 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 4488 a copy of it at runtime, adding in the information we want but isn't 4489 there. I think it'd be better to have an awk script hack the table 4490 at compile time. Or even just xstr the table and use it as-is. But 4491 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 4492 names. */ 4493 4494 if (flag_mri) 4495 { 4496 flag_reg_prefix_optional = 1; 4497 m68k_abspcadd = 1; 4498 if (! m68k_rel32_from_cmdline) 4499 m68k_rel32 = 0; 4500 } 4501 4502 /* First sort the opcode table into alphabetical order to separate 4503 the order that the assembler wants to see the opcodes from the 4504 order that the disassembler wants to see them. */ 4505 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes); 4506 4507 for (i = m68k_numopcodes; i--;) 4508 m68k_sorted_opcodes[i] = m68k_opcodes + i; 4509 4510 qsort (m68k_sorted_opcodes, m68k_numopcodes, 4511 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); 4512 4513 op_hash = str_htab_create (); 4514 4515 obstack_begin (&robyn, 4000); 4516 for (i = 0; i < m68k_numopcodes; i++) 4517 { 4518 hack = slak = XOBNEW (&robyn, struct m68k_incant); 4519 do 4520 { 4521 ins = m68k_sorted_opcodes[i]; 4522 4523 /* We must enter all insns into the table, because .arch and 4524 .cpu directives can change things. */ 4525 slak->m_operands = ins->args; 4526 slak->m_arch = ins->arch; 4527 slak->m_opcode = ins->opcode; 4528 4529 /* In most cases we can determine the number of opcode words 4530 by checking the second word of the mask. Unfortunately 4531 some instructions have 2 opcode words, but no fixed bits 4532 in the second word. A leading dot in the operands 4533 string also indicates 2 opcodes. */ 4534 if (*slak->m_operands == '.') 4535 { 4536 slak->m_operands++; 4537 slak->m_codenum = 2; 4538 } 4539 else if (ins->match & 0xffffL) 4540 slak->m_codenum = 2; 4541 else 4542 slak->m_codenum = 1; 4543 slak->m_opnum = strlen (slak->m_operands) / 2; 4544 4545 if (i + 1 != m68k_numopcodes 4546 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) 4547 { 4548 slak->m_next = XOBNEW (&robyn, struct m68k_incant); 4549 i++; 4550 } 4551 else 4552 slak->m_next = 0; 4553 slak = slak->m_next; 4554 } 4555 while (slak); 4556 4557 if (str_hash_insert (op_hash, ins->name, hack, 0) != NULL) 4558 as_fatal (_("duplicate %s"), ins->name); 4559 } 4560 4561 for (i = 0; i < m68k_numaliases; i++) 4562 { 4563 const char *name = m68k_opcode_aliases[i].primary; 4564 const char *alias = m68k_opcode_aliases[i].alias; 4565 void *val = (void *) str_hash_find (op_hash, name); 4566 4567 if (!val) 4568 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4569 if (str_hash_insert (op_hash, alias, val, 0) != NULL) 4570 as_fatal (_("duplicate %s"), alias); 4571 } 4572 4573 /* In MRI mode, all unsized branches are variable sized. Normally, 4574 they are word sized. */ 4575 if (flag_mri) 4576 { 4577 static struct m68k_opcode_alias mri_aliases[] = 4578 { 4579 { "bhi", "jhi", }, 4580 { "bls", "jls", }, 4581 { "bcc", "jcc", }, 4582 { "bcs", "jcs", }, 4583 { "bne", "jne", }, 4584 { "beq", "jeq", }, 4585 { "bvc", "jvc", }, 4586 { "bvs", "jvs", }, 4587 { "bpl", "jpl", }, 4588 { "bmi", "jmi", }, 4589 { "bge", "jge", }, 4590 { "blt", "jlt", }, 4591 { "bgt", "jgt", }, 4592 { "ble", "jle", }, 4593 { "bra", "jra", }, 4594 { "bsr", "jbsr", }, 4595 }; 4596 4597 for (i = 0; 4598 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); 4599 i++) 4600 { 4601 const char *name = mri_aliases[i].primary; 4602 const char *alias = mri_aliases[i].alias; 4603 void *val = (void *) str_hash_find (op_hash, name); 4604 4605 if (!val) 4606 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4607 str_hash_insert (op_hash, alias, val, 1); 4608 } 4609 } 4610 4611 for (i = 0; i < (int) sizeof (notend_table); i++) 4612 { 4613 notend_table[i] = 0; 4614 alt_notend_table[i] = 0; 4615 } 4616 4617 notend_table[','] = 1; 4618 notend_table['{'] = 1; 4619 notend_table['}'] = 1; 4620 alt_notend_table['a'] = 1; 4621 alt_notend_table['A'] = 1; 4622 alt_notend_table['d'] = 1; 4623 alt_notend_table['D'] = 1; 4624 alt_notend_table['#'] = 1; 4625 alt_notend_table['&'] = 1; 4626 alt_notend_table['f'] = 1; 4627 alt_notend_table['F'] = 1; 4628#ifdef REGISTER_PREFIX 4629 alt_notend_table[REGISTER_PREFIX] = 1; 4630#endif 4631 4632 /* We need to put '(' in alt_notend_table to handle 4633 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ 4634 alt_notend_table['('] = 1; 4635 4636 /* We need to put '@' in alt_notend_table to handle 4637 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ 4638 alt_notend_table['@'] = 1; 4639 4640 /* We need to put digits in alt_notend_table to handle 4641 bfextu %d0{24:1},%d0 */ 4642 alt_notend_table['0'] = 1; 4643 alt_notend_table['1'] = 1; 4644 alt_notend_table['2'] = 1; 4645 alt_notend_table['3'] = 1; 4646 alt_notend_table['4'] = 1; 4647 alt_notend_table['5'] = 1; 4648 alt_notend_table['6'] = 1; 4649 alt_notend_table['7'] = 1; 4650 alt_notend_table['8'] = 1; 4651 alt_notend_table['9'] = 1; 4652 4653#ifndef MIT_SYNTAX_ONLY 4654 /* Insert pseudo ops, these have to go into the opcode table since 4655 gas expects pseudo ops to start with a dot. */ 4656 { 4657 int n = 0; 4658 4659 while (mote_pseudo_table[n].poc_name) 4660 { 4661 hack = XOBNEW (&robyn, struct m68k_incant); 4662 str_hash_insert (op_hash, 4663 mote_pseudo_table[n].poc_name, hack, 0); 4664 hack->m_operands = 0; 4665 hack->m_opnum = n; 4666 n++; 4667 } 4668 } 4669#endif 4670 4671 init_regtable (); 4672 4673 record_alignment (text_section, 2); 4674 record_alignment (data_section, 2); 4675 record_alignment (bss_section, 2); 4676} 4677 4678 4679/* This is called when a label is defined. */ 4680 4681void 4682m68k_frob_label (symbolS *sym) 4683{ 4684 struct m68k_tc_sy *n; 4685 4686 n = symbol_get_tc (sym); 4687 n->file = as_where (&n->line); 4688 n->text = 0; 4689 current_label = n; 4690 4691 dwarf2_emit_label (sym); 4692} 4693 4694/* This is called when a value that is not an instruction is emitted. */ 4695 4696void 4697m68k_flush_pending_output (void) 4698{ 4699 current_label = NULL; 4700} 4701 4702/* This is called at the end of the assembly, when the final value of 4703 the label is known. We warn if this is a text symbol aligned at an 4704 odd location. */ 4705 4706void 4707m68k_frob_symbol (symbolS *sym) 4708{ 4709 if (S_GET_SEGMENT (sym) == reg_section 4710 && (int) S_GET_VALUE (sym) < 0) 4711 { 4712 S_SET_SEGMENT (sym, absolute_section); 4713 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); 4714 } 4715 else if ((S_GET_VALUE (sym) & 1) != 0) 4716 { 4717 struct m68k_tc_sy *l; 4718 l = symbol_get_tc (sym); 4719 4720 if (l->text) 4721 as_warn_where (l->file, l->line, 4722 _("text label `%s' aligned to odd boundary"), 4723 S_GET_NAME (sym)); 4724 } 4725} 4726 4727/* This is called if we go in or out of MRI mode because of the .mri 4728 pseudo-op. */ 4729 4730void 4731m68k_mri_mode_change (int on) 4732{ 4733 if (on) 4734 { 4735 if (! flag_reg_prefix_optional) 4736 { 4737 flag_reg_prefix_optional = 1; 4738#ifdef REGISTER_PREFIX 4739 init_regtable (); 4740#endif 4741 } 4742 m68k_abspcadd = 1; 4743 if (! m68k_rel32_from_cmdline) 4744 m68k_rel32 = 0; 4745 } 4746 else 4747 { 4748 if (! reg_prefix_optional_seen) 4749 { 4750#ifdef REGISTER_PREFIX_OPTIONAL 4751 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 4752#else 4753 flag_reg_prefix_optional = 0; 4754#endif 4755#ifdef REGISTER_PREFIX 4756 init_regtable (); 4757#endif 4758 } 4759 m68k_abspcadd = 0; 4760 if (! m68k_rel32_from_cmdline) 4761 m68k_rel32 = 1; 4762 } 4763} 4764 4765const char * 4766md_atof (int type, char *litP, int *sizeP) 4767{ 4768 return ieee_md_atof (type, litP, sizeP, true); 4769} 4770 4771void 4772md_number_to_chars (char *buf, valueT val, int n) 4773{ 4774 number_to_chars_bigendian (buf, val, n); 4775} 4776 4777void 4778md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4779{ 4780 offsetT val = *valP; 4781 addressT upper_limit; 4782 offsetT lower_limit; 4783 4784 /* This is unnecessary but it convinces the native rs6000 compiler 4785 to generate the code we want. */ 4786 char *buf = fixP->fx_frag->fr_literal; 4787 buf += fixP->fx_where; 4788 /* End ibm compiler workaround. */ 4789 4790 val = SEXT (val); 4791 4792 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 4793 fixP->fx_done = 1; 4794 4795 if (fixP->fx_addsy) 4796 { 4797 memset (buf, 0, fixP->fx_size); 4798 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4799 4800 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4801 && !S_IS_DEFINED (fixP->fx_addsy) 4802 && !S_IS_WEAK (fixP->fx_addsy)) 4803 S_SET_WEAK (fixP->fx_addsy); 4804 4805 switch (fixP->fx_r_type) 4806 { 4807 case BFD_RELOC_68K_TLS_GD32: 4808 case BFD_RELOC_68K_TLS_GD16: 4809 case BFD_RELOC_68K_TLS_GD8: 4810 case BFD_RELOC_68K_TLS_LDM32: 4811 case BFD_RELOC_68K_TLS_LDM16: 4812 case BFD_RELOC_68K_TLS_LDM8: 4813 case BFD_RELOC_68K_TLS_LDO32: 4814 case BFD_RELOC_68K_TLS_LDO16: 4815 case BFD_RELOC_68K_TLS_LDO8: 4816 case BFD_RELOC_68K_TLS_IE32: 4817 case BFD_RELOC_68K_TLS_IE16: 4818 case BFD_RELOC_68K_TLS_IE8: 4819 case BFD_RELOC_68K_TLS_LE32: 4820 case BFD_RELOC_68K_TLS_LE16: 4821 case BFD_RELOC_68K_TLS_LE8: 4822 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4823 break; 4824 4825 default: 4826 break; 4827 } 4828 4829 return; 4830 } 4831 4832 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4833 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4834 return; 4835 4836 switch (fixP->fx_size) 4837 { 4838 /* The cast to offsetT below are necessary to make code 4839 correct for machines where ints are smaller than offsetT. */ 4840 case 1: 4841 *buf++ = val; 4842 upper_limit = 0x7f; 4843 lower_limit = - (offsetT) 0x80; 4844 break; 4845 case 2: 4846 *buf++ = (val >> 8); 4847 *buf++ = val; 4848 upper_limit = 0x7fff; 4849 lower_limit = - (offsetT) 0x8000; 4850 break; 4851 case 4: 4852 *buf++ = (val >> 24); 4853 *buf++ = (val >> 16); 4854 *buf++ = (val >> 8); 4855 *buf++ = val; 4856 upper_limit = 0x7fffffff; 4857 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ 4858 break; 4859 default: 4860 BAD_CASE (fixP->fx_size); 4861 } 4862 4863 /* Fix up a negative reloc. */ 4864 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) 4865 { 4866 fixP->fx_addsy = fixP->fx_subsy; 4867 fixP->fx_subsy = NULL; 4868 fixP->fx_tcbit = 1; 4869 } 4870 4871 /* For non-pc-relative values, it's conceivable we might get something 4872 like "0xff" for a byte field. So extend the upper part of the range 4873 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", 4874 so that we can do any range checking at all. */ 4875 if (! fixP->fx_pcrel && ! fixP->fx_signed) 4876 upper_limit = upper_limit * 2 + 1; 4877 4878 if ((addressT) val > upper_limit 4879 && (val > 0 || val < lower_limit)) 4880 as_bad_where (fixP->fx_file, fixP->fx_line, 4881 _("value %ld out of range"), (long)val); 4882 4883 /* A one byte PC-relative reloc means a short branch. We can't use 4884 a short branch with a value of 0 or -1, because those indicate 4885 different opcodes (branches with longer offsets). fixup_segment 4886 in write.c may have clobbered fx_pcrel, so we need to examine the 4887 reloc type. */ 4888 if ((fixP->fx_pcrel 4889 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 4890 && fixP->fx_size == 1 4891 && (fixP->fx_addsy == NULL 4892 || S_IS_DEFINED (fixP->fx_addsy)) 4893 && (val == 0 || val == -1)) 4894 as_bad_where (fixP->fx_file, fixP->fx_line, 4895 _("invalid byte branch offset")); 4896} 4897 4898/* *fragP has been relaxed to its final size, and now needs to have 4899 the bytes inside it modified to conform to the new size There is UGLY 4900 MAGIC here. .. 4901 */ 4902static void 4903md_convert_frag_1 (fragS *fragP) 4904{ 4905 long disp; 4906 fixS *fixP = NULL; 4907 4908 /* Address in object code of the displacement. */ 4909 int object_address = fragP->fr_fix + fragP->fr_address; 4910 4911 /* Address in gas core of the place to store the displacement. */ 4912 /* This convinces the native rs6000 compiler to generate the code we 4913 want. */ 4914 char *buffer_address = fragP->fr_literal; 4915 buffer_address += fragP->fr_fix; 4916 /* End ibm compiler workaround. */ 4917 4918 /* The displacement of the address, from current location. */ 4919 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; 4920 disp = (disp + fragP->fr_offset) - object_address; 4921 4922 switch (fragP->fr_subtype) 4923 { 4924 case TAB (BRANCHBWL, BYTE): 4925 case TAB (BRABSJUNC, BYTE): 4926 case TAB (BRABSJCOND, BYTE): 4927 case TAB (BRANCHBW, BYTE): 4928 case TAB (BRANCHBWPL, BYTE): 4929 know (issbyte (disp)); 4930 if (disp == 0) 4931 as_bad_where (fragP->fr_file, fragP->fr_line, 4932 _("short branch with zero offset: use :w")); 4933 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 4934 fragP->fr_offset, 1, RELAX_RELOC_PC8); 4935 fixP->fx_pcrel_adjust = -1; 4936 break; 4937 case TAB (BRANCHBWL, SHORT): 4938 case TAB (BRABSJUNC, SHORT): 4939 case TAB (BRABSJCOND, SHORT): 4940 case TAB (BRANCHBW, SHORT): 4941 case TAB (BRANCHBWPL, SHORT): 4942 fragP->fr_opcode[1] = 0x00; 4943 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4944 fragP->fr_offset, 1, RELAX_RELOC_PC16); 4945 fragP->fr_fix += 2; 4946 break; 4947 case TAB (BRANCHBWL, LONG): 4948 fragP->fr_opcode[1] = (char) 0xFF; 4949 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4950 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4951 fragP->fr_fix += 4; 4952 break; 4953 case TAB (BRANCHBWPL, LONG): 4954 /* Here we are converting an unconditional branch into a pair of 4955 conditional branches, in order to get the range. */ 4956 fragP->fr_opcode[0] = 0x66; /* bne */ 4957 fragP->fr_opcode[1] = 0xFF; 4958 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4959 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4960 fixP->fx_file = fragP->fr_file; 4961 fixP->fx_line = fragP->fr_line; 4962 fragP->fr_fix += 4; /* Skip first offset */ 4963 buffer_address += 4; 4964 *buffer_address++ = 0x67; /* beq */ 4965 *buffer_address++ = 0xff; 4966 fragP->fr_fix += 2; /* Skip second branch opcode */ 4967 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4968 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4969 fragP->fr_fix += 4; 4970 break; 4971 case TAB (BRABSJUNC, LONG): 4972 if (fragP->fr_opcode[0] == 0x61) /* jbsr */ 4973 { 4974 if (flag_keep_pcrel) 4975 as_bad_where (fragP->fr_file, fragP->fr_line, 4976 _("Conversion of PC relative BSR to absolute JSR")); 4977 fragP->fr_opcode[0] = 0x4E; 4978 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ 4979 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4980 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 4981 fragP->fr_fix += 4; 4982 } 4983 else if (fragP->fr_opcode[0] == 0x60) /* jbra */ 4984 { 4985 if (flag_keep_pcrel) 4986 as_bad_where (fragP->fr_file, fragP->fr_line, 4987 _("Conversion of PC relative branch to absolute jump")); 4988 fragP->fr_opcode[0] = 0x4E; 4989 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ 4990 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4991 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 4992 fragP->fr_fix += 4; 4993 } 4994 else 4995 { 4996 /* This cannot happen, because jbsr and jbra are the only two 4997 unconditional branches. */ 4998 abort (); 4999 } 5000 break; 5001 case TAB (BRABSJCOND, LONG): 5002 if (flag_keep_pcrel) 5003 as_bad_where (fragP->fr_file, fragP->fr_line, 5004 _("Conversion of PC relative conditional branch to absolute jump")); 5005 5006 /* Only Bcc 68000 instructions can come here 5007 Change bcc into b!cc/jmp absl long. */ 5008 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ 5009 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ 5010 5011 /* JF: these used to be fr_opcode[2,3], but they may be in a 5012 different frag, in which case referring to them is a no-no. 5013 Only fr_opcode[0,1] are guaranteed to work. */ 5014 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ 5015 *buffer_address++ = (char) 0xf9; 5016 fragP->fr_fix += 2; /* Account for jmp instruction. */ 5017 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5018 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5019 fragP->fr_fix += 4; 5020 break; 5021 case TAB (FBRANCH, SHORT): 5022 know ((fragP->fr_opcode[1] & 0x40) == 0); 5023 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5024 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5025 fragP->fr_fix += 2; 5026 break; 5027 case TAB (FBRANCH, LONG): 5028 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ 5029 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5030 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5031 fragP->fr_fix += 4; 5032 break; 5033 case TAB (DBCCLBR, SHORT): 5034 case TAB (DBCCABSJ, SHORT): 5035 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5036 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5037 fragP->fr_fix += 2; 5038 break; 5039 case TAB (DBCCLBR, LONG): 5040 /* Only DBcc instructions can come here. 5041 Change dbcc into dbcc/bral. 5042 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5043 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5044 *buffer_address++ = 0x04; 5045 *buffer_address++ = 0x60; /* Put in bra pc+6. */ 5046 *buffer_address++ = 0x06; 5047 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ 5048 *buffer_address++ = (char) 0xff; 5049 5050 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5051 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5052 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5053 fragP->fr_fix += 4; 5054 break; 5055 case TAB (DBCCABSJ, LONG): 5056 /* Only DBcc instructions can come here. 5057 Change dbcc into dbcc/jmp. 5058 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5059 if (flag_keep_pcrel) 5060 as_bad_where (fragP->fr_file, fragP->fr_line, 5061 _("Conversion of PC relative conditional branch to absolute jump")); 5062 5063 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5064 *buffer_address++ = 0x04; 5065 *buffer_address++ = 0x60; /* Put in bra pc + 6. */ 5066 *buffer_address++ = 0x06; 5067 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ 5068 *buffer_address++ = (char) 0xf9; 5069 5070 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5071 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5072 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5073 fragP->fr_fix += 4; 5074 break; 5075 case TAB (PCREL1632, SHORT): 5076 fragP->fr_opcode[1] &= ~0x3F; 5077 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ 5078 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5079 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5080 fragP->fr_fix += 2; 5081 break; 5082 case TAB (PCREL1632, LONG): 5083 /* Already set to mode 7.3; this indicates: PC indirect with 5084 suppressed index, 32-bit displacement. */ 5085 *buffer_address++ = 0x01; 5086 *buffer_address++ = 0x70; 5087 fragP->fr_fix += 2; 5088 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5089 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5090 fixP->fx_pcrel_adjust = 2; 5091 fragP->fr_fix += 4; 5092 break; 5093 case TAB (PCINDEX, BYTE): 5094 gas_assert (fragP->fr_fix >= 2); 5095 buffer_address[-2] &= ~1; 5096 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5097 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5098 fixP->fx_pcrel_adjust = 1; 5099 break; 5100 case TAB (PCINDEX, SHORT): 5101 gas_assert (fragP->fr_fix >= 2); 5102 buffer_address[-2] |= 0x1; 5103 buffer_address[-1] = 0x20; 5104 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5105 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5106 fixP->fx_pcrel_adjust = 2; 5107 fragP->fr_fix += 2; 5108 break; 5109 case TAB (PCINDEX, LONG): 5110 gas_assert (fragP->fr_fix >= 2); 5111 buffer_address[-2] |= 0x1; 5112 buffer_address[-1] = 0x30; 5113 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5114 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5115 fixP->fx_pcrel_adjust = 2; 5116 fragP->fr_fix += 4; 5117 break; 5118 case TAB (ABSTOPCREL, SHORT): 5119 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5120 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5121 fragP->fr_fix += 2; 5122 break; 5123 case TAB (ABSTOPCREL, LONG): 5124 if (flag_keep_pcrel) 5125 as_bad_where (fragP->fr_file, fragP->fr_line, 5126 _("Conversion of PC relative displacement to absolute")); 5127 /* The thing to do here is force it to ABSOLUTE LONG, since 5128 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ 5129 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) 5130 abort (); 5131 fragP->fr_opcode[1] &= ~0x3F; 5132 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 5133 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5134 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5135 fragP->fr_fix += 4; 5136 break; 5137 } 5138 if (fixP) 5139 { 5140 fixP->fx_file = fragP->fr_file; 5141 fixP->fx_line = fragP->fr_line; 5142 } 5143} 5144 5145void 5146md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 5147 segT sec ATTRIBUTE_UNUSED, 5148 fragS *fragP) 5149{ 5150 md_convert_frag_1 (fragP); 5151} 5152 5153/* Force truly undefined symbols to their maximum size, and generally set up 5154 the frag list to be relaxed 5155 */ 5156int 5157md_estimate_size_before_relax (fragS *fragP, segT segment) 5158{ 5159 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ 5160 switch (fragP->fr_subtype) 5161 { 5162 case TAB (BRANCHBWL, SZ_UNDEF): 5163 case TAB (BRANCHBWPL, SZ_UNDEF): 5164 case TAB (BRABSJUNC, SZ_UNDEF): 5165 case TAB (BRABSJCOND, SZ_UNDEF): 5166 { 5167 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5168 && relaxable_symbol (fragP->fr_symbol)) 5169 { 5170 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5171 } 5172 else if (flag_short_refs) 5173 { 5174 /* Symbol is undefined and we want short ref. */ 5175 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5176 } 5177 else 5178 { 5179 /* Symbol is still undefined. Make it LONG. */ 5180 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5181 } 5182 break; 5183 } 5184 5185 case TAB (BRANCHBW, SZ_UNDEF): 5186 { 5187 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5188 && relaxable_symbol (fragP->fr_symbol)) 5189 { 5190 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5191 } 5192 else 5193 { 5194 /* Symbol is undefined and we don't have long branches. */ 5195 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5196 } 5197 break; 5198 } 5199 5200 case TAB (FBRANCH, SZ_UNDEF): 5201 case TAB (DBCCLBR, SZ_UNDEF): 5202 case TAB (DBCCABSJ, SZ_UNDEF): 5203 case TAB (PCREL1632, SZ_UNDEF): 5204 { 5205 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5206 && relaxable_symbol (fragP->fr_symbol)) 5207 || flag_short_refs) 5208 { 5209 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5210 } 5211 else 5212 { 5213 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5214 } 5215 break; 5216 } 5217 5218 case TAB (PCINDEX, SZ_UNDEF): 5219 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5220 && relaxable_symbol (fragP->fr_symbol))) 5221 { 5222 fragP->fr_subtype = TAB (PCINDEX, BYTE); 5223 } 5224 else 5225 { 5226 fragP->fr_subtype = TAB (PCINDEX, LONG); 5227 } 5228 break; 5229 5230 case TAB (ABSTOPCREL, SZ_UNDEF): 5231 { 5232 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5233 && relaxable_symbol (fragP->fr_symbol))) 5234 { 5235 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); 5236 } 5237 else 5238 { 5239 fragP->fr_subtype = TAB (ABSTOPCREL, LONG); 5240 } 5241 break; 5242 } 5243 5244 default: 5245 break; 5246 } 5247 5248 /* Now that SZ_UNDEF are taken care of, check others. */ 5249 switch (fragP->fr_subtype) 5250 { 5251 case TAB (BRANCHBWL, BYTE): 5252 case TAB (BRABSJUNC, BYTE): 5253 case TAB (BRABSJCOND, BYTE): 5254 case TAB (BRANCHBW, BYTE): 5255 /* We can't do a short jump to the next instruction, so in that 5256 case we force word mode. If the symbol is at the start of a 5257 frag, and it is the next frag with any data in it (usually 5258 this is just the next frag, but assembler listings may 5259 introduce empty frags), we must use word mode. */ 5260 if (fragP->fr_symbol) 5261 { 5262 fragS *sym_frag; 5263 5264 sym_frag = symbol_get_frag (fragP->fr_symbol); 5265 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) 5266 { 5267 fragS *l; 5268 5269 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) 5270 if (l->fr_fix != 0) 5271 break; 5272 if (l == sym_frag) 5273 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5274 } 5275 } 5276 break; 5277 default: 5278 break; 5279 } 5280 return md_relax_table[fragP->fr_subtype].rlx_length; 5281} 5282 5283#ifndef WORKING_DOT_WORD 5284int md_short_jump_size = 4; 5285int md_long_jump_size = 6; 5286 5287void 5288md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, 5289 fragS *frag ATTRIBUTE_UNUSED, 5290 symbolS *to_symbol ATTRIBUTE_UNUSED) 5291{ 5292 valueT offset; 5293 5294 offset = to_addr - (from_addr + 2); 5295 5296 md_number_to_chars (ptr, (valueT) 0x6000, 2); 5297 md_number_to_chars (ptr + 2, (valueT) offset, 2); 5298} 5299 5300void 5301md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, 5302 fragS *frag, symbolS *to_symbol) 5303{ 5304 valueT offset; 5305 5306 if (!HAVE_LONG_BRANCH (current_architecture)) 5307 { 5308 if (flag_keep_pcrel) 5309 as_fatal (_("Tried to convert PC relative branch to absolute jump")); 5310 offset = to_addr - S_GET_VALUE (to_symbol); 5311 md_number_to_chars (ptr, (valueT) 0x4EF9, 2); 5312 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5313 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, 5314 0, NO_RELOC); 5315 } 5316 else 5317 { 5318 offset = to_addr - (from_addr + 2); 5319 md_number_to_chars (ptr, (valueT) 0x60ff, 2); 5320 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5321 } 5322} 5323 5324#endif 5325 5326/* Different values of OK tell what it's OK to return. Things that 5327 aren't OK are an error (what a shock, no?) 5328 5329 0: Everything is OK 5330 10: Absolute 1:8 only 5331 20: Absolute 0:7 only 5332 30: absolute 0:15 only 5333 40: Absolute 0:31 only 5334 50: absolute 0:127 only 5335 55: absolute -64:63 only 5336 60: absolute -128:127 only 5337 65: absolute 0:511 only 5338 70: absolute 0:4095 only 5339 80: absolute -1, 1:7 only 5340 90: No bignums. */ 5341 5342static int 5343get_num (struct m68k_exp *exp, int ok) 5344{ 5345 if (exp->exp.X_op == O_absent) 5346 { 5347 /* Do the same thing the VAX asm does. */ 5348 op (exp) = O_constant; 5349 adds (exp) = 0; 5350 subs (exp) = 0; 5351 offs (exp) = 0; 5352 if (ok == 10) 5353 { 5354 as_warn (_("expression out of range: defaulting to 1")); 5355 offs (exp) = 1; 5356 } 5357 } 5358 else if (exp->exp.X_op == O_constant) 5359 { 5360 switch (ok) 5361 { 5362 case 10: 5363 if ((valueT) TRUNC (offs (exp)) - 1 > 7) 5364 { 5365 as_warn (_("expression out of range: defaulting to 1")); 5366 offs (exp) = 1; 5367 } 5368 break; 5369 case 20: 5370 if ((valueT) TRUNC (offs (exp)) > 7) 5371 goto outrange; 5372 break; 5373 case 30: 5374 if ((valueT) TRUNC (offs (exp)) > 15) 5375 goto outrange; 5376 break; 5377 case 40: 5378 if ((valueT) TRUNC (offs (exp)) > 32) 5379 goto outrange; 5380 break; 5381 case 50: 5382 if ((valueT) TRUNC (offs (exp)) > 127) 5383 goto outrange; 5384 break; 5385 case 55: 5386 if ((valueT) SEXT (offs (exp)) + 64 > 127) 5387 goto outrange; 5388 break; 5389 case 60: 5390 if ((valueT) SEXT (offs (exp)) + 128 > 255) 5391 goto outrange; 5392 break; 5393 case 65: 5394 if ((valueT) TRUNC (offs (exp)) > 511) 5395 goto outrange; 5396 break; 5397 case 70: 5398 if ((valueT) TRUNC (offs (exp)) > 4095) 5399 { 5400 outrange: 5401 as_warn (_("expression out of range: defaulting to 0")); 5402 offs (exp) = 0; 5403 } 5404 break; 5405 case 80: 5406 if ((valueT) TRUNC (offs (exp)) != 0xffffffff 5407 && (valueT) TRUNC (offs (exp)) - 1 > 6) 5408 { 5409 as_warn (_("expression out of range: defaulting to 1")); 5410 offs (exp) = 1; 5411 } 5412 break; 5413 default: 5414 break; 5415 } 5416 } 5417 else if (exp->exp.X_op == O_big) 5418 { 5419 if (offs (exp) <= 0 /* flonum. */ 5420 && (ok == 90 /* no bignums */ 5421 || (ok > 10 /* Small-int ranges including 0 ok. */ 5422 /* If we have a flonum zero, a zero integer should 5423 do as well (e.g., in moveq). */ 5424 && generic_floating_point_number.exponent == 0 5425 && generic_floating_point_number.low[0] == 0))) 5426 { 5427 /* HACK! Turn it into a long. */ 5428 LITTLENUM_TYPE words[6]; 5429 5430 gen_to_words (words, 2, 8L); /* These numbers are magic! */ 5431 op (exp) = O_constant; 5432 adds (exp) = 0; 5433 subs (exp) = 0; 5434 offs (exp) = words[1] | (words[0] << 16); 5435 } 5436 else if (ok != 0) 5437 { 5438 op (exp) = O_constant; 5439 adds (exp) = 0; 5440 subs (exp) = 0; 5441 offs (exp) = (ok == 10) ? 1 : 0; 5442 as_warn (_("Can't deal with expression; defaulting to %ld"), 5443 (long) offs (exp)); 5444 } 5445 } 5446 else 5447 { 5448 if (ok >= 10 && ok <= 80) 5449 { 5450 op (exp) = O_constant; 5451 adds (exp) = 0; 5452 subs (exp) = 0; 5453 offs (exp) = (ok == 10) ? 1 : 0; 5454 as_warn (_("Can't deal with expression; defaulting to %ld"), 5455 (long) offs (exp)); 5456 } 5457 } 5458 5459 if (exp->size != SIZE_UNSPEC) 5460 { 5461 switch (exp->size) 5462 { 5463 case SIZE_UNSPEC: 5464 case SIZE_LONG: 5465 break; 5466 case SIZE_BYTE: 5467 if (!isbyte (offs (exp))) 5468 as_warn (_("expression doesn't fit in BYTE")); 5469 break; 5470 case SIZE_WORD: 5471 if (!isword (offs (exp))) 5472 as_warn (_("expression doesn't fit in WORD")); 5473 break; 5474 } 5475 } 5476 5477 return offs (exp); 5478} 5479 5480/* These are the back-ends for the various machine dependent pseudo-ops. */ 5481 5482static void 5483s_data1 (int ignore ATTRIBUTE_UNUSED) 5484{ 5485 subseg_set (data_section, 1); 5486 demand_empty_rest_of_line (); 5487} 5488 5489static void 5490s_data2 (int ignore ATTRIBUTE_UNUSED) 5491{ 5492 subseg_set (data_section, 2); 5493 demand_empty_rest_of_line (); 5494} 5495 5496static void 5497s_bss (int ignore ATTRIBUTE_UNUSED) 5498{ 5499 /* We don't support putting frags in the BSS segment, we fake it 5500 by marking in_bss, then looking at s_skip for clues. */ 5501 5502 subseg_set (bss_section, 0); 5503 demand_empty_rest_of_line (); 5504} 5505 5506static void 5507s_even (int ignore ATTRIBUTE_UNUSED) 5508{ 5509 int temp; 5510 long temp_fill; 5511 5512 temp = 1; /* JF should be 2? */ 5513 temp_fill = get_absolute_expression (); 5514 if (!need_pass_2) /* Never make frag if expect extra pass. */ 5515 frag_align (temp, (int) temp_fill, 0); 5516 demand_empty_rest_of_line (); 5517 record_alignment (now_seg, temp); 5518} 5519 5520static void 5521s_proc (int ignore ATTRIBUTE_UNUSED) 5522{ 5523 demand_empty_rest_of_line (); 5524} 5525 5526/* Pseudo-ops handled for MRI compatibility. */ 5527 5528/* This function returns non-zero if the argument is a conditional 5529 pseudo-op. This is called when checking whether a pending 5530 alignment is needed. */ 5531 5532int 5533m68k_conditional_pseudoop (const pseudo_typeS *pop) 5534{ 5535 return (pop->poc_handler == s_mri_if 5536 || pop->poc_handler == s_mri_else); 5537} 5538 5539/* Handle an MRI style chip specification. */ 5540 5541static void 5542mri_chip (void) 5543{ 5544 char *s; 5545 char c; 5546 int i; 5547 5548 s = input_line_pointer; 5549 /* We can't use get_symbol_name since the processor names are not proper 5550 symbols. */ 5551 while (is_part_of_name (c = *input_line_pointer++)) 5552 ; 5553 *--input_line_pointer = 0; 5554 for (i = 0; m68k_cpus[i].name; i++) 5555 if (strcasecmp (s, m68k_cpus[i].name) == 0) 5556 break; 5557 if (!m68k_cpus[i].name) 5558 { 5559 as_bad (_("%s: unrecognized processor name"), s); 5560 *input_line_pointer = c; 5561 ignore_rest_of_line (); 5562 return; 5563 } 5564 *input_line_pointer = c; 5565 5566 if (*input_line_pointer == '/') 5567 current_architecture = 0; 5568 else 5569 current_architecture &= m68881 | m68851; 5570 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); 5571 control_regs = m68k_cpus[i].control_regs; 5572 5573 while (*input_line_pointer == '/') 5574 { 5575 ++input_line_pointer; 5576 s = input_line_pointer; 5577 /* We can't use get_symbol_name since the processor names are not 5578 proper symbols. */ 5579 while (is_part_of_name (c = *input_line_pointer++)) 5580 ; 5581 *--input_line_pointer = 0; 5582 if (strcmp (s, "68881") == 0) 5583 current_architecture |= m68881; 5584 else if (strcmp (s, "68851") == 0) 5585 current_architecture |= m68851; 5586 *input_line_pointer = c; 5587 } 5588} 5589 5590/* The MRI CHIP pseudo-op. */ 5591 5592static void 5593s_chip (int ignore ATTRIBUTE_UNUSED) 5594{ 5595 char *stop = NULL; 5596 char stopc; 5597 5598 if (flag_mri) 5599 stop = mri_comment_field (&stopc); 5600 mri_chip (); 5601 if (flag_mri) 5602 mri_comment_end (stop, stopc); 5603 demand_empty_rest_of_line (); 5604} 5605 5606/* The MRI FOPT pseudo-op. */ 5607 5608static void 5609s_fopt (int ignore ATTRIBUTE_UNUSED) 5610{ 5611 SKIP_WHITESPACE (); 5612 5613 if (strncasecmp (input_line_pointer, "ID=", 3) == 0) 5614 { 5615 int temp; 5616 5617 input_line_pointer += 3; 5618 temp = get_absolute_expression (); 5619 if (temp < 0 || temp > 7) 5620 as_bad (_("bad coprocessor id")); 5621 else 5622 m68k_float_copnum = COP0 + temp; 5623 } 5624 else 5625 { 5626 as_bad (_("unrecognized fopt option")); 5627 ignore_rest_of_line (); 5628 return; 5629 } 5630 5631 demand_empty_rest_of_line (); 5632} 5633 5634/* The structure used to handle the MRI OPT pseudo-op. */ 5635 5636struct opt_action 5637{ 5638 /* The name of the option. */ 5639 const char *name; 5640 5641 /* If this is not NULL, just call this function. The first argument 5642 is the ARG field of this structure, the second argument is 5643 whether the option was negated. */ 5644 void (*pfn) (int arg, int on); 5645 5646 /* If this is not NULL, and the PFN field is NULL, set the variable 5647 this points to. Set it to the ARG field if the option was not 5648 negated, and the NOTARG field otherwise. */ 5649 int *pvar; 5650 5651 /* The value to pass to PFN or to assign to *PVAR. */ 5652 int arg; 5653 5654 /* The value to assign to *PVAR if the option is negated. If PFN is 5655 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then 5656 the option may not be negated. */ 5657 int notarg; 5658}; 5659 5660/* The table used to handle the MRI OPT pseudo-op. */ 5661 5662static void skip_to_comma (int, int); 5663static void opt_nest (int, int); 5664static void opt_chip (int, int); 5665static void opt_list (int, int); 5666static void opt_list_symbols (int, int); 5667 5668static const struct opt_action opt_table[] = 5669{ 5670 { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, 5671 5672 /* We do relaxing, so there is little use for these options. */ 5673 { "b", 0, 0, 0, 0 }, 5674 { "brs", 0, 0, 0, 0 }, 5675 { "brb", 0, 0, 0, 0 }, 5676 { "brl", 0, 0, 0, 0 }, 5677 { "brw", 0, 0, 0, 0 }, 5678 5679 { "c", 0, 0, 0, 0 }, 5680 { "cex", 0, 0, 0, 0 }, 5681 { "case", 0, &symbols_case_sensitive, 1, 0 }, 5682 { "cl", 0, 0, 0, 0 }, 5683 { "cre", 0, 0, 0, 0 }, 5684 { "d", 0, &flag_keep_locals, 1, 0 }, 5685 { "e", 0, 0, 0, 0 }, 5686 { "f", 0, &flag_short_refs, 1, 0 }, 5687 { "frs", 0, &flag_short_refs, 1, 0 }, 5688 { "frl", 0, &flag_short_refs, 0, 1 }, 5689 { "g", 0, 0, 0, 0 }, 5690 { "i", 0, 0, 0, 0 }, 5691 { "m", 0, 0, 0, 0 }, 5692 { "mex", 0, 0, 0, 0 }, 5693 { "mc", 0, 0, 0, 0 }, 5694 { "md", 0, 0, 0, 0 }, 5695 { "nest", opt_nest, 0, 0, 0 }, 5696 { "next", skip_to_comma, 0, 0, 0 }, 5697 { "o", 0, 0, 0, 0 }, 5698 { "old", 0, 0, 0, 0 }, 5699 { "op", skip_to_comma, 0, 0, 0 }, 5700 { "pco", 0, 0, 0, 0 }, 5701 { "p", opt_chip, 0, 0, 0 }, 5702 { "pcr", 0, 0, 0, 0 }, 5703 { "pcs", 0, 0, 0, 0 }, 5704 { "r", 0, 0, 0, 0 }, 5705 { "quick", 0, &m68k_quick, 1, 0 }, 5706 { "rel32", 0, &m68k_rel32, 1, 0 }, 5707 { "s", opt_list, 0, 0, 0 }, 5708 { "t", opt_list_symbols, 0, 0, 0 }, 5709 { "w", 0, &flag_no_warnings, 0, 1 }, 5710 { "x", 0, 0, 0, 0 } 5711}; 5712 5713#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) 5714 5715/* The MRI OPT pseudo-op. */ 5716 5717static void 5718s_opt (int ignore ATTRIBUTE_UNUSED) 5719{ 5720 do 5721 { 5722 int t; 5723 char *s; 5724 char c; 5725 int i; 5726 const struct opt_action *o; 5727 5728 SKIP_WHITESPACE (); 5729 5730 t = 1; 5731 if (*input_line_pointer == '-') 5732 { 5733 ++input_line_pointer; 5734 t = 0; 5735 } 5736 else if (strncasecmp (input_line_pointer, "NO", 2) == 0) 5737 { 5738 input_line_pointer += 2; 5739 t = 0; 5740 } 5741 5742 c = get_symbol_name (&s); 5743 5744 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) 5745 { 5746 if (strcasecmp (s, o->name) == 0) 5747 { 5748 if (o->pfn) 5749 { 5750 /* Restore input_line_pointer now in case the option 5751 takes arguments. */ 5752 (void) restore_line_pointer (c); 5753 (*o->pfn) (o->arg, t); 5754 } 5755 else if (o->pvar != NULL) 5756 { 5757 if (! t && o->arg == o->notarg) 5758 as_bad (_("option `%s' may not be negated"), s); 5759 restore_line_pointer (c); 5760 *o->pvar = t ? o->arg : o->notarg; 5761 } 5762 else 5763 *input_line_pointer = c; 5764 break; 5765 } 5766 } 5767 if (i >= OPTCOUNT) 5768 { 5769 as_bad (_("option `%s' not recognized"), s); 5770 restore_line_pointer (c); 5771 } 5772 } 5773 while (*input_line_pointer++ == ','); 5774 5775 /* Move back to terminating character. */ 5776 --input_line_pointer; 5777 demand_empty_rest_of_line (); 5778} 5779 5780/* Skip ahead to a comma. This is used for OPT options which we do 5781 not support and which take arguments. */ 5782 5783static void 5784skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5785{ 5786 while (*input_line_pointer != ',' 5787 && ! is_end_of_line[(unsigned char) *input_line_pointer]) 5788 ++input_line_pointer; 5789} 5790 5791/* Handle the OPT NEST=depth option. */ 5792 5793static void 5794opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5795{ 5796 if (*input_line_pointer != '=') 5797 { 5798 as_bad (_("bad format of OPT NEST=depth")); 5799 return; 5800 } 5801 5802 ++input_line_pointer; 5803 max_macro_nest = get_absolute_expression (); 5804} 5805 5806/* Handle the OPT P=chip option. */ 5807 5808static void 5809opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5810{ 5811 if (*input_line_pointer != '=') 5812 { 5813 /* This is just OPT P, which we do not support. */ 5814 return; 5815 } 5816 5817 ++input_line_pointer; 5818 mri_chip (); 5819} 5820 5821/* Handle the OPT S option. */ 5822 5823static void 5824opt_list (int arg ATTRIBUTE_UNUSED, int on) 5825{ 5826 listing_list (on); 5827} 5828 5829/* Handle the OPT T option. */ 5830 5831static void 5832opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) 5833{ 5834 if (on) 5835 listing |= LISTING_SYMBOLS; 5836 else 5837 listing &= ~LISTING_SYMBOLS; 5838} 5839 5840/* Handle the MRI REG pseudo-op. */ 5841 5842static void 5843s_reg (int ignore ATTRIBUTE_UNUSED) 5844{ 5845 char *s; 5846 int c; 5847 struct m68k_op rop; 5848 int mask; 5849 char *stop = NULL; 5850 char stopc; 5851 5852 if (line_label == NULL) 5853 { 5854 as_bad (_("missing label")); 5855 ignore_rest_of_line (); 5856 return; 5857 } 5858 5859 if (flag_mri) 5860 stop = mri_comment_field (&stopc); 5861 5862 SKIP_WHITESPACE (); 5863 5864 s = input_line_pointer; 5865 while (ISALNUM (*input_line_pointer) 5866#ifdef REGISTER_PREFIX 5867 || *input_line_pointer == REGISTER_PREFIX 5868#endif 5869 || *input_line_pointer == '/' 5870 || *input_line_pointer == '-') 5871 ++input_line_pointer; 5872 c = *input_line_pointer; 5873 *input_line_pointer = '\0'; 5874 5875 if (m68k_ip_op (s, &rop) != 0) 5876 { 5877 if (rop.error == NULL) 5878 as_bad (_("bad register list")); 5879 else 5880 as_bad (_("bad register list: %s"), rop.error); 5881 *input_line_pointer = c; 5882 ignore_rest_of_line (); 5883 return; 5884 } 5885 5886 *input_line_pointer = c; 5887 5888 if (rop.mode == REGLST) 5889 mask = rop.mask; 5890 else if (rop.mode == DREG) 5891 mask = 1 << (rop.reg - DATA0); 5892 else if (rop.mode == AREG) 5893 mask = 1 << (rop.reg - ADDR0 + 8); 5894 else if (rop.mode == FPREG) 5895 mask = 1 << (rop.reg - FP0 + 16); 5896 else if (rop.mode == CONTROL 5897 && rop.reg == FPI) 5898 mask = 1 << 24; 5899 else if (rop.mode == CONTROL 5900 && rop.reg == FPS) 5901 mask = 1 << 25; 5902 else if (rop.mode == CONTROL 5903 && rop.reg == FPC) 5904 mask = 1 << 26; 5905 else 5906 { 5907 as_bad (_("bad register list")); 5908 ignore_rest_of_line (); 5909 return; 5910 } 5911 5912 S_SET_SEGMENT (line_label, reg_section); 5913 S_SET_VALUE (line_label, ~mask); 5914 symbol_set_frag (line_label, &zero_address_frag); 5915 5916 if (flag_mri) 5917 mri_comment_end (stop, stopc); 5918 5919 demand_empty_rest_of_line (); 5920} 5921 5922/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ 5923 5924struct save_opts 5925{ 5926 struct save_opts *next; 5927 int abspcadd; 5928 int symbols_case_sensitive; 5929 int keep_locals; 5930 int short_refs; 5931 int architecture; 5932 const enum m68k_register *control_regs; 5933 int quick; 5934 int rel32; 5935 int listing; 5936 int no_warnings; 5937 /* FIXME: We don't save OPT S. */ 5938}; 5939 5940/* This variable holds the stack of saved options. */ 5941 5942static struct save_opts *save_stack; 5943 5944/* The MRI SAVE pseudo-op. */ 5945 5946static void 5947s_save (int ignore ATTRIBUTE_UNUSED) 5948{ 5949 struct save_opts *s; 5950 5951 s = XNEW (struct save_opts); 5952 s->abspcadd = m68k_abspcadd; 5953 s->symbols_case_sensitive = symbols_case_sensitive; 5954 s->keep_locals = flag_keep_locals; 5955 s->short_refs = flag_short_refs; 5956 s->architecture = current_architecture; 5957 s->control_regs = control_regs; 5958 s->quick = m68k_quick; 5959 s->rel32 = m68k_rel32; 5960 s->listing = listing; 5961 s->no_warnings = flag_no_warnings; 5962 5963 s->next = save_stack; 5964 save_stack = s; 5965 5966 demand_empty_rest_of_line (); 5967} 5968 5969/* The MRI RESTORE pseudo-op. */ 5970 5971static void 5972s_restore (int ignore ATTRIBUTE_UNUSED) 5973{ 5974 struct save_opts *s; 5975 5976 if (save_stack == NULL) 5977 { 5978 as_bad (_("restore without save")); 5979 ignore_rest_of_line (); 5980 return; 5981 } 5982 5983 s = save_stack; 5984 save_stack = s->next; 5985 5986 m68k_abspcadd = s->abspcadd; 5987 symbols_case_sensitive = s->symbols_case_sensitive; 5988 flag_keep_locals = s->keep_locals; 5989 flag_short_refs = s->short_refs; 5990 current_architecture = s->architecture; 5991 control_regs = s->control_regs; 5992 m68k_quick = s->quick; 5993 m68k_rel32 = s->rel32; 5994 listing = s->listing; 5995 flag_no_warnings = s->no_warnings; 5996 5997 free (s); 5998 5999 demand_empty_rest_of_line (); 6000} 6001 6002/* Types of MRI structured control directives. */ 6003 6004enum mri_control_type 6005{ 6006 mri_for, 6007 mri_if, 6008 mri_repeat, 6009 mri_while 6010}; 6011 6012/* This structure is used to stack the MRI structured control 6013 directives. */ 6014 6015struct mri_control_info 6016{ 6017 /* The directive within which this one is enclosed. */ 6018 struct mri_control_info *outer; 6019 6020 /* The type of directive. */ 6021 enum mri_control_type type; 6022 6023 /* Whether an ELSE has been in an IF. */ 6024 int else_seen; 6025 6026 /* The add or sub statement at the end of a FOR. */ 6027 char *incr; 6028 6029 /* The label of the top of a FOR or REPEAT loop. */ 6030 char *top; 6031 6032 /* The label to jump to for the next iteration, or the else 6033 expression of a conditional. */ 6034 char *next; 6035 6036 /* The label to jump to to break out of the loop, or the label past 6037 the end of a conditional. */ 6038 char *bottom; 6039}; 6040 6041/* The stack of MRI structured control directives. */ 6042 6043static struct mri_control_info *mri_control_stack; 6044 6045/* The current MRI structured control directive index number, used to 6046 generate label names. */ 6047 6048static int mri_control_index; 6049 6050/* Assemble an instruction for an MRI structured control directive. */ 6051 6052static void 6053mri_assemble (char *str) 6054{ 6055 char *s; 6056 6057 /* md_assemble expects the opcode to be in lower case. */ 6058 for (s = str; *s != ' ' && *s != '\0'; s++) 6059 *s = TOLOWER (*s); 6060 6061 md_assemble (str); 6062} 6063 6064/* Generate a new MRI label structured control directive label name. */ 6065 6066static char * 6067mri_control_label (void) 6068{ 6069 char *n; 6070 6071 n = XNEWVEC (char, 20); 6072 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); 6073 ++mri_control_index; 6074 return n; 6075} 6076 6077/* Create a new MRI structured control directive. */ 6078 6079static struct mri_control_info * 6080push_mri_control (enum mri_control_type type) 6081{ 6082 struct mri_control_info *n; 6083 6084 n = XNEW (struct mri_control_info); 6085 6086 n->type = type; 6087 n->else_seen = 0; 6088 if (type == mri_if || type == mri_while) 6089 n->top = NULL; 6090 else 6091 n->top = mri_control_label (); 6092 n->next = mri_control_label (); 6093 n->bottom = mri_control_label (); 6094 6095 n->outer = mri_control_stack; 6096 mri_control_stack = n; 6097 6098 return n; 6099} 6100 6101/* Pop off the stack of MRI structured control directives. */ 6102 6103static void 6104pop_mri_control (void) 6105{ 6106 struct mri_control_info *n; 6107 6108 n = mri_control_stack; 6109 mri_control_stack = n->outer; 6110 free (n->top); 6111 free (n->next); 6112 free (n->bottom); 6113 free (n); 6114} 6115 6116/* Recognize a condition code in an MRI structured control expression. */ 6117 6118static int 6119parse_mri_condition (int *pcc) 6120{ 6121 char c1, c2; 6122 6123 know (*input_line_pointer == '<'); 6124 6125 ++input_line_pointer; 6126 c1 = *input_line_pointer++; 6127 c2 = *input_line_pointer++; 6128 6129 if (*input_line_pointer != '>') 6130 { 6131 as_bad (_("syntax error in structured control directive")); 6132 return 0; 6133 } 6134 6135 ++input_line_pointer; 6136 SKIP_WHITESPACE (); 6137 6138 c1 = TOLOWER (c1); 6139 c2 = TOLOWER (c2); 6140 6141 *pcc = (c1 << 8) | c2; 6142 6143 return 1; 6144} 6145 6146/* Parse a single operand in an MRI structured control expression. */ 6147 6148static int 6149parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, 6150 char **rightstart, char **rightstop) 6151{ 6152 char *s; 6153 6154 SKIP_WHITESPACE (); 6155 6156 *pcc = -1; 6157 *leftstart = NULL; 6158 *leftstop = NULL; 6159 *rightstart = NULL; 6160 *rightstop = NULL; 6161 6162 if (*input_line_pointer == '<') 6163 { 6164 /* It's just a condition code. */ 6165 return parse_mri_condition (pcc); 6166 } 6167 6168 /* Look ahead for the condition code. */ 6169 for (s = input_line_pointer; *s != '\0'; ++s) 6170 { 6171 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') 6172 break; 6173 } 6174 if (*s == '\0') 6175 { 6176 as_bad (_("missing condition code in structured control directive")); 6177 return 0; 6178 } 6179 6180 *leftstart = input_line_pointer; 6181 *leftstop = s; 6182 if (*leftstop > *leftstart 6183 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) 6184 --*leftstop; 6185 6186 input_line_pointer = s; 6187 if (! parse_mri_condition (pcc)) 6188 return 0; 6189 6190 /* Look ahead for AND or OR or end of line. */ 6191 for (s = input_line_pointer; *s != '\0'; ++s) 6192 { 6193 /* We must make sure we don't misinterpret AND/OR at the end of labels! 6194 if d0 <eq> #FOOAND and d1 <ne> #BAROR then 6195 ^^^ ^^ */ 6196 if ((s == input_line_pointer 6197 || *(s-1) == ' ' 6198 || *(s-1) == '\t') 6199 && ((strncasecmp (s, "AND", 3) == 0 6200 && (s[3] == '.' || ! is_part_of_name (s[3]))) 6201 || (strncasecmp (s, "OR", 2) == 0 6202 && (s[2] == '.' || ! is_part_of_name (s[2]))))) 6203 break; 6204 } 6205 6206 *rightstart = input_line_pointer; 6207 *rightstop = s; 6208 if (*rightstop > *rightstart 6209 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) 6210 --*rightstop; 6211 6212 input_line_pointer = s; 6213 6214 return 1; 6215} 6216 6217#define MCC(b1, b2) (((b1) << 8) | (b2)) 6218 6219/* Swap the sense of a condition. This changes the condition so that 6220 it generates the same result when the operands are swapped. */ 6221 6222static int 6223swap_mri_condition (int cc) 6224{ 6225 switch (cc) 6226 { 6227 case MCC ('h', 'i'): return MCC ('c', 's'); 6228 case MCC ('l', 's'): return MCC ('c', 'c'); 6229 /* <HS> is an alias for <CC>. */ 6230 case MCC ('h', 's'): 6231 case MCC ('c', 'c'): return MCC ('l', 's'); 6232 /* <LO> is an alias for <CS>. */ 6233 case MCC ('l', 'o'): 6234 case MCC ('c', 's'): return MCC ('h', 'i'); 6235 case MCC ('p', 'l'): return MCC ('m', 'i'); 6236 case MCC ('m', 'i'): return MCC ('p', 'l'); 6237 case MCC ('g', 'e'): return MCC ('l', 'e'); 6238 case MCC ('l', 't'): return MCC ('g', 't'); 6239 case MCC ('g', 't'): return MCC ('l', 't'); 6240 case MCC ('l', 'e'): return MCC ('g', 'e'); 6241 /* Issue a warning for conditions we can not swap. */ 6242 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ 6243 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ 6244 case MCC ('v', 'c'): 6245 case MCC ('v', 's'): 6246 default : 6247 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), 6248 (char) (cc >> 8), (char) (cc)); 6249 break; 6250 } 6251 return cc; 6252} 6253 6254/* Reverse the sense of a condition. */ 6255 6256static int 6257reverse_mri_condition (int cc) 6258{ 6259 switch (cc) 6260 { 6261 case MCC ('h', 'i'): return MCC ('l', 's'); 6262 case MCC ('l', 's'): return MCC ('h', 'i'); 6263 /* <HS> is an alias for <CC> */ 6264 case MCC ('h', 's'): return MCC ('l', 'o'); 6265 case MCC ('c', 'c'): return MCC ('c', 's'); 6266 /* <LO> is an alias for <CS> */ 6267 case MCC ('l', 'o'): return MCC ('h', 's'); 6268 case MCC ('c', 's'): return MCC ('c', 'c'); 6269 case MCC ('n', 'e'): return MCC ('e', 'q'); 6270 case MCC ('e', 'q'): return MCC ('n', 'e'); 6271 case MCC ('v', 'c'): return MCC ('v', 's'); 6272 case MCC ('v', 's'): return MCC ('v', 'c'); 6273 case MCC ('p', 'l'): return MCC ('m', 'i'); 6274 case MCC ('m', 'i'): return MCC ('p', 'l'); 6275 case MCC ('g', 'e'): return MCC ('l', 't'); 6276 case MCC ('l', 't'): return MCC ('g', 'e'); 6277 case MCC ('g', 't'): return MCC ('l', 'e'); 6278 case MCC ('l', 'e'): return MCC ('g', 't'); 6279 } 6280 return cc; 6281} 6282 6283/* Build an MRI structured control expression. This generates test 6284 and branch instructions. It goes to TRUELAB if the condition is 6285 true, and to FALSELAB if the condition is false. Exactly one of 6286 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL 6287 is the size qualifier for the expression. EXTENT is the size to 6288 use for the branch. */ 6289 6290static void 6291build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, 6292 char *rightstart, char *rightstop, 6293 const char *truelab, const char *falselab, 6294 int extent) 6295{ 6296 char *buf; 6297 char *s; 6298 6299 if (leftstart != NULL) 6300 { 6301 struct m68k_op leftop, rightop; 6302 char c; 6303 6304 /* Swap the compare operands, if necessary, to produce a legal 6305 m68k compare instruction. Comparing a register operand with 6306 a non-register operand requires the register to be on the 6307 right (cmp, cmpa). Comparing an immediate value with 6308 anything requires the immediate value to be on the left 6309 (cmpi). */ 6310 6311 c = *leftstop; 6312 *leftstop = '\0'; 6313 (void) m68k_ip_op (leftstart, &leftop); 6314 *leftstop = c; 6315 6316 c = *rightstop; 6317 *rightstop = '\0'; 6318 (void) m68k_ip_op (rightstart, &rightop); 6319 *rightstop = c; 6320 6321 if (rightop.mode == IMMED 6322 || ((leftop.mode == DREG || leftop.mode == AREG) 6323 && (rightop.mode != DREG && rightop.mode != AREG))) 6324 { 6325 char *temp; 6326 6327 /* Correct conditional handling: 6328 if #1 <lt> d0 then ;means if (1 < d0) 6329 ... 6330 endi 6331 6332 should assemble to: 6333 6334 cmp #1,d0 if we do *not* swap the operands 6335 bgt true we need the swapped condition! 6336 ble false 6337 true: 6338 ... 6339 false: 6340 */ 6341 temp = leftstart; 6342 leftstart = rightstart; 6343 rightstart = temp; 6344 temp = leftstop; 6345 leftstop = rightstop; 6346 rightstop = temp; 6347 } 6348 else 6349 { 6350 cc = swap_mri_condition (cc); 6351 } 6352 } 6353 6354 if (truelab == NULL) 6355 { 6356 cc = reverse_mri_condition (cc); 6357 truelab = falselab; 6358 } 6359 6360 if (leftstart != NULL) 6361 { 6362 buf = XNEWVEC (char, (20 6363 + (leftstop - leftstart) 6364 + (rightstop - rightstart))); 6365 s = buf; 6366 *s++ = 'c'; 6367 *s++ = 'm'; 6368 *s++ = 'p'; 6369 if (qual != '\0') 6370 *s++ = TOLOWER (qual); 6371 *s++ = ' '; 6372 memcpy (s, leftstart, leftstop - leftstart); 6373 s += leftstop - leftstart; 6374 *s++ = ','; 6375 memcpy (s, rightstart, rightstop - rightstart); 6376 s += rightstop - rightstart; 6377 *s = '\0'; 6378 mri_assemble (buf); 6379 free (buf); 6380 } 6381 6382 buf = XNEWVEC (char, 20 + strlen (truelab)); 6383 s = buf; 6384 *s++ = 'b'; 6385 *s++ = cc >> 8; 6386 *s++ = cc & 0xff; 6387 if (extent != '\0') 6388 *s++ = TOLOWER (extent); 6389 *s++ = ' '; 6390 strcpy (s, truelab); 6391 mri_assemble (buf); 6392 free (buf); 6393} 6394 6395/* Parse an MRI structured control expression. This generates test 6396 and branch instructions. STOP is where the expression ends. It 6397 goes to TRUELAB if the condition is true, and to FALSELAB if the 6398 condition is false. Exactly one of TRUELAB and FALSELAB will be 6399 NULL, meaning to fall through. QUAL is the size qualifier for the 6400 expression. EXTENT is the size to use for the branch. */ 6401 6402static void 6403parse_mri_control_expression (char *stop, int qual, const char *truelab, 6404 const char *falselab, int extent) 6405{ 6406 int c; 6407 int cc; 6408 char *leftstart; 6409 char *leftstop; 6410 char *rightstart; 6411 char *rightstop; 6412 6413 c = *stop; 6414 *stop = '\0'; 6415 6416 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6417 &rightstart, &rightstop)) 6418 { 6419 *stop = c; 6420 return; 6421 } 6422 6423 if (strncasecmp (input_line_pointer, "AND", 3) == 0) 6424 { 6425 const char *flab; 6426 6427 if (falselab != NULL) 6428 flab = falselab; 6429 else 6430 flab = mri_control_label (); 6431 6432 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6433 rightstop, (const char *) NULL, flab, extent); 6434 6435 input_line_pointer += 3; 6436 if (*input_line_pointer != '.' 6437 || input_line_pointer[1] == '\0') 6438 qual = '\0'; 6439 else 6440 { 6441 qual = input_line_pointer[1]; 6442 input_line_pointer += 2; 6443 } 6444 6445 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6446 &rightstart, &rightstop)) 6447 { 6448 *stop = c; 6449 return; 6450 } 6451 6452 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6453 rightstop, truelab, falselab, extent); 6454 6455 if (falselab == NULL) 6456 colon (flab); 6457 } 6458 else if (strncasecmp (input_line_pointer, "OR", 2) == 0) 6459 { 6460 const char *tlab; 6461 6462 if (truelab != NULL) 6463 tlab = truelab; 6464 else 6465 tlab = mri_control_label (); 6466 6467 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6468 rightstop, tlab, (const char *) NULL, extent); 6469 6470 input_line_pointer += 2; 6471 if (*input_line_pointer != '.' 6472 || input_line_pointer[1] == '\0') 6473 qual = '\0'; 6474 else 6475 { 6476 qual = input_line_pointer[1]; 6477 input_line_pointer += 2; 6478 } 6479 6480 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6481 &rightstart, &rightstop)) 6482 { 6483 *stop = c; 6484 return; 6485 } 6486 6487 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6488 rightstop, truelab, falselab, extent); 6489 6490 if (truelab == NULL) 6491 colon (tlab); 6492 } 6493 else 6494 { 6495 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6496 rightstop, truelab, falselab, extent); 6497 } 6498 6499 *stop = c; 6500 if (input_line_pointer != stop) 6501 as_bad (_("syntax error in structured control directive")); 6502} 6503 6504/* Handle the MRI IF pseudo-op. This may be a structured control 6505 directive, or it may be a regular assembler conditional, depending 6506 on its operands. */ 6507 6508static void 6509s_mri_if (int qual) 6510{ 6511 char *s; 6512 int c; 6513 struct mri_control_info *n; 6514 6515 /* A structured control directive must end with THEN with an 6516 optional qualifier. */ 6517 s = input_line_pointer; 6518 /* We only accept '*' as introduction of comments if preceded by white space 6519 or at first column of a line (I think this can't actually happen here?) 6520 This is important when assembling: 6521 if d0 <ne> 12(a0,d0*2) then 6522 if d0 <ne> #CONST*20 then. */ 6523 while (! (is_end_of_line[(unsigned char) *s] 6524 || (flag_mri 6525 && *s == '*' 6526 && (s == input_line_pointer 6527 || *(s-1) == ' ' 6528 || *(s-1) == '\t')))) 6529 ++s; 6530 --s; 6531 while (s > input_line_pointer && (*s == ' ' || *s == '\t')) 6532 --s; 6533 6534 if (s - input_line_pointer > 1 6535 && s[-1] == '.') 6536 s -= 2; 6537 6538 if (s - input_line_pointer < 3 6539 || strncasecmp (s - 3, "THEN", 4) != 0) 6540 { 6541 if (qual != '\0') 6542 { 6543 as_bad (_("missing then")); 6544 ignore_rest_of_line (); 6545 return; 6546 } 6547 6548 /* It's a conditional. */ 6549 s_if (O_ne); 6550 return; 6551 } 6552 6553 /* Since this might be a conditional if, this pseudo-op will be 6554 called even if we are supported to be ignoring input. Double 6555 check now. Clobber *input_line_pointer so that ignore_input 6556 thinks that this is not a special pseudo-op. */ 6557 c = *input_line_pointer; 6558 *input_line_pointer = 0; 6559 if (ignore_input ()) 6560 { 6561 *input_line_pointer = c; 6562 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6563 ++input_line_pointer; 6564 demand_empty_rest_of_line (); 6565 return; 6566 } 6567 *input_line_pointer = c; 6568 6569 n = push_mri_control (mri_if); 6570 6571 parse_mri_control_expression (s - 3, qual, (const char *) NULL, 6572 n->next, s[1] == '.' ? s[2] : '\0'); 6573 6574 if (s[1] == '.') 6575 input_line_pointer = s + 3; 6576 else 6577 input_line_pointer = s + 1; 6578 6579 if (flag_mri) 6580 { 6581 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6582 ++input_line_pointer; 6583 } 6584 6585 demand_empty_rest_of_line (); 6586} 6587 6588/* Handle the MRI else pseudo-op. If we are currently doing an MRI 6589 structured IF, associate the ELSE with the IF. Otherwise, assume 6590 it is a conditional else. */ 6591 6592static void 6593s_mri_else (int qual) 6594{ 6595 int c; 6596 char *buf; 6597 char q[2]; 6598 6599 if (qual == '\0' 6600 && (mri_control_stack == NULL 6601 || mri_control_stack->type != mri_if 6602 || mri_control_stack->else_seen)) 6603 { 6604 s_else (0); 6605 return; 6606 } 6607 6608 c = *input_line_pointer; 6609 *input_line_pointer = 0; 6610 if (ignore_input ()) 6611 { 6612 *input_line_pointer = c; 6613 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6614 ++input_line_pointer; 6615 demand_empty_rest_of_line (); 6616 return; 6617 } 6618 *input_line_pointer = c; 6619 6620 if (mri_control_stack == NULL 6621 || mri_control_stack->type != mri_if 6622 || mri_control_stack->else_seen) 6623 { 6624 as_bad (_("else without matching if")); 6625 ignore_rest_of_line (); 6626 return; 6627 } 6628 6629 mri_control_stack->else_seen = 1; 6630 6631 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom)); 6632 q[0] = TOLOWER (qual); 6633 q[1] = '\0'; 6634 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); 6635 mri_assemble (buf); 6636 free (buf); 6637 6638 colon (mri_control_stack->next); 6639 6640 if (flag_mri) 6641 { 6642 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6643 ++input_line_pointer; 6644 } 6645 6646 demand_empty_rest_of_line (); 6647} 6648 6649/* Handle the MRI ENDI pseudo-op. */ 6650 6651static void 6652s_mri_endi (int ignore ATTRIBUTE_UNUSED) 6653{ 6654 if (mri_control_stack == NULL 6655 || mri_control_stack->type != mri_if) 6656 { 6657 as_bad (_("endi without matching if")); 6658 ignore_rest_of_line (); 6659 return; 6660 } 6661 6662 /* ignore_input will not return true for ENDI, so we don't need to 6663 worry about checking it again here. */ 6664 6665 if (! mri_control_stack->else_seen) 6666 colon (mri_control_stack->next); 6667 colon (mri_control_stack->bottom); 6668 6669 pop_mri_control (); 6670 6671 if (flag_mri) 6672 { 6673 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6674 ++input_line_pointer; 6675 } 6676 6677 demand_empty_rest_of_line (); 6678} 6679 6680/* Handle the MRI BREAK pseudo-op. */ 6681 6682static void 6683s_mri_break (int extent) 6684{ 6685 struct mri_control_info *n; 6686 char *buf; 6687 char ex[2]; 6688 6689 n = mri_control_stack; 6690 while (n != NULL 6691 && n->type != mri_for 6692 && n->type != mri_repeat 6693 && n->type != mri_while) 6694 n = n->outer; 6695 if (n == NULL) 6696 { 6697 as_bad (_("break outside of structured loop")); 6698 ignore_rest_of_line (); 6699 return; 6700 } 6701 6702 buf = XNEWVEC (char, 20 + strlen (n->bottom)); 6703 ex[0] = TOLOWER (extent); 6704 ex[1] = '\0'; 6705 sprintf (buf, "bra%s %s", ex, n->bottom); 6706 mri_assemble (buf); 6707 free (buf); 6708 6709 if (flag_mri) 6710 { 6711 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6712 ++input_line_pointer; 6713 } 6714 6715 demand_empty_rest_of_line (); 6716} 6717 6718/* Handle the MRI NEXT pseudo-op. */ 6719 6720static void 6721s_mri_next (int extent) 6722{ 6723 struct mri_control_info *n; 6724 char *buf; 6725 char ex[2]; 6726 6727 n = mri_control_stack; 6728 while (n != NULL 6729 && n->type != mri_for 6730 && n->type != mri_repeat 6731 && n->type != mri_while) 6732 n = n->outer; 6733 if (n == NULL) 6734 { 6735 as_bad (_("next outside of structured loop")); 6736 ignore_rest_of_line (); 6737 return; 6738 } 6739 6740 buf = XNEWVEC (char, 20 + strlen (n->next)); 6741 ex[0] = TOLOWER (extent); 6742 ex[1] = '\0'; 6743 sprintf (buf, "bra%s %s", ex, n->next); 6744 mri_assemble (buf); 6745 free (buf); 6746 6747 if (flag_mri) 6748 { 6749 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6750 ++input_line_pointer; 6751 } 6752 6753 demand_empty_rest_of_line (); 6754} 6755 6756/* Handle the MRI FOR pseudo-op. */ 6757 6758static void 6759s_mri_for (int qual) 6760{ 6761 const char *varstart, *varstop; 6762 const char *initstart, *initstop; 6763 const char *endstart, *endstop; 6764 const char *bystart, *bystop; 6765 int up; 6766 int by; 6767 int extent; 6768 struct mri_control_info *n; 6769 char *buf; 6770 char *s; 6771 char ex[2]; 6772 6773 /* The syntax is 6774 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e 6775 */ 6776 6777 SKIP_WHITESPACE (); 6778 varstart = input_line_pointer; 6779 6780 /* Look for the '='. */ 6781 while (! is_end_of_line[(unsigned char) *input_line_pointer] 6782 && *input_line_pointer != '=') 6783 ++input_line_pointer; 6784 if (*input_line_pointer != '=') 6785 { 6786 as_bad (_("missing =")); 6787 ignore_rest_of_line (); 6788 return; 6789 } 6790 6791 varstop = input_line_pointer; 6792 if (varstop > varstart 6793 && (varstop[-1] == ' ' || varstop[-1] == '\t')) 6794 --varstop; 6795 6796 ++input_line_pointer; 6797 6798 initstart = input_line_pointer; 6799 6800 /* Look for TO or DOWNTO. */ 6801 up = 1; 6802 initstop = NULL; 6803 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6804 { 6805 if (strncasecmp (input_line_pointer, "TO", 2) == 0 6806 && ! is_part_of_name (input_line_pointer[2])) 6807 { 6808 initstop = input_line_pointer; 6809 input_line_pointer += 2; 6810 break; 6811 } 6812 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 6813 && ! is_part_of_name (input_line_pointer[6])) 6814 { 6815 initstop = input_line_pointer; 6816 up = 0; 6817 input_line_pointer += 6; 6818 break; 6819 } 6820 ++input_line_pointer; 6821 } 6822 if (initstop == NULL) 6823 { 6824 as_bad (_("missing to or downto")); 6825 ignore_rest_of_line (); 6826 return; 6827 } 6828 if (initstop > initstart 6829 && (initstop[-1] == ' ' || initstop[-1] == '\t')) 6830 --initstop; 6831 6832 SKIP_WHITESPACE (); 6833 endstart = input_line_pointer; 6834 6835 /* Look for BY or DO. */ 6836 by = 0; 6837 endstop = NULL; 6838 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6839 { 6840 if (strncasecmp (input_line_pointer, "BY", 2) == 0 6841 && ! is_part_of_name (input_line_pointer[2])) 6842 { 6843 endstop = input_line_pointer; 6844 by = 1; 6845 input_line_pointer += 2; 6846 break; 6847 } 6848 if (strncasecmp (input_line_pointer, "DO", 2) == 0 6849 && (input_line_pointer[2] == '.' 6850 || ! is_part_of_name (input_line_pointer[2]))) 6851 { 6852 endstop = input_line_pointer; 6853 input_line_pointer += 2; 6854 break; 6855 } 6856 ++input_line_pointer; 6857 } 6858 if (endstop == NULL) 6859 { 6860 as_bad (_("missing do")); 6861 ignore_rest_of_line (); 6862 return; 6863 } 6864 if (endstop > endstart 6865 && (endstop[-1] == ' ' || endstop[-1] == '\t')) 6866 --endstop; 6867 6868 if (! by) 6869 { 6870 bystart = "#1"; 6871 bystop = bystart + 2; 6872 } 6873 else 6874 { 6875 SKIP_WHITESPACE (); 6876 bystart = input_line_pointer; 6877 6878 /* Look for DO. */ 6879 bystop = NULL; 6880 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6881 { 6882 if (strncasecmp (input_line_pointer, "DO", 2) == 0 6883 && (input_line_pointer[2] == '.' 6884 || ! is_part_of_name (input_line_pointer[2]))) 6885 { 6886 bystop = input_line_pointer; 6887 input_line_pointer += 2; 6888 break; 6889 } 6890 ++input_line_pointer; 6891 } 6892 if (bystop == NULL) 6893 { 6894 as_bad (_("missing do")); 6895 ignore_rest_of_line (); 6896 return; 6897 } 6898 if (bystop > bystart 6899 && (bystop[-1] == ' ' || bystop[-1] == '\t')) 6900 --bystop; 6901 } 6902 6903 if (*input_line_pointer != '.') 6904 extent = '\0'; 6905 else 6906 { 6907 extent = input_line_pointer[1]; 6908 input_line_pointer += 2; 6909 } 6910 6911 /* We have fully parsed the FOR operands. Now build the loop. */ 6912 n = push_mri_control (mri_for); 6913 6914 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart)); 6915 6916 /* Move init,var. */ 6917 s = buf; 6918 *s++ = 'm'; 6919 *s++ = 'o'; 6920 *s++ = 'v'; 6921 *s++ = 'e'; 6922 if (qual != '\0') 6923 *s++ = TOLOWER (qual); 6924 *s++ = ' '; 6925 memcpy (s, initstart, initstop - initstart); 6926 s += initstop - initstart; 6927 *s++ = ','; 6928 memcpy (s, varstart, varstop - varstart); 6929 s += varstop - varstart; 6930 *s = '\0'; 6931 mri_assemble (buf); 6932 6933 colon (n->top); 6934 6935 /* cmp end,var. */ 6936 s = buf; 6937 *s++ = 'c'; 6938 *s++ = 'm'; 6939 *s++ = 'p'; 6940 if (qual != '\0') 6941 *s++ = TOLOWER (qual); 6942 *s++ = ' '; 6943 memcpy (s, endstart, endstop - endstart); 6944 s += endstop - endstart; 6945 *s++ = ','; 6946 memcpy (s, varstart, varstop - varstart); 6947 s += varstop - varstart; 6948 *s = '\0'; 6949 mri_assemble (buf); 6950 6951 /* bcc bottom. */ 6952 ex[0] = TOLOWER (extent); 6953 ex[1] = '\0'; 6954 if (up) 6955 sprintf (buf, "blt%s %s", ex, n->bottom); 6956 else 6957 sprintf (buf, "bgt%s %s", ex, n->bottom); 6958 mri_assemble (buf); 6959 6960 /* Put together the add or sub instruction used by ENDF. */ 6961 s = buf; 6962 if (up) 6963 strcpy (s, "add"); 6964 else 6965 strcpy (s, "sub"); 6966 s += 3; 6967 if (qual != '\0') 6968 *s++ = TOLOWER (qual); 6969 *s++ = ' '; 6970 memcpy (s, bystart, bystop - bystart); 6971 s += bystop - bystart; 6972 *s++ = ','; 6973 memcpy (s, varstart, varstop - varstart); 6974 s += varstop - varstart; 6975 *s = '\0'; 6976 n->incr = buf; 6977 6978 if (flag_mri) 6979 { 6980 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6981 ++input_line_pointer; 6982 } 6983 6984 demand_empty_rest_of_line (); 6985} 6986 6987/* Handle the MRI ENDF pseudo-op. */ 6988 6989static void 6990s_mri_endf (int ignore ATTRIBUTE_UNUSED) 6991{ 6992 if (mri_control_stack == NULL 6993 || mri_control_stack->type != mri_for) 6994 { 6995 as_bad (_("endf without for")); 6996 ignore_rest_of_line (); 6997 return; 6998 } 6999 7000 colon (mri_control_stack->next); 7001 7002 mri_assemble (mri_control_stack->incr); 7003 7004 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); 7005 mri_assemble (mri_control_stack->incr); 7006 7007 free (mri_control_stack->incr); 7008 7009 colon (mri_control_stack->bottom); 7010 7011 pop_mri_control (); 7012 7013 if (flag_mri) 7014 { 7015 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7016 ++input_line_pointer; 7017 } 7018 7019 demand_empty_rest_of_line (); 7020} 7021 7022/* Handle the MRI REPEAT pseudo-op. */ 7023 7024static void 7025s_mri_repeat (int ignore ATTRIBUTE_UNUSED) 7026{ 7027 struct mri_control_info *n; 7028 7029 n = push_mri_control (mri_repeat); 7030 colon (n->top); 7031 if (flag_mri) 7032 { 7033 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7034 ++input_line_pointer; 7035 } 7036 demand_empty_rest_of_line (); 7037} 7038 7039/* Handle the MRI UNTIL pseudo-op. */ 7040 7041static void 7042s_mri_until (int qual) 7043{ 7044 char *s; 7045 7046 if (mri_control_stack == NULL 7047 || mri_control_stack->type != mri_repeat) 7048 { 7049 as_bad (_("until without repeat")); 7050 ignore_rest_of_line (); 7051 return; 7052 } 7053 7054 colon (mri_control_stack->next); 7055 7056 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) 7057 ; 7058 7059 parse_mri_control_expression (s, qual, (const char *) NULL, 7060 mri_control_stack->top, '\0'); 7061 7062 colon (mri_control_stack->bottom); 7063 7064 input_line_pointer = s; 7065 7066 pop_mri_control (); 7067 7068 if (flag_mri) 7069 { 7070 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7071 ++input_line_pointer; 7072 } 7073 7074 demand_empty_rest_of_line (); 7075} 7076 7077/* Handle the MRI WHILE pseudo-op. */ 7078 7079static void 7080s_mri_while (int qual) 7081{ 7082 char *s; 7083 7084 struct mri_control_info *n; 7085 7086 s = input_line_pointer; 7087 /* We only accept '*' as introduction of comments if preceded by white space 7088 or at first column of a line (I think this can't actually happen here?) 7089 This is important when assembling: 7090 while d0 <ne> 12(a0,d0*2) do 7091 while d0 <ne> #CONST*20 do. */ 7092 while (! (is_end_of_line[(unsigned char) *s] 7093 || (flag_mri 7094 && *s == '*' 7095 && (s == input_line_pointer 7096 || *(s-1) == ' ' 7097 || *(s-1) == '\t')))) 7098 s++; 7099 --s; 7100 while (*s == ' ' || *s == '\t') 7101 --s; 7102 if (s - input_line_pointer > 1 7103 && s[-1] == '.') 7104 s -= 2; 7105 if (s - input_line_pointer < 2 7106 || strncasecmp (s - 1, "DO", 2) != 0) 7107 { 7108 as_bad (_("missing do")); 7109 ignore_rest_of_line (); 7110 return; 7111 } 7112 7113 n = push_mri_control (mri_while); 7114 7115 colon (n->next); 7116 7117 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, 7118 s[1] == '.' ? s[2] : '\0'); 7119 7120 input_line_pointer = s + 1; 7121 if (*input_line_pointer == '.') 7122 input_line_pointer += 2; 7123 7124 if (flag_mri) 7125 { 7126 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7127 ++input_line_pointer; 7128 } 7129 7130 demand_empty_rest_of_line (); 7131} 7132 7133/* Handle the MRI ENDW pseudo-op. */ 7134 7135static void 7136s_mri_endw (int ignore ATTRIBUTE_UNUSED) 7137{ 7138 char *buf; 7139 7140 if (mri_control_stack == NULL 7141 || mri_control_stack->type != mri_while) 7142 { 7143 as_bad (_("endw without while")); 7144 ignore_rest_of_line (); 7145 return; 7146 } 7147 7148 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next)); 7149 sprintf (buf, "bra %s", mri_control_stack->next); 7150 mri_assemble (buf); 7151 free (buf); 7152 7153 colon (mri_control_stack->bottom); 7154 7155 pop_mri_control (); 7156 7157 if (flag_mri) 7158 { 7159 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7160 ++input_line_pointer; 7161 } 7162 7163 demand_empty_rest_of_line (); 7164} 7165 7166/* Parse a .cpu directive. */ 7167 7168static void 7169s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) 7170{ 7171 char saved_char; 7172 char *name; 7173 7174 if (initialized) 7175 { 7176 as_bad (_("already assembled instructions")); 7177 ignore_rest_of_line (); 7178 return; 7179 } 7180 7181 name = input_line_pointer; 7182 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 7183 input_line_pointer++; 7184 saved_char = *input_line_pointer; 7185 *input_line_pointer = 0; 7186 7187 m68k_set_cpu (name, 1, 0); 7188 7189 *input_line_pointer = saved_char; 7190 demand_empty_rest_of_line (); 7191 return; 7192} 7193 7194/* Parse a .arch directive. */ 7195 7196static void 7197s_m68k_arch (int ignored ATTRIBUTE_UNUSED) 7198{ 7199 char saved_char; 7200 char *name; 7201 7202 if (initialized) 7203 { 7204 as_bad (_("already assembled instructions")); 7205 ignore_rest_of_line (); 7206 return; 7207 } 7208 7209 name = input_line_pointer; 7210 while (*input_line_pointer && *input_line_pointer != ',' 7211 && !ISSPACE (*input_line_pointer)) 7212 input_line_pointer++; 7213 saved_char = *input_line_pointer; 7214 *input_line_pointer = 0; 7215 7216 if (m68k_set_arch (name, 1, 0)) 7217 { 7218 /* Scan extensions. */ 7219 do 7220 { 7221 *input_line_pointer++ = saved_char; 7222 if (!*input_line_pointer || ISSPACE (*input_line_pointer)) 7223 break; 7224 name = input_line_pointer; 7225 while (*input_line_pointer && *input_line_pointer != ',' 7226 && !ISSPACE (*input_line_pointer)) 7227 input_line_pointer++; 7228 saved_char = *input_line_pointer; 7229 *input_line_pointer = 0; 7230 } 7231 while (m68k_set_extension (name, 1, 0)); 7232 } 7233 7234 *input_line_pointer = saved_char; 7235 demand_empty_rest_of_line (); 7236 return; 7237} 7238 7239/* Lookup a cpu name in TABLE and return the slot found. Return NULL 7240 if none is found, the caller is responsible for emitting an error 7241 message. If ALLOW_M is non-zero, we allow an initial 'm' on the 7242 cpu name, if it begins with a '6' (possibly skipping an intervening 7243 'c'. We also allow a 'c' in the same place. if NEGATED is 7244 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if 7245 the option is indeed negated. */ 7246 7247static const struct m68k_cpu * 7248m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, 7249 int allow_m, int *negated) 7250{ 7251 /* allow negated value? */ 7252 if (negated) 7253 { 7254 *negated = 0; 7255 7256 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') 7257 { 7258 arg += 3; 7259 *negated = 1; 7260 } 7261 } 7262 7263 /* Remove 'm' or 'mc' prefix from 68k variants. */ 7264 if (allow_m) 7265 { 7266 if (arg[0] == 'm') 7267 { 7268 if (arg[1] == '6' || arg[1] == '5') 7269 arg += 1; 7270 else if (arg[1] == 'c' && arg[2] == '6') 7271 arg += 2; 7272 } 7273 } 7274 else if (arg[0] == 'c' && arg[1] == '6') 7275 arg += 1; 7276 7277 for (; table->name; table++) 7278 if (!strcmp (arg, table->name)) 7279 { 7280 if (table->alias < -1 || table->alias > 1) 7281 as_bad (_("`%s' is deprecated, use `%s'"), 7282 table->name, table[table->alias < 0 ? 1 : -1].name); 7283 return table; 7284 } 7285 return 0; 7286} 7287 7288/* Set the cpu, issuing errors if it is unrecognized. */ 7289 7290static int 7291m68k_set_cpu (char const *name, int allow_m, int silent) 7292{ 7293 const struct m68k_cpu *cpu; 7294 7295 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); 7296 7297 if (!cpu) 7298 { 7299 if (!silent) 7300 as_bad (_("cpu `%s' unrecognized"), name); 7301 return 0; 7302 } 7303 selected_cpu = cpu; 7304 return 1; 7305} 7306 7307/* Set the architecture, issuing errors if it is unrecognized. */ 7308 7309static int 7310m68k_set_arch (char const *name, int allow_m, int silent) 7311{ 7312 const struct m68k_cpu *arch; 7313 7314 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); 7315 7316 if (!arch) 7317 { 7318 if (!silent) 7319 as_bad (_("architecture `%s' unrecognized"), name); 7320 return 0; 7321 } 7322 selected_arch = arch; 7323 return 1; 7324} 7325 7326/* Set the architecture extension, issuing errors if it is 7327 unrecognized, or invalid */ 7328 7329static int 7330m68k_set_extension (char const *name, int allow_m, int silent) 7331{ 7332 int negated; 7333 const struct m68k_cpu *ext; 7334 7335 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); 7336 7337 if (!ext) 7338 { 7339 if (!silent) 7340 as_bad (_("extension `%s' unrecognized"), name); 7341 return 0; 7342 } 7343 7344 if (negated) 7345 not_current_architecture |= (ext->control_regs 7346 ? *(unsigned *)ext->control_regs: ext->arch); 7347 else 7348 current_architecture |= ext->arch; 7349 return 1; 7350} 7351 7352/* md_parse_option 7353 Invocation line includes a switch not recognized by the base assembler. 7354 */ 7355 7356const char *md_shortopts = "lSA:m:kQ:V"; 7357 7358struct option md_longopts[] = { 7359#define OPTION_PIC (OPTION_MD_BASE) 7360 {"pic", no_argument, NULL, OPTION_PIC}, 7361#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) 7362 {"register-prefix-optional", no_argument, NULL, 7363 OPTION_REGISTER_PREFIX_OPTIONAL}, 7364#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) 7365 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, 7366#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) 7367 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, 7368#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) 7369 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, 7370#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) 7371 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, 7372#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) 7373 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 7374#define OPTION_PCREL (OPTION_MD_BASE + 7) 7375 {"pcrel", no_argument, NULL, OPTION_PCREL}, 7376 {NULL, no_argument, NULL, 0} 7377}; 7378size_t md_longopts_size = sizeof (md_longopts); 7379 7380int 7381md_parse_option (int c, const char *arg) 7382{ 7383 switch (c) 7384 { 7385 case 'l': /* -l means keep external to 2 bit offset 7386 rather than 16 bit one. */ 7387 flag_short_refs = 1; 7388 break; 7389 7390 case 'S': /* -S means that jbsr's always turn into 7391 jsr's. */ 7392 flag_long_jumps = 1; 7393 break; 7394 7395 case OPTION_PCREL: /* --pcrel means never turn PC-relative 7396 branches into absolute jumps. */ 7397 flag_keep_pcrel = 1; 7398 break; 7399 7400 case OPTION_PIC: 7401 case 'k': 7402 flag_want_pic = 1; 7403 break; /* -pic, Position Independent Code. */ 7404 7405 case OPTION_REGISTER_PREFIX_OPTIONAL: 7406 flag_reg_prefix_optional = 1; 7407 reg_prefix_optional_seen = 1; 7408 break; 7409 7410 /* -V: SVR4 argument to print version ID. */ 7411 case 'V': 7412 print_version_id (); 7413 break; 7414 7415 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 7416 should be emitted or not. FIXME: Not implemented. */ 7417 case 'Q': 7418 break; 7419 7420 case OPTION_BITWISE_OR: 7421 { 7422 char *n, *t; 7423 const char *s; 7424 7425 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1); 7426 t = n; 7427 for (s = m68k_comment_chars; *s != '\0'; s++) 7428 if (*s != '|') 7429 *t++ = *s; 7430 *t = '\0'; 7431 m68k_comment_chars = n; 7432 } 7433 break; 7434 7435 case OPTION_BASE_SIZE_DEFAULT_16: 7436 m68k_index_width_default = SIZE_WORD; 7437 break; 7438 7439 case OPTION_BASE_SIZE_DEFAULT_32: 7440 m68k_index_width_default = SIZE_LONG; 7441 break; 7442 7443 case OPTION_DISP_SIZE_DEFAULT_16: 7444 m68k_rel32 = 0; 7445 m68k_rel32_from_cmdline = 1; 7446 break; 7447 7448 case OPTION_DISP_SIZE_DEFAULT_32: 7449 m68k_rel32 = 1; 7450 m68k_rel32_from_cmdline = 1; 7451 break; 7452 7453 case 'A': 7454#if WARN_DEPRECATED 7455 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", 7456 arg, arg)); 7457#endif 7458 /* Intentional fall-through. */ 7459 case 'm': 7460 if (startswith (arg, "arch=")) 7461 m68k_set_arch (arg + 5, 1, 0); 7462 else if (startswith (arg, "cpu=")) 7463 m68k_set_cpu (arg + 4, 1, 0); 7464 else if (m68k_set_extension (arg, 0, 1)) 7465 ; 7466 else if (m68k_set_arch (arg, 0, 1)) 7467 ; 7468 else if (m68k_set_cpu (arg, 0, 1)) 7469 ; 7470 else 7471 return 0; 7472 break; 7473 7474 default: 7475 return 0; 7476 } 7477 7478 return 1; 7479} 7480 7481/* Setup tables from the selected arch and/or cpu */ 7482 7483static void 7484m68k_init_arch (void) 7485{ 7486 if (not_current_architecture & current_architecture) 7487 { 7488 as_bad (_("architecture features both enabled and disabled")); 7489 not_current_architecture &= ~current_architecture; 7490 } 7491 if (selected_arch) 7492 { 7493 current_architecture |= selected_arch->arch; 7494 control_regs = selected_arch->control_regs; 7495 } 7496 else 7497 current_architecture |= selected_cpu->arch; 7498 7499 current_architecture &= ~not_current_architecture; 7500 7501 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) 7502 { 7503 /* Determine which float is really meant. */ 7504 if (current_architecture & (m68k_mask & ~m68881)) 7505 current_architecture ^= cfloat; 7506 else 7507 current_architecture ^= m68881; 7508 } 7509 7510 if (selected_cpu) 7511 { 7512 control_regs = selected_cpu->control_regs; 7513 if (current_architecture & ~selected_cpu->arch) 7514 { 7515 as_bad (_("selected processor does not have all features of selected architecture")); 7516 current_architecture 7517 = selected_cpu->arch & ~not_current_architecture; 7518 } 7519 } 7520 7521 if ((current_architecture & m68k_mask) 7522 && (current_architecture & ~m68k_mask)) 7523 { 7524 as_bad (_ ("m68k and cf features both selected")); 7525 if (current_architecture & m68k_mask) 7526 current_architecture &= m68k_mask; 7527 else 7528 current_architecture &= ~m68k_mask; 7529 } 7530 7531 /* Permit m68881 specification with all cpus; those that can't work 7532 with a coprocessor could be doing emulation. */ 7533 if (current_architecture & m68851) 7534 { 7535 if (current_architecture & m68040) 7536 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); 7537 } 7538 /* What other incompatibilities could we check for? */ 7539 7540 if (cpu_of_arch (current_architecture) < m68020 7541 || arch_coldfire_p (current_architecture)) 7542 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; 7543 7544 initialized = 1; 7545} 7546 7547void 7548md_show_usage (FILE *stream) 7549{ 7550 const char *default_cpu = TARGET_CPU; 7551 int i; 7552 7553 /* Get the canonical name for the default target CPU. */ 7554 if (*default_cpu == 'm') 7555 default_cpu++; 7556 for (i = 0; m68k_cpus[i].name; i++) 7557 { 7558 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) 7559 { 7560 while (m68k_cpus[i].alias > 0) 7561 i--; 7562 while (m68k_cpus[i].alias < 0) 7563 i++; 7564 default_cpu = m68k_cpus[i].name; 7565 } 7566 } 7567 7568 fprintf (stream, _("\ 7569-march=<arch> set architecture\n\ 7570-mcpu=<cpu> set cpu [default %s]\n\ 7571"), default_cpu); 7572 for (i = 0; m68k_extensions[i].name; i++) 7573 fprintf (stream, _("\ 7574-m[no-]%-16s enable/disable %s architecture extension\n\ 7575"), m68k_extensions[i].name, 7576 m68k_extensions[i].alias > 0 ? " ColdFire" 7577 : m68k_extensions[i].alias < 0 ? " m68k" : ""); 7578 7579 fprintf (stream, _("\ 7580-l use 1 word for refs to undefined symbols [default 2]\n\ 7581-pic, -k generate position independent code\n\ 7582-S turn jbsr into jsr\n\ 7583--pcrel never turn PC-relative branches into absolute jumps\n\ 7584--register-prefix-optional\n\ 7585 recognize register names without prefix character\n\ 7586--bitwise-or do not treat `|' as a comment character\n\ 7587--base-size-default-16 base reg without size is 16 bits\n\ 7588--base-size-default-32 base reg without size is 32 bits (default)\n\ 7589--disp-size-default-16 displacement with unknown size is 16 bits\n\ 7590--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ 7591")); 7592 7593 fprintf (stream, _("Architecture variants are: ")); 7594 for (i = 0; m68k_archs[i].name; i++) 7595 { 7596 if (i) 7597 fprintf (stream, " | "); 7598 fprintf (stream, "%s", m68k_archs[i].name); 7599 } 7600 fprintf (stream, "\n"); 7601 7602 fprintf (stream, _("Processor variants are: ")); 7603 for (i = 0; m68k_cpus[i].name; i++) 7604 { 7605 if (i) 7606 fprintf (stream, " | "); 7607 fprintf (stream, "%s", m68k_cpus[i].name); 7608 } 7609 fprintf (stream, _("\n")); 7610} 7611 7612#ifdef TEST2 7613 7614/* TEST2: Test md_assemble() */ 7615/* Warning, this routine probably doesn't work anymore. */ 7616int 7617main (void) 7618{ 7619 struct m68k_it the_ins; 7620 char buf[120]; 7621 char *cp; 7622 int n; 7623 7624 m68k_ip_begin (); 7625 for (;;) 7626 { 7627 if (!gets (buf) || !*buf) 7628 break; 7629 if (buf[0] == '|' || buf[1] == '.') 7630 continue; 7631 for (cp = buf; *cp; cp++) 7632 if (*cp == '\t') 7633 *cp = ' '; 7634 if (is_label (buf)) 7635 continue; 7636 memset (&the_ins, '\0', sizeof (the_ins)); 7637 m68k_ip (&the_ins, buf); 7638 if (the_ins.error) 7639 { 7640 printf (_("Error %s in %s\n"), the_ins.error, buf); 7641 } 7642 else 7643 { 7644 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); 7645 for (n = 0; n < the_ins.numo; n++) 7646 printf (" 0x%x", the_ins.opcode[n] & 0xffff); 7647 printf (" "); 7648 print_the_insn (&the_ins.opcode[0], stdout); 7649 (void) putchar ('\n'); 7650 } 7651 for (n = 0; n < strlen (the_ins.args) / 2; n++) 7652 { 7653 if (the_ins.operands[n].error) 7654 { 7655 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); 7656 continue; 7657 } 7658 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, 7659 the_ins.operands[n].reg); 7660 if (the_ins.operands[n].b_const) 7661 printf ("Constant: '%.*s', ", 7662 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, 7663 the_ins.operands[n].b_const); 7664 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, 7665 the_ins.operands[n].isiz, the_ins.operands[n].imul); 7666 if (the_ins.operands[n].b_iadd) 7667 printf ("Iadd: '%.*s',", 7668 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, 7669 the_ins.operands[n].b_iadd); 7670 putchar ('\n'); 7671 } 7672 } 7673 m68k_ip_end (); 7674 return 0; 7675} 7676 7677int 7678is_label (char *str) 7679{ 7680 while (*str == ' ') 7681 str++; 7682 while (*str && *str != ' ') 7683 str++; 7684 if (str[-1] == ':' || str[1] == '=') 7685 return 1; 7686 return 0; 7687} 7688 7689#endif 7690 7691/* Possible states for relaxation: 7692 7693 0 0 branch offset byte (bra, etc) 7694 0 1 word 7695 0 2 long 7696 7697 1 0 indexed offsets byte a0@(32,d4:w:1) etc 7698 1 1 word 7699 1 2 long 7700 7701 2 0 two-offset index word-word a0@(32,d4)@(45) etc 7702 2 1 word-long 7703 2 2 long-word 7704 2 3 long-long 7705 7706 */ 7707 7708/* We have no need to default values of symbols. */ 7709 7710symbolS * 7711md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 7712{ 7713 return 0; 7714} 7715 7716/* Round up a section size to the appropriate boundary. */ 7717valueT 7718md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 7719{ 7720 return size; 7721} 7722 7723/* Exactly what point is a PC-relative offset relative TO? 7724 On the 68k, it is relative to the address of the first extension 7725 word. The difference between the addresses of the offset and the 7726 first extension word is stored in fx_pcrel_adjust. */ 7727long 7728md_pcrel_from (fixS *fixP) 7729{ 7730 int adjust; 7731 7732 adjust = fixP->fx_pcrel_adjust; 7733 if (adjust == 64) 7734 adjust = -1; 7735 return fixP->fx_where + fixP->fx_frag->fr_address - adjust; 7736} 7737 7738void 7739m68k_elf_final_processing (void) 7740{ 7741 unsigned flags = 0; 7742 7743 if (arch_coldfire_fpu (current_architecture)) 7744 flags |= EF_M68K_CFV4E; 7745 /* Set file-specific flags if this is a cpu32 processor. */ 7746 if (cpu_of_arch (current_architecture) & cpu32) 7747 flags |= EF_M68K_CPU32; 7748 else if (cpu_of_arch (current_architecture) & fido_a) 7749 flags |= EF_M68K_FIDO; 7750 else if ((cpu_of_arch (current_architecture) & m68000up) 7751 && !(cpu_of_arch (current_architecture) & m68020up)) 7752 flags |= EF_M68K_M68000; 7753 7754 if (current_architecture & mcfisa_a) 7755 { 7756 static const unsigned isa_features[][2] = 7757 { 7758 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, 7759 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, 7760 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, 7761 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, 7762 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, 7763 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, 7764 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, 7765 {0,0}, 7766 }; 7767 static const unsigned mac_features[][2] = 7768 { 7769 {EF_M68K_CF_MAC, mcfmac}, 7770 {EF_M68K_CF_EMAC, mcfemac}, 7771 {0,0}, 7772 }; 7773 unsigned ix; 7774 unsigned pattern; 7775 7776 pattern = (current_architecture 7777 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); 7778 for (ix = 0; isa_features[ix][1]; ix++) 7779 { 7780 if (pattern == isa_features[ix][1]) 7781 { 7782 flags |= isa_features[ix][0]; 7783 break; 7784 } 7785 } 7786 if (!isa_features[ix][1]) 7787 { 7788 cf_bad: 7789 as_warn (_("Not a defined coldfire architecture")); 7790 } 7791 else 7792 { 7793 if (current_architecture & cfloat) 7794 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; 7795 7796 pattern = current_architecture & (mcfmac|mcfemac); 7797 if (pattern) 7798 { 7799 for (ix = 0; mac_features[ix][1]; ix++) 7800 { 7801 if (pattern == mac_features[ix][1]) 7802 { 7803 flags |= mac_features[ix][0]; 7804 break; 7805 } 7806 } 7807 if (!mac_features[ix][1]) 7808 goto cf_bad; 7809 } 7810 } 7811 } 7812 elf_elfheader (stdoutput)->e_flags |= flags; 7813} 7814 7815/* Parse @TLSLDO and return the desired relocation. */ 7816static bfd_reloc_code_real_type 7817m68k_elf_suffix (char **str_p, expressionS *exp_p) 7818{ 7819 char ident[20]; 7820 char *str = *str_p; 7821 char *str2; 7822 int ch; 7823 int len; 7824 7825 if (*str++ != '@') 7826 return BFD_RELOC_UNUSED; 7827 7828 for (ch = *str, str2 = ident; 7829 (str2 < ident + sizeof (ident) - 1 7830 && (ISALNUM (ch) || ch == '@')); 7831 ch = *++str) 7832 { 7833 *str2++ = ch; 7834 } 7835 7836 *str2 = '\0'; 7837 len = str2 - ident; 7838 7839 if (startswith (ident, "TLSLDO") 7840 && len == 6) 7841 { 7842 /* Now check for identifier@suffix+constant. */ 7843 if (*str == '-' || *str == '+') 7844 { 7845 char *orig_line = input_line_pointer; 7846 expressionS new_exp; 7847 7848 input_line_pointer = str; 7849 expression (&new_exp); 7850 if (new_exp.X_op == O_constant) 7851 { 7852 exp_p->X_add_number += new_exp.X_add_number; 7853 str = input_line_pointer; 7854 } 7855 7856 if (&input_line_pointer != str_p) 7857 input_line_pointer = orig_line; 7858 } 7859 *str_p = str; 7860 7861 return BFD_RELOC_68K_TLS_LDO32; 7862 } 7863 7864 return BFD_RELOC_UNUSED; 7865} 7866 7867/* Handles .long <tls_symbol>+0x8000 debug info. 7868 Clobbers input_line_pointer, checks end-of-line. 7869 Adapted from tc-ppc.c:ppc_elf_cons. */ 7870static void 7871m68k_elf_cons (int nbytes /* 4=.long */) 7872{ 7873 if (is_it_end_of_statement ()) 7874 { 7875 demand_empty_rest_of_line (); 7876 return; 7877 } 7878 7879 do 7880 { 7881 expressionS exp; 7882 bfd_reloc_code_real_type reloc; 7883 7884 expression (&exp); 7885 if (exp.X_op == O_symbol 7886 && *input_line_pointer == '@' 7887 && (reloc = m68k_elf_suffix (&input_line_pointer, 7888 &exp)) != BFD_RELOC_UNUSED) 7889 { 7890 reloc_howto_type *reloc_howto; 7891 int size; 7892 7893 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); 7894 size = bfd_get_reloc_size (reloc_howto); 7895 7896 if (size > nbytes) 7897 { 7898 as_bad (ngettext ("%s relocations do not fit in %u byte", 7899 "%s relocations do not fit in %u bytes", 7900 nbytes), 7901 reloc_howto->name, nbytes); 7902 } 7903 else 7904 { 7905 char *p; 7906 int offset; 7907 7908 p = frag_more (nbytes); 7909 offset = 0; 7910 if (target_big_endian) 7911 offset = nbytes - size; 7912 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, 7913 &exp, 0, reloc); 7914 } 7915 } 7916 else 7917 emit_expr (&exp, (unsigned int) nbytes); 7918 } 7919 while (*input_line_pointer++ == ','); 7920 7921 /* Put terminator back into stream. */ 7922 input_line_pointer--; 7923 demand_empty_rest_of_line (); 7924} 7925 7926/* Parse a .gnu_attribute directive. */ 7927static void 7928m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) 7929{ 7930 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); 7931 7932 /* Check validity of defined m68k tags. */ 7933 if (tag == Tag_GNU_M68K_ABI_FP) 7934 { 7935 unsigned int val; 7936 7937 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); 7938 7939 if (tag == Tag_GNU_M68K_ABI_FP && val > 2) 7940 as_warn (_("unknown .gnu_attribute value")); 7941 } 7942} 7943 7944int 7945tc_m68k_regname_to_dw2regnum (const char *regname) 7946{ 7947 unsigned int regnum; 7948 static const char *const regnames[] = 7949 { 7950 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 7951 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", 7952 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", 7953 "pc" 7954 }; 7955 7956 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) 7957 if (strcmp (regname, regnames[regnum]) == 0) 7958 return regnum; 7959 7960 return -1; 7961} 7962 7963void 7964tc_m68k_frame_initial_instructions (void) 7965{ 7966 static int sp_regno = -1; 7967 7968 if (sp_regno < 0) 7969 sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); 7970 7971 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); 7972 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); 7973} 7974 7975/* Check and emit error if broken-word handling has failed to fix up a 7976 case-table. This is called from write.c, after doing everything it 7977 knows about how to handle broken words. */ 7978 7979void 7980tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 7981{ 7982 if (new_offset > 32767 || new_offset < -32768) 7983 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 7984 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."), 7985 (long) new_offset); 7986} 7987 7988