reloc.texi revision 1.8
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. Note - the value 2 is used so that it 31 will not be mistaken for the boolean TRUE or FALSE values. */ 32 bfd_reloc_ok = 2, 33 34 /* The relocation was performed, but there was an overflow. */ 35 bfd_reloc_overflow, 36 37 /* The address to relocate was not within the section supplied. */ 38 bfd_reloc_outofrange, 39 40 /* Used by special functions. */ 41 bfd_reloc_continue, 42 43 /* Unsupported relocation size requested. */ 44 bfd_reloc_notsupported, 45 46 /* Unused. */ 47 bfd_reloc_other, 48 49 /* The symbol to relocate against was undefined. */ 50 bfd_reloc_undefined, 51 52 /* The relocation was performed, but may not be ok. If this type is 53 returned, the error_message argument to bfd_perform_relocation 54 will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59typedef const struct reloc_howto_struct reloc_howto_type; 60 61typedef struct reloc_cache_entry 62@{ 63 /* A pointer into the canonical table of pointers. */ 64 struct bfd_symbol **sym_ptr_ptr; 65 66 /* offset in section. */ 67 bfd_size_type address; 68 69 /* addend for relocation value. */ 70 bfd_vma addend; 71 72 /* Pointer to how to perform the required relocation. */ 73 reloc_howto_type *howto; 74 75@} 76arelent; 77 78@end example 79@strong{Description}@* 80Here is a description of each of the fields within an @code{arelent}: 81 82@itemize @bullet 83 84@item 85@code{sym_ptr_ptr} 86@end itemize 87The symbol table pointer points to a pointer to the symbol 88associated with the relocation request. It is the pointer 89into the table returned by the back end's 90@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 91referenced through a pointer to a pointer so that tools like 92the linker can fix up all the symbols of the same name by 93modifying only one pointer. The relocation routine looks in 94the symbol and uses the base of the section the symbol is 95attached to and the value of the symbol as the initial 96relocation offset. If the symbol pointer is zero, then the 97section provided is looked up. 98 99@itemize @bullet 100 101@item 102@code{address} 103@end itemize 104The @code{address} field gives the offset in bytes from the base of 105the section data which owns the relocation record to the first 106byte of relocatable information. The actual data relocated 107will be relative to this point; for example, a relocation 108type which modifies the bottom two bytes of a four byte word 109would not touch the first byte pointed to in a big endian 110world. 111 112@itemize @bullet 113 114@item 115@code{addend} 116@end itemize 117The @code{addend} is a value provided by the back end to be added (!) 118to the relocation offset. Its interpretation is dependent upon 119the howto. For example, on the 68k the code: 120 121@example 122 char foo[]; 123 main() 124 @{ 125 return foo[0x12345678]; 126 @} 127@end example 128 129Could be compiled into: 130 131@example 132 linkw fp,#-4 133 moveb @@#12345678,d0 134 extbl d0 135 unlk fp 136 rts 137@end example 138 139This could create a reloc pointing to @code{foo}, but leave the 140offset in the data, something like: 141 142@example 143RELOCATION RECORDS FOR [.text]: 144offset type value 14500000006 32 _foo 146 14700000000 4e56 fffc ; linkw fp,#-4 14800000004 1039 1234 5678 ; moveb @@#12345678,d0 1490000000a 49c0 ; extbl d0 1500000000c 4e5e ; unlk fp 1510000000e 4e75 ; rts 152@end example 153 154Using coff and an 88k, some instructions don't have enough 155space in them to represent the full address range, and 156pointers have to be loaded in two parts. So you'd get something like: 157 158@example 159 or.u r13,r0,hi16(_foo+0x12345678) 160 ld.b r2,r13,lo16(_foo+0x12345678) 161 jmp r1 162@end example 163 164This should create two relocs, both pointing to @code{_foo}, and with 1650x12340000 in their addend field. The data would consist of: 166 167@example 168RELOCATION RECORDS FOR [.text]: 169offset type value 17000000002 HVRT16 _foo+0x12340000 17100000006 LVRT16 _foo+0x12340000 172 17300000000 5da05678 ; or.u r13,r0,0x5678 17400000004 1c4d5678 ; ld.b r2,r13,0x5678 17500000008 f400c001 ; jmp r1 176@end example 177 178The relocation routine digs out the value from the data, adds 179it to the addend to get the original offset, and then adds the 180value of @code{_foo}. Note that all 32 bits have to be kept around 181somewhere, to cope with carry from bit 15 to bit 16. 182 183One further example is the sparc and the a.out format. The 184sparc has a similar problem to the 88k, in that some 185instructions don't have room for an entire offset, but on the 186sparc the parts are created in odd sized lumps. The designers of 187the a.out format chose to not use the data within the section 188for storing part of the offset; all the offset is kept within 189the reloc. Anything in the data should be ignored. 190 191@example 192 save %sp,-112,%sp 193 sethi %hi(_foo+0x12345678),%g2 194 ldsb [%g2+%lo(_foo+0x12345678)],%i0 195 ret 196 restore 197@end example 198 199Both relocs contain a pointer to @code{foo}, and the offsets 200contain junk. 201 202@example 203RELOCATION RECORDS FOR [.text]: 204offset type value 20500000004 HI22 _foo+0x12345678 20600000008 LO10 _foo+0x12345678 207 20800000000 9de3bf90 ; save %sp,-112,%sp 20900000004 05000000 ; sethi %hi(_foo+0),%g2 21000000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2110000000c 81c7e008 ; ret 21200000010 81e80000 ; restore 213@end example 214 215@itemize @bullet 216 217@item 218@code{howto} 219@end itemize 220The @code{howto} field can be imagined as a 221relocation instruction. It is a pointer to a structure which 222contains information on what to do with all of the other 223information in the reloc record and data section. A back end 224would normally have a relocation instruction set and turn 225relocations into pointers to the correct structure on input - 226but it would be possible to create each howto field on demand. 227 228@subsubsection @code{enum complain_overflow} 229Indicates what sort of overflow checking should be done when 230performing a relocation. 231 232 233@example 234 235enum complain_overflow 236@{ 237 /* Do not complain on overflow. */ 238 complain_overflow_dont, 239 240 /* Complain if the value overflows when considered as a signed 241 number one bit larger than the field. ie. A bitfield of N bits 242 is allowed to represent -2**n to 2**n-1. */ 243 complain_overflow_bitfield, 244 245 /* Complain if the value overflows when considered as a signed 246 number. */ 247 complain_overflow_signed, 248 249 /* Complain if the value overflows when considered as an 250 unsigned number. */ 251 complain_overflow_unsigned 252@}; 253@end example 254@subsubsection @code{reloc_howto_type} 255The @code{reloc_howto_type} is a structure which contains all the 256information that libbfd needs to know to tie up a back end's data. 257 258 259@example 260struct reloc_howto_struct 261@{ 262 /* The type field has mainly a documentary use - the back end can 263 do what it wants with it, though normally the back end's idea of 264 an external reloc number is stored in this field. */ 265 unsigned int type; 266 267 /* The encoded size of the item to be relocated. This is *not* a 268 power-of-two measure. Use bfd_get_reloc_size to find the size 269 of the item in bytes. */ 270 unsigned int size:3; 271 272 /* The number of bits in the field to be relocated. This is used 273 when doing overflow checking. */ 274 unsigned int bitsize:7; 275 276 /* The value the final relocation is shifted right by. This drops 277 unwanted data from the relocation. */ 278 unsigned int rightshift:6; 279 280 /* The bit position of the reloc value in the destination. 281 The relocated value is left shifted by this amount. */ 282 unsigned int bitpos:6; 283 284 /* What type of overflow error should be checked for when 285 relocating. */ 286 ENUM_BITFIELD (complain_overflow) complain_on_overflow:2; 287 288 /* The relocation value should be negated before applying. */ 289 unsigned int negate:1; 290 291 /* The relocation is relative to the item being relocated. */ 292 unsigned int pc_relative:1; 293 294 /* Some formats record a relocation addend in the section contents 295 rather than with the relocation. For ELF formats this is the 296 distinction between USE_REL and USE_RELA (though the code checks 297 for USE_REL == 1/0). The value of this field is TRUE if the 298 addend is recorded with the section contents; when performing a 299 partial link (ld -r) the section contents (the data) will be 300 modified. The value of this field is FALSE if addends are 301 recorded with the relocation (in arelent.addend); when performing 302 a partial link the relocation will be modified. 303 All relocations for all ELF USE_RELA targets should set this field 304 to FALSE (values of TRUE should be looked on with suspicion). 305 However, the converse is not true: not all relocations of all ELF 306 USE_REL targets set this field to TRUE. Why this is so is peculiar 307 to each particular target. For relocs that aren't used in partial 308 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 309 unsigned int partial_inplace:1; 310 311 /* When some formats create PC relative instructions, they leave 312 the value of the pc of the place being relocated in the offset 313 slot of the instruction, so that a PC relative relocation can 314 be made just by adding in an ordinary offset (e.g., sun3 a.out). 315 Some formats leave the displacement part of an instruction 316 empty (e.g., ELF); this flag signals the fact. */ 317 unsigned int pcrel_offset:1; 318 319 /* src_mask selects the part of the instruction (or data) to be used 320 in the relocation sum. If the target relocations don't have an 321 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 322 dst_mask to extract the addend from the section contents. If 323 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 324 field should normally be zero. Non-zero values for ELF USE_RELA 325 targets should be viewed with suspicion as normally the value in 326 the dst_mask part of the section contents should be ignored. */ 327 bfd_vma src_mask; 328 329 /* dst_mask selects which parts of the instruction (or data) are 330 replaced with a relocated value. */ 331 bfd_vma dst_mask; 332 333 /* If this field is non null, then the supplied function is 334 called rather than the normal function. This allows really 335 strange relocation methods to be accommodated. */ 336 bfd_reloc_status_type (*special_function) 337 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 338 bfd *, char **); 339 340 /* The textual name of the relocation type. */ 341 const char *name; 342@}; 343 344@end example 345@findex The HOWTO Macro 346@subsubsection @code{The HOWTO Macro} 347@strong{Description}@* 348The HOWTO macro fills in a reloc_howto_type (a typedef for 349const struct reloc_howto_struct). 350@example 351#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \ 352 inplace, src_mask, dst_mask, pcrel_off) \ 353 @{ (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \ 354 size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name @} 355@end example 356 357@strong{Description}@* 358This is used to fill in an empty howto entry in an array. 359@example 360#define EMPTY_HOWTO(C) \ 361 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 362 NULL, FALSE, 0, 0, FALSE) 363 364@end example 365 366@findex bfd_get_reloc_size 367@subsubsection @code{bfd_get_reloc_size} 368@strong{Synopsis} 369@example 370unsigned int bfd_get_reloc_size (reloc_howto_type *); 371@end example 372@strong{Description}@* 373For a reloc_howto_type that operates on a fixed number of bytes, 374this returns the number of bytes operated on. 375 376@findex arelent_chain 377@subsubsection @code{arelent_chain} 378@strong{Description}@* 379How relocs are tied together in an @code{asection}: 380@example 381typedef struct relent_chain 382@{ 383 arelent relent; 384 struct relent_chain *next; 385@} 386arelent_chain; 387 388@end example 389 390@findex bfd_check_overflow 391@subsubsection @code{bfd_check_overflow} 392@strong{Synopsis} 393@example 394bfd_reloc_status_type bfd_check_overflow 395 (enum complain_overflow how, 396 unsigned int bitsize, 397 unsigned int rightshift, 398 unsigned int addrsize, 399 bfd_vma relocation); 400@end example 401@strong{Description}@* 402Perform overflow checking on @var{relocation} which has 403@var{bitsize} significant bits and will be shifted right by 404@var{rightshift} bits, on a machine with addresses containing 405@var{addrsize} significant bits. The result is either of 406@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 407 408@findex bfd_reloc_offset_in_range 409@subsubsection @code{bfd_reloc_offset_in_range} 410@strong{Synopsis} 411@example 412bfd_boolean bfd_reloc_offset_in_range 413 (reloc_howto_type *howto, 414 bfd *abfd, 415 asection *section, 416 bfd_size_type offset); 417@end example 418@strong{Description}@* 419Returns TRUE if the reloc described by @var{HOWTO} can be 420applied at @var{OFFSET} octets in @var{SECTION}. 421 422@findex bfd_perform_relocation 423@subsubsection @code{bfd_perform_relocation} 424@strong{Synopsis} 425@example 426bfd_reloc_status_type bfd_perform_relocation 427 (bfd *abfd, 428 arelent *reloc_entry, 429 void *data, 430 asection *input_section, 431 bfd *output_bfd, 432 char **error_message); 433@end example 434@strong{Description}@* 435If @var{output_bfd} is supplied to this function, the 436generated image will be relocatable; the relocations are 437copied to the output file after they have been changed to 438reflect the new state of the world. There are two ways of 439reflecting the results of partial linkage in an output file: 440by modifying the output data in place, and by modifying the 441relocation record. Some native formats (e.g., basic a.out and 442basic coff) have no way of specifying an addend in the 443relocation type, so the addend has to go in the output data. 444This is no big deal since in these formats the output data 445slot will always be big enough for the addend. Complex reloc 446types with addends were invented to solve just this problem. 447The @var{error_message} argument is set to an error message if 448this return @code{bfd_reloc_dangerous}. 449 450@findex bfd_install_relocation 451@subsubsection @code{bfd_install_relocation} 452@strong{Synopsis} 453@example 454bfd_reloc_status_type bfd_install_relocation 455 (bfd *abfd, 456 arelent *reloc_entry, 457 void *data, bfd_vma data_start, 458 asection *input_section, 459 char **error_message); 460@end example 461@strong{Description}@* 462This looks remarkably like @code{bfd_perform_relocation}, except it 463does not expect that the section contents have been filled in. 464I.e., it's suitable for use when creating, rather than applying 465a relocation. 466 467For now, this function should be considered reserved for the 468assembler. 469 470 471@node howto manager, , typedef arelent, Relocations 472@subsection The howto manager 473When an application wants to create a relocation, but doesn't 474know what the target machine might call it, it can find out by 475using this bit of code. 476 477@findex bfd_reloc_code_type 478@subsubsection @code{bfd_reloc_code_type} 479@strong{Description}@* 480The insides of a reloc code. The idea is that, eventually, there 481will be one enumerator for every type of relocation we ever do. 482Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 483return a howto pointer. 484 485This does mean that the application must determine the correct 486enumerator value; you can't get a howto pointer from a random set 487of attributes. 488 489Here are the possible values for @code{enum bfd_reloc_code_real}: 490 491@deffn {} BFD_RELOC_64 492@deffnx {} BFD_RELOC_32 493@deffnx {} BFD_RELOC_26 494@deffnx {} BFD_RELOC_24 495@deffnx {} BFD_RELOC_16 496@deffnx {} BFD_RELOC_14 497@deffnx {} BFD_RELOC_8 498Basic absolute relocations of N bits. 499@end deffn 500@deffn {} BFD_RELOC_64_PCREL 501@deffnx {} BFD_RELOC_32_PCREL 502@deffnx {} BFD_RELOC_24_PCREL 503@deffnx {} BFD_RELOC_16_PCREL 504@deffnx {} BFD_RELOC_12_PCREL 505@deffnx {} BFD_RELOC_8_PCREL 506PC-relative relocations. Sometimes these are relative to the address 507of the relocation itself; sometimes they are relative to the start of 508the section containing the relocation. It depends on the specific target. 509@end deffn 510@deffn {} BFD_RELOC_32_SECREL 511Section relative relocations. Some targets need this for DWARF2. 512@end deffn 513@deffn {} BFD_RELOC_32_GOT_PCREL 514@deffnx {} BFD_RELOC_16_GOT_PCREL 515@deffnx {} BFD_RELOC_8_GOT_PCREL 516@deffnx {} BFD_RELOC_32_GOTOFF 517@deffnx {} BFD_RELOC_16_GOTOFF 518@deffnx {} BFD_RELOC_LO16_GOTOFF 519@deffnx {} BFD_RELOC_HI16_GOTOFF 520@deffnx {} BFD_RELOC_HI16_S_GOTOFF 521@deffnx {} BFD_RELOC_8_GOTOFF 522@deffnx {} BFD_RELOC_64_PLT_PCREL 523@deffnx {} BFD_RELOC_32_PLT_PCREL 524@deffnx {} BFD_RELOC_24_PLT_PCREL 525@deffnx {} BFD_RELOC_16_PLT_PCREL 526@deffnx {} BFD_RELOC_8_PLT_PCREL 527@deffnx {} BFD_RELOC_64_PLTOFF 528@deffnx {} BFD_RELOC_32_PLTOFF 529@deffnx {} BFD_RELOC_16_PLTOFF 530@deffnx {} BFD_RELOC_LO16_PLTOFF 531@deffnx {} BFD_RELOC_HI16_PLTOFF 532@deffnx {} BFD_RELOC_HI16_S_PLTOFF 533@deffnx {} BFD_RELOC_8_PLTOFF 534For ELF. 535@end deffn 536@deffn {} BFD_RELOC_SIZE32 537@deffnx {} BFD_RELOC_SIZE64 538Size relocations. 539@end deffn 540@deffn {} BFD_RELOC_68K_GLOB_DAT 541@deffnx {} BFD_RELOC_68K_JMP_SLOT 542@deffnx {} BFD_RELOC_68K_RELATIVE 543@deffnx {} BFD_RELOC_68K_TLS_GD32 544@deffnx {} BFD_RELOC_68K_TLS_GD16 545@deffnx {} BFD_RELOC_68K_TLS_GD8 546@deffnx {} BFD_RELOC_68K_TLS_LDM32 547@deffnx {} BFD_RELOC_68K_TLS_LDM16 548@deffnx {} BFD_RELOC_68K_TLS_LDM8 549@deffnx {} BFD_RELOC_68K_TLS_LDO32 550@deffnx {} BFD_RELOC_68K_TLS_LDO16 551@deffnx {} BFD_RELOC_68K_TLS_LDO8 552@deffnx {} BFD_RELOC_68K_TLS_IE32 553@deffnx {} BFD_RELOC_68K_TLS_IE16 554@deffnx {} BFD_RELOC_68K_TLS_IE8 555@deffnx {} BFD_RELOC_68K_TLS_LE32 556@deffnx {} BFD_RELOC_68K_TLS_LE16 557@deffnx {} BFD_RELOC_68K_TLS_LE8 558Relocations used by 68K ELF. 559@end deffn 560@deffn {} BFD_RELOC_VAX_GLOB_DAT 561@deffnx {} BFD_RELOC_VAX_GLOB_REF 562@deffnx {} BFD_RELOC_VAX_JMP_SLOT 563@deffnx {} BFD_RELOC_VAX_RELATIVE 564Relocations used by VAX ELF. 565@end deffn 566@deffn {} BFD_RELOC_32_BASEREL 567@deffnx {} BFD_RELOC_16_BASEREL 568@deffnx {} BFD_RELOC_LO16_BASEREL 569@deffnx {} BFD_RELOC_HI16_BASEREL 570@deffnx {} BFD_RELOC_HI16_S_BASEREL 571@deffnx {} BFD_RELOC_8_BASEREL 572@deffnx {} BFD_RELOC_RVA 573Linkage-table relative. 574@end deffn 575@deffn {} BFD_RELOC_8_FFnn 576Absolute 8-bit relocation, but used to form an address like 0xFFnn. 577@end deffn 578@deffn {} BFD_RELOC_32_PCREL_S2 579@deffnx {} BFD_RELOC_16_PCREL_S2 580@deffnx {} BFD_RELOC_23_PCREL_S2 581These PC-relative relocations are stored as word displacements -- 582i.e., byte displacements shifted right two bits. The 30-bit word 583displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 584SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 585signed 16-bit displacement is used on the MIPS, and the 23-bit 586displacement is used on the Alpha. 587@end deffn 588@deffn {} BFD_RELOC_HI22 589@deffnx {} BFD_RELOC_LO10 590High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 591the target word. These are used on the SPARC. 592@end deffn 593@deffn {} BFD_RELOC_GPREL16 594@deffnx {} BFD_RELOC_GPREL32 595For systems that allocate a Global Pointer register, these are 596displacements off that register. These relocation types are 597handled specially, because the value the register will have is 598decided relatively late. 599@end deffn 600@deffn {} BFD_RELOC_NONE 601@deffnx {} BFD_RELOC_SPARC_WDISP22 602@deffnx {} BFD_RELOC_SPARC22 603@deffnx {} BFD_RELOC_SPARC13 604@deffnx {} BFD_RELOC_SPARC_GOT10 605@deffnx {} BFD_RELOC_SPARC_GOT13 606@deffnx {} BFD_RELOC_SPARC_GOT22 607@deffnx {} BFD_RELOC_SPARC_PC10 608@deffnx {} BFD_RELOC_SPARC_PC22 609@deffnx {} BFD_RELOC_SPARC_WPLT30 610@deffnx {} BFD_RELOC_SPARC_COPY 611@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 612@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 613@deffnx {} BFD_RELOC_SPARC_RELATIVE 614@deffnx {} BFD_RELOC_SPARC_UA16 615@deffnx {} BFD_RELOC_SPARC_UA32 616@deffnx {} BFD_RELOC_SPARC_UA64 617@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 618@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 619@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 620@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 621@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 622@deffnx {} BFD_RELOC_SPARC_JMP_IREL 623@deffnx {} BFD_RELOC_SPARC_IRELATIVE 624SPARC ELF relocations. There is probably some overlap with other 625relocation types already defined. 626@end deffn 627@deffn {} BFD_RELOC_SPARC_BASE13 628@deffnx {} BFD_RELOC_SPARC_BASE22 629I think these are specific to SPARC a.out (e.g., Sun 4). 630@end deffn 631@deffn {} BFD_RELOC_SPARC_64 632@deffnx {} BFD_RELOC_SPARC_10 633@deffnx {} BFD_RELOC_SPARC_11 634@deffnx {} BFD_RELOC_SPARC_OLO10 635@deffnx {} BFD_RELOC_SPARC_HH22 636@deffnx {} BFD_RELOC_SPARC_HM10 637@deffnx {} BFD_RELOC_SPARC_LM22 638@deffnx {} BFD_RELOC_SPARC_PC_HH22 639@deffnx {} BFD_RELOC_SPARC_PC_HM10 640@deffnx {} BFD_RELOC_SPARC_PC_LM22 641@deffnx {} BFD_RELOC_SPARC_WDISP16 642@deffnx {} BFD_RELOC_SPARC_WDISP19 643@deffnx {} BFD_RELOC_SPARC_7 644@deffnx {} BFD_RELOC_SPARC_6 645@deffnx {} BFD_RELOC_SPARC_5 646@deffnx {} BFD_RELOC_SPARC_DISP64 647@deffnx {} BFD_RELOC_SPARC_PLT32 648@deffnx {} BFD_RELOC_SPARC_PLT64 649@deffnx {} BFD_RELOC_SPARC_HIX22 650@deffnx {} BFD_RELOC_SPARC_LOX10 651@deffnx {} BFD_RELOC_SPARC_H44 652@deffnx {} BFD_RELOC_SPARC_M44 653@deffnx {} BFD_RELOC_SPARC_L44 654@deffnx {} BFD_RELOC_SPARC_REGISTER 655@deffnx {} BFD_RELOC_SPARC_H34 656@deffnx {} BFD_RELOC_SPARC_SIZE32 657@deffnx {} BFD_RELOC_SPARC_SIZE64 658@deffnx {} BFD_RELOC_SPARC_WDISP10 659SPARC64 relocations 660@end deffn 661@deffn {} BFD_RELOC_SPARC_REV32 662SPARC little endian relocation 663@end deffn 664@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 665@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 666@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 667@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 668@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 669@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 670@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 671@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 672@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 673@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 674@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 675@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 676@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 677@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 678@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 679@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 680@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 681@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 682@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 683@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 684@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 685@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 686@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 687@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 688SPARC TLS relocations 689@end deffn 690@deffn {} BFD_RELOC_SPU_IMM7 691@deffnx {} BFD_RELOC_SPU_IMM8 692@deffnx {} BFD_RELOC_SPU_IMM10 693@deffnx {} BFD_RELOC_SPU_IMM10W 694@deffnx {} BFD_RELOC_SPU_IMM16 695@deffnx {} BFD_RELOC_SPU_IMM16W 696@deffnx {} BFD_RELOC_SPU_IMM18 697@deffnx {} BFD_RELOC_SPU_PCREL9a 698@deffnx {} BFD_RELOC_SPU_PCREL9b 699@deffnx {} BFD_RELOC_SPU_PCREL16 700@deffnx {} BFD_RELOC_SPU_LO16 701@deffnx {} BFD_RELOC_SPU_HI16 702@deffnx {} BFD_RELOC_SPU_PPU32 703@deffnx {} BFD_RELOC_SPU_PPU64 704@deffnx {} BFD_RELOC_SPU_ADD_PIC 705SPU Relocations. 706@end deffn 707@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 708Alpha ECOFF and ELF relocations. Some of these treat the symbol or 709"addend" in some special way. 710For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 711writing; when reading, it will be the absolute section symbol. The 712addend is the displacement in bytes of the "lda" instruction from 713the "ldah" instruction (which is at the address of this reloc). 714@end deffn 715@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 716For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 717with GPDISP_HI16 relocs. The addend is ignored when writing the 718relocations out, and is filled in with the file's GP value on 719reading, for convenience. 720@end deffn 721@deffn {} BFD_RELOC_ALPHA_GPDISP 722The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 723relocation except that there is no accompanying GPDISP_LO16 724relocation. 725@end deffn 726@deffn {} BFD_RELOC_ALPHA_LITERAL 727@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 728@deffnx {} BFD_RELOC_ALPHA_LITUSE 729The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 730the assembler turns it into a LDQ instruction to load the address of 731the symbol, and then fills in a register in the real instruction. 732 733The LITERAL reloc, at the LDQ instruction, refers to the .lita 734section symbol. The addend is ignored when writing, but is filled 735in with the file's GP value on reading, for convenience, as with the 736GPDISP_LO16 reloc. 737 738The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 739It should refer to the symbol to be referenced, as with 16_GOTOFF, 740but it generates output not based on the position within the .got 741section, but relative to the GP value chosen for the file during the 742final link stage. 743 744The LITUSE reloc, on the instruction using the loaded address, gives 745information to the linker that it might be able to use to optimize 746away some literal section references. The symbol is ignored (read 747as the absolute section symbol), and the "addend" indicates the type 748of instruction using the register: 7491 - "memory" fmt insn 7502 - byte-manipulation (byte offset reg) 7513 - jsr (target of branch) 752@end deffn 753@deffn {} BFD_RELOC_ALPHA_HINT 754The HINT relocation indicates a value that should be filled into the 755"hint" field of a jmp/jsr/ret instruction, for possible branch- 756prediction logic which may be provided on some processors. 757@end deffn 758@deffn {} BFD_RELOC_ALPHA_LINKAGE 759The LINKAGE relocation outputs a linkage pair in the object file, 760which is filled by the linker. 761@end deffn 762@deffn {} BFD_RELOC_ALPHA_CODEADDR 763The CODEADDR relocation outputs a STO_CA in the object file, 764which is filled by the linker. 765@end deffn 766@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 767@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 768The GPREL_HI/LO relocations together form a 32-bit offset from the 769GP register. 770@end deffn 771@deffn {} BFD_RELOC_ALPHA_BRSGP 772Like BFD_RELOC_23_PCREL_S2, except that the source and target must 773share a common GP, and the target address is adjusted for 774STO_ALPHA_STD_GPLOAD. 775@end deffn 776@deffn {} BFD_RELOC_ALPHA_NOP 777The NOP relocation outputs a NOP if the longword displacement 778between two procedure entry points is < 2^21. 779@end deffn 780@deffn {} BFD_RELOC_ALPHA_BSR 781The BSR relocation outputs a BSR if the longword displacement 782between two procedure entry points is < 2^21. 783@end deffn 784@deffn {} BFD_RELOC_ALPHA_LDA 785The LDA relocation outputs a LDA if the longword displacement 786between two procedure entry points is < 2^16. 787@end deffn 788@deffn {} BFD_RELOC_ALPHA_BOH 789The BOH relocation outputs a BSR if the longword displacement 790between two procedure entry points is < 2^21, or else a hint. 791@end deffn 792@deffn {} BFD_RELOC_ALPHA_TLSGD 793@deffnx {} BFD_RELOC_ALPHA_TLSLDM 794@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 795@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 796@deffnx {} BFD_RELOC_ALPHA_DTPREL64 797@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 798@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 799@deffnx {} BFD_RELOC_ALPHA_DTPREL16 800@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 801@deffnx {} BFD_RELOC_ALPHA_TPREL64 802@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 803@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 804@deffnx {} BFD_RELOC_ALPHA_TPREL16 805Alpha thread-local storage relocations. 806@end deffn 807@deffn {} BFD_RELOC_MIPS_JMP 808@deffnx {} BFD_RELOC_MICROMIPS_JMP 809The MIPS jump instruction. 810@end deffn 811@deffn {} BFD_RELOC_MIPS16_JMP 812The MIPS16 jump instruction. 813@end deffn 814@deffn {} BFD_RELOC_MIPS16_GPREL 815MIPS16 GP relative reloc. 816@end deffn 817@deffn {} BFD_RELOC_HI16 818High 16 bits of 32-bit value; simple reloc. 819@end deffn 820@deffn {} BFD_RELOC_HI16_S 821High 16 bits of 32-bit value but the low 16 bits will be sign 822extended and added to form the final result. If the low 16 823bits form a negative number, we need to add one to the high value 824to compensate for the borrow when the low bits are added. 825@end deffn 826@deffn {} BFD_RELOC_LO16 827Low 16 bits. 828@end deffn 829@deffn {} BFD_RELOC_HI16_PCREL 830High 16 bits of 32-bit pc-relative value 831@end deffn 832@deffn {} BFD_RELOC_HI16_S_PCREL 833High 16 bits of 32-bit pc-relative value, adjusted 834@end deffn 835@deffn {} BFD_RELOC_LO16_PCREL 836Low 16 bits of pc-relative value 837@end deffn 838@deffn {} BFD_RELOC_MIPS16_GOT16 839@deffnx {} BFD_RELOC_MIPS16_CALL16 840Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 84116-bit immediate fields 842@end deffn 843@deffn {} BFD_RELOC_MIPS16_HI16 844MIPS16 high 16 bits of 32-bit value. 845@end deffn 846@deffn {} BFD_RELOC_MIPS16_HI16_S 847MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 848extended and added to form the final result. If the low 16 849bits form a negative number, we need to add one to the high value 850to compensate for the borrow when the low bits are added. 851@end deffn 852@deffn {} BFD_RELOC_MIPS16_LO16 853MIPS16 low 16 bits. 854@end deffn 855@deffn {} BFD_RELOC_MIPS16_TLS_GD 856@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 857@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 858@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 859@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 860@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 861@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 862MIPS16 TLS relocations 863@end deffn 864@deffn {} BFD_RELOC_MIPS_LITERAL 865@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 866Relocation against a MIPS literal section. 867@end deffn 868@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 869@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 870@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 871microMIPS PC-relative relocations. 872@end deffn 873@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 874MIPS16 PC-relative relocation. 875@end deffn 876@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 877@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 878@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 879@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 880MIPS PC-relative relocations. 881@end deffn 882@deffn {} BFD_RELOC_MICROMIPS_GPREL16 883@deffnx {} BFD_RELOC_MICROMIPS_HI16 884@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 885@deffnx {} BFD_RELOC_MICROMIPS_LO16 886microMIPS versions of generic BFD relocs. 887@end deffn 888@deffn {} BFD_RELOC_MIPS_GOT16 889@deffnx {} BFD_RELOC_MICROMIPS_GOT16 890@deffnx {} BFD_RELOC_MIPS_CALL16 891@deffnx {} BFD_RELOC_MICROMIPS_CALL16 892@deffnx {} BFD_RELOC_MIPS_GOT_HI16 893@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 894@deffnx {} BFD_RELOC_MIPS_GOT_LO16 895@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 896@deffnx {} BFD_RELOC_MIPS_CALL_HI16 897@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 898@deffnx {} BFD_RELOC_MIPS_CALL_LO16 899@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 900@deffnx {} BFD_RELOC_MIPS_SUB 901@deffnx {} BFD_RELOC_MICROMIPS_SUB 902@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 903@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 904@deffnx {} BFD_RELOC_MIPS_GOT_OFST 905@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 906@deffnx {} BFD_RELOC_MIPS_GOT_DISP 907@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 908@deffnx {} BFD_RELOC_MIPS_SHIFT5 909@deffnx {} BFD_RELOC_MIPS_SHIFT6 910@deffnx {} BFD_RELOC_MIPS_INSERT_A 911@deffnx {} BFD_RELOC_MIPS_INSERT_B 912@deffnx {} BFD_RELOC_MIPS_DELETE 913@deffnx {} BFD_RELOC_MIPS_HIGHEST 914@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 915@deffnx {} BFD_RELOC_MIPS_HIGHER 916@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 917@deffnx {} BFD_RELOC_MIPS_SCN_DISP 918@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 919@deffnx {} BFD_RELOC_MIPS_REL16 920@deffnx {} BFD_RELOC_MIPS_RELGOT 921@deffnx {} BFD_RELOC_MIPS_JALR 922@deffnx {} BFD_RELOC_MICROMIPS_JALR 923@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 924@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 925@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 926@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 927@deffnx {} BFD_RELOC_MIPS_TLS_GD 928@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 929@deffnx {} BFD_RELOC_MIPS_TLS_LDM 930@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 931@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 932@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 933@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 934@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 935@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 936@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 937@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 938@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 939@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 940@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 941@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 942@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 943@deffnx {} BFD_RELOC_MIPS_EH 944MIPS ELF relocations. 945@end deffn 946@deffn {} BFD_RELOC_MIPS_COPY 947@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 948MIPS ELF relocations (VxWorks and PLT extensions). 949@end deffn 950@deffn {} BFD_RELOC_MOXIE_10_PCREL 951Moxie ELF relocations. 952@end deffn 953@deffn {} BFD_RELOC_FT32_10 954@deffnx {} BFD_RELOC_FT32_20 955@deffnx {} BFD_RELOC_FT32_17 956@deffnx {} BFD_RELOC_FT32_18 957@deffnx {} BFD_RELOC_FT32_RELAX 958@deffnx {} BFD_RELOC_FT32_SC0 959@deffnx {} BFD_RELOC_FT32_SC1 960@deffnx {} BFD_RELOC_FT32_15 961@deffnx {} BFD_RELOC_FT32_DIFF32 962FT32 ELF relocations. 963@end deffn 964@deffn {} BFD_RELOC_FRV_LABEL16 965@deffnx {} BFD_RELOC_FRV_LABEL24 966@deffnx {} BFD_RELOC_FRV_LO16 967@deffnx {} BFD_RELOC_FRV_HI16 968@deffnx {} BFD_RELOC_FRV_GPREL12 969@deffnx {} BFD_RELOC_FRV_GPRELU12 970@deffnx {} BFD_RELOC_FRV_GPREL32 971@deffnx {} BFD_RELOC_FRV_GPRELHI 972@deffnx {} BFD_RELOC_FRV_GPRELLO 973@deffnx {} BFD_RELOC_FRV_GOT12 974@deffnx {} BFD_RELOC_FRV_GOTHI 975@deffnx {} BFD_RELOC_FRV_GOTLO 976@deffnx {} BFD_RELOC_FRV_FUNCDESC 977@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 978@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 979@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 980@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 981@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 982@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 983@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 984@deffnx {} BFD_RELOC_FRV_GOTOFF12 985@deffnx {} BFD_RELOC_FRV_GOTOFFHI 986@deffnx {} BFD_RELOC_FRV_GOTOFFLO 987@deffnx {} BFD_RELOC_FRV_GETTLSOFF 988@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 989@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 990@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 991@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 992@deffnx {} BFD_RELOC_FRV_TLSMOFF12 993@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 994@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 995@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 996@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 997@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 998@deffnx {} BFD_RELOC_FRV_TLSOFF 999@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 1000@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 1001@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 1002@deffnx {} BFD_RELOC_FRV_TLSMOFF 1003Fujitsu Frv Relocations. 1004@end deffn 1005@deffn {} BFD_RELOC_MN10300_GOTOFF24 1006This is a 24bit GOT-relative reloc for the mn10300. 1007@end deffn 1008@deffn {} BFD_RELOC_MN10300_GOT32 1009This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1010in the instruction. 1011@end deffn 1012@deffn {} BFD_RELOC_MN10300_GOT24 1013This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1014in the instruction. 1015@end deffn 1016@deffn {} BFD_RELOC_MN10300_GOT16 1017This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1018in the instruction. 1019@end deffn 1020@deffn {} BFD_RELOC_MN10300_COPY 1021Copy symbol at runtime. 1022@end deffn 1023@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1024Create GOT entry. 1025@end deffn 1026@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1027Create PLT entry. 1028@end deffn 1029@deffn {} BFD_RELOC_MN10300_RELATIVE 1030Adjust by program base. 1031@end deffn 1032@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1033Together with another reloc targeted at the same location, 1034allows for a value that is the difference of two symbols 1035in the same section. 1036@end deffn 1037@deffn {} BFD_RELOC_MN10300_ALIGN 1038The addend of this reloc is an alignment power that must 1039be honoured at the offset's location, regardless of linker 1040relaxation. 1041@end deffn 1042@deffn {} BFD_RELOC_MN10300_TLS_GD 1043@deffnx {} BFD_RELOC_MN10300_TLS_LD 1044@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1045@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1046@deffnx {} BFD_RELOC_MN10300_TLS_IE 1047@deffnx {} BFD_RELOC_MN10300_TLS_LE 1048@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1049@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1050@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1051Various TLS-related relocations. 1052@end deffn 1053@deffn {} BFD_RELOC_MN10300_32_PCREL 1054This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1055instruction. 1056@end deffn 1057@deffn {} BFD_RELOC_MN10300_16_PCREL 1058This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1059instruction. 1060@end deffn 1061@deffn {} BFD_RELOC_386_GOT32 1062@deffnx {} BFD_RELOC_386_PLT32 1063@deffnx {} BFD_RELOC_386_COPY 1064@deffnx {} BFD_RELOC_386_GLOB_DAT 1065@deffnx {} BFD_RELOC_386_JUMP_SLOT 1066@deffnx {} BFD_RELOC_386_RELATIVE 1067@deffnx {} BFD_RELOC_386_GOTOFF 1068@deffnx {} BFD_RELOC_386_GOTPC 1069@deffnx {} BFD_RELOC_386_TLS_TPOFF 1070@deffnx {} BFD_RELOC_386_TLS_IE 1071@deffnx {} BFD_RELOC_386_TLS_GOTIE 1072@deffnx {} BFD_RELOC_386_TLS_LE 1073@deffnx {} BFD_RELOC_386_TLS_GD 1074@deffnx {} BFD_RELOC_386_TLS_LDM 1075@deffnx {} BFD_RELOC_386_TLS_LDO_32 1076@deffnx {} BFD_RELOC_386_TLS_IE_32 1077@deffnx {} BFD_RELOC_386_TLS_LE_32 1078@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1079@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1080@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1081@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1082@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1083@deffnx {} BFD_RELOC_386_TLS_DESC 1084@deffnx {} BFD_RELOC_386_IRELATIVE 1085@deffnx {} BFD_RELOC_386_GOT32X 1086i386/elf relocations 1087@end deffn 1088@deffn {} BFD_RELOC_X86_64_GOT32 1089@deffnx {} BFD_RELOC_X86_64_PLT32 1090@deffnx {} BFD_RELOC_X86_64_COPY 1091@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1092@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1093@deffnx {} BFD_RELOC_X86_64_RELATIVE 1094@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1095@deffnx {} BFD_RELOC_X86_64_32S 1096@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1097@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1098@deffnx {} BFD_RELOC_X86_64_TPOFF64 1099@deffnx {} BFD_RELOC_X86_64_TLSGD 1100@deffnx {} BFD_RELOC_X86_64_TLSLD 1101@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1102@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1103@deffnx {} BFD_RELOC_X86_64_TPOFF32 1104@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1105@deffnx {} BFD_RELOC_X86_64_GOTPC32 1106@deffnx {} BFD_RELOC_X86_64_GOT64 1107@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1108@deffnx {} BFD_RELOC_X86_64_GOTPC64 1109@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1110@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1111@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1112@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1113@deffnx {} BFD_RELOC_X86_64_TLSDESC 1114@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1115@deffnx {} BFD_RELOC_X86_64_PC32_BND 1116@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1117@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1118@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1119x86-64/elf relocations 1120@end deffn 1121@deffn {} BFD_RELOC_NS32K_IMM_8 1122@deffnx {} BFD_RELOC_NS32K_IMM_16 1123@deffnx {} BFD_RELOC_NS32K_IMM_32 1124@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1125@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1126@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1127@deffnx {} BFD_RELOC_NS32K_DISP_8 1128@deffnx {} BFD_RELOC_NS32K_DISP_16 1129@deffnx {} BFD_RELOC_NS32K_DISP_32 1130@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1131@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1132@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1133ns32k relocations 1134@end deffn 1135@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1136@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1137PDP11 relocations 1138@end deffn 1139@deffn {} BFD_RELOC_PJ_CODE_HI16 1140@deffnx {} BFD_RELOC_PJ_CODE_LO16 1141@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1142@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1143@deffnx {} BFD_RELOC_PJ_CODE_REL16 1144@deffnx {} BFD_RELOC_PJ_CODE_REL32 1145Picojava relocs. Not all of these appear in object files. 1146@end deffn 1147@deffn {} BFD_RELOC_PPC_B26 1148@deffnx {} BFD_RELOC_PPC_BA26 1149@deffnx {} BFD_RELOC_PPC_TOC16 1150@deffnx {} BFD_RELOC_PPC_B16 1151@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1152@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1153@deffnx {} BFD_RELOC_PPC_BA16 1154@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1155@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1156@deffnx {} BFD_RELOC_PPC_COPY 1157@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1158@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1159@deffnx {} BFD_RELOC_PPC_RELATIVE 1160@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1161@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1162@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1163@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1164@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1165@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1166@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1167@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1168@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1169@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1170@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1171@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1172@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1173@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1174@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1175@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1176@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1177@deffnx {} BFD_RELOC_PPC_VLE_REL8 1178@deffnx {} BFD_RELOC_PPC_VLE_REL15 1179@deffnx {} BFD_RELOC_PPC_VLE_REL24 1180@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1181@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1182@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1183@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1184@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1185@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1186@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1187@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1188@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1189@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1190@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1191@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1192@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1193@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1194@deffnx {} BFD_RELOC_PPC_16DX_HA 1195@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1196@deffnx {} BFD_RELOC_PPC64_HIGHER 1197@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1198@deffnx {} BFD_RELOC_PPC64_HIGHEST 1199@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1200@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1201@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1202@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1203@deffnx {} BFD_RELOC_PPC64_TOC 1204@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1205@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1206@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1207@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1208@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1209@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1210@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1211@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1212@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1213@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1214@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1215@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1216@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1217@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1218@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1219@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1220@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1221@deffnx {} BFD_RELOC_PPC64_REL16_HIGH 1222@deffnx {} BFD_RELOC_PPC64_REL16_HIGHA 1223@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER 1224@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA 1225@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST 1226@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA 1227@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1228@deffnx {} BFD_RELOC_PPC64_ENTRY 1229@deffnx {} BFD_RELOC_PPC64_REL24_NOTOC 1230@deffnx {} BFD_RELOC_PPC64_D34 1231@deffnx {} BFD_RELOC_PPC64_D34_LO 1232@deffnx {} BFD_RELOC_PPC64_D34_HI30 1233@deffnx {} BFD_RELOC_PPC64_D34_HA30 1234@deffnx {} BFD_RELOC_PPC64_PCREL34 1235@deffnx {} BFD_RELOC_PPC64_GOT_PCREL34 1236@deffnx {} BFD_RELOC_PPC64_PLT_PCREL34 1237@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHER34 1238@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHERA34 1239@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHEST34 1240@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHESTA34 1241@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER34 1242@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA34 1243@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST34 1244@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA34 1245@deffnx {} BFD_RELOC_PPC64_D28 1246@deffnx {} BFD_RELOC_PPC64_PCREL28 1247Power(rs6000) and PowerPC relocations. 1248@end deffn 1249@deffn {} BFD_RELOC_PPC_TLS 1250@deffnx {} BFD_RELOC_PPC_TLSGD 1251@deffnx {} BFD_RELOC_PPC_TLSLD 1252@deffnx {} BFD_RELOC_PPC_DTPMOD 1253@deffnx {} BFD_RELOC_PPC_TPREL16 1254@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1255@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1256@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1257@deffnx {} BFD_RELOC_PPC_TPREL 1258@deffnx {} BFD_RELOC_PPC_DTPREL16 1259@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1260@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1261@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1262@deffnx {} BFD_RELOC_PPC_DTPREL 1263@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1264@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1265@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1266@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1267@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1268@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1269@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1270@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1271@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1272@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1273@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1274@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1275@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1276@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1277@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1278@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1279@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1280@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1281@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1282@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1283@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1284@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1285@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1286@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1287@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1288@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1289@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1290@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1291@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1292@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1293@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1294@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1295@deffnx {} BFD_RELOC_PPC64_TPREL34 1296@deffnx {} BFD_RELOC_PPC64_DTPREL34 1297@deffnx {} BFD_RELOC_PPC64_GOT_TLSGD34 1298@deffnx {} BFD_RELOC_PPC64_GOT_TLSLD34 1299@deffnx {} BFD_RELOC_PPC64_GOT_TPREL34 1300@deffnx {} BFD_RELOC_PPC64_GOT_DTPREL34 1301@deffnx {} BFD_RELOC_PPC64_TLS_PCREL 1302PowerPC and PowerPC64 thread-local storage relocations. 1303@end deffn 1304@deffn {} BFD_RELOC_I370_D12 1305IBM 370/390 relocations 1306@end deffn 1307@deffn {} BFD_RELOC_CTOR 1308The type of reloc used to build a constructor table - at the moment 1309probably a 32 bit wide absolute relocation, but the target can choose. 1310It generally does map to one of the other relocation types. 1311@end deffn 1312@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1313ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1314not stored in the instruction. 1315@end deffn 1316@deffn {} BFD_RELOC_ARM_PCREL_BLX 1317ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1318not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1319field in the instruction. 1320@end deffn 1321@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1322Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1323not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1324field in the instruction. 1325@end deffn 1326@deffn {} BFD_RELOC_ARM_PCREL_CALL 1327ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1328@end deffn 1329@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1330ARM 26-bit pc-relative branch for B or conditional BL instruction. 1331@end deffn 1332@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH5 1333ARM 5-bit pc-relative branch for Branch Future instructions. 1334@end deffn 1335@deffn {} BFD_RELOC_THUMB_PCREL_BFCSEL 1336ARM 6-bit pc-relative branch for BFCSEL instruction. 1337@end deffn 1338@deffn {} BFD_RELOC_ARM_THUMB_BF17 1339ARM 17-bit pc-relative branch for Branch Future instructions. 1340@end deffn 1341@deffn {} BFD_RELOC_ARM_THUMB_BF13 1342ARM 13-bit pc-relative branch for BFCSEL instruction. 1343@end deffn 1344@deffn {} BFD_RELOC_ARM_THUMB_BF19 1345ARM 19-bit pc-relative branch for Branch Future Link instruction. 1346@end deffn 1347@deffn {} BFD_RELOC_ARM_THUMB_LOOP12 1348ARM 12-bit pc-relative branch for Low Overhead Loop instructions. 1349@end deffn 1350@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1351@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1352@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1353@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1354@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1355@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1356Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1357The lowest bit must be zero and is not stored in the instruction. 1358Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1359"nn" one smaller in all cases. Note further that BRANCH23 1360corresponds to R_ARM_THM_CALL. 1361@end deffn 1362@deffn {} BFD_RELOC_ARM_OFFSET_IMM 136312-bit immediate offset, used in ARM-format ldr and str instructions. 1364@end deffn 1365@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13665-bit immediate offset, used in Thumb-format ldr and str instructions. 1367@end deffn 1368@deffn {} BFD_RELOC_ARM_TARGET1 1369Pc-relative or absolute relocation depending on target. Used for 1370entries in .init_array sections. 1371@end deffn 1372@deffn {} BFD_RELOC_ARM_ROSEGREL32 1373Read-only segment base relative address. 1374@end deffn 1375@deffn {} BFD_RELOC_ARM_SBREL32 1376Data segment base relative address. 1377@end deffn 1378@deffn {} BFD_RELOC_ARM_TARGET2 1379This reloc is used for references to RTTI data from exception handling 1380tables. The actual definition depends on the target. It may be a 1381pc-relative or some form of GOT-indirect relocation. 1382@end deffn 1383@deffn {} BFD_RELOC_ARM_PREL31 138431-bit PC relative address. 1385@end deffn 1386@deffn {} BFD_RELOC_ARM_MOVW 1387@deffnx {} BFD_RELOC_ARM_MOVT 1388@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1389@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1390@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1391@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1392@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1393@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1394Low and High halfword relocations for MOVW and MOVT instructions. 1395@end deffn 1396@deffn {} BFD_RELOC_ARM_GOTFUNCDESC 1397@deffnx {} BFD_RELOC_ARM_GOTOFFFUNCDESC 1398@deffnx {} BFD_RELOC_ARM_FUNCDESC 1399@deffnx {} BFD_RELOC_ARM_FUNCDESC_VALUE 1400@deffnx {} BFD_RELOC_ARM_TLS_GD32_FDPIC 1401@deffnx {} BFD_RELOC_ARM_TLS_LDM32_FDPIC 1402@deffnx {} BFD_RELOC_ARM_TLS_IE32_FDPIC 1403ARM FDPIC specific relocations. 1404@end deffn 1405@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1406@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1407@deffnx {} BFD_RELOC_ARM_GOT32 1408@deffnx {} BFD_RELOC_ARM_PLT32 1409@deffnx {} BFD_RELOC_ARM_RELATIVE 1410@deffnx {} BFD_RELOC_ARM_GOTOFF 1411@deffnx {} BFD_RELOC_ARM_GOTPC 1412@deffnx {} BFD_RELOC_ARM_GOT_PREL 1413Relocations for setting up GOTs and PLTs for shared libraries. 1414@end deffn 1415@deffn {} BFD_RELOC_ARM_TLS_GD32 1416@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1417@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1418@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1419@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1420@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1421@deffnx {} BFD_RELOC_ARM_TLS_IE32 1422@deffnx {} BFD_RELOC_ARM_TLS_LE32 1423@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1424@deffnx {} BFD_RELOC_ARM_TLS_CALL 1425@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1426@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1427@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1428@deffnx {} BFD_RELOC_ARM_TLS_DESC 1429ARM thread-local storage relocations. 1430@end deffn 1431@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1432@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1433@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1434@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1435@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1436@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1437@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1438@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1439@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1440@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1441@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1442@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1443@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1444@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1445@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1446@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1447@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1448@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1449@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1450@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1451@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1452@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1453@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1454@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1455@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1456@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1457@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1458@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1459ARM group relocations. 1460@end deffn 1461@deffn {} BFD_RELOC_ARM_V4BX 1462Annotation of BX instructions. 1463@end deffn 1464@deffn {} BFD_RELOC_ARM_IRELATIVE 1465ARM support for STT_GNU_IFUNC. 1466@end deffn 1467@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1468@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1469@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1470@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1471Thumb1 relocations to support execute-only code. 1472@end deffn 1473@deffn {} BFD_RELOC_ARM_IMMEDIATE 1474@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1475@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1476@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1477@deffnx {} BFD_RELOC_ARM_T32_IMM12 1478@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1479@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1480@deffnx {} BFD_RELOC_ARM_SMC 1481@deffnx {} BFD_RELOC_ARM_HVC 1482@deffnx {} BFD_RELOC_ARM_SWI 1483@deffnx {} BFD_RELOC_ARM_MULTI 1484@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1485@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1486@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1487@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1488@deffnx {} BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM 1489@deffnx {} BFD_RELOC_ARM_ADR_IMM 1490@deffnx {} BFD_RELOC_ARM_LDR_IMM 1491@deffnx {} BFD_RELOC_ARM_LITERAL 1492@deffnx {} BFD_RELOC_ARM_IN_POOL 1493@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1494@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1495@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1496@deffnx {} BFD_RELOC_ARM_HWLITERAL 1497@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1498@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1499@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1500These relocs are only used within the ARM assembler. They are not 1501(at present) written to any object files. 1502@end deffn 1503@deffn {} BFD_RELOC_SH_PCDISP8BY2 1504@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1505@deffnx {} BFD_RELOC_SH_IMM3 1506@deffnx {} BFD_RELOC_SH_IMM3U 1507@deffnx {} BFD_RELOC_SH_DISP12 1508@deffnx {} BFD_RELOC_SH_DISP12BY2 1509@deffnx {} BFD_RELOC_SH_DISP12BY4 1510@deffnx {} BFD_RELOC_SH_DISP12BY8 1511@deffnx {} BFD_RELOC_SH_DISP20 1512@deffnx {} BFD_RELOC_SH_DISP20BY8 1513@deffnx {} BFD_RELOC_SH_IMM4 1514@deffnx {} BFD_RELOC_SH_IMM4BY2 1515@deffnx {} BFD_RELOC_SH_IMM4BY4 1516@deffnx {} BFD_RELOC_SH_IMM8 1517@deffnx {} BFD_RELOC_SH_IMM8BY2 1518@deffnx {} BFD_RELOC_SH_IMM8BY4 1519@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1520@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1521@deffnx {} BFD_RELOC_SH_SWITCH16 1522@deffnx {} BFD_RELOC_SH_SWITCH32 1523@deffnx {} BFD_RELOC_SH_USES 1524@deffnx {} BFD_RELOC_SH_COUNT 1525@deffnx {} BFD_RELOC_SH_ALIGN 1526@deffnx {} BFD_RELOC_SH_CODE 1527@deffnx {} BFD_RELOC_SH_DATA 1528@deffnx {} BFD_RELOC_SH_LABEL 1529@deffnx {} BFD_RELOC_SH_LOOP_START 1530@deffnx {} BFD_RELOC_SH_LOOP_END 1531@deffnx {} BFD_RELOC_SH_COPY 1532@deffnx {} BFD_RELOC_SH_GLOB_DAT 1533@deffnx {} BFD_RELOC_SH_JMP_SLOT 1534@deffnx {} BFD_RELOC_SH_RELATIVE 1535@deffnx {} BFD_RELOC_SH_GOTPC 1536@deffnx {} BFD_RELOC_SH_GOT_LOW16 1537@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1538@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1539@deffnx {} BFD_RELOC_SH_GOT_HI16 1540@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1541@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1542@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1543@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1544@deffnx {} BFD_RELOC_SH_PLT_LOW16 1545@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1546@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1547@deffnx {} BFD_RELOC_SH_PLT_HI16 1548@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1549@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1550@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1551@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1552@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1553@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1554@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1555@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1556@deffnx {} BFD_RELOC_SH_COPY64 1557@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1558@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1559@deffnx {} BFD_RELOC_SH_RELATIVE64 1560@deffnx {} BFD_RELOC_SH_GOT10BY4 1561@deffnx {} BFD_RELOC_SH_GOT10BY8 1562@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1563@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1564@deffnx {} BFD_RELOC_SH_GOTPLT32 1565@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1566@deffnx {} BFD_RELOC_SH_IMMU5 1567@deffnx {} BFD_RELOC_SH_IMMS6 1568@deffnx {} BFD_RELOC_SH_IMMS6BY32 1569@deffnx {} BFD_RELOC_SH_IMMU6 1570@deffnx {} BFD_RELOC_SH_IMMS10 1571@deffnx {} BFD_RELOC_SH_IMMS10BY2 1572@deffnx {} BFD_RELOC_SH_IMMS10BY4 1573@deffnx {} BFD_RELOC_SH_IMMS10BY8 1574@deffnx {} BFD_RELOC_SH_IMMS16 1575@deffnx {} BFD_RELOC_SH_IMMU16 1576@deffnx {} BFD_RELOC_SH_IMM_LOW16 1577@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1578@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1579@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1580@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1581@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1582@deffnx {} BFD_RELOC_SH_IMM_HI16 1583@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1584@deffnx {} BFD_RELOC_SH_PT_16 1585@deffnx {} BFD_RELOC_SH_TLS_GD_32 1586@deffnx {} BFD_RELOC_SH_TLS_LD_32 1587@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1588@deffnx {} BFD_RELOC_SH_TLS_IE_32 1589@deffnx {} BFD_RELOC_SH_TLS_LE_32 1590@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1591@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1592@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1593@deffnx {} BFD_RELOC_SH_GOT20 1594@deffnx {} BFD_RELOC_SH_GOTOFF20 1595@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1596@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1597@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1598@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1599@deffnx {} BFD_RELOC_SH_FUNCDESC 1600Renesas / SuperH SH relocs. Not all of these appear in object files. 1601@end deffn 1602@deffn {} BFD_RELOC_ARC_NONE 1603@deffnx {} BFD_RELOC_ARC_8 1604@deffnx {} BFD_RELOC_ARC_16 1605@deffnx {} BFD_RELOC_ARC_24 1606@deffnx {} BFD_RELOC_ARC_32 1607@deffnx {} BFD_RELOC_ARC_N8 1608@deffnx {} BFD_RELOC_ARC_N16 1609@deffnx {} BFD_RELOC_ARC_N24 1610@deffnx {} BFD_RELOC_ARC_N32 1611@deffnx {} BFD_RELOC_ARC_SDA 1612@deffnx {} BFD_RELOC_ARC_SECTOFF 1613@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1614@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1615@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1616@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1617@deffnx {} BFD_RELOC_ARC_SDA32 1618@deffnx {} BFD_RELOC_ARC_SDA_LDST 1619@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1620@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1621@deffnx {} BFD_RELOC_ARC_SDA16_LD 1622@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1623@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1624@deffnx {} BFD_RELOC_ARC_S13_PCREL 1625@deffnx {} BFD_RELOC_ARC_W 1626@deffnx {} BFD_RELOC_ARC_32_ME 1627@deffnx {} BFD_RELOC_ARC_32_ME_S 1628@deffnx {} BFD_RELOC_ARC_N32_ME 1629@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1630@deffnx {} BFD_RELOC_ARC_SDA32_ME 1631@deffnx {} BFD_RELOC_ARC_W_ME 1632@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1633@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1634@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1635@deffnx {} BFD_RELOC_AC_SECTOFF_S9 1636@deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1637@deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1638@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1639@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1640@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1641@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1642@deffnx {} BFD_RELOC_ARC_SDA_12 1643@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1644@deffnx {} BFD_RELOC_ARC_32_PCREL 1645@deffnx {} BFD_RELOC_ARC_PC32 1646@deffnx {} BFD_RELOC_ARC_GOT32 1647@deffnx {} BFD_RELOC_ARC_GOTPC32 1648@deffnx {} BFD_RELOC_ARC_PLT32 1649@deffnx {} BFD_RELOC_ARC_COPY 1650@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1651@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1652@deffnx {} BFD_RELOC_ARC_RELATIVE 1653@deffnx {} BFD_RELOC_ARC_GOTOFF 1654@deffnx {} BFD_RELOC_ARC_GOTPC 1655@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1656@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1657@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1658@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1659@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1660@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1661@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1662@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1663@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1664@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1665@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1666@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1667@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1668@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1669@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1670@deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1671ARC relocs. 1672@end deffn 1673@deffn {} BFD_RELOC_BFIN_16_IMM 1674ADI Blackfin 16 bit immediate absolute reloc. 1675@end deffn 1676@deffn {} BFD_RELOC_BFIN_16_HIGH 1677ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1678@end deffn 1679@deffn {} BFD_RELOC_BFIN_4_PCREL 1680ADI Blackfin 'a' part of LSETUP. 1681@end deffn 1682@deffn {} BFD_RELOC_BFIN_5_PCREL 1683ADI Blackfin. 1684@end deffn 1685@deffn {} BFD_RELOC_BFIN_16_LOW 1686ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1687@end deffn 1688@deffn {} BFD_RELOC_BFIN_10_PCREL 1689ADI Blackfin. 1690@end deffn 1691@deffn {} BFD_RELOC_BFIN_11_PCREL 1692ADI Blackfin 'b' part of LSETUP. 1693@end deffn 1694@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1695ADI Blackfin. 1696@end deffn 1697@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1698ADI Blackfin Short jump, pcrel. 1699@end deffn 1700@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1701ADI Blackfin Call.x not implemented. 1702@end deffn 1703@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1704ADI Blackfin Long Jump pcrel. 1705@end deffn 1706@deffn {} BFD_RELOC_BFIN_GOT17M4 1707@deffnx {} BFD_RELOC_BFIN_GOTHI 1708@deffnx {} BFD_RELOC_BFIN_GOTLO 1709@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1710@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1711@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1712@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1713@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1714@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1715@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1716@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1717@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1718@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1719@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1720ADI Blackfin FD-PIC relocations. 1721@end deffn 1722@deffn {} BFD_RELOC_BFIN_GOT 1723ADI Blackfin GOT relocation. 1724@end deffn 1725@deffn {} BFD_RELOC_BFIN_PLTPC 1726ADI Blackfin PLTPC relocation. 1727@end deffn 1728@deffn {} BFD_ARELOC_BFIN_PUSH 1729ADI Blackfin arithmetic relocation. 1730@end deffn 1731@deffn {} BFD_ARELOC_BFIN_CONST 1732ADI Blackfin arithmetic relocation. 1733@end deffn 1734@deffn {} BFD_ARELOC_BFIN_ADD 1735ADI Blackfin arithmetic relocation. 1736@end deffn 1737@deffn {} BFD_ARELOC_BFIN_SUB 1738ADI Blackfin arithmetic relocation. 1739@end deffn 1740@deffn {} BFD_ARELOC_BFIN_MULT 1741ADI Blackfin arithmetic relocation. 1742@end deffn 1743@deffn {} BFD_ARELOC_BFIN_DIV 1744ADI Blackfin arithmetic relocation. 1745@end deffn 1746@deffn {} BFD_ARELOC_BFIN_MOD 1747ADI Blackfin arithmetic relocation. 1748@end deffn 1749@deffn {} BFD_ARELOC_BFIN_LSHIFT 1750ADI Blackfin arithmetic relocation. 1751@end deffn 1752@deffn {} BFD_ARELOC_BFIN_RSHIFT 1753ADI Blackfin arithmetic relocation. 1754@end deffn 1755@deffn {} BFD_ARELOC_BFIN_AND 1756ADI Blackfin arithmetic relocation. 1757@end deffn 1758@deffn {} BFD_ARELOC_BFIN_OR 1759ADI Blackfin arithmetic relocation. 1760@end deffn 1761@deffn {} BFD_ARELOC_BFIN_XOR 1762ADI Blackfin arithmetic relocation. 1763@end deffn 1764@deffn {} BFD_ARELOC_BFIN_LAND 1765ADI Blackfin arithmetic relocation. 1766@end deffn 1767@deffn {} BFD_ARELOC_BFIN_LOR 1768ADI Blackfin arithmetic relocation. 1769@end deffn 1770@deffn {} BFD_ARELOC_BFIN_LEN 1771ADI Blackfin arithmetic relocation. 1772@end deffn 1773@deffn {} BFD_ARELOC_BFIN_NEG 1774ADI Blackfin arithmetic relocation. 1775@end deffn 1776@deffn {} BFD_ARELOC_BFIN_COMP 1777ADI Blackfin arithmetic relocation. 1778@end deffn 1779@deffn {} BFD_ARELOC_BFIN_PAGE 1780ADI Blackfin arithmetic relocation. 1781@end deffn 1782@deffn {} BFD_ARELOC_BFIN_HWPAGE 1783ADI Blackfin arithmetic relocation. 1784@end deffn 1785@deffn {} BFD_ARELOC_BFIN_ADDR 1786ADI Blackfin arithmetic relocation. 1787@end deffn 1788@deffn {} BFD_RELOC_D10V_10_PCREL_R 1789Mitsubishi D10V relocs. 1790This is a 10-bit reloc with the right 2 bits 1791assumed to be 0. 1792@end deffn 1793@deffn {} BFD_RELOC_D10V_10_PCREL_L 1794Mitsubishi D10V relocs. 1795This is a 10-bit reloc with the right 2 bits 1796assumed to be 0. This is the same as the previous reloc 1797except it is in the left container, i.e., 1798shifted left 15 bits. 1799@end deffn 1800@deffn {} BFD_RELOC_D10V_18 1801This is an 18-bit reloc with the right 2 bits 1802assumed to be 0. 1803@end deffn 1804@deffn {} BFD_RELOC_D10V_18_PCREL 1805This is an 18-bit reloc with the right 2 bits 1806assumed to be 0. 1807@end deffn 1808@deffn {} BFD_RELOC_D30V_6 1809Mitsubishi D30V relocs. 1810This is a 6-bit absolute reloc. 1811@end deffn 1812@deffn {} BFD_RELOC_D30V_9_PCREL 1813This is a 6-bit pc-relative reloc with 1814the right 3 bits assumed to be 0. 1815@end deffn 1816@deffn {} BFD_RELOC_D30V_9_PCREL_R 1817This is a 6-bit pc-relative reloc with 1818the right 3 bits assumed to be 0. Same 1819as the previous reloc but on the right side 1820of the container. 1821@end deffn 1822@deffn {} BFD_RELOC_D30V_15 1823This is a 12-bit absolute reloc with the 1824right 3 bitsassumed to be 0. 1825@end deffn 1826@deffn {} BFD_RELOC_D30V_15_PCREL 1827This is a 12-bit pc-relative reloc with 1828the right 3 bits assumed to be 0. 1829@end deffn 1830@deffn {} BFD_RELOC_D30V_15_PCREL_R 1831This is a 12-bit pc-relative reloc with 1832the right 3 bits assumed to be 0. Same 1833as the previous reloc but on the right side 1834of the container. 1835@end deffn 1836@deffn {} BFD_RELOC_D30V_21 1837This is an 18-bit absolute reloc with 1838the right 3 bits assumed to be 0. 1839@end deffn 1840@deffn {} BFD_RELOC_D30V_21_PCREL 1841This is an 18-bit pc-relative reloc with 1842the right 3 bits assumed to be 0. 1843@end deffn 1844@deffn {} BFD_RELOC_D30V_21_PCREL_R 1845This is an 18-bit pc-relative reloc with 1846the right 3 bits assumed to be 0. Same 1847as the previous reloc but on the right side 1848of the container. 1849@end deffn 1850@deffn {} BFD_RELOC_D30V_32 1851This is a 32-bit absolute reloc. 1852@end deffn 1853@deffn {} BFD_RELOC_D30V_32_PCREL 1854This is a 32-bit pc-relative reloc. 1855@end deffn 1856@deffn {} BFD_RELOC_DLX_HI16_S 1857DLX relocs 1858@end deffn 1859@deffn {} BFD_RELOC_DLX_LO16 1860DLX relocs 1861@end deffn 1862@deffn {} BFD_RELOC_DLX_JMP26 1863DLX relocs 1864@end deffn 1865@deffn {} BFD_RELOC_M32C_HI8 1866@deffnx {} BFD_RELOC_M32C_RL_JUMP 1867@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1868@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1869Renesas M16C/M32C Relocations. 1870@end deffn 1871@deffn {} BFD_RELOC_M32R_24 1872Renesas M32R (formerly Mitsubishi M32R) relocs. 1873This is a 24 bit absolute address. 1874@end deffn 1875@deffn {} BFD_RELOC_M32R_10_PCREL 1876This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1877@end deffn 1878@deffn {} BFD_RELOC_M32R_18_PCREL 1879This is an 18-bit reloc with the right 2 bits assumed to be 0. 1880@end deffn 1881@deffn {} BFD_RELOC_M32R_26_PCREL 1882This is a 26-bit reloc with the right 2 bits assumed to be 0. 1883@end deffn 1884@deffn {} BFD_RELOC_M32R_HI16_ULO 1885This is a 16-bit reloc containing the high 16 bits of an address 1886used when the lower 16 bits are treated as unsigned. 1887@end deffn 1888@deffn {} BFD_RELOC_M32R_HI16_SLO 1889This is a 16-bit reloc containing the high 16 bits of an address 1890used when the lower 16 bits are treated as signed. 1891@end deffn 1892@deffn {} BFD_RELOC_M32R_LO16 1893This is a 16-bit reloc containing the lower 16 bits of an address. 1894@end deffn 1895@deffn {} BFD_RELOC_M32R_SDA16 1896This is a 16-bit reloc containing the small data area offset for use in 1897add3, load, and store instructions. 1898@end deffn 1899@deffn {} BFD_RELOC_M32R_GOT24 1900@deffnx {} BFD_RELOC_M32R_26_PLTREL 1901@deffnx {} BFD_RELOC_M32R_COPY 1902@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1903@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1904@deffnx {} BFD_RELOC_M32R_RELATIVE 1905@deffnx {} BFD_RELOC_M32R_GOTOFF 1906@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1907@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1908@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1909@deffnx {} BFD_RELOC_M32R_GOTPC24 1910@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1911@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1912@deffnx {} BFD_RELOC_M32R_GOT16_LO 1913@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1914@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1915@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1916For PIC. 1917@end deffn 1918@deffn {} BFD_RELOC_NDS32_20 1919NDS32 relocs. 1920This is a 20 bit absolute address. 1921@end deffn 1922@deffn {} BFD_RELOC_NDS32_9_PCREL 1923This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1924@end deffn 1925@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1926This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1927@end deffn 1928@deffn {} BFD_RELOC_NDS32_15_PCREL 1929This is an 15-bit reloc with the right 1 bit assumed to be 0. 1930@end deffn 1931@deffn {} BFD_RELOC_NDS32_17_PCREL 1932This is an 17-bit reloc with the right 1 bit assumed to be 0. 1933@end deffn 1934@deffn {} BFD_RELOC_NDS32_25_PCREL 1935This is a 25-bit reloc with the right 1 bit assumed to be 0. 1936@end deffn 1937@deffn {} BFD_RELOC_NDS32_HI20 1938This is a 20-bit reloc containing the high 20 bits of an address 1939used with the lower 12 bits 1940@end deffn 1941@deffn {} BFD_RELOC_NDS32_LO12S3 1942This is a 12-bit reloc containing the lower 12 bits of an address 1943then shift right by 3. This is used with ldi,sdi... 1944@end deffn 1945@deffn {} BFD_RELOC_NDS32_LO12S2 1946This is a 12-bit reloc containing the lower 12 bits of an address 1947then shift left by 2. This is used with lwi,swi... 1948@end deffn 1949@deffn {} BFD_RELOC_NDS32_LO12S1 1950This is a 12-bit reloc containing the lower 12 bits of an address 1951then shift left by 1. This is used with lhi,shi... 1952@end deffn 1953@deffn {} BFD_RELOC_NDS32_LO12S0 1954This is a 12-bit reloc containing the lower 12 bits of an address 1955then shift left by 0. This is used with lbisbi... 1956@end deffn 1957@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1958This is a 12-bit reloc containing the lower 12 bits of an address 1959then shift left by 0. This is only used with branch relaxations 1960@end deffn 1961@deffn {} BFD_RELOC_NDS32_SDA15S3 1962This is a 15-bit reloc containing the small data area 18-bit signed offset 1963and shift left by 3 for use in ldi, sdi... 1964@end deffn 1965@deffn {} BFD_RELOC_NDS32_SDA15S2 1966This is a 15-bit reloc containing the small data area 17-bit signed offset 1967and shift left by 2 for use in lwi, swi... 1968@end deffn 1969@deffn {} BFD_RELOC_NDS32_SDA15S1 1970This is a 15-bit reloc containing the small data area 16-bit signed offset 1971and shift left by 1 for use in lhi, shi... 1972@end deffn 1973@deffn {} BFD_RELOC_NDS32_SDA15S0 1974This is a 15-bit reloc containing the small data area 15-bit signed offset 1975and shift left by 0 for use in lbi, sbi... 1976@end deffn 1977@deffn {} BFD_RELOC_NDS32_SDA16S3 1978This is a 16-bit reloc containing the small data area 16-bit signed offset 1979and shift left by 3 1980@end deffn 1981@deffn {} BFD_RELOC_NDS32_SDA17S2 1982This is a 17-bit reloc containing the small data area 17-bit signed offset 1983and shift left by 2 for use in lwi.gp, swi.gp... 1984@end deffn 1985@deffn {} BFD_RELOC_NDS32_SDA18S1 1986This is a 18-bit reloc containing the small data area 18-bit signed offset 1987and shift left by 1 for use in lhi.gp, shi.gp... 1988@end deffn 1989@deffn {} BFD_RELOC_NDS32_SDA19S0 1990This is a 19-bit reloc containing the small data area 19-bit signed offset 1991and shift left by 0 for use in lbi.gp, sbi.gp... 1992@end deffn 1993@deffn {} BFD_RELOC_NDS32_GOT20 1994@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1995@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1996@deffnx {} BFD_RELOC_NDS32_COPY 1997@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1998@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1999@deffnx {} BFD_RELOC_NDS32_RELATIVE 2000@deffnx {} BFD_RELOC_NDS32_GOTOFF 2001@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 2002@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 2003@deffnx {} BFD_RELOC_NDS32_GOTPC20 2004@deffnx {} BFD_RELOC_NDS32_GOT_HI20 2005@deffnx {} BFD_RELOC_NDS32_GOT_LO12 2006@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 2007@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 2008for PIC 2009@end deffn 2010@deffn {} BFD_RELOC_NDS32_INSN16 2011@deffnx {} BFD_RELOC_NDS32_LABEL 2012@deffnx {} BFD_RELOC_NDS32_LONGCALL1 2013@deffnx {} BFD_RELOC_NDS32_LONGCALL2 2014@deffnx {} BFD_RELOC_NDS32_LONGCALL3 2015@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 2016@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 2017@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 2018@deffnx {} BFD_RELOC_NDS32_LOADSTORE 2019@deffnx {} BFD_RELOC_NDS32_9_FIXED 2020@deffnx {} BFD_RELOC_NDS32_15_FIXED 2021@deffnx {} BFD_RELOC_NDS32_17_FIXED 2022@deffnx {} BFD_RELOC_NDS32_25_FIXED 2023@deffnx {} BFD_RELOC_NDS32_LONGCALL4 2024@deffnx {} BFD_RELOC_NDS32_LONGCALL5 2025@deffnx {} BFD_RELOC_NDS32_LONGCALL6 2026@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 2027@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 2028@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 2029@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 2030for relax 2031@end deffn 2032@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 2033@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 2034@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 2035@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 2036for PIC 2037@end deffn 2038@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 2039@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 2040@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 2041@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 2042for floating point 2043@end deffn 2044@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 2045@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 2046@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 2047for dwarf2 debug_line. 2048@end deffn 2049@deffn {} BFD_RELOC_NDS32_UPDATE_TA 2050for eliminate 16-bit instructions 2051@end deffn 2052@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2053@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2054@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2055@deffnx {} BFD_RELOC_NDS32_GOT_LO15 2056@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2057@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2058@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2059@deffnx {} BFD_RELOC_NDS32_GOT15S2 2060@deffnx {} BFD_RELOC_NDS32_GOT17S2 2061for PIC object relaxation 2062@end deffn 2063@deffn {} BFD_RELOC_NDS32_5 2064NDS32 relocs. 2065This is a 5 bit absolute address. 2066@end deffn 2067@deffn {} BFD_RELOC_NDS32_10_UPCREL 2068This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2069@end deffn 2070@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2071If fp were omitted, fp can used as another gp. 2072@end deffn 2073@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2074@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2075@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2076@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2077@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2078@deffnx {} BFD_RELOC_NDS32_PTR 2079@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2080@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2081@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2082@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2083@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2084@deffnx {} BFD_RELOC_NDS32_MINUEND 2085@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2086@deffnx {} BFD_RELOC_NDS32_DIFF8 2087@deffnx {} BFD_RELOC_NDS32_DIFF16 2088@deffnx {} BFD_RELOC_NDS32_DIFF32 2089@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2090@deffnx {} BFD_RELOC_NDS32_EMPTY 2091relaxation relative relocation types 2092@end deffn 2093@deffn {} BFD_RELOC_NDS32_25_ABS 2094This is a 25 bit absolute address. 2095@end deffn 2096@deffn {} BFD_RELOC_NDS32_DATA 2097@deffnx {} BFD_RELOC_NDS32_TRAN 2098@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2099@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2100For ex9 and ifc using. 2101@end deffn 2102@deffn {} BFD_RELOC_NDS32_TPOFF 2103@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2104@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2105@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2106@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2107@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2108@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2109@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2110@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2111@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2112@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2113@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12 2114@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2115@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_HI20 2116@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12 2117@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12S2 2118@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LW 2119@deffnx {} BFD_RELOC_NDS32_TLS_DESC 2120@deffnx {} BFD_RELOC_NDS32_TLS_DESC_HI20 2121@deffnx {} BFD_RELOC_NDS32_TLS_DESC_LO12 2122@deffnx {} BFD_RELOC_NDS32_TLS_DESC_20 2123@deffnx {} BFD_RELOC_NDS32_TLS_DESC_SDA17S2 2124@deffnx {} BFD_RELOC_NDS32_TLS_DESC_ADD 2125@deffnx {} BFD_RELOC_NDS32_TLS_DESC_FUNC 2126@deffnx {} BFD_RELOC_NDS32_TLS_DESC_CALL 2127@deffnx {} BFD_RELOC_NDS32_TLS_DESC_MEM 2128@deffnx {} BFD_RELOC_NDS32_REMOVE 2129@deffnx {} BFD_RELOC_NDS32_GROUP 2130For TLS. 2131@end deffn 2132@deffn {} BFD_RELOC_NDS32_LSI 2133For floating load store relaxation. 2134@end deffn 2135@deffn {} BFD_RELOC_V850_9_PCREL 2136This is a 9-bit reloc 2137@end deffn 2138@deffn {} BFD_RELOC_V850_22_PCREL 2139This is a 22-bit reloc 2140@end deffn 2141@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2142This is a 16 bit offset from the short data area pointer. 2143@end deffn 2144@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2145This is a 16 bit offset (of which only 15 bits are used) from the 2146short data area pointer. 2147@end deffn 2148@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2149This is a 16 bit offset from the zero data area pointer. 2150@end deffn 2151@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2152This is a 16 bit offset (of which only 15 bits are used) from the 2153zero data area pointer. 2154@end deffn 2155@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2156This is an 8 bit offset (of which only 6 bits are used) from the 2157tiny data area pointer. 2158@end deffn 2159@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2160This is an 8bit offset (of which only 7 bits are used) from the tiny 2161data area pointer. 2162@end deffn 2163@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2164This is a 7 bit offset from the tiny data area pointer. 2165@end deffn 2166@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2167This is a 16 bit offset from the tiny data area pointer. 2168@end deffn 2169@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2170This is a 5 bit offset (of which only 4 bits are used) from the tiny 2171data area pointer. 2172@end deffn 2173@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2174This is a 4 bit offset from the tiny data area pointer. 2175@end deffn 2176@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2177This is a 16 bit offset from the short data area pointer, with the 2178bits placed non-contiguously in the instruction. 2179@end deffn 2180@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2181This is a 16 bit offset from the zero data area pointer, with the 2182bits placed non-contiguously in the instruction. 2183@end deffn 2184@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2185This is a 6 bit offset from the call table base pointer. 2186@end deffn 2187@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2188This is a 16 bit offset from the call table base pointer. 2189@end deffn 2190@deffn {} BFD_RELOC_V850_LONGCALL 2191Used for relaxing indirect function calls. 2192@end deffn 2193@deffn {} BFD_RELOC_V850_LONGJUMP 2194Used for relaxing indirect jumps. 2195@end deffn 2196@deffn {} BFD_RELOC_V850_ALIGN 2197Used to maintain alignment whilst relaxing. 2198@end deffn 2199@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2200This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2201instructions. 2202@end deffn 2203@deffn {} BFD_RELOC_V850_16_PCREL 2204This is a 16-bit reloc. 2205@end deffn 2206@deffn {} BFD_RELOC_V850_17_PCREL 2207This is a 17-bit reloc. 2208@end deffn 2209@deffn {} BFD_RELOC_V850_23 2210This is a 23-bit reloc. 2211@end deffn 2212@deffn {} BFD_RELOC_V850_32_PCREL 2213This is a 32-bit reloc. 2214@end deffn 2215@deffn {} BFD_RELOC_V850_32_ABS 2216This is a 32-bit reloc. 2217@end deffn 2218@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2219This is a 16-bit reloc. 2220@end deffn 2221@deffn {} BFD_RELOC_V850_16_S1 2222This is a 16-bit reloc. 2223@end deffn 2224@deffn {} BFD_RELOC_V850_LO16_S1 2225Low 16 bits. 16 bit shifted by 1. 2226@end deffn 2227@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2228This is a 16 bit offset from the call table base pointer. 2229@end deffn 2230@deffn {} BFD_RELOC_V850_32_GOTPCREL 2231DSO relocations. 2232@end deffn 2233@deffn {} BFD_RELOC_V850_16_GOT 2234DSO relocations. 2235@end deffn 2236@deffn {} BFD_RELOC_V850_32_GOT 2237DSO relocations. 2238@end deffn 2239@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2240DSO relocations. 2241@end deffn 2242@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2243DSO relocations. 2244@end deffn 2245@deffn {} BFD_RELOC_V850_COPY 2246DSO relocations. 2247@end deffn 2248@deffn {} BFD_RELOC_V850_GLOB_DAT 2249DSO relocations. 2250@end deffn 2251@deffn {} BFD_RELOC_V850_JMP_SLOT 2252DSO relocations. 2253@end deffn 2254@deffn {} BFD_RELOC_V850_RELATIVE 2255DSO relocations. 2256@end deffn 2257@deffn {} BFD_RELOC_V850_16_GOTOFF 2258DSO relocations. 2259@end deffn 2260@deffn {} BFD_RELOC_V850_32_GOTOFF 2261DSO relocations. 2262@end deffn 2263@deffn {} BFD_RELOC_V850_CODE 2264start code. 2265@end deffn 2266@deffn {} BFD_RELOC_V850_DATA 2267start data in text. 2268@end deffn 2269@deffn {} BFD_RELOC_TIC30_LDP 2270This is a 8bit DP reloc for the tms320c30, where the most 2271significant 8 bits of a 24 bit word are placed into the least 2272significant 8 bits of the opcode. 2273@end deffn 2274@deffn {} BFD_RELOC_TIC54X_PARTLS7 2275This is a 7bit reloc for the tms320c54x, where the least 2276significant 7 bits of a 16 bit word are placed into the least 2277significant 7 bits of the opcode. 2278@end deffn 2279@deffn {} BFD_RELOC_TIC54X_PARTMS9 2280This is a 9bit DP reloc for the tms320c54x, where the most 2281significant 9 bits of a 16 bit word are placed into the least 2282significant 9 bits of the opcode. 2283@end deffn 2284@deffn {} BFD_RELOC_TIC54X_23 2285This is an extended address 23-bit reloc for the tms320c54x. 2286@end deffn 2287@deffn {} BFD_RELOC_TIC54X_16_OF_23 2288This is a 16-bit reloc for the tms320c54x, where the least 2289significant 16 bits of a 23-bit extended address are placed into 2290the opcode. 2291@end deffn 2292@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2293This is a reloc for the tms320c54x, where the most 2294significant 7 bits of a 23-bit extended address are placed into 2295the opcode. 2296@end deffn 2297@deffn {} BFD_RELOC_C6000_PCR_S21 2298@deffnx {} BFD_RELOC_C6000_PCR_S12 2299@deffnx {} BFD_RELOC_C6000_PCR_S10 2300@deffnx {} BFD_RELOC_C6000_PCR_S7 2301@deffnx {} BFD_RELOC_C6000_ABS_S16 2302@deffnx {} BFD_RELOC_C6000_ABS_L16 2303@deffnx {} BFD_RELOC_C6000_ABS_H16 2304@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2305@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2306@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2307@deffnx {} BFD_RELOC_C6000_SBR_S16 2308@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2309@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2310@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2311@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2312@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2313@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2314@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2315@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2316@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2317@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2318@deffnx {} BFD_RELOC_C6000_PREL31 2319@deffnx {} BFD_RELOC_C6000_COPY 2320@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2321@deffnx {} BFD_RELOC_C6000_EHTYPE 2322@deffnx {} BFD_RELOC_C6000_PCR_H16 2323@deffnx {} BFD_RELOC_C6000_PCR_L16 2324@deffnx {} BFD_RELOC_C6000_ALIGN 2325@deffnx {} BFD_RELOC_C6000_FPHEAD 2326@deffnx {} BFD_RELOC_C6000_NOCMP 2327TMS320C6000 relocations. 2328@end deffn 2329@deffn {} BFD_RELOC_FR30_48 2330This is a 48 bit reloc for the FR30 that stores 32 bits. 2331@end deffn 2332@deffn {} BFD_RELOC_FR30_20 2333This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2334two sections. 2335@end deffn 2336@deffn {} BFD_RELOC_FR30_6_IN_4 2337This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 23384 bits. 2339@end deffn 2340@deffn {} BFD_RELOC_FR30_8_IN_8 2341This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2342into 8 bits. 2343@end deffn 2344@deffn {} BFD_RELOC_FR30_9_IN_8 2345This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2346into 8 bits. 2347@end deffn 2348@deffn {} BFD_RELOC_FR30_10_IN_8 2349This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2350into 8 bits. 2351@end deffn 2352@deffn {} BFD_RELOC_FR30_9_PCREL 2353This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2354short offset into 8 bits. 2355@end deffn 2356@deffn {} BFD_RELOC_FR30_12_PCREL 2357This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2358short offset into 11 bits. 2359@end deffn 2360@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2361@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2362@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2363@deffnx {} BFD_RELOC_MCORE_PCREL_32 2364@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2365@deffnx {} BFD_RELOC_MCORE_RVA 2366Motorola Mcore relocations. 2367@end deffn 2368@deffn {} BFD_RELOC_MEP_8 2369@deffnx {} BFD_RELOC_MEP_16 2370@deffnx {} BFD_RELOC_MEP_32 2371@deffnx {} BFD_RELOC_MEP_PCREL8A2 2372@deffnx {} BFD_RELOC_MEP_PCREL12A2 2373@deffnx {} BFD_RELOC_MEP_PCREL17A2 2374@deffnx {} BFD_RELOC_MEP_PCREL24A2 2375@deffnx {} BFD_RELOC_MEP_PCABS24A2 2376@deffnx {} BFD_RELOC_MEP_LOW16 2377@deffnx {} BFD_RELOC_MEP_HI16U 2378@deffnx {} BFD_RELOC_MEP_HI16S 2379@deffnx {} BFD_RELOC_MEP_GPREL 2380@deffnx {} BFD_RELOC_MEP_TPREL 2381@deffnx {} BFD_RELOC_MEP_TPREL7 2382@deffnx {} BFD_RELOC_MEP_TPREL7A2 2383@deffnx {} BFD_RELOC_MEP_TPREL7A4 2384@deffnx {} BFD_RELOC_MEP_UIMM24 2385@deffnx {} BFD_RELOC_MEP_ADDR24A4 2386@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2387@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2388Toshiba Media Processor Relocations. 2389@end deffn 2390@deffn {} BFD_RELOC_METAG_HIADDR16 2391@deffnx {} BFD_RELOC_METAG_LOADDR16 2392@deffnx {} BFD_RELOC_METAG_RELBRANCH 2393@deffnx {} BFD_RELOC_METAG_GETSETOFF 2394@deffnx {} BFD_RELOC_METAG_HIOG 2395@deffnx {} BFD_RELOC_METAG_LOOG 2396@deffnx {} BFD_RELOC_METAG_REL8 2397@deffnx {} BFD_RELOC_METAG_REL16 2398@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2399@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2400@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2401@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2402@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2403@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2404@deffnx {} BFD_RELOC_METAG_HI16_PLT 2405@deffnx {} BFD_RELOC_METAG_LO16_PLT 2406@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2407@deffnx {} BFD_RELOC_METAG_GOTOFF 2408@deffnx {} BFD_RELOC_METAG_PLT 2409@deffnx {} BFD_RELOC_METAG_COPY 2410@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2411@deffnx {} BFD_RELOC_METAG_RELATIVE 2412@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2413@deffnx {} BFD_RELOC_METAG_TLS_GD 2414@deffnx {} BFD_RELOC_METAG_TLS_LDM 2415@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2416@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2417@deffnx {} BFD_RELOC_METAG_TLS_LDO 2418@deffnx {} BFD_RELOC_METAG_TLS_IE 2419@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2420@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2421@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2422@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2423@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2424@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2425@deffnx {} BFD_RELOC_METAG_TLS_LE 2426@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2427@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2428Imagination Technologies Meta relocations. 2429@end deffn 2430@deffn {} BFD_RELOC_MMIX_GETA 2431@deffnx {} BFD_RELOC_MMIX_GETA_1 2432@deffnx {} BFD_RELOC_MMIX_GETA_2 2433@deffnx {} BFD_RELOC_MMIX_GETA_3 2434These are relocations for the GETA instruction. 2435@end deffn 2436@deffn {} BFD_RELOC_MMIX_CBRANCH 2437@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2438@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2439@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2440@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2441These are relocations for a conditional branch instruction. 2442@end deffn 2443@deffn {} BFD_RELOC_MMIX_PUSHJ 2444@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2445@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2446@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2447@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2448These are relocations for the PUSHJ instruction. 2449@end deffn 2450@deffn {} BFD_RELOC_MMIX_JMP 2451@deffnx {} BFD_RELOC_MMIX_JMP_1 2452@deffnx {} BFD_RELOC_MMIX_JMP_2 2453@deffnx {} BFD_RELOC_MMIX_JMP_3 2454These are relocations for the JMP instruction. 2455@end deffn 2456@deffn {} BFD_RELOC_MMIX_ADDR19 2457This is a relocation for a relative address as in a GETA instruction or 2458a branch. 2459@end deffn 2460@deffn {} BFD_RELOC_MMIX_ADDR27 2461This is a relocation for a relative address as in a JMP instruction. 2462@end deffn 2463@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2464This is a relocation for an instruction field that may be a general 2465register or a value 0..255. 2466@end deffn 2467@deffn {} BFD_RELOC_MMIX_REG 2468This is a relocation for an instruction field that may be a general 2469register. 2470@end deffn 2471@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2472This is a relocation for two instruction fields holding a register and 2473an offset, the equivalent of the relocation. 2474@end deffn 2475@deffn {} BFD_RELOC_MMIX_LOCAL 2476This relocation is an assertion that the expression is not allocated as 2477a global register. It does not modify contents. 2478@end deffn 2479@deffn {} BFD_RELOC_AVR_7_PCREL 2480This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2481short offset into 7 bits. 2482@end deffn 2483@deffn {} BFD_RELOC_AVR_13_PCREL 2484This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2485short offset into 12 bits. 2486@end deffn 2487@deffn {} BFD_RELOC_AVR_16_PM 2488This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2489program memory address) into 16 bits. 2490@end deffn 2491@deffn {} BFD_RELOC_AVR_LO8_LDI 2492This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2493data memory address) into 8 bit immediate value of LDI insn. 2494@end deffn 2495@deffn {} BFD_RELOC_AVR_HI8_LDI 2496This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2497of data memory address) into 8 bit immediate value of LDI insn. 2498@end deffn 2499@deffn {} BFD_RELOC_AVR_HH8_LDI 2500This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2501of program memory address) into 8 bit immediate value of LDI insn. 2502@end deffn 2503@deffn {} BFD_RELOC_AVR_MS8_LDI 2504This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2505of 32 bit value) into 8 bit immediate value of LDI insn. 2506@end deffn 2507@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2508This is a 16 bit reloc for the AVR that stores negated 8 bit value 2509(usually data memory address) into 8 bit immediate value of SUBI insn. 2510@end deffn 2511@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2512This is a 16 bit reloc for the AVR that stores negated 8 bit value 2513(high 8 bit of data memory address) into 8 bit immediate value of 2514SUBI insn. 2515@end deffn 2516@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2517This is a 16 bit reloc for the AVR that stores negated 8 bit value 2518(most high 8 bit of program memory address) into 8 bit immediate value 2519of LDI or SUBI insn. 2520@end deffn 2521@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2522This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2523of 32 bit value) into 8 bit immediate value of LDI insn. 2524@end deffn 2525@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2526This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2527command address) into 8 bit immediate value of LDI insn. 2528@end deffn 2529@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2530This is a 16 bit reloc for the AVR that stores 8 bit value 2531(command address) into 8 bit immediate value of LDI insn. If the address 2532is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2533in the lower 128k. 2534@end deffn 2535@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2536This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2537of command address) into 8 bit immediate value of LDI insn. 2538@end deffn 2539@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2540This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2541of command address) into 8 bit immediate value of LDI insn. If the address 2542is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2543below 128k. 2544@end deffn 2545@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2546This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2547of command address) into 8 bit immediate value of LDI insn. 2548@end deffn 2549@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2550This is a 16 bit reloc for the AVR that stores negated 8 bit value 2551(usually command address) into 8 bit immediate value of SUBI insn. 2552@end deffn 2553@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2554This is a 16 bit reloc for the AVR that stores negated 8 bit value 2555(high 8 bit of 16 bit command address) into 8 bit immediate value 2556of SUBI insn. 2557@end deffn 2558@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2559This is a 16 bit reloc for the AVR that stores negated 8 bit value 2560(high 6 bit of 22 bit command address) into 8 bit immediate 2561value of SUBI insn. 2562@end deffn 2563@deffn {} BFD_RELOC_AVR_CALL 2564This is a 32 bit reloc for the AVR that stores 23 bit value 2565into 22 bits. 2566@end deffn 2567@deffn {} BFD_RELOC_AVR_LDI 2568This is a 16 bit reloc for the AVR that stores all needed bits 2569for absolute addressing with ldi with overflow check to linktime 2570@end deffn 2571@deffn {} BFD_RELOC_AVR_6 2572This is a 6 bit reloc for the AVR that stores offset for ldd/std 2573instructions 2574@end deffn 2575@deffn {} BFD_RELOC_AVR_6_ADIW 2576This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2577instructions 2578@end deffn 2579@deffn {} BFD_RELOC_AVR_8_LO 2580This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2581in .byte lo8(symbol) 2582@end deffn 2583@deffn {} BFD_RELOC_AVR_8_HI 2584This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2585in .byte hi8(symbol) 2586@end deffn 2587@deffn {} BFD_RELOC_AVR_8_HLO 2588This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2589in .byte hlo8(symbol) 2590@end deffn 2591@deffn {} BFD_RELOC_AVR_DIFF8 2592@deffnx {} BFD_RELOC_AVR_DIFF16 2593@deffnx {} BFD_RELOC_AVR_DIFF32 2594AVR relocations to mark the difference of two local symbols. 2595These are only needed to support linker relaxation and can be ignored 2596when not relaxing. The field is set to the value of the difference 2597assuming no relaxation. The relocation encodes the position of the 2598second symbol so the linker can determine whether to adjust the field 2599value. 2600@end deffn 2601@deffn {} BFD_RELOC_AVR_LDS_STS_16 2602This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2603lds and sts instructions supported only tiny core. 2604@end deffn 2605@deffn {} BFD_RELOC_AVR_PORT6 2606This is a 6 bit reloc for the AVR that stores an I/O register 2607number for the IN and OUT instructions 2608@end deffn 2609@deffn {} BFD_RELOC_AVR_PORT5 2610This is a 5 bit reloc for the AVR that stores an I/O register 2611number for the SBIC, SBIS, SBI and CBI instructions 2612@end deffn 2613@deffn {} BFD_RELOC_RISCV_HI20 2614@deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2615@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2616@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2617@deffnx {} BFD_RELOC_RISCV_LO12_I 2618@deffnx {} BFD_RELOC_RISCV_LO12_S 2619@deffnx {} BFD_RELOC_RISCV_GPREL12_I 2620@deffnx {} BFD_RELOC_RISCV_GPREL12_S 2621@deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2622@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2623@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2624@deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2625@deffnx {} BFD_RELOC_RISCV_CALL 2626@deffnx {} BFD_RELOC_RISCV_CALL_PLT 2627@deffnx {} BFD_RELOC_RISCV_ADD8 2628@deffnx {} BFD_RELOC_RISCV_ADD16 2629@deffnx {} BFD_RELOC_RISCV_ADD32 2630@deffnx {} BFD_RELOC_RISCV_ADD64 2631@deffnx {} BFD_RELOC_RISCV_SUB8 2632@deffnx {} BFD_RELOC_RISCV_SUB16 2633@deffnx {} BFD_RELOC_RISCV_SUB32 2634@deffnx {} BFD_RELOC_RISCV_SUB64 2635@deffnx {} BFD_RELOC_RISCV_GOT_HI20 2636@deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2637@deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2638@deffnx {} BFD_RELOC_RISCV_JMP 2639@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2640@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2641@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2642@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2643@deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2644@deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2645@deffnx {} BFD_RELOC_RISCV_ALIGN 2646@deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2647@deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2648@deffnx {} BFD_RELOC_RISCV_RVC_LUI 2649@deffnx {} BFD_RELOC_RISCV_GPREL_I 2650@deffnx {} BFD_RELOC_RISCV_GPREL_S 2651@deffnx {} BFD_RELOC_RISCV_TPREL_I 2652@deffnx {} BFD_RELOC_RISCV_TPREL_S 2653@deffnx {} BFD_RELOC_RISCV_RELAX 2654@deffnx {} BFD_RELOC_RISCV_CFA 2655@deffnx {} BFD_RELOC_RISCV_SUB6 2656@deffnx {} BFD_RELOC_RISCV_SET6 2657@deffnx {} BFD_RELOC_RISCV_SET8 2658@deffnx {} BFD_RELOC_RISCV_SET16 2659@deffnx {} BFD_RELOC_RISCV_SET32 2660@deffnx {} BFD_RELOC_RISCV_32_PCREL 2661RISC-V relocations. 2662@end deffn 2663@deffn {} BFD_RELOC_RL78_NEG8 2664@deffnx {} BFD_RELOC_RL78_NEG16 2665@deffnx {} BFD_RELOC_RL78_NEG24 2666@deffnx {} BFD_RELOC_RL78_NEG32 2667@deffnx {} BFD_RELOC_RL78_16_OP 2668@deffnx {} BFD_RELOC_RL78_24_OP 2669@deffnx {} BFD_RELOC_RL78_32_OP 2670@deffnx {} BFD_RELOC_RL78_8U 2671@deffnx {} BFD_RELOC_RL78_16U 2672@deffnx {} BFD_RELOC_RL78_24U 2673@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2674@deffnx {} BFD_RELOC_RL78_DIFF 2675@deffnx {} BFD_RELOC_RL78_GPRELB 2676@deffnx {} BFD_RELOC_RL78_GPRELW 2677@deffnx {} BFD_RELOC_RL78_GPRELL 2678@deffnx {} BFD_RELOC_RL78_SYM 2679@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2680@deffnx {} BFD_RELOC_RL78_OP_NEG 2681@deffnx {} BFD_RELOC_RL78_OP_AND 2682@deffnx {} BFD_RELOC_RL78_OP_SHRA 2683@deffnx {} BFD_RELOC_RL78_ABS8 2684@deffnx {} BFD_RELOC_RL78_ABS16 2685@deffnx {} BFD_RELOC_RL78_ABS16_REV 2686@deffnx {} BFD_RELOC_RL78_ABS32 2687@deffnx {} BFD_RELOC_RL78_ABS32_REV 2688@deffnx {} BFD_RELOC_RL78_ABS16U 2689@deffnx {} BFD_RELOC_RL78_ABS16UW 2690@deffnx {} BFD_RELOC_RL78_ABS16UL 2691@deffnx {} BFD_RELOC_RL78_RELAX 2692@deffnx {} BFD_RELOC_RL78_HI16 2693@deffnx {} BFD_RELOC_RL78_HI8 2694@deffnx {} BFD_RELOC_RL78_LO16 2695@deffnx {} BFD_RELOC_RL78_CODE 2696@deffnx {} BFD_RELOC_RL78_SADDR 2697Renesas RL78 Relocations. 2698@end deffn 2699@deffn {} BFD_RELOC_RX_NEG8 2700@deffnx {} BFD_RELOC_RX_NEG16 2701@deffnx {} BFD_RELOC_RX_NEG24 2702@deffnx {} BFD_RELOC_RX_NEG32 2703@deffnx {} BFD_RELOC_RX_16_OP 2704@deffnx {} BFD_RELOC_RX_24_OP 2705@deffnx {} BFD_RELOC_RX_32_OP 2706@deffnx {} BFD_RELOC_RX_8U 2707@deffnx {} BFD_RELOC_RX_16U 2708@deffnx {} BFD_RELOC_RX_24U 2709@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2710@deffnx {} BFD_RELOC_RX_DIFF 2711@deffnx {} BFD_RELOC_RX_GPRELB 2712@deffnx {} BFD_RELOC_RX_GPRELW 2713@deffnx {} BFD_RELOC_RX_GPRELL 2714@deffnx {} BFD_RELOC_RX_SYM 2715@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2716@deffnx {} BFD_RELOC_RX_OP_NEG 2717@deffnx {} BFD_RELOC_RX_ABS8 2718@deffnx {} BFD_RELOC_RX_ABS16 2719@deffnx {} BFD_RELOC_RX_ABS16_REV 2720@deffnx {} BFD_RELOC_RX_ABS32 2721@deffnx {} BFD_RELOC_RX_ABS32_REV 2722@deffnx {} BFD_RELOC_RX_ABS16U 2723@deffnx {} BFD_RELOC_RX_ABS16UW 2724@deffnx {} BFD_RELOC_RX_ABS16UL 2725@deffnx {} BFD_RELOC_RX_RELAX 2726Renesas RX Relocations. 2727@end deffn 2728@deffn {} BFD_RELOC_390_12 2729Direct 12 bit. 2730@end deffn 2731@deffn {} BFD_RELOC_390_GOT12 273212 bit GOT offset. 2733@end deffn 2734@deffn {} BFD_RELOC_390_PLT32 273532 bit PC relative PLT address. 2736@end deffn 2737@deffn {} BFD_RELOC_390_COPY 2738Copy symbol at runtime. 2739@end deffn 2740@deffn {} BFD_RELOC_390_GLOB_DAT 2741Create GOT entry. 2742@end deffn 2743@deffn {} BFD_RELOC_390_JMP_SLOT 2744Create PLT entry. 2745@end deffn 2746@deffn {} BFD_RELOC_390_RELATIVE 2747Adjust by program base. 2748@end deffn 2749@deffn {} BFD_RELOC_390_GOTPC 275032 bit PC relative offset to GOT. 2751@end deffn 2752@deffn {} BFD_RELOC_390_GOT16 275316 bit GOT offset. 2754@end deffn 2755@deffn {} BFD_RELOC_390_PC12DBL 2756PC relative 12 bit shifted by 1. 2757@end deffn 2758@deffn {} BFD_RELOC_390_PLT12DBL 275912 bit PC rel. PLT shifted by 1. 2760@end deffn 2761@deffn {} BFD_RELOC_390_PC16DBL 2762PC relative 16 bit shifted by 1. 2763@end deffn 2764@deffn {} BFD_RELOC_390_PLT16DBL 276516 bit PC rel. PLT shifted by 1. 2766@end deffn 2767@deffn {} BFD_RELOC_390_PC24DBL 2768PC relative 24 bit shifted by 1. 2769@end deffn 2770@deffn {} BFD_RELOC_390_PLT24DBL 277124 bit PC rel. PLT shifted by 1. 2772@end deffn 2773@deffn {} BFD_RELOC_390_PC32DBL 2774PC relative 32 bit shifted by 1. 2775@end deffn 2776@deffn {} BFD_RELOC_390_PLT32DBL 277732 bit PC rel. PLT shifted by 1. 2778@end deffn 2779@deffn {} BFD_RELOC_390_GOTPCDBL 278032 bit PC rel. GOT shifted by 1. 2781@end deffn 2782@deffn {} BFD_RELOC_390_GOT64 278364 bit GOT offset. 2784@end deffn 2785@deffn {} BFD_RELOC_390_PLT64 278664 bit PC relative PLT address. 2787@end deffn 2788@deffn {} BFD_RELOC_390_GOTENT 278932 bit rel. offset to GOT entry. 2790@end deffn 2791@deffn {} BFD_RELOC_390_GOTOFF64 279264 bit offset to GOT. 2793@end deffn 2794@deffn {} BFD_RELOC_390_GOTPLT12 279512-bit offset to symbol-entry within GOT, with PLT handling. 2796@end deffn 2797@deffn {} BFD_RELOC_390_GOTPLT16 279816-bit offset to symbol-entry within GOT, with PLT handling. 2799@end deffn 2800@deffn {} BFD_RELOC_390_GOTPLT32 280132-bit offset to symbol-entry within GOT, with PLT handling. 2802@end deffn 2803@deffn {} BFD_RELOC_390_GOTPLT64 280464-bit offset to symbol-entry within GOT, with PLT handling. 2805@end deffn 2806@deffn {} BFD_RELOC_390_GOTPLTENT 280732-bit rel. offset to symbol-entry within GOT, with PLT handling. 2808@end deffn 2809@deffn {} BFD_RELOC_390_PLTOFF16 281016-bit rel. offset from the GOT to a PLT entry. 2811@end deffn 2812@deffn {} BFD_RELOC_390_PLTOFF32 281332-bit rel. offset from the GOT to a PLT entry. 2814@end deffn 2815@deffn {} BFD_RELOC_390_PLTOFF64 281664-bit rel. offset from the GOT to a PLT entry. 2817@end deffn 2818@deffn {} BFD_RELOC_390_TLS_LOAD 2819@deffnx {} BFD_RELOC_390_TLS_GDCALL 2820@deffnx {} BFD_RELOC_390_TLS_LDCALL 2821@deffnx {} BFD_RELOC_390_TLS_GD32 2822@deffnx {} BFD_RELOC_390_TLS_GD64 2823@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2824@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2825@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2826@deffnx {} BFD_RELOC_390_TLS_LDM32 2827@deffnx {} BFD_RELOC_390_TLS_LDM64 2828@deffnx {} BFD_RELOC_390_TLS_IE32 2829@deffnx {} BFD_RELOC_390_TLS_IE64 2830@deffnx {} BFD_RELOC_390_TLS_IEENT 2831@deffnx {} BFD_RELOC_390_TLS_LE32 2832@deffnx {} BFD_RELOC_390_TLS_LE64 2833@deffnx {} BFD_RELOC_390_TLS_LDO32 2834@deffnx {} BFD_RELOC_390_TLS_LDO64 2835@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2836@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2837@deffnx {} BFD_RELOC_390_TLS_TPOFF 2838s390 tls relocations. 2839@end deffn 2840@deffn {} BFD_RELOC_390_20 2841@deffnx {} BFD_RELOC_390_GOT20 2842@deffnx {} BFD_RELOC_390_GOTPLT20 2843@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2844Long displacement extension. 2845@end deffn 2846@deffn {} BFD_RELOC_390_IRELATIVE 2847STT_GNU_IFUNC relocation. 2848@end deffn 2849@deffn {} BFD_RELOC_SCORE_GPREL15 2850Score relocations 2851Low 16 bit for load/store 2852@end deffn 2853@deffn {} BFD_RELOC_SCORE_DUMMY2 2854@deffnx {} BFD_RELOC_SCORE_JMP 2855This is a 24-bit reloc with the right 1 bit assumed to be 0 2856@end deffn 2857@deffn {} BFD_RELOC_SCORE_BRANCH 2858This is a 19-bit reloc with the right 1 bit assumed to be 0 2859@end deffn 2860@deffn {} BFD_RELOC_SCORE_IMM30 2861This is a 32-bit reloc for 48-bit instructions. 2862@end deffn 2863@deffn {} BFD_RELOC_SCORE_IMM32 2864This is a 32-bit reloc for 48-bit instructions. 2865@end deffn 2866@deffn {} BFD_RELOC_SCORE16_JMP 2867This is a 11-bit reloc with the right 1 bit assumed to be 0 2868@end deffn 2869@deffn {} BFD_RELOC_SCORE16_BRANCH 2870This is a 8-bit reloc with the right 1 bit assumed to be 0 2871@end deffn 2872@deffn {} BFD_RELOC_SCORE_BCMP 2873This is a 9-bit reloc with the right 1 bit assumed to be 0 2874@end deffn 2875@deffn {} BFD_RELOC_SCORE_GOT15 2876@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2877@deffnx {} BFD_RELOC_SCORE_CALL15 2878@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2879Undocumented Score relocs 2880@end deffn 2881@deffn {} BFD_RELOC_IP2K_FR9 2882Scenix IP2K - 9-bit register number / data address 2883@end deffn 2884@deffn {} BFD_RELOC_IP2K_BANK 2885Scenix IP2K - 4-bit register/data bank number 2886@end deffn 2887@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2888Scenix IP2K - low 13 bits of instruction word address 2889@end deffn 2890@deffn {} BFD_RELOC_IP2K_PAGE3 2891Scenix IP2K - high 3 bits of instruction word address 2892@end deffn 2893@deffn {} BFD_RELOC_IP2K_LO8DATA 2894@deffnx {} BFD_RELOC_IP2K_HI8DATA 2895@deffnx {} BFD_RELOC_IP2K_EX8DATA 2896Scenix IP2K - ext/low/high 8 bits of data address 2897@end deffn 2898@deffn {} BFD_RELOC_IP2K_LO8INSN 2899@deffnx {} BFD_RELOC_IP2K_HI8INSN 2900Scenix IP2K - low/high 8 bits of instruction word address 2901@end deffn 2902@deffn {} BFD_RELOC_IP2K_PC_SKIP 2903Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2904@end deffn 2905@deffn {} BFD_RELOC_IP2K_TEXT 2906Scenix IP2K - 16 bit word address in text section. 2907@end deffn 2908@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2909Scenix IP2K - 7-bit sp or dp offset 2910@end deffn 2911@deffn {} BFD_RELOC_VPE4KMATH_DATA 2912@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2913Scenix VPE4K coprocessor - data/insn-space addressing 2914@end deffn 2915@deffn {} BFD_RELOC_VTABLE_INHERIT 2916@deffnx {} BFD_RELOC_VTABLE_ENTRY 2917These two relocations are used by the linker to determine which of 2918the entries in a C++ virtual function table are actually used. When 2919the --gc-sections option is given, the linker will zero out the entries 2920that are not used, so that the code for those functions need not be 2921included in the output. 2922 2923VTABLE_INHERIT is a zero-space relocation used to describe to the 2924linker the inheritance tree of a C++ virtual function table. The 2925relocation's symbol should be the parent class' vtable, and the 2926relocation should be located at the child vtable. 2927 2928VTABLE_ENTRY is a zero-space relocation that describes the use of a 2929virtual function table entry. The reloc's symbol should refer to the 2930table of the class mentioned in the code. Off of that base, an offset 2931describes the entry that is being used. For Rela hosts, this offset 2932is stored in the reloc's addend. For Rel hosts, we are forced to put 2933this offset in the reloc's section offset. 2934@end deffn 2935@deffn {} BFD_RELOC_IA64_IMM14 2936@deffnx {} BFD_RELOC_IA64_IMM22 2937@deffnx {} BFD_RELOC_IA64_IMM64 2938@deffnx {} BFD_RELOC_IA64_DIR32MSB 2939@deffnx {} BFD_RELOC_IA64_DIR32LSB 2940@deffnx {} BFD_RELOC_IA64_DIR64MSB 2941@deffnx {} BFD_RELOC_IA64_DIR64LSB 2942@deffnx {} BFD_RELOC_IA64_GPREL22 2943@deffnx {} BFD_RELOC_IA64_GPREL64I 2944@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2945@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2946@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2947@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2948@deffnx {} BFD_RELOC_IA64_LTOFF22 2949@deffnx {} BFD_RELOC_IA64_LTOFF64I 2950@deffnx {} BFD_RELOC_IA64_PLTOFF22 2951@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2952@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2953@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2954@deffnx {} BFD_RELOC_IA64_FPTR64I 2955@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2956@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2957@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2958@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2959@deffnx {} BFD_RELOC_IA64_PCREL21B 2960@deffnx {} BFD_RELOC_IA64_PCREL21BI 2961@deffnx {} BFD_RELOC_IA64_PCREL21M 2962@deffnx {} BFD_RELOC_IA64_PCREL21F 2963@deffnx {} BFD_RELOC_IA64_PCREL22 2964@deffnx {} BFD_RELOC_IA64_PCREL60B 2965@deffnx {} BFD_RELOC_IA64_PCREL64I 2966@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2967@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2968@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2969@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2970@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2971@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2972@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2973@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2974@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2975@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2976@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2977@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2978@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2979@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2980@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2981@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2982@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2983@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2984@deffnx {} BFD_RELOC_IA64_REL32MSB 2985@deffnx {} BFD_RELOC_IA64_REL32LSB 2986@deffnx {} BFD_RELOC_IA64_REL64MSB 2987@deffnx {} BFD_RELOC_IA64_REL64LSB 2988@deffnx {} BFD_RELOC_IA64_LTV32MSB 2989@deffnx {} BFD_RELOC_IA64_LTV32LSB 2990@deffnx {} BFD_RELOC_IA64_LTV64MSB 2991@deffnx {} BFD_RELOC_IA64_LTV64LSB 2992@deffnx {} BFD_RELOC_IA64_IPLTMSB 2993@deffnx {} BFD_RELOC_IA64_IPLTLSB 2994@deffnx {} BFD_RELOC_IA64_COPY 2995@deffnx {} BFD_RELOC_IA64_LTOFF22X 2996@deffnx {} BFD_RELOC_IA64_LDXMOV 2997@deffnx {} BFD_RELOC_IA64_TPREL14 2998@deffnx {} BFD_RELOC_IA64_TPREL22 2999@deffnx {} BFD_RELOC_IA64_TPREL64I 3000@deffnx {} BFD_RELOC_IA64_TPREL64MSB 3001@deffnx {} BFD_RELOC_IA64_TPREL64LSB 3002@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 3003@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 3004@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 3005@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 3006@deffnx {} BFD_RELOC_IA64_DTPREL14 3007@deffnx {} BFD_RELOC_IA64_DTPREL22 3008@deffnx {} BFD_RELOC_IA64_DTPREL64I 3009@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 3010@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 3011@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 3012@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 3013@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 3014Intel IA64 Relocations. 3015@end deffn 3016@deffn {} BFD_RELOC_M68HC11_HI8 3017Motorola 68HC11 reloc. 3018This is the 8 bit high part of an absolute address. 3019@end deffn 3020@deffn {} BFD_RELOC_M68HC11_LO8 3021Motorola 68HC11 reloc. 3022This is the 8 bit low part of an absolute address. 3023@end deffn 3024@deffn {} BFD_RELOC_M68HC11_3B 3025Motorola 68HC11 reloc. 3026This is the 3 bit of a value. 3027@end deffn 3028@deffn {} BFD_RELOC_M68HC11_RL_JUMP 3029Motorola 68HC11 reloc. 3030This reloc marks the beginning of a jump/call instruction. 3031It is used for linker relaxation to correctly identify beginning 3032of instruction and change some branches to use PC-relative 3033addressing mode. 3034@end deffn 3035@deffn {} BFD_RELOC_M68HC11_RL_GROUP 3036Motorola 68HC11 reloc. 3037This reloc marks a group of several instructions that gcc generates 3038and for which the linker relaxation pass can modify and/or remove 3039some of them. 3040@end deffn 3041@deffn {} BFD_RELOC_M68HC11_LO16 3042Motorola 68HC11 reloc. 3043This is the 16-bit lower part of an address. It is used for 'call' 3044instruction to specify the symbol address without any special 3045transformation (due to memory bank window). 3046@end deffn 3047@deffn {} BFD_RELOC_M68HC11_PAGE 3048Motorola 68HC11 reloc. 3049This is a 8-bit reloc that specifies the page number of an address. 3050It is used by 'call' instruction to specify the page number of 3051the symbol. 3052@end deffn 3053@deffn {} BFD_RELOC_M68HC11_24 3054Motorola 68HC11 reloc. 3055This is a 24-bit reloc that represents the address with a 16-bit 3056value and a 8-bit page number. The symbol address is transformed 3057to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 3058@end deffn 3059@deffn {} BFD_RELOC_M68HC12_5B 3060Motorola 68HC12 reloc. 3061This is the 5 bits of a value. 3062@end deffn 3063@deffn {} BFD_RELOC_XGATE_RL_JUMP 3064Freescale XGATE reloc. 3065This reloc marks the beginning of a bra/jal instruction. 3066@end deffn 3067@deffn {} BFD_RELOC_XGATE_RL_GROUP 3068Freescale XGATE reloc. 3069This reloc marks a group of several instructions that gcc generates 3070and for which the linker relaxation pass can modify and/or remove 3071some of them. 3072@end deffn 3073@deffn {} BFD_RELOC_XGATE_LO16 3074Freescale XGATE reloc. 3075This is the 16-bit lower part of an address. It is used for the '16-bit' 3076instructions. 3077@end deffn 3078@deffn {} BFD_RELOC_XGATE_GPAGE 3079Freescale XGATE reloc. 3080@end deffn 3081@deffn {} BFD_RELOC_XGATE_24 3082Freescale XGATE reloc. 3083@end deffn 3084@deffn {} BFD_RELOC_XGATE_PCREL_9 3085Freescale XGATE reloc. 3086This is a 9-bit pc-relative reloc. 3087@end deffn 3088@deffn {} BFD_RELOC_XGATE_PCREL_10 3089Freescale XGATE reloc. 3090This is a 10-bit pc-relative reloc. 3091@end deffn 3092@deffn {} BFD_RELOC_XGATE_IMM8_LO 3093Freescale XGATE reloc. 3094This is the 16-bit lower part of an address. It is used for the '16-bit' 3095instructions. 3096@end deffn 3097@deffn {} BFD_RELOC_XGATE_IMM8_HI 3098Freescale XGATE reloc. 3099This is the 16-bit higher part of an address. It is used for the '16-bit' 3100instructions. 3101@end deffn 3102@deffn {} BFD_RELOC_XGATE_IMM3 3103Freescale XGATE reloc. 3104This is a 3-bit pc-relative reloc. 3105@end deffn 3106@deffn {} BFD_RELOC_XGATE_IMM4 3107Freescale XGATE reloc. 3108This is a 4-bit pc-relative reloc. 3109@end deffn 3110@deffn {} BFD_RELOC_XGATE_IMM5 3111Freescale XGATE reloc. 3112This is a 5-bit pc-relative reloc. 3113@end deffn 3114@deffn {} BFD_RELOC_M68HC12_9B 3115Motorola 68HC12 reloc. 3116This is the 9 bits of a value. 3117@end deffn 3118@deffn {} BFD_RELOC_M68HC12_16B 3119Motorola 68HC12 reloc. 3120This is the 16 bits of a value. 3121@end deffn 3122@deffn {} BFD_RELOC_M68HC12_9_PCREL 3123Motorola 68HC12/XGATE reloc. 3124This is a PCREL9 branch. 3125@end deffn 3126@deffn {} BFD_RELOC_M68HC12_10_PCREL 3127Motorola 68HC12/XGATE reloc. 3128This is a PCREL10 branch. 3129@end deffn 3130@deffn {} BFD_RELOC_M68HC12_LO8XG 3131Motorola 68HC12/XGATE reloc. 3132This is the 8 bit low part of an absolute address and immediately precedes 3133a matching HI8XG part. 3134@end deffn 3135@deffn {} BFD_RELOC_M68HC12_HI8XG 3136Motorola 68HC12/XGATE reloc. 3137This is the 8 bit high part of an absolute address and immediately follows 3138a matching LO8XG part. 3139@end deffn 3140@deffn {} BFD_RELOC_S12Z_15_PCREL 3141Freescale S12Z reloc. 3142This is a 15 bit relative address. If the most significant bits are all zero 3143then it may be truncated to 8 bits. 3144@end deffn 3145@deffn {} BFD_RELOC_CR16_NUM8 3146@deffnx {} BFD_RELOC_CR16_NUM16 3147@deffnx {} BFD_RELOC_CR16_NUM32 3148@deffnx {} BFD_RELOC_CR16_NUM32a 3149@deffnx {} BFD_RELOC_CR16_REGREL0 3150@deffnx {} BFD_RELOC_CR16_REGREL4 3151@deffnx {} BFD_RELOC_CR16_REGREL4a 3152@deffnx {} BFD_RELOC_CR16_REGREL14 3153@deffnx {} BFD_RELOC_CR16_REGREL14a 3154@deffnx {} BFD_RELOC_CR16_REGREL16 3155@deffnx {} BFD_RELOC_CR16_REGREL20 3156@deffnx {} BFD_RELOC_CR16_REGREL20a 3157@deffnx {} BFD_RELOC_CR16_ABS20 3158@deffnx {} BFD_RELOC_CR16_ABS24 3159@deffnx {} BFD_RELOC_CR16_IMM4 3160@deffnx {} BFD_RELOC_CR16_IMM8 3161@deffnx {} BFD_RELOC_CR16_IMM16 3162@deffnx {} BFD_RELOC_CR16_IMM20 3163@deffnx {} BFD_RELOC_CR16_IMM24 3164@deffnx {} BFD_RELOC_CR16_IMM32 3165@deffnx {} BFD_RELOC_CR16_IMM32a 3166@deffnx {} BFD_RELOC_CR16_DISP4 3167@deffnx {} BFD_RELOC_CR16_DISP8 3168@deffnx {} BFD_RELOC_CR16_DISP16 3169@deffnx {} BFD_RELOC_CR16_DISP20 3170@deffnx {} BFD_RELOC_CR16_DISP24 3171@deffnx {} BFD_RELOC_CR16_DISP24a 3172@deffnx {} BFD_RELOC_CR16_SWITCH8 3173@deffnx {} BFD_RELOC_CR16_SWITCH16 3174@deffnx {} BFD_RELOC_CR16_SWITCH32 3175@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3176@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3177@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3178NS CR16 Relocations. 3179@end deffn 3180@deffn {} BFD_RELOC_CRX_REL4 3181@deffnx {} BFD_RELOC_CRX_REL8 3182@deffnx {} BFD_RELOC_CRX_REL8_CMP 3183@deffnx {} BFD_RELOC_CRX_REL16 3184@deffnx {} BFD_RELOC_CRX_REL24 3185@deffnx {} BFD_RELOC_CRX_REL32 3186@deffnx {} BFD_RELOC_CRX_REGREL12 3187@deffnx {} BFD_RELOC_CRX_REGREL22 3188@deffnx {} BFD_RELOC_CRX_REGREL28 3189@deffnx {} BFD_RELOC_CRX_REGREL32 3190@deffnx {} BFD_RELOC_CRX_ABS16 3191@deffnx {} BFD_RELOC_CRX_ABS32 3192@deffnx {} BFD_RELOC_CRX_NUM8 3193@deffnx {} BFD_RELOC_CRX_NUM16 3194@deffnx {} BFD_RELOC_CRX_NUM32 3195@deffnx {} BFD_RELOC_CRX_IMM16 3196@deffnx {} BFD_RELOC_CRX_IMM32 3197@deffnx {} BFD_RELOC_CRX_SWITCH8 3198@deffnx {} BFD_RELOC_CRX_SWITCH16 3199@deffnx {} BFD_RELOC_CRX_SWITCH32 3200NS CRX Relocations. 3201@end deffn 3202@deffn {} BFD_RELOC_CRIS_BDISP8 3203@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3204@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3205@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3206@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3207@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3208@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3209@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3210@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3211@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3212These relocs are only used within the CRIS assembler. They are not 3213(at present) written to any object files. 3214@end deffn 3215@deffn {} BFD_RELOC_CRIS_COPY 3216@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3217@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3218@deffnx {} BFD_RELOC_CRIS_RELATIVE 3219Relocs used in ELF shared libraries for CRIS. 3220@end deffn 3221@deffn {} BFD_RELOC_CRIS_32_GOT 322232-bit offset to symbol-entry within GOT. 3223@end deffn 3224@deffn {} BFD_RELOC_CRIS_16_GOT 322516-bit offset to symbol-entry within GOT. 3226@end deffn 3227@deffn {} BFD_RELOC_CRIS_32_GOTPLT 322832-bit offset to symbol-entry within GOT, with PLT handling. 3229@end deffn 3230@deffn {} BFD_RELOC_CRIS_16_GOTPLT 323116-bit offset to symbol-entry within GOT, with PLT handling. 3232@end deffn 3233@deffn {} BFD_RELOC_CRIS_32_GOTREL 323432-bit offset to symbol, relative to GOT. 3235@end deffn 3236@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 323732-bit offset to symbol with PLT entry, relative to GOT. 3238@end deffn 3239@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 324032-bit offset to symbol with PLT entry, relative to this relocation. 3241@end deffn 3242@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3243@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3244@deffnx {} BFD_RELOC_CRIS_32_GD 3245@deffnx {} BFD_RELOC_CRIS_DTP 3246@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3247@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3248@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3249@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3250@deffnx {} BFD_RELOC_CRIS_32_TPREL 3251@deffnx {} BFD_RELOC_CRIS_16_TPREL 3252@deffnx {} BFD_RELOC_CRIS_DTPMOD 3253@deffnx {} BFD_RELOC_CRIS_32_IE 3254Relocs used in TLS code for CRIS. 3255@end deffn 3256@deffn {} BFD_RELOC_OR1K_REL_26 3257@deffnx {} BFD_RELOC_OR1K_SLO16 3258@deffnx {} BFD_RELOC_OR1K_PCREL_PG21 3259@deffnx {} BFD_RELOC_OR1K_LO13 3260@deffnx {} BFD_RELOC_OR1K_SLO13 3261@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3262@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3263@deffnx {} BFD_RELOC_OR1K_GOT16 3264@deffnx {} BFD_RELOC_OR1K_GOT_PG21 3265@deffnx {} BFD_RELOC_OR1K_GOT_LO13 3266@deffnx {} BFD_RELOC_OR1K_PLT26 3267@deffnx {} BFD_RELOC_OR1K_PLTA26 3268@deffnx {} BFD_RELOC_OR1K_GOTOFF_SLO16 3269@deffnx {} BFD_RELOC_OR1K_COPY 3270@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3271@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3272@deffnx {} BFD_RELOC_OR1K_RELATIVE 3273@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3274@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3275@deffnx {} BFD_RELOC_OR1K_TLS_GD_PG21 3276@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO13 3277@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3278@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3279@deffnx {} BFD_RELOC_OR1K_TLS_LDM_PG21 3280@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO13 3281@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3282@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3283@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3284@deffnx {} BFD_RELOC_OR1K_TLS_IE_AHI16 3285@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3286@deffnx {} BFD_RELOC_OR1K_TLS_IE_PG21 3287@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO13 3288@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3289@deffnx {} BFD_RELOC_OR1K_TLS_LE_AHI16 3290@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3291@deffnx {} BFD_RELOC_OR1K_TLS_LE_SLO16 3292@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3293@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3294@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3295OpenRISC 1000 Relocations. 3296@end deffn 3297@deffn {} BFD_RELOC_H8_DIR16A8 3298@deffnx {} BFD_RELOC_H8_DIR16R8 3299@deffnx {} BFD_RELOC_H8_DIR24A8 3300@deffnx {} BFD_RELOC_H8_DIR24R8 3301@deffnx {} BFD_RELOC_H8_DIR32A16 3302@deffnx {} BFD_RELOC_H8_DISP32A16 3303H8 elf Relocations. 3304@end deffn 3305@deffn {} BFD_RELOC_XSTORMY16_REL_12 3306@deffnx {} BFD_RELOC_XSTORMY16_12 3307@deffnx {} BFD_RELOC_XSTORMY16_24 3308@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3309Sony Xstormy16 Relocations. 3310@end deffn 3311@deffn {} BFD_RELOC_RELC 3312Self-describing complex relocations. 3313@end deffn 3314@deffn {} BFD_RELOC_XC16X_PAG 3315@deffnx {} BFD_RELOC_XC16X_POF 3316@deffnx {} BFD_RELOC_XC16X_SEG 3317@deffnx {} BFD_RELOC_XC16X_SOF 3318Infineon Relocations. 3319@end deffn 3320@deffn {} BFD_RELOC_VAX_GLOB_DAT 3321@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3322@deffnx {} BFD_RELOC_VAX_RELATIVE 3323Relocations used by VAX ELF. 3324@end deffn 3325@deffn {} BFD_RELOC_MT_PC16 3326Morpho MT - 16 bit immediate relocation. 3327@end deffn 3328@deffn {} BFD_RELOC_MT_HI16 3329Morpho MT - Hi 16 bits of an address. 3330@end deffn 3331@deffn {} BFD_RELOC_MT_LO16 3332Morpho MT - Low 16 bits of an address. 3333@end deffn 3334@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3335Morpho MT - Used to tell the linker which vtable entries are used. 3336@end deffn 3337@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3338Morpho MT - Used to tell the linker which vtable entries are used. 3339@end deffn 3340@deffn {} BFD_RELOC_MT_PCINSN8 3341Morpho MT - 8 bit immediate relocation. 3342@end deffn 3343@deffn {} BFD_RELOC_MSP430_10_PCREL 3344@deffnx {} BFD_RELOC_MSP430_16_PCREL 3345@deffnx {} BFD_RELOC_MSP430_16 3346@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3347@deffnx {} BFD_RELOC_MSP430_16_BYTE 3348@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3349@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3350@deffnx {} BFD_RELOC_MSP430_ABS8 3351@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3352@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3353@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3354@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3355@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3356@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3357@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3358@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3359@deffnx {} BFD_RELOC_MSP430X_PCR16 3360@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3361@deffnx {} BFD_RELOC_MSP430X_ABS16 3362@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3363@deffnx {} BFD_RELOC_MSP430_PREL31 3364@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3365msp430 specific relocation codes 3366@end deffn 3367@deffn {} BFD_RELOC_NIOS2_S16 3368@deffnx {} BFD_RELOC_NIOS2_U16 3369@deffnx {} BFD_RELOC_NIOS2_CALL26 3370@deffnx {} BFD_RELOC_NIOS2_IMM5 3371@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3372@deffnx {} BFD_RELOC_NIOS2_IMM6 3373@deffnx {} BFD_RELOC_NIOS2_IMM8 3374@deffnx {} BFD_RELOC_NIOS2_HI16 3375@deffnx {} BFD_RELOC_NIOS2_LO16 3376@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3377@deffnx {} BFD_RELOC_NIOS2_GPREL 3378@deffnx {} BFD_RELOC_NIOS2_UJMP 3379@deffnx {} BFD_RELOC_NIOS2_CJMP 3380@deffnx {} BFD_RELOC_NIOS2_CALLR 3381@deffnx {} BFD_RELOC_NIOS2_ALIGN 3382@deffnx {} BFD_RELOC_NIOS2_GOT16 3383@deffnx {} BFD_RELOC_NIOS2_CALL16 3384@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3385@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3386@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3387@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3388@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3389@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3390@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3391@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3392@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3393@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3394@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3395@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3396@deffnx {} BFD_RELOC_NIOS2_COPY 3397@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3398@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3399@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3400@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3401@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3402@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3403@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3404@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3405@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3406@deffnx {} BFD_RELOC_NIOS2_R2_S12 3407@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3408@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3409@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3410@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3411@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3412@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3413@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3414@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3415@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3416@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3417@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3418@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3419Relocations used by the Altera Nios II core. 3420@end deffn 3421@deffn {} BFD_RELOC_PRU_U16 3422PRU LDI 16-bit unsigned data-memory relocation. 3423@end deffn 3424@deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3425PRU LDI 16-bit unsigned instruction-memory relocation. 3426@end deffn 3427@deffn {} BFD_RELOC_PRU_LDI32 3428PRU relocation for two consecutive LDI load instructions that load a 342932 bit value into a register. If the higher bits are all zero, then 3430the second instruction may be relaxed. 3431@end deffn 3432@deffn {} BFD_RELOC_PRU_S10_PCREL 3433PRU QBBx 10-bit signed PC-relative relocation. 3434@end deffn 3435@deffn {} BFD_RELOC_PRU_U8_PCREL 3436PRU 8-bit unsigned relocation used for the LOOP instruction. 3437@end deffn 3438@deffn {} BFD_RELOC_PRU_32_PMEM 3439@deffnx {} BFD_RELOC_PRU_16_PMEM 3440PRU Program Memory relocations. Used to convert from byte addressing to 344132-bit word addressing. 3442@end deffn 3443@deffn {} BFD_RELOC_PRU_GNU_DIFF8 3444@deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3445@deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3446@deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3447@deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3448PRU relocations to mark the difference of two local symbols. 3449These are only needed to support linker relaxation and can be ignored 3450when not relaxing. The field is set to the value of the difference 3451assuming no relaxation. The relocation encodes the position of the 3452second symbol so the linker can determine whether to adjust the field 3453value. The PMEM variants encode the word difference, instead of byte 3454difference between symbols. 3455@end deffn 3456@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3457@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3458@deffnx {} BFD_RELOC_IQ2000_UHI16 3459IQ2000 Relocations. 3460@end deffn 3461@deffn {} BFD_RELOC_XTENSA_RTLD 3462Special Xtensa relocation used only by PLT entries in ELF shared 3463objects to indicate that the runtime linker should set the value 3464to one of its own internal functions or data structures. 3465@end deffn 3466@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3467@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3468@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3469Xtensa relocations for ELF shared objects. 3470@end deffn 3471@deffn {} BFD_RELOC_XTENSA_PLT 3472Xtensa relocation used in ELF object files for symbols that may require 3473PLT entries. Otherwise, this is just a generic 32-bit relocation. 3474@end deffn 3475@deffn {} BFD_RELOC_XTENSA_DIFF8 3476@deffnx {} BFD_RELOC_XTENSA_DIFF16 3477@deffnx {} BFD_RELOC_XTENSA_DIFF32 3478Xtensa relocations to mark the difference of two local symbols. 3479These are only needed to support linker relaxation and can be ignored 3480when not relaxing. The field is set to the value of the difference 3481assuming no relaxation. The relocation encodes the position of the 3482first symbol so the linker can determine whether to adjust the field 3483value. 3484@end deffn 3485@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3486@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3487@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3488@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3489@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3490@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3491@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3492@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3493@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3494@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3495@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3496@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3497@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3498@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3499@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3500Generic Xtensa relocations for instruction operands. Only the slot 3501number is encoded in the relocation. The relocation applies to the 3502last PC-relative immediate operand, or if there are no PC-relative 3503immediates, to the last immediate operand. 3504@end deffn 3505@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3506@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3507@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3508@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3509@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3510@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3511@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3512@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3513@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3514@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3515@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3516@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3517@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3518@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3519@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3520Alternate Xtensa relocations. Only the slot is encoded in the 3521relocation. The meaning of these relocations is opcode-specific. 3522@end deffn 3523@deffn {} BFD_RELOC_XTENSA_OP0 3524@deffnx {} BFD_RELOC_XTENSA_OP1 3525@deffnx {} BFD_RELOC_XTENSA_OP2 3526Xtensa relocations for backward compatibility. These have all been 3527replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3528@end deffn 3529@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3530Xtensa relocation to mark that the assembler expanded the 3531instructions from an original target. The expansion size is 3532encoded in the reloc size. 3533@end deffn 3534@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3535Xtensa relocation to mark that the linker should simplify 3536assembler-expanded instructions. This is commonly used 3537internally by the linker after analysis of a 3538BFD_RELOC_XTENSA_ASM_EXPAND. 3539@end deffn 3540@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3541@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3542@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3543@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3544@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3545@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3546@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3547Xtensa TLS relocations. 3548@end deffn 3549@deffn {} BFD_RELOC_Z80_DISP8 35508 bit signed offset in (ix+d) or (iy+d). 3551@end deffn 3552@deffn {} BFD_RELOC_Z80_BYTE0 3553First 8 bits of multibyte (32, 24 or 16 bit) value. 3554@end deffn 3555@deffn {} BFD_RELOC_Z80_BYTE1 3556Second 8 bits of multibyte (32, 24 or 16 bit) value. 3557@end deffn 3558@deffn {} BFD_RELOC_Z80_BYTE2 3559Third 8 bits of multibyte (32 or 24 bit) value. 3560@end deffn 3561@deffn {} BFD_RELOC_Z80_BYTE3 3562Fourth 8 bits of multibyte (32 bit) value. 3563@end deffn 3564@deffn {} BFD_RELOC_Z80_WORD0 3565Lowest 16 bits of multibyte (32 or 24 bit) value. 3566@end deffn 3567@deffn {} BFD_RELOC_Z80_WORD1 3568Highest 16 bits of multibyte (32 or 24 bit) value. 3569@end deffn 3570@deffn {} BFD_RELOC_Z8K_DISP7 3571DJNZ offset. 3572@end deffn 3573@deffn {} BFD_RELOC_Z8K_CALLR 3574CALR offset. 3575@end deffn 3576@deffn {} BFD_RELOC_Z8K_IMM4L 35774 bit value. 3578@end deffn 3579@deffn {} BFD_RELOC_LM32_CALL 3580@deffnx {} BFD_RELOC_LM32_BRANCH 3581@deffnx {} BFD_RELOC_LM32_16_GOT 3582@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3583@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3584@deffnx {} BFD_RELOC_LM32_COPY 3585@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3586@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3587@deffnx {} BFD_RELOC_LM32_RELATIVE 3588Lattice Mico32 relocations. 3589@end deffn 3590@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3591Difference between two section addreses. Must be followed by a 3592BFD_RELOC_MACH_O_PAIR. 3593@end deffn 3594@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3595Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3596@end deffn 3597@deffn {} BFD_RELOC_MACH_O_PAIR 3598Pair of relocation. Contains the first symbol. 3599@end deffn 3600@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3601Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3602@end deffn 3603@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3604Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3605@end deffn 3606@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3607@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3608PCREL relocations. They are marked as branch to create PLT entry if 3609required. 3610@end deffn 3611@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3612Used when referencing a GOT entry. 3613@end deffn 3614@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3615Used when loading a GOT entry with movq. It is specially marked so that 3616the linker could optimize the movq to a leaq if possible. 3617@end deffn 3618@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3619Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3620@end deffn 3621@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3622Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3623@end deffn 3624@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3625Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3626@end deffn 3627@deffn {} BFD_RELOC_MACH_O_X86_64_TLV 3628Used when referencing a TLV entry. 3629@end deffn 3630@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3631Addend for PAGE or PAGEOFF. 3632@end deffn 3633@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3634Relative offset to page of GOT slot. 3635@end deffn 3636@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3637Relative offset within page of GOT slot. 3638@end deffn 3639@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3640Address of a GOT entry. 3641@end deffn 3642@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3643This is a 32 bit reloc for the microblaze that stores the 3644low 16 bits of a value 3645@end deffn 3646@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3647This is a 32 bit pc-relative reloc for the microblaze that 3648stores the low 16 bits of a value 3649@end deffn 3650@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3651This is a 32 bit reloc for the microblaze that stores a 3652value relative to the read-only small data area anchor 3653@end deffn 3654@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3655This is a 32 bit reloc for the microblaze that stores a 3656value relative to the read-write small data area anchor 3657@end deffn 3658@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3659This is a 32 bit reloc for the microblaze to handle 3660expressions of the form "Symbol Op Symbol" 3661@end deffn 3662@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3663This is a 64 bit reloc that stores the 32 bit pc relative 3664value in two words (with an imm instruction). No relocation is 3665done here - only used for relaxing 3666@end deffn 3667@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3668This is a 64 bit reloc that stores the 32 bit pc relative 3669value in two words (with an imm instruction). The relocation is 3670PC-relative GOT offset 3671@end deffn 3672@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3673This is a 64 bit reloc that stores the 32 bit pc relative 3674value in two words (with an imm instruction). The relocation is 3675GOT offset 3676@end deffn 3677@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3678This is a 64 bit reloc that stores the 32 bit pc relative 3679value in two words (with an imm instruction). The relocation is 3680PC-relative offset into PLT 3681@end deffn 3682@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3683This is a 64 bit reloc that stores the 32 bit GOT relative 3684value in two words (with an imm instruction). The relocation is 3685relative offset from _GLOBAL_OFFSET_TABLE_ 3686@end deffn 3687@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3688This is a 32 bit reloc that stores the 32 bit GOT relative 3689value in a word. The relocation is relative offset from 3690@end deffn 3691@deffn {} BFD_RELOC_MICROBLAZE_COPY 3692This is used to tell the dynamic linker to copy the value out of 3693the dynamic object into the runtime process image. 3694@end deffn 3695@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3696Unused Reloc 3697@end deffn 3698@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3699This is a 64 bit reloc that stores the 32 bit GOT relative value 3700of the GOT TLS GD info entry in two words (with an imm instruction). The 3701relocation is GOT offset. 3702@end deffn 3703@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3704This is a 64 bit reloc that stores the 32 bit GOT relative value 3705of the GOT TLS LD info entry in two words (with an imm instruction). The 3706relocation is GOT offset. 3707@end deffn 3708@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3709This is a 32 bit reloc that stores the Module ID to GOT(n). 3710@end deffn 3711@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3712This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3713@end deffn 3714@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3715This is a 32 bit reloc for storing TLS offset to two words (uses imm 3716instruction) 3717@end deffn 3718@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3719This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3720to two words (uses imm instruction). 3721@end deffn 3722@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3723This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3724to two words (uses imm instruction). 3725@end deffn 3726@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTPCREL 3727This is a 64 bit reloc that stores the 32 bit pc relative 3728value in two words (with an imm instruction). The relocation is 3729PC-relative offset from start of TEXT. 3730@end deffn 3731@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTREL 3732This is a 64 bit reloc that stores the 32 bit offset 3733value in two words (with an imm instruction). The relocation is 3734relative offset from start of TEXT. 3735@end deffn 3736@deffn {} BFD_RELOC_AARCH64_RELOC_START 3737AArch64 pseudo relocation code to mark the start of the AArch64 3738relocation enumerators. N.B. the order of the enumerators is 3739important as several tables in the AArch64 bfd backend are indexed 3740by these enumerators; make sure they are all synced. 3741@end deffn 3742@deffn {} BFD_RELOC_AARCH64_NULL 3743Deprecated AArch64 null relocation code. 3744@end deffn 3745@deffn {} BFD_RELOC_AARCH64_NONE 3746AArch64 null relocation code. 3747@end deffn 3748@deffn {} BFD_RELOC_AARCH64_64 3749@deffnx {} BFD_RELOC_AARCH64_32 3750@deffnx {} BFD_RELOC_AARCH64_16 3751Basic absolute relocations of N bits. These are equivalent to 3752BFD_RELOC_N and they were added to assist the indexing of the howto 3753table. 3754@end deffn 3755@deffn {} BFD_RELOC_AARCH64_64_PCREL 3756@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3757@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3758PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3759and they were added to assist the indexing of the howto table. 3760@end deffn 3761@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3762AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3763of an unsigned address/value. 3764@end deffn 3765@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3766AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3767an address/value. No overflow checking. 3768@end deffn 3769@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3770AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3771of an unsigned address/value. 3772@end deffn 3773@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3774AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3775of an address/value. No overflow checking. 3776@end deffn 3777@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3778AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3779of an unsigned address/value. 3780@end deffn 3781@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3782AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3783of an address/value. No overflow checking. 3784@end deffn 3785@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3786AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3787of a signed or unsigned address/value. 3788@end deffn 3789@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3790AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3791of a signed value. Changes instruction to MOVZ or MOVN depending on the 3792value's sign. 3793@end deffn 3794@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3795AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3796of a signed value. Changes instruction to MOVZ or MOVN depending on the 3797value's sign. 3798@end deffn 3799@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3800AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3801of a signed value. Changes instruction to MOVZ or MOVN depending on the 3802value's sign. 3803@end deffn 3804@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0 3805AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3806of a signed value. Changes instruction to MOVZ or MOVN depending on the 3807value's sign. 3808@end deffn 3809@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0_NC 3810AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3811of a signed value. Changes instruction to MOVZ or MOVN depending on the 3812value's sign. 3813@end deffn 3814@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1 3815AArch64 MOVK instruction with most significant bits 16 to 31 3816of a signed value. 3817@end deffn 3818@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1_NC 3819AArch64 MOVK instruction with most significant bits 16 to 31 3820of a signed value. 3821@end deffn 3822@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2 3823AArch64 MOVK instruction with most significant bits 32 to 47 3824of a signed value. 3825@end deffn 3826@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2_NC 3827AArch64 MOVK instruction with most significant bits 32 to 47 3828of a signed value. 3829@end deffn 3830@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G3 3831AArch64 MOVK instruction with most significant bits 47 to 63 3832of a signed value. 3833@end deffn 3834@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3835AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3836offset. The lowest two bits must be zero and are not stored in the 3837instruction, giving a 21 bit signed byte offset. 3838@end deffn 3839@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3840AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3841@end deffn 3842@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3843AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3844offset, giving a 4KB aligned page base address. 3845@end deffn 3846@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3847AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3848offset, giving a 4KB aligned page base address, but with no overflow 3849checking. 3850@end deffn 3851@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3852AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3853Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3854@end deffn 3855@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3856AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3857address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3858@end deffn 3859@deffn {} BFD_RELOC_AARCH64_TSTBR14 3860AArch64 14 bit pc-relative test bit and branch. 3861The lowest two bits must be zero and are not stored in the instruction, 3862giving a 16 bit signed byte offset. 3863@end deffn 3864@deffn {} BFD_RELOC_AARCH64_BRANCH19 3865AArch64 19 bit pc-relative conditional branch and compare & branch. 3866The lowest two bits must be zero and are not stored in the instruction, 3867giving a 21 bit signed byte offset. 3868@end deffn 3869@deffn {} BFD_RELOC_AARCH64_JUMP26 3870AArch64 26 bit pc-relative unconditional branch. 3871The lowest two bits must be zero and are not stored in the instruction, 3872giving a 28 bit signed byte offset. 3873@end deffn 3874@deffn {} BFD_RELOC_AARCH64_CALL26 3875AArch64 26 bit pc-relative unconditional branch and link. 3876The lowest two bits must be zero and are not stored in the instruction, 3877giving a 28 bit signed byte offset. 3878@end deffn 3879@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3880AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3881address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3882@end deffn 3883@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3884AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3885address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3886@end deffn 3887@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3888AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3889address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3890@end deffn 3891@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3892AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3893address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3894@end deffn 3895@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3896AArch64 Load Literal instruction, holding a 19 bit PC relative word 3897offset of the global offset table entry for a symbol. The lowest two 3898bits must be zero and are not stored in the instruction, giving a 21 3899bit signed byte offset. This relocation type requires signed overflow 3900checking. 3901@end deffn 3902@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3903Get to the page base of the global offset table entry for a symbol as 3904part of an ADRP instruction using a 21 bit PC relative value.Used in 3905conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3906@end deffn 3907@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3908Unsigned 12 bit byte offset for 64 bit load/store from the page of 3909the GOT entry for this symbol. Used in conjunction with 3910BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3911@end deffn 3912@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3913Unsigned 12 bit byte offset for 32 bit load/store from the page of 3914the GOT entry for this symbol. Used in conjunction with 3915BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3916@end deffn 3917@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3918Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3919for this symbol. Valid in LP64 ABI only. 3920@end deffn 3921@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3922Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3923for this symbol. Valid in LP64 ABI only. 3924@end deffn 3925@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3926Unsigned 15 bit byte offset for 64 bit load/store from the page of 3927the GOT entry for this symbol. Valid in LP64 ABI only. 3928@end deffn 3929@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3930Scaled 14 bit byte offset to the page base of the global offset table. 3931@end deffn 3932@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3933Scaled 15 bit byte offset to the page base of the global offset table. 3934@end deffn 3935@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3936Get to the page base of the global offset table entry for a symbols 3937tls_index structure as part of an adrp instruction using a 21 bit PC 3938relative value. Used in conjunction with 3939BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3940@end deffn 3941@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3942AArch64 TLS General Dynamic 3943@end deffn 3944@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3945Unsigned 12 bit byte offset to global offset table entry for a symbols 3946tls_index structure. Used in conjunction with 3947BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3948@end deffn 3949@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3950AArch64 TLS General Dynamic relocation. 3951@end deffn 3952@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3953AArch64 TLS General Dynamic relocation. 3954@end deffn 3955@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3956AArch64 TLS INITIAL EXEC relocation. 3957@end deffn 3958@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3959AArch64 TLS INITIAL EXEC relocation. 3960@end deffn 3961@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3962AArch64 TLS INITIAL EXEC relocation. 3963@end deffn 3964@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3965AArch64 TLS INITIAL EXEC relocation. 3966@end deffn 3967@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3968AArch64 TLS INITIAL EXEC relocation. 3969@end deffn 3970@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3971AArch64 TLS INITIAL EXEC relocation. 3972@end deffn 3973@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3974bit[23:12] of byte offset to module TLS base address. 3975@end deffn 3976@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3977Unsigned 12 bit byte offset to module TLS base address. 3978@end deffn 3979@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3980No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3981@end deffn 3982@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3983Unsigned 12 bit byte offset to global offset table entry for a symbols 3984tls_index structure. Used in conjunction with 3985BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3986@end deffn 3987@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3988GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3989instruction. 3990@end deffn 3991@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3992GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 3993@end deffn 3994@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 3995bit[11:1] of byte offset to module TLS base address, encoded in ldst 3996instructions. 3997@end deffn 3998@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 3999Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 4000@end deffn 4001@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 4002bit[11:2] of byte offset to module TLS base address, encoded in ldst 4003instructions. 4004@end deffn 4005@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 4006Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 4007@end deffn 4008@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 4009bit[11:3] of byte offset to module TLS base address, encoded in ldst 4010instructions. 4011@end deffn 4012@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 4013Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 4014@end deffn 4015@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 4016bit[11:0] of byte offset to module TLS base address, encoded in ldst 4017instructions. 4018@end deffn 4019@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 4020Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 4021@end deffn 4022@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4023bit[15:0] of byte offset to module TLS base address. 4024@end deffn 4025@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 4026No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4027@end deffn 4028@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4029bit[31:16] of byte offset to module TLS base address. 4030@end deffn 4031@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 4032No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4033@end deffn 4034@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 4035bit[47:32] of byte offset to module TLS base address. 4036@end deffn 4037@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 4038AArch64 TLS LOCAL EXEC relocation. 4039@end deffn 4040@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 4041AArch64 TLS LOCAL EXEC relocation. 4042@end deffn 4043@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 4044AArch64 TLS LOCAL EXEC relocation. 4045@end deffn 4046@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4047AArch64 TLS LOCAL EXEC relocation. 4048@end deffn 4049@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4050AArch64 TLS LOCAL EXEC relocation. 4051@end deffn 4052@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4053AArch64 TLS LOCAL EXEC relocation. 4054@end deffn 4055@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4056AArch64 TLS LOCAL EXEC relocation. 4057@end deffn 4058@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4059AArch64 TLS LOCAL EXEC relocation. 4060@end deffn 4061@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 4062bit[11:1] of byte offset to module TLS base address, encoded in ldst 4063instructions. 4064@end deffn 4065@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 4066Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check. 4067@end deffn 4068@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 4069bit[11:2] of byte offset to module TLS base address, encoded in ldst 4070instructions. 4071@end deffn 4072@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 4073Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check. 4074@end deffn 4075@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 4076bit[11:3] of byte offset to module TLS base address, encoded in ldst 4077instructions. 4078@end deffn 4079@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 4080Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check. 4081@end deffn 4082@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 4083bit[11:0] of byte offset to module TLS base address, encoded in ldst 4084instructions. 4085@end deffn 4086@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 4087Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check. 4088@end deffn 4089@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4090AArch64 TLS DESC relocation. 4091@end deffn 4092@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4093AArch64 TLS DESC relocation. 4094@end deffn 4095@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4096AArch64 TLS DESC relocation. 4097@end deffn 4098@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4099AArch64 TLS DESC relocation. 4100@end deffn 4101@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4102AArch64 TLS DESC relocation. 4103@end deffn 4104@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4105AArch64 TLS DESC relocation. 4106@end deffn 4107@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4108AArch64 TLS DESC relocation. 4109@end deffn 4110@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4111AArch64 TLS DESC relocation. 4112@end deffn 4113@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 4114AArch64 TLS DESC relocation. 4115@end deffn 4116@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 4117AArch64 TLS DESC relocation. 4118@end deffn 4119@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 4120AArch64 TLS DESC relocation. 4121@end deffn 4122@deffn {} BFD_RELOC_AARCH64_COPY 4123AArch64 TLS relocation. 4124@end deffn 4125@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 4126AArch64 TLS relocation. 4127@end deffn 4128@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 4129AArch64 TLS relocation. 4130@end deffn 4131@deffn {} BFD_RELOC_AARCH64_RELATIVE 4132AArch64 TLS relocation. 4133@end deffn 4134@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4135AArch64 TLS relocation. 4136@end deffn 4137@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 4138AArch64 TLS relocation. 4139@end deffn 4140@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 4141AArch64 TLS relocation. 4142@end deffn 4143@deffn {} BFD_RELOC_AARCH64_TLSDESC 4144AArch64 TLS relocation. 4145@end deffn 4146@deffn {} BFD_RELOC_AARCH64_IRELATIVE 4147AArch64 support for STT_GNU_IFUNC. 4148@end deffn 4149@deffn {} BFD_RELOC_AARCH64_RELOC_END 4150AArch64 pseudo relocation code to mark the end of the AArch64 4151relocation enumerators that have direct mapping to ELF reloc codes. 4152There are a few more enumerators after this one; those are mainly 4153used by the AArch64 assembler for the internal fixup or to select 4154one of the above enumerators. 4155@end deffn 4156@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4157AArch64 pseudo relocation code to be used internally by the AArch64 4158assembler and not (currently) written to any object files. 4159@end deffn 4160@deffn {} BFD_RELOC_AARCH64_LDST_LO12 4161AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4162address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4163@end deffn 4164@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4165AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 4166used internally by the AArch64 assembler and not (currently) written to 4167any object files. 4168@end deffn 4169@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4170Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 4171@end deffn 4172@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 4173AArch64 pseudo relocation code for TLS local exec mode. It's to be 4174used internally by the AArch64 assembler and not (currently) written to 4175any object files. 4176@end deffn 4177@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC 4178Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check. 4179@end deffn 4180@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4181AArch64 pseudo relocation code to be used internally by the AArch64 4182assembler and not (currently) written to any object files. 4183@end deffn 4184@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4185AArch64 pseudo relocation code to be used internally by the AArch64 4186assembler and not (currently) written to any object files. 4187@end deffn 4188@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4189AArch64 pseudo relocation code to be used internally by the AArch64 4190assembler and not (currently) written to any object files. 4191@end deffn 4192@deffn {} BFD_RELOC_TILEPRO_COPY 4193@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4194@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4195@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4196@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4197@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4198@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4199@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4200@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4201@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4202@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4203@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4204@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4205@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4206@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4207@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4208@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4209@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4210@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4211@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4212@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4213@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4214@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4215@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4216@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4217@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4218@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4219@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4220@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4221@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4222@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4223@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4224@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4225@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4226@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4227@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4228@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4229@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4230@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4231@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4232@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4233@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4234@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4235@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4236@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4237@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4238@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4239@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4240@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4241@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4242@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4243@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4244@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4245@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4246@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4247@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4248@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4249@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4250@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4251@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4252@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4253@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4254@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4255@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4256@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4257@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4258@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4259@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4260@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4261@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4262@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4263@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4264@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4265@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4266@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4267@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4268@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4269@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4270@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4271Tilera TILEPro Relocations. 4272@end deffn 4273@deffn {} BFD_RELOC_TILEGX_HW0 4274@deffnx {} BFD_RELOC_TILEGX_HW1 4275@deffnx {} BFD_RELOC_TILEGX_HW2 4276@deffnx {} BFD_RELOC_TILEGX_HW3 4277@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4278@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4279@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4280@deffnx {} BFD_RELOC_TILEGX_COPY 4281@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4282@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4283@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4284@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4285@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4286@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4287@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4288@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4289@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4290@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4291@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4292@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4293@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4294@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4295@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4296@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4297@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4298@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4299@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4300@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4301@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4302@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4303@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4304@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4305@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4306@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4307@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4308@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4309@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4310@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4311@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4312@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4313@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4314@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4315@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4316@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4317@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4318@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4319@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4320@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4321@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4322@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4323@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4324@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4325@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4326@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4327@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4328@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4329@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4330@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4331@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4332@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4333@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4334@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4335@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4336@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4337@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4338@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4339@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4340@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4341@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4342@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4343@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4344@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4345@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4346@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4347@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4348@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4349@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4350@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4351@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4352@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4353@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4354@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4355@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4356@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4357@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4358@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4359@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4360@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4361@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4362@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4363@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4364@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4365@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4366@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4367@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4368@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4369@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4370@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4371@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4372@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4373@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4374@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4375@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4376@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4377@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4378@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4379@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4380@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4381@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4382Tilera TILE-Gx Relocations. 4383@end deffn 4384@deffn {} BFD_RELOC_BPF_64 4385@deffnx {} BFD_RELOC_BPF_32 4386@deffnx {} BFD_RELOC_BPF_16 4387@deffnx {} BFD_RELOC_BPF_DISP16 4388@deffnx {} BFD_RELOC_BPF_DISP32 4389Linux eBPF relocations. 4390@end deffn 4391@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4392Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4393@end deffn 4394@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4395Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4396@end deffn 4397@deffn {} BFD_RELOC_EPIPHANY_HIGH 4398Adapteva EPIPHANY - 16 most-significant bits of absolute address 4399@end deffn 4400@deffn {} BFD_RELOC_EPIPHANY_LOW 4401Adapteva EPIPHANY - 16 least-significant bits of absolute address 4402@end deffn 4403@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4404Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4405@end deffn 4406@deffn {} BFD_RELOC_EPIPHANY_IMM11 4407Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4408@end deffn 4409@deffn {} BFD_RELOC_EPIPHANY_IMM8 4410Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4411@end deffn 4412@deffn {} BFD_RELOC_VISIUM_HI16 4413@deffnx {} BFD_RELOC_VISIUM_LO16 4414@deffnx {} BFD_RELOC_VISIUM_IM16 4415@deffnx {} BFD_RELOC_VISIUM_REL16 4416@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4417@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4418@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4419Visium Relocations. 4420@end deffn 4421@deffn {} BFD_RELOC_WASM32_LEB128 4422@deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4423@deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4424@deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4425@deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4426@deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4427@deffnx {} BFD_RELOC_WASM32_COPY 4428@deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4429@deffnx {} BFD_RELOC_WASM32_INDEX 4430@deffnx {} BFD_RELOC_WASM32_PLT_SIG 4431WebAssembly relocations. 4432@end deffn 4433@deffn {} BFD_RELOC_CKCORE_NONE 4434@deffnx {} BFD_RELOC_CKCORE_ADDR32 4435@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM8BY4 4436@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM11BY2 4437@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM4BY2 4438@deffnx {} BFD_RELOC_CKCORE_PCREL32 4439@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2 4440@deffnx {} BFD_RELOC_CKCORE_GNU_VTINHERIT 4441@deffnx {} BFD_RELOC_CKCORE_GNU_VTENTRY 4442@deffnx {} BFD_RELOC_CKCORE_RELATIVE 4443@deffnx {} BFD_RELOC_CKCORE_COPY 4444@deffnx {} BFD_RELOC_CKCORE_GLOB_DAT 4445@deffnx {} BFD_RELOC_CKCORE_JUMP_SLOT 4446@deffnx {} BFD_RELOC_CKCORE_GOTOFF 4447@deffnx {} BFD_RELOC_CKCORE_GOTPC 4448@deffnx {} BFD_RELOC_CKCORE_GOT32 4449@deffnx {} BFD_RELOC_CKCORE_PLT32 4450@deffnx {} BFD_RELOC_CKCORE_ADDRGOT 4451@deffnx {} BFD_RELOC_CKCORE_ADDRPLT 4452@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM26BY2 4453@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY2 4454@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY4 4455@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY2 4456@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY4 4457@deffnx {} BFD_RELOC_CKCORE_ADDR_HI16 4458@deffnx {} BFD_RELOC_CKCORE_ADDR_LO16 4459@deffnx {} BFD_RELOC_CKCORE_GOTPC_HI16 4460@deffnx {} BFD_RELOC_CKCORE_GOTPC_LO16 4461@deffnx {} BFD_RELOC_CKCORE_GOTOFF_HI16 4462@deffnx {} BFD_RELOC_CKCORE_GOTOFF_LO16 4463@deffnx {} BFD_RELOC_CKCORE_GOT12 4464@deffnx {} BFD_RELOC_CKCORE_GOT_HI16 4465@deffnx {} BFD_RELOC_CKCORE_GOT_LO16 4466@deffnx {} BFD_RELOC_CKCORE_PLT12 4467@deffnx {} BFD_RELOC_CKCORE_PLT_HI16 4468@deffnx {} BFD_RELOC_CKCORE_PLT_LO16 4469@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_HI16 4470@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_LO16 4471@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_HI16 4472@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_LO16 4473@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2 4474@deffnx {} BFD_RELOC_CKCORE_TOFFSET_LO16 4475@deffnx {} BFD_RELOC_CKCORE_DOFFSET_LO16 4476@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM18BY2 4477@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18 4478@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 4479@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 4480@deffnx {} BFD_RELOC_CKCORE_GOTOFF_IMM18 4481@deffnx {} BFD_RELOC_CKCORE_GOT_IMM18BY4 4482@deffnx {} BFD_RELOC_CKCORE_PLT_IMM18BY4 4483@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM7BY4 4484@deffnx {} BFD_RELOC_CKCORE_TLS_LE32 4485@deffnx {} BFD_RELOC_CKCORE_TLS_IE32 4486@deffnx {} BFD_RELOC_CKCORE_TLS_GD32 4487@deffnx {} BFD_RELOC_CKCORE_TLS_LDM32 4488@deffnx {} BFD_RELOC_CKCORE_TLS_LDO32 4489@deffnx {} BFD_RELOC_CKCORE_TLS_DTPMOD32 4490@deffnx {} BFD_RELOC_CKCORE_TLS_DTPOFF32 4491@deffnx {} BFD_RELOC_CKCORE_TLS_TPOFF32 4492@deffnx {} BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 4493@deffnx {} BFD_RELOC_CKCORE_NOJSRI 4494@deffnx {} BFD_RELOC_CKCORE_CALLGRAPH 4495@deffnx {} BFD_RELOC_CKCORE_IRELATIVE 4496@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4 4497@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4 4498C-SKY relocations. 4499@end deffn 4500@deffn {} BFD_RELOC_S12Z_OPR 4501S12Z relocations. 4502@end deffn 4503 4504@example 4505 4506typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4507@end example 4508@findex bfd_reloc_type_lookup 4509@subsubsection @code{bfd_reloc_type_lookup} 4510@strong{Synopsis} 4511@example 4512reloc_howto_type *bfd_reloc_type_lookup 4513 (bfd *abfd, bfd_reloc_code_real_type code); 4514reloc_howto_type *bfd_reloc_name_lookup 4515 (bfd *abfd, const char *reloc_name); 4516@end example 4517@strong{Description}@* 4518Return a pointer to a howto structure which, when 4519invoked, will perform the relocation @var{code} on data from the 4520architecture noted. 4521 4522@findex bfd_default_reloc_type_lookup 4523@subsubsection @code{bfd_default_reloc_type_lookup} 4524@strong{Synopsis} 4525@example 4526reloc_howto_type *bfd_default_reloc_type_lookup 4527 (bfd *abfd, bfd_reloc_code_real_type code); 4528@end example 4529@strong{Description}@* 4530Provides a default relocation lookup routine for any architecture. 4531 4532@findex bfd_get_reloc_code_name 4533@subsubsection @code{bfd_get_reloc_code_name} 4534@strong{Synopsis} 4535@example 4536const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4537@end example 4538@strong{Description}@* 4539Provides a printable name for the supplied relocation code. 4540Useful mainly for printing error messages. 4541 4542@findex bfd_generic_relax_section 4543@subsubsection @code{bfd_generic_relax_section} 4544@strong{Synopsis} 4545@example 4546bfd_boolean bfd_generic_relax_section 4547 (bfd *abfd, 4548 asection *section, 4549 struct bfd_link_info *, 4550 bfd_boolean *); 4551@end example 4552@strong{Description}@* 4553Provides default handling for relaxing for back ends which 4554don't do relaxing. 4555 4556@findex bfd_generic_gc_sections 4557@subsubsection @code{bfd_generic_gc_sections} 4558@strong{Synopsis} 4559@example 4560bfd_boolean bfd_generic_gc_sections 4561 (bfd *, struct bfd_link_info *); 4562@end example 4563@strong{Description}@* 4564Provides default handling for relaxing for back ends which 4565don't do section gc -- i.e., does nothing. 4566 4567@findex bfd_generic_lookup_section_flags 4568@subsubsection @code{bfd_generic_lookup_section_flags} 4569@strong{Synopsis} 4570@example 4571bfd_boolean bfd_generic_lookup_section_flags 4572 (struct bfd_link_info *, struct flag_info *, asection *); 4573@end example 4574@strong{Description}@* 4575Provides default handling for section flags lookup 4576-- i.e., does nothing. 4577Returns FALSE if the section should be omitted, otherwise TRUE. 4578 4579@findex bfd_generic_merge_sections 4580@subsubsection @code{bfd_generic_merge_sections} 4581@strong{Synopsis} 4582@example 4583bfd_boolean bfd_generic_merge_sections 4584 (bfd *, struct bfd_link_info *); 4585@end example 4586@strong{Description}@* 4587Provides default handling for SEC_MERGE section merging for back ends 4588which don't have SEC_MERGE support -- i.e., does nothing. 4589 4590@findex bfd_generic_get_relocated_section_contents 4591@subsubsection @code{bfd_generic_get_relocated_section_contents} 4592@strong{Synopsis} 4593@example 4594bfd_byte *bfd_generic_get_relocated_section_contents 4595 (bfd *abfd, 4596 struct bfd_link_info *link_info, 4597 struct bfd_link_order *link_order, 4598 bfd_byte *data, 4599 bfd_boolean relocatable, 4600 asymbol **symbols); 4601@end example 4602@strong{Description}@* 4603Provides default handling of relocation effort for back ends 4604which can't be bothered to do it efficiently. 4605 4606@findex _bfd_generic_set_reloc 4607@subsubsection @code{_bfd_generic_set_reloc} 4608@strong{Synopsis} 4609@example 4610void _bfd_generic_set_reloc 4611 (bfd *abfd, 4612 sec_ptr section, 4613 arelent **relptr, 4614 unsigned int count); 4615@end example 4616@strong{Description}@* 4617Installs a new set of internal relocations in SECTION. 4618 4619@findex _bfd_unrecognized_reloc 4620@subsubsection @code{_bfd_unrecognized_reloc} 4621@strong{Synopsis} 4622@example 4623bfd_boolean _bfd_unrecognized_reloc 4624 (bfd * abfd, 4625 sec_ptr section, 4626 unsigned int r_type); 4627@end example 4628@strong{Description}@* 4629Reports an unrecognized reloc. 4630Written as a function in order to reduce code duplication. 4631Returns FALSE so that it can be called from a return statement. 4632 4633