1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27struct reloc_cache_entry 28@{ 29 /* A pointer into the canonical table of pointers. */ 30 struct bfd_symbol **sym_ptr_ptr; 31 32 /* offset in section. */ 33 bfd_size_type address; 34 35 /* addend for relocation value. */ 36 bfd_vma addend; 37 38 /* Pointer to how to perform the required relocation. */ 39 reloc_howto_type *howto; 40 41@}; 42 43@end example 44Here is a description of each of the fields within an @code{arelent}: 45 46@itemize @bullet 47 48@item 49@code{sym_ptr_ptr} 50@end itemize 51The symbol table pointer points to a pointer to the symbol 52associated with the relocation request. It is the pointer 53into the table returned by the back end's 54@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 55referenced through a pointer to a pointer so that tools like 56the linker can fix up all the symbols of the same name by 57modifying only one pointer. The relocation routine looks in 58the symbol and uses the base of the section the symbol is 59attached to and the value of the symbol as the initial 60relocation offset. If the symbol pointer is zero, then the 61section provided is looked up. 62 63@itemize @bullet 64 65@item 66@code{address} 67@end itemize 68The @code{address} field gives the offset in bytes from the base of 69the section data which owns the relocation record to the first 70byte of relocatable information. The actual data relocated 71will be relative to this point; for example, a relocation 72type which modifies the bottom two bytes of a four byte word 73would not touch the first byte pointed to in a big endian 74world. 75 76@itemize @bullet 77 78@item 79@code{addend} 80@end itemize 81The @code{addend} is a value provided by the back end to be added (!) 82to the relocation offset. Its interpretation is dependent upon 83the howto. For example, on the 68k the code: 84 85@example 86 char foo[]; 87 main() 88 @{ 89 return foo[0x12345678]; 90 @} 91@end example 92 93Could be compiled into: 94 95@example 96 linkw fp,#-4 97 moveb @@#12345678,d0 98 extbl d0 99 unlk fp 100 rts 101@end example 102 103This could create a reloc pointing to @code{foo}, but leave the 104offset in the data, something like: 105 106@example 107RELOCATION RECORDS FOR [.text]: 108offset type value 10900000006 32 _foo 110 11100000000 4e56 fffc ; linkw fp,#-4 11200000004 1039 1234 5678 ; moveb @@#12345678,d0 1130000000a 49c0 ; extbl d0 1140000000c 4e5e ; unlk fp 1150000000e 4e75 ; rts 116@end example 117 118Using coff and an 88k, some instructions don't have enough 119space in them to represent the full address range, and 120pointers have to be loaded in two parts. So you'd get something like: 121 122@example 123 or.u r13,r0,hi16(_foo+0x12345678) 124 ld.b r2,r13,lo16(_foo+0x12345678) 125 jmp r1 126@end example 127 128This should create two relocs, both pointing to @code{_foo}, and with 1290x12340000 in their addend field. The data would consist of: 130 131@example 132RELOCATION RECORDS FOR [.text]: 133offset type value 13400000002 HVRT16 _foo+0x12340000 13500000006 LVRT16 _foo+0x12340000 136 13700000000 5da05678 ; or.u r13,r0,0x5678 13800000004 1c4d5678 ; ld.b r2,r13,0x5678 13900000008 f400c001 ; jmp r1 140@end example 141 142The relocation routine digs out the value from the data, adds 143it to the addend to get the original offset, and then adds the 144value of @code{_foo}. Note that all 32 bits have to be kept around 145somewhere, to cope with carry from bit 15 to bit 16. 146 147One further example is the sparc and the a.out format. The 148sparc has a similar problem to the 88k, in that some 149instructions don't have room for an entire offset, but on the 150sparc the parts are created in odd sized lumps. The designers of 151the a.out format chose to not use the data within the section 152for storing part of the offset; all the offset is kept within 153the reloc. Anything in the data should be ignored. 154 155@example 156 save %sp,-112,%sp 157 sethi %hi(_foo+0x12345678),%g2 158 ldsb [%g2+%lo(_foo+0x12345678)],%i0 159 ret 160 restore 161@end example 162 163Both relocs contain a pointer to @code{foo}, and the offsets 164contain junk. 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000004 HI22 _foo+0x12345678 17000000008 LO10 _foo+0x12345678 171 17200000000 9de3bf90 ; save %sp,-112,%sp 17300000004 05000000 ; sethi %hi(_foo+0),%g2 17400000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 1750000000c 81c7e008 ; ret 17600000010 81e80000 ; restore 177@end example 178 179@itemize @bullet 180 181@item 182@code{howto} 183@end itemize 184The @code{howto} field can be imagined as a 185relocation instruction. It is a pointer to a structure which 186contains information on what to do with all of the other 187information in the reloc record and data section. A back end 188would normally have a relocation instruction set and turn 189relocations into pointers to the correct structure on input - 190but it would be possible to create each howto field on demand. 191 192@subsubsection @code{enum complain_overflow} 193Indicates what sort of overflow checking should be done when 194performing a relocation. 195 196 197@example 198enum complain_overflow 199@{ 200 /* Do not complain on overflow. */ 201 complain_overflow_dont, 202 203 /* Complain if the value overflows when considered as a signed 204 number one bit larger than the field. ie. A bitfield of N bits 205 is allowed to represent -2**n to 2**n-1. */ 206 complain_overflow_bitfield, 207 208 /* Complain if the value overflows when considered as a signed 209 number. */ 210 complain_overflow_signed, 211 212 /* Complain if the value overflows when considered as an 213 unsigned number. */ 214 complain_overflow_unsigned 215@}; 216 217@end example 218@subsubsection @code{reloc_howto_type} 219The @code{reloc_howto_type} is a structure which contains all the 220information that libbfd needs to know to tie up a back end's data. 221 222 223@example 224struct reloc_howto_struct 225@{ 226 /* The type field has mainly a documentary use - the back end can 227 do what it wants with it, though normally the back end's idea of 228 an external reloc number is stored in this field. */ 229 unsigned int type; 230 231 /* The size of the item to be relocated in bytes. */ 232 unsigned int size:4; 233 234 /* The number of bits in the field to be relocated. This is used 235 when doing overflow checking. */ 236 unsigned int bitsize:7; 237 238 /* The value the final relocation is shifted right by. This drops 239 unwanted data from the relocation. */ 240 unsigned int rightshift:6; 241 242 /* The bit position of the reloc value in the destination. 243 The relocated value is left shifted by this amount. */ 244 unsigned int bitpos:6; 245 246 /* What type of overflow error should be checked for when 247 relocating. */ 248 ENUM_BITFIELD (complain_overflow) complain_on_overflow:2; 249 250 /* The relocation value should be negated before applying. */ 251 unsigned int negate:1; 252 253 /* The relocation is relative to the item being relocated. */ 254 unsigned int pc_relative:1; 255 256 /* Some formats record a relocation addend in the section contents 257 rather than with the relocation. For ELF formats this is the 258 distinction between USE_REL and USE_RELA (though the code checks 259 for USE_REL == 1/0). The value of this field is TRUE if the 260 addend is recorded with the section contents; when performing a 261 partial link (ld -r) the section contents (the data) will be 262 modified. The value of this field is FALSE if addends are 263 recorded with the relocation (in arelent.addend); when performing 264 a partial link the relocation will be modified. 265 All relocations for all ELF USE_RELA targets should set this field 266 to FALSE (values of TRUE should be looked on with suspicion). 267 However, the converse is not true: not all relocations of all ELF 268 USE_REL targets set this field to TRUE. Why this is so is peculiar 269 to each particular target. For relocs that aren't used in partial 270 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 271 unsigned int partial_inplace:1; 272 273 /* When some formats create PC relative instructions, they leave 274 the value of the pc of the place being relocated in the offset 275 slot of the instruction, so that a PC relative relocation can 276 be made just by adding in an ordinary offset (e.g., sun3 a.out). 277 Some formats leave the displacement part of an instruction 278 empty (e.g., ELF); this flag signals the fact. */ 279 unsigned int pcrel_offset:1; 280 281 /* Whether bfd_install_relocation should just install the addend, 282 or should follow the practice of some older object formats and 283 install a value including the symbol. */ 284 unsigned int install_addend:1; 285 286 /* src_mask selects the part of the instruction (or data) to be used 287 in the relocation sum. If the target relocations don't have an 288 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 289 dst_mask to extract the addend from the section contents. If 290 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 291 field should normally be zero. Non-zero values for ELF USE_RELA 292 targets should be viewed with suspicion as normally the value in 293 the dst_mask part of the section contents should be ignored. */ 294 bfd_vma src_mask; 295 296 /* dst_mask selects which parts of the instruction (or data) are 297 replaced with a relocated value. */ 298 bfd_vma dst_mask; 299 300 /* If this field is non null, then the supplied function is 301 called rather than the normal function. This allows really 302 strange relocation methods to be accommodated. */ 303 bfd_reloc_status_type (*special_function) 304 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 305 bfd *, char **); 306 307 /* The textual name of the relocation type. */ 308 const char *name; 309@}; 310 311@end example 312@findex The HOWTO Macro 313@subsubsection @code{The HOWTO Macro} 314The HOWTO macro fills in a reloc_howto_type (a typedef for 315const struct reloc_howto_struct). 316@example 317#define HOWTO_INSTALL_ADDEND 0 318#define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz)) 319#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \ 320 inplace, src_mask, dst_mask, pcrel_off) \ 321 @{ (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \ 322 size < 0, pcrel, inplace, pcrel_off, HOWTO_INSTALL_ADDEND, \ 323 src_mask, dst_mask, func, name @} 324@end example 325 326This is used to fill in an empty howto entry in an array. 327@example 328#define EMPTY_HOWTO(C) \ 329 HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \ 330 NULL, false, 0, 0, false) 331 332static inline unsigned int 333bfd_get_reloc_size (reloc_howto_type *howto) 334@{ 335 return howto->size; 336@} 337 338@end example 339 340@findex arelent_chain 341@subsubsection @code{arelent_chain} 342How relocs are tied together in an @code{asection}: 343@example 344typedef struct relent_chain 345@{ 346 arelent relent; 347 struct relent_chain *next; 348@} 349arelent_chain; 350 351@end example 352 353@findex bfd_check_overflow 354@subsubsection @code{bfd_check_overflow} 355@deftypefn {Function} bfd_reloc_status_type bfd_check_overflow (enum complain_overflow how, unsigned int bitsize, unsigned int rightshift, unsigned int addrsize, bfd_vma relocation); 356Perform overflow checking on @var{relocation} which has 357@var{bitsize} significant bits and will be shifted right by 358@var{rightshift} bits, on a machine with addresses containing 359@var{addrsize} significant bits. The result is either of 360@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 361 362@end deftypefn 363@findex bfd_reloc_offset_in_range 364@subsubsection @code{bfd_reloc_offset_in_range} 365@deftypefn {Function} bool bfd_reloc_offset_in_range (reloc_howto_type *howto, bfd *abfd, asection *section, bfd_size_type offset); 366Returns TRUE if the reloc described by @var{HOWTO} can be 367applied at @var{OFFSET} octets in @var{SECTION}. 368 369@end deftypefn 370@findex bfd_perform_relocation 371@subsubsection @code{bfd_perform_relocation} 372@deftypefn {Function} bfd_reloc_status_type bfd_perform_relocation (bfd *abfd, arelent *reloc_entry, void *data, asection *input_section, bfd *output_bfd, char **error_message); 373If @var{output_bfd} is supplied to this function, the 374generated image will be relocatable; the relocations are 375copied to the output file after they have been changed to 376reflect the new state of the world. There are two ways of 377reflecting the results of partial linkage in an output file: 378by modifying the output data in place, and by modifying the 379relocation record. Some native formats (e.g., basic a.out and 380basic coff) have no way of specifying an addend in the 381relocation type, so the addend has to go in the output data. 382This is no big deal since in these formats the output data 383slot will always be big enough for the addend. Complex reloc 384types with addends were invented to solve just this problem. 385The @var{error_message} argument is set to an error message if 386this return @code{bfd_reloc_dangerous}. 387 388@end deftypefn 389@findex bfd_install_relocation 390@subsubsection @code{bfd_install_relocation} 391@deftypefn {Function} bfd_reloc_status_type bfd_install_relocation (bfd *abfd, arelent *reloc_entry, void *data, bfd_vma data_start, asection *input_section, char **error_message); 392This looks remarkably like @code{bfd_perform_relocation}, except it 393does not expect that the section contents have been filled in. 394I.e., it's suitable for use when creating, rather than applying 395a relocation. 396 397For now, this function should be considered reserved for the 398assembler. 399 400@end deftypefn 401 402@node howto manager, , typedef arelent, Relocations 403@subsection The howto manager 404When an application wants to create a relocation, but doesn't 405know what the target machine might call it, it can find out by 406using this bit of code. 407 408@findex bfd_reloc_code_real_type 409@subsubsection @code{bfd_reloc_code_real_type} 410The insides of a reloc code. The idea is that, eventually, there 411will be one enumerator for every type of relocation we ever do. 412Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 413return a howto pointer. 414 415This does mean that the application must determine the correct 416enumerator value; you can't get a howto pointer from a random set 417of attributes. 418 419Here are the possible values for @code{enum bfd_reloc_code_real}: 420 421@deffn {} BFD_RELOC_64 422@deffnx {} BFD_RELOC_32 423@deffnx {} BFD_RELOC_26 424@deffnx {} BFD_RELOC_24 425@deffnx {} BFD_RELOC_16 426@deffnx {} BFD_RELOC_14 427@deffnx {} BFD_RELOC_8 428Basic absolute relocations of N bits. 429@end deffn 430@deffn {} BFD_RELOC_64_PCREL 431@deffnx {} BFD_RELOC_32_PCREL 432@deffnx {} BFD_RELOC_24_PCREL 433@deffnx {} BFD_RELOC_16_PCREL 434@deffnx {} BFD_RELOC_12_PCREL 435@deffnx {} BFD_RELOC_8_PCREL 436PC-relative relocations. Sometimes these are relative to the 437address of the relocation itself; sometimes they are relative to the 438start of the section containing the relocation. It depends on the 439specific target. 440@end deffn 441@deffn {} BFD_RELOC_32_SECREL 442@deffnx {} BFD_RELOC_16_SECIDX 443Section relative relocations. Some targets need this for DWARF2. 444@end deffn 445@deffn {} BFD_RELOC_32_GOT_PCREL 446@deffnx {} BFD_RELOC_16_GOT_PCREL 447@deffnx {} BFD_RELOC_8_GOT_PCREL 448@deffnx {} BFD_RELOC_32_GOTOFF 449@deffnx {} BFD_RELOC_16_GOTOFF 450@deffnx {} BFD_RELOC_LO16_GOTOFF 451@deffnx {} BFD_RELOC_HI16_GOTOFF 452@deffnx {} BFD_RELOC_HI16_S_GOTOFF 453@deffnx {} BFD_RELOC_8_GOTOFF 454@deffnx {} BFD_RELOC_64_PLT_PCREL 455@deffnx {} BFD_RELOC_32_PLT_PCREL 456@deffnx {} BFD_RELOC_24_PLT_PCREL 457@deffnx {} BFD_RELOC_16_PLT_PCREL 458@deffnx {} BFD_RELOC_8_PLT_PCREL 459@deffnx {} BFD_RELOC_64_PLTOFF 460@deffnx {} BFD_RELOC_32_PLTOFF 461@deffnx {} BFD_RELOC_16_PLTOFF 462@deffnx {} BFD_RELOC_LO16_PLTOFF 463@deffnx {} BFD_RELOC_HI16_PLTOFF 464@deffnx {} BFD_RELOC_HI16_S_PLTOFF 465@deffnx {} BFD_RELOC_8_PLTOFF 466For ELF. 467@end deffn 468@deffn {} BFD_RELOC_SIZE32 469@deffnx {} BFD_RELOC_SIZE64 470Size relocations. 471@end deffn 472@deffn {} BFD_RELOC_68K_GLOB_DAT 473@deffnx {} BFD_RELOC_68K_JMP_SLOT 474@deffnx {} BFD_RELOC_68K_RELATIVE 475@deffnx {} BFD_RELOC_68K_TLS_GD32 476@deffnx {} BFD_RELOC_68K_TLS_GD16 477@deffnx {} BFD_RELOC_68K_TLS_GD8 478@deffnx {} BFD_RELOC_68K_TLS_LDM32 479@deffnx {} BFD_RELOC_68K_TLS_LDM16 480@deffnx {} BFD_RELOC_68K_TLS_LDM8 481@deffnx {} BFD_RELOC_68K_TLS_LDO32 482@deffnx {} BFD_RELOC_68K_TLS_LDO16 483@deffnx {} BFD_RELOC_68K_TLS_LDO8 484@deffnx {} BFD_RELOC_68K_TLS_IE32 485@deffnx {} BFD_RELOC_68K_TLS_IE16 486@deffnx {} BFD_RELOC_68K_TLS_IE8 487@deffnx {} BFD_RELOC_68K_TLS_LE32 488@deffnx {} BFD_RELOC_68K_TLS_LE16 489@deffnx {} BFD_RELOC_68K_TLS_LE8 490Relocations used by 68K ELF. 491@end deffn 492@deffn {} BFD_RELOC_VAX_GLOB_DAT 493@deffnx {} BFD_RELOC_VAX_GLOB_REF 494@deffnx {} BFD_RELOC_VAX_JMP_SLOT 495@deffnx {} BFD_RELOC_VAX_RELATIVE 496Relocations used by VAX ELF. 497@end deffn 498@deffn {} BFD_RELOC_32_BASEREL 499@deffnx {} BFD_RELOC_16_BASEREL 500@deffnx {} BFD_RELOC_LO16_BASEREL 501@deffnx {} BFD_RELOC_HI16_BASEREL 502@deffnx {} BFD_RELOC_HI16_S_BASEREL 503@deffnx {} BFD_RELOC_8_BASEREL 504@deffnx {} BFD_RELOC_RVA 505Linkage-table relative. 506@end deffn 507@deffn {} BFD_RELOC_8_FFnn 508Absolute 8-bit relocation, but used to form an address like 0xFFnn. 509@end deffn 510@deffn {} BFD_RELOC_32_PCREL_S2 511@deffnx {} BFD_RELOC_16_PCREL_S2 512@deffnx {} BFD_RELOC_23_PCREL_S2 513These PC-relative relocations are stored as word displacements -- 514i.e., byte displacements shifted right two bits. The 30-bit word 515displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 516SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 517signed 16-bit displacement is used on the MIPS, and the 23-bit 518displacement is used on the Alpha. 519@end deffn 520@deffn {} BFD_RELOC_HI22 521@deffnx {} BFD_RELOC_LO10 522High 22 bits and low 10 bits of 32-bit value, placed into lower bits 523of the target word. These are used on the SPARC. 524@end deffn 525@deffn {} BFD_RELOC_GPREL16 526@deffnx {} BFD_RELOC_GPREL32 527For systems that allocate a Global Pointer register, these are 528displacements off that register. These relocation types are 529handled specially, because the value the register will have is 530decided relatively late. 531@end deffn 532@deffn {} BFD_RELOC_NONE 533@deffnx {} BFD_RELOC_SPARC_WDISP22 534@deffnx {} BFD_RELOC_SPARC22 535@deffnx {} BFD_RELOC_SPARC13 536@deffnx {} BFD_RELOC_SPARC_GOT10 537@deffnx {} BFD_RELOC_SPARC_GOT13 538@deffnx {} BFD_RELOC_SPARC_GOT22 539@deffnx {} BFD_RELOC_SPARC_PC10 540@deffnx {} BFD_RELOC_SPARC_PC22 541@deffnx {} BFD_RELOC_SPARC_WPLT30 542@deffnx {} BFD_RELOC_SPARC_COPY 543@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 544@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 545@deffnx {} BFD_RELOC_SPARC_RELATIVE 546@deffnx {} BFD_RELOC_SPARC_UA16 547@deffnx {} BFD_RELOC_SPARC_UA32 548@deffnx {} BFD_RELOC_SPARC_UA64 549@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 550@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 551@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 552@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 553@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 554@deffnx {} BFD_RELOC_SPARC_JMP_IREL 555@deffnx {} BFD_RELOC_SPARC_IRELATIVE 556SPARC ELF relocations. There is probably some overlap with other 557relocation types already defined. 558@end deffn 559@deffn {} BFD_RELOC_SPARC_BASE13 560@deffnx {} BFD_RELOC_SPARC_BASE22 561I think these are specific to SPARC a.out (e.g., Sun 4). 562@end deffn 563@deffn {} BFD_RELOC_SPARC_64 564@deffnx {} BFD_RELOC_SPARC_10 565@deffnx {} BFD_RELOC_SPARC_11 566@deffnx {} BFD_RELOC_SPARC_OLO10 567@deffnx {} BFD_RELOC_SPARC_HH22 568@deffnx {} BFD_RELOC_SPARC_HM10 569@deffnx {} BFD_RELOC_SPARC_LM22 570@deffnx {} BFD_RELOC_SPARC_PC_HH22 571@deffnx {} BFD_RELOC_SPARC_PC_HM10 572@deffnx {} BFD_RELOC_SPARC_PC_LM22 573@deffnx {} BFD_RELOC_SPARC_WDISP16 574@deffnx {} BFD_RELOC_SPARC_WDISP19 575@deffnx {} BFD_RELOC_SPARC_7 576@deffnx {} BFD_RELOC_SPARC_6 577@deffnx {} BFD_RELOC_SPARC_5 578@deffnx {} BFD_RELOC_SPARC_DISP64 579@deffnx {} BFD_RELOC_SPARC_PLT32 580@deffnx {} BFD_RELOC_SPARC_PLT64 581@deffnx {} BFD_RELOC_SPARC_HIX22 582@deffnx {} BFD_RELOC_SPARC_LOX10 583@deffnx {} BFD_RELOC_SPARC_H44 584@deffnx {} BFD_RELOC_SPARC_M44 585@deffnx {} BFD_RELOC_SPARC_L44 586@deffnx {} BFD_RELOC_SPARC_REGISTER 587@deffnx {} BFD_RELOC_SPARC_H34 588@deffnx {} BFD_RELOC_SPARC_SIZE32 589@deffnx {} BFD_RELOC_SPARC_SIZE64 590@deffnx {} BFD_RELOC_SPARC_WDISP10 591SPARC64 relocations. 592@end deffn 593@deffn {} BFD_RELOC_SPARC_REV32 594SPARC little endian relocation. 595@end deffn 596@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 597@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 598@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 599@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 600@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 601@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 602@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 603@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 604@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 605@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 606@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 607@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 608@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 609@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 610@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 611@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 612@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 613@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 614@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 615@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 616@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 617@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 618@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 619@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 620SPARC TLS relocations. 621@end deffn 622@deffn {} BFD_RELOC_SPU_IMM7 623@deffnx {} BFD_RELOC_SPU_IMM8 624@deffnx {} BFD_RELOC_SPU_IMM10 625@deffnx {} BFD_RELOC_SPU_IMM10W 626@deffnx {} BFD_RELOC_SPU_IMM16 627@deffnx {} BFD_RELOC_SPU_IMM16W 628@deffnx {} BFD_RELOC_SPU_IMM18 629@deffnx {} BFD_RELOC_SPU_PCREL9a 630@deffnx {} BFD_RELOC_SPU_PCREL9b 631@deffnx {} BFD_RELOC_SPU_PCREL16 632@deffnx {} BFD_RELOC_SPU_LO16 633@deffnx {} BFD_RELOC_SPU_HI16 634@deffnx {} BFD_RELOC_SPU_PPU32 635@deffnx {} BFD_RELOC_SPU_PPU64 636@deffnx {} BFD_RELOC_SPU_ADD_PIC 637SPU Relocations. 638@end deffn 639@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 640Alpha ECOFF and ELF relocations. Some of these treat the symbol or 641"addend" in some special way. 642For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 643writing; when reading, it will be the absolute section symbol. The 644addend is the displacement in bytes of the "lda" instruction from 645the "ldah" instruction (which is at the address of this reloc). 646@end deffn 647@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 648For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 649with GPDISP_HI16 relocs. The addend is ignored when writing the 650relocations out, and is filled in with the file's GP value on 651reading, for convenience. 652@end deffn 653@deffn {} BFD_RELOC_ALPHA_GPDISP 654The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 655relocation except that there is no accompanying GPDISP_LO16 656relocation. 657@end deffn 658@deffn {} BFD_RELOC_ALPHA_LITERAL 659@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 660@deffnx {} BFD_RELOC_ALPHA_LITUSE 661The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 662the assembler turns it into a LDQ instruction to load the address of 663the symbol, and then fills in a register in the real instruction. 664 665The LITERAL reloc, at the LDQ instruction, refers to the .lita 666section symbol. The addend is ignored when writing, but is filled 667in with the file's GP value on reading, for convenience, as with the 668GPDISP_LO16 reloc. 669 670The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 671It should refer to the symbol to be referenced, as with 16_GOTOFF, 672but it generates output not based on the position within the .got 673section, but relative to the GP value chosen for the file during the 674final link stage. 675 676The LITUSE reloc, on the instruction using the loaded address, gives 677information to the linker that it might be able to use to optimize 678away some literal section references. The symbol is ignored (read 679as the absolute section symbol), and the "addend" indicates the type 680of instruction using the register: 6811 - "memory" fmt insn 6822 - byte-manipulation (byte offset reg) 6833 - jsr (target of branch) 684@end deffn 685@deffn {} BFD_RELOC_ALPHA_HINT 686The HINT relocation indicates a value that should be filled into the 687"hint" field of a jmp/jsr/ret instruction, for possible branch- 688prediction logic which may be provided on some processors. 689@end deffn 690@deffn {} BFD_RELOC_ALPHA_LINKAGE 691The LINKAGE relocation outputs a linkage pair in the object file, 692which is filled by the linker. 693@end deffn 694@deffn {} BFD_RELOC_ALPHA_CODEADDR 695The CODEADDR relocation outputs a STO_CA in the object file, 696which is filled by the linker. 697@end deffn 698@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 699@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 700The GPREL_HI/LO relocations together form a 32-bit offset from the 701GP register. 702@end deffn 703@deffn {} BFD_RELOC_ALPHA_BRSGP 704Like BFD_RELOC_23_PCREL_S2, except that the source and target must 705share a common GP, and the target address is adjusted for 706STO_ALPHA_STD_GPLOAD. 707@end deffn 708@deffn {} BFD_RELOC_ALPHA_NOP 709The NOP relocation outputs a NOP if the longword displacement 710between two procedure entry points is < 2^21. 711@end deffn 712@deffn {} BFD_RELOC_ALPHA_BSR 713The BSR relocation outputs a BSR if the longword displacement 714between two procedure entry points is < 2^21. 715@end deffn 716@deffn {} BFD_RELOC_ALPHA_LDA 717The LDA relocation outputs a LDA if the longword displacement 718between two procedure entry points is < 2^16. 719@end deffn 720@deffn {} BFD_RELOC_ALPHA_BOH 721The BOH relocation outputs a BSR if the longword displacement 722between two procedure entry points is < 2^21, or else a hint. 723@end deffn 724@deffn {} BFD_RELOC_ALPHA_TLSGD 725@deffnx {} BFD_RELOC_ALPHA_TLSLDM 726@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 727@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 728@deffnx {} BFD_RELOC_ALPHA_DTPREL64 729@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 730@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 731@deffnx {} BFD_RELOC_ALPHA_DTPREL16 732@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 733@deffnx {} BFD_RELOC_ALPHA_TPREL64 734@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 735@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 736@deffnx {} BFD_RELOC_ALPHA_TPREL16 737Alpha thread-local storage relocations. 738@end deffn 739@deffn {} BFD_RELOC_MIPS_JMP 740@deffnx {} BFD_RELOC_MICROMIPS_JMP 741The MIPS jump instruction. 742@end deffn 743@deffn {} BFD_RELOC_MIPS16_JMP 744The MIPS16 jump instruction. 745@end deffn 746@deffn {} BFD_RELOC_MIPS16_GPREL 747MIPS16 GP relative reloc. 748@end deffn 749@deffn {} BFD_RELOC_HI16 750High 16 bits of 32-bit value; simple reloc. 751@end deffn 752@deffn {} BFD_RELOC_HI16_S 753High 16 bits of 32-bit value but the low 16 bits will be sign 754extended and added to form the final result. If the low 16 755bits form a negative number, we need to add one to the high value 756to compensate for the borrow when the low bits are added. 757@end deffn 758@deffn {} BFD_RELOC_LO16 759Low 16 bits. 760@end deffn 761@deffn {} BFD_RELOC_HI16_PCREL 762High 16 bits of 32-bit pc-relative value. 763@end deffn 764@deffn {} BFD_RELOC_HI16_S_PCREL 765High 16 bits of 32-bit pc-relative value, adjusted. 766@end deffn 767@deffn {} BFD_RELOC_LO16_PCREL 768Low 16 bits of pc-relative value. 769@end deffn 770@deffn {} BFD_RELOC_MIPS16_GOT16 771@deffnx {} BFD_RELOC_MIPS16_CALL16 772Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 77316-bit immediate fields. 774@end deffn 775@deffn {} BFD_RELOC_MIPS16_HI16 776MIPS16 high 16 bits of 32-bit value. 777@end deffn 778@deffn {} BFD_RELOC_MIPS16_HI16_S 779MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 780extended and added to form the final result. If the low 16 781bits form a negative number, we need to add one to the high value 782to compensate for the borrow when the low bits are added. 783@end deffn 784@deffn {} BFD_RELOC_MIPS16_LO16 785MIPS16 low 16 bits. 786@end deffn 787@deffn {} BFD_RELOC_MIPS16_TLS_GD 788@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 789@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 790@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 791@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 792@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 793@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 794MIPS16 TLS relocations. 795@end deffn 796@deffn {} BFD_RELOC_MIPS_LITERAL 797@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 798Relocation against a MIPS literal section. 799@end deffn 800@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 801@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 802@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 803microMIPS PC-relative relocations. 804@end deffn 805@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 806MIPS16 PC-relative relocation. 807@end deffn 808@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 809@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 810@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 811@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 812MIPS PC-relative relocations. 813@end deffn 814@deffn {} BFD_RELOC_MICROMIPS_GPREL16 815@deffnx {} BFD_RELOC_MICROMIPS_HI16 816@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 817@deffnx {} BFD_RELOC_MICROMIPS_LO16 818microMIPS versions of generic BFD relocs. 819@end deffn 820@deffn {} BFD_RELOC_MIPS_GOT16 821@deffnx {} BFD_RELOC_MICROMIPS_GOT16 822@deffnx {} BFD_RELOC_MIPS_CALL16 823@deffnx {} BFD_RELOC_MICROMIPS_CALL16 824@deffnx {} BFD_RELOC_MIPS_GOT_HI16 825@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 826@deffnx {} BFD_RELOC_MIPS_GOT_LO16 827@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 828@deffnx {} BFD_RELOC_MIPS_CALL_HI16 829@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 830@deffnx {} BFD_RELOC_MIPS_CALL_LO16 831@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 832@deffnx {} BFD_RELOC_MIPS_SUB 833@deffnx {} BFD_RELOC_MICROMIPS_SUB 834@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 835@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 836@deffnx {} BFD_RELOC_MIPS_GOT_OFST 837@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 838@deffnx {} BFD_RELOC_MIPS_GOT_DISP 839@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 840@deffnx {} BFD_RELOC_MIPS_SHIFT5 841@deffnx {} BFD_RELOC_MIPS_SHIFT6 842@deffnx {} BFD_RELOC_MIPS_INSERT_A 843@deffnx {} BFD_RELOC_MIPS_INSERT_B 844@deffnx {} BFD_RELOC_MIPS_DELETE 845@deffnx {} BFD_RELOC_MIPS_HIGHEST 846@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 847@deffnx {} BFD_RELOC_MIPS_HIGHER 848@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 849@deffnx {} BFD_RELOC_MIPS_SCN_DISP 850@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 851@deffnx {} BFD_RELOC_MIPS_16 852@deffnx {} BFD_RELOC_MIPS_RELGOT 853@deffnx {} BFD_RELOC_MIPS_JALR 854@deffnx {} BFD_RELOC_MICROMIPS_JALR 855@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 856@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 857@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 858@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 859@deffnx {} BFD_RELOC_MIPS_TLS_GD 860@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 861@deffnx {} BFD_RELOC_MIPS_TLS_LDM 862@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 863@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 864@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 865@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 866@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 867@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 868@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 869@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 870@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 871@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 872@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 873@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 874@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 875@deffnx {} BFD_RELOC_MIPS_EH 876MIPS ELF relocations. 877@end deffn 878@deffn {} BFD_RELOC_MIPS_COPY 879@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 880MIPS ELF relocations (VxWorks and PLT extensions). 881@end deffn 882@deffn {} BFD_RELOC_MOXIE_10_PCREL 883Moxie ELF relocations. 884@end deffn 885@deffn {} BFD_RELOC_FT32_10 886@deffnx {} BFD_RELOC_FT32_20 887@deffnx {} BFD_RELOC_FT32_17 888@deffnx {} BFD_RELOC_FT32_18 889@deffnx {} BFD_RELOC_FT32_RELAX 890@deffnx {} BFD_RELOC_FT32_SC0 891@deffnx {} BFD_RELOC_FT32_SC1 892@deffnx {} BFD_RELOC_FT32_15 893@deffnx {} BFD_RELOC_FT32_DIFF32 894FT32 ELF relocations. 895@end deffn 896@deffn {} BFD_RELOC_FRV_LABEL16 897@deffnx {} BFD_RELOC_FRV_LABEL24 898@deffnx {} BFD_RELOC_FRV_LO16 899@deffnx {} BFD_RELOC_FRV_HI16 900@deffnx {} BFD_RELOC_FRV_GPREL12 901@deffnx {} BFD_RELOC_FRV_GPRELU12 902@deffnx {} BFD_RELOC_FRV_GPREL32 903@deffnx {} BFD_RELOC_FRV_GPRELHI 904@deffnx {} BFD_RELOC_FRV_GPRELLO 905@deffnx {} BFD_RELOC_FRV_GOT12 906@deffnx {} BFD_RELOC_FRV_GOTHI 907@deffnx {} BFD_RELOC_FRV_GOTLO 908@deffnx {} BFD_RELOC_FRV_FUNCDESC 909@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 910@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 911@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 912@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 913@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 914@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 915@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 916@deffnx {} BFD_RELOC_FRV_GOTOFF12 917@deffnx {} BFD_RELOC_FRV_GOTOFFHI 918@deffnx {} BFD_RELOC_FRV_GOTOFFLO 919@deffnx {} BFD_RELOC_FRV_GETTLSOFF 920@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 921@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 922@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 923@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 924@deffnx {} BFD_RELOC_FRV_TLSMOFF12 925@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 926@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 927@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 928@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 929@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 930@deffnx {} BFD_RELOC_FRV_TLSOFF 931@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 932@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 933@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 934@deffnx {} BFD_RELOC_FRV_TLSMOFF 935Fujitsu Frv Relocations. 936@end deffn 937@deffn {} BFD_RELOC_MN10300_GOTOFF24 938This is a 24bit GOT-relative reloc for the mn10300. 939@end deffn 940@deffn {} BFD_RELOC_MN10300_GOT32 941This is a 32bit GOT-relative reloc for the mn10300, offset by two 942bytes in the instruction. 943@end deffn 944@deffn {} BFD_RELOC_MN10300_GOT24 945This is a 24bit GOT-relative reloc for the mn10300, offset by two 946bytes in the instruction. 947@end deffn 948@deffn {} BFD_RELOC_MN10300_GOT16 949This is a 16bit GOT-relative reloc for the mn10300, offset by two 950bytes in the instruction. 951@end deffn 952@deffn {} BFD_RELOC_MN10300_COPY 953Copy symbol at runtime. 954@end deffn 955@deffn {} BFD_RELOC_MN10300_GLOB_DAT 956Create GOT entry. 957@end deffn 958@deffn {} BFD_RELOC_MN10300_JMP_SLOT 959Create PLT entry. 960@end deffn 961@deffn {} BFD_RELOC_MN10300_RELATIVE 962Adjust by program base. 963@end deffn 964@deffn {} BFD_RELOC_MN10300_SYM_DIFF 965Together with another reloc targeted at the same location, allows 966for a value that is the difference of two symbols in the same 967section. 968@end deffn 969@deffn {} BFD_RELOC_MN10300_ALIGN 970The addend of this reloc is an alignment power that must be honoured 971at the offset's location, regardless of linker relaxation. 972@end deffn 973@deffn {} BFD_RELOC_MN10300_TLS_GD 974@deffnx {} BFD_RELOC_MN10300_TLS_LD 975@deffnx {} BFD_RELOC_MN10300_TLS_LDO 976@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 977@deffnx {} BFD_RELOC_MN10300_TLS_IE 978@deffnx {} BFD_RELOC_MN10300_TLS_LE 979@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 980@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 981@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 982Various TLS-related relocations. 983@end deffn 984@deffn {} BFD_RELOC_MN10300_32_PCREL 985This is a 32bit pcrel reloc for the mn10300, offset by two bytes in 986the instruction. 987@end deffn 988@deffn {} BFD_RELOC_MN10300_16_PCREL 989This is a 16bit pcrel reloc for the mn10300, offset by two bytes in 990the instruction. 991@end deffn 992@deffn {} BFD_RELOC_386_GOT32 993@deffnx {} BFD_RELOC_386_PLT32 994@deffnx {} BFD_RELOC_386_COPY 995@deffnx {} BFD_RELOC_386_GLOB_DAT 996@deffnx {} BFD_RELOC_386_JUMP_SLOT 997@deffnx {} BFD_RELOC_386_RELATIVE 998@deffnx {} BFD_RELOC_386_GOTOFF 999@deffnx {} BFD_RELOC_386_GOTPC 1000@deffnx {} BFD_RELOC_386_TLS_TPOFF 1001@deffnx {} BFD_RELOC_386_TLS_IE 1002@deffnx {} BFD_RELOC_386_TLS_GOTIE 1003@deffnx {} BFD_RELOC_386_TLS_LE 1004@deffnx {} BFD_RELOC_386_TLS_GD 1005@deffnx {} BFD_RELOC_386_TLS_LDM 1006@deffnx {} BFD_RELOC_386_TLS_LDO_32 1007@deffnx {} BFD_RELOC_386_TLS_IE_32 1008@deffnx {} BFD_RELOC_386_TLS_LE_32 1009@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1010@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1011@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1012@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1013@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1014@deffnx {} BFD_RELOC_386_TLS_DESC 1015@deffnx {} BFD_RELOC_386_IRELATIVE 1016@deffnx {} BFD_RELOC_386_GOT32X 1017i386/elf relocations. 1018@end deffn 1019@deffn {} BFD_RELOC_X86_64_GOT32 1020@deffnx {} BFD_RELOC_X86_64_PLT32 1021@deffnx {} BFD_RELOC_X86_64_COPY 1022@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1023@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1024@deffnx {} BFD_RELOC_X86_64_RELATIVE 1025@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1026@deffnx {} BFD_RELOC_X86_64_32S 1027@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1028@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1029@deffnx {} BFD_RELOC_X86_64_TPOFF64 1030@deffnx {} BFD_RELOC_X86_64_TLSGD 1031@deffnx {} BFD_RELOC_X86_64_TLSLD 1032@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1033@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1034@deffnx {} BFD_RELOC_X86_64_TPOFF32 1035@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1036@deffnx {} BFD_RELOC_X86_64_GOTPC32 1037@deffnx {} BFD_RELOC_X86_64_GOT64 1038@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1039@deffnx {} BFD_RELOC_X86_64_GOTPC64 1040@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1041@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1042@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1043@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1044@deffnx {} BFD_RELOC_X86_64_TLSDESC 1045@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1046@deffnx {} BFD_RELOC_X86_64_PC32_BND 1047@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1048@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1049@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1050@deffnx {} BFD_RELOC_X86_64_CODE_4_GOTPCRELX 1051@deffnx {} BFD_RELOC_X86_64_CODE_4_GOTTPOFF 1052@deffnx {} BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC 1053x86-64/elf relocations. 1054@end deffn 1055@deffn {} BFD_RELOC_NS32K_IMM_8 1056@deffnx {} BFD_RELOC_NS32K_IMM_16 1057@deffnx {} BFD_RELOC_NS32K_IMM_32 1058@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1059@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1060@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1061@deffnx {} BFD_RELOC_NS32K_DISP_8 1062@deffnx {} BFD_RELOC_NS32K_DISP_16 1063@deffnx {} BFD_RELOC_NS32K_DISP_32 1064@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1065@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1066@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1067ns32k relocations. 1068@end deffn 1069@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1070@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1071PDP11 relocations. 1072@end deffn 1073@deffn {} BFD_RELOC_PJ_CODE_HI16 1074@deffnx {} BFD_RELOC_PJ_CODE_LO16 1075@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1076@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1077@deffnx {} BFD_RELOC_PJ_CODE_REL16 1078@deffnx {} BFD_RELOC_PJ_CODE_REL32 1079Picojava relocs. Not all of these appear in object files. 1080@end deffn 1081@deffn {} BFD_RELOC_PPC_B26 1082@deffnx {} BFD_RELOC_PPC_BA26 1083@deffnx {} BFD_RELOC_PPC_TOC16 1084@deffnx {} BFD_RELOC_PPC_TOC16_LO 1085@deffnx {} BFD_RELOC_PPC_TOC16_HI 1086@deffnx {} BFD_RELOC_PPC_B16 1087@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1088@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1089@deffnx {} BFD_RELOC_PPC_BA16 1090@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1091@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1092@deffnx {} BFD_RELOC_PPC_COPY 1093@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1094@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1095@deffnx {} BFD_RELOC_PPC_RELATIVE 1096@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1097@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1098@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1099@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1100@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1101@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1102@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1103@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1104@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1105@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1106@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1107@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1108@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1109@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1110@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1111@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1112@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1113@deffnx {} BFD_RELOC_PPC_VLE_REL8 1114@deffnx {} BFD_RELOC_PPC_VLE_REL15 1115@deffnx {} BFD_RELOC_PPC_VLE_REL24 1116@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1117@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1118@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1119@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1120@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1121@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1122@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1123@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1124@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1125@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1126@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1127@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1128@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1129@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1130@deffnx {} BFD_RELOC_PPC_16DX_HA 1131@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1132@deffnx {} BFD_RELOC_PPC_NEG 1133@deffnx {} BFD_RELOC_PPC64_HIGHER 1134@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1135@deffnx {} BFD_RELOC_PPC64_HIGHEST 1136@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1137@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1138@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1139@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1140@deffnx {} BFD_RELOC_PPC64_TOC 1141@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1142@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1143@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1144@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1145@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1146@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1147@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1148@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1149@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1150@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1151@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1152@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1153@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1154@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1155@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1156@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1157@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1158@deffnx {} BFD_RELOC_PPC64_REL16_HIGH 1159@deffnx {} BFD_RELOC_PPC64_REL16_HIGHA 1160@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER 1161@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA 1162@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST 1163@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA 1164@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1165@deffnx {} BFD_RELOC_PPC64_ENTRY 1166@deffnx {} BFD_RELOC_PPC64_REL24_NOTOC 1167@deffnx {} BFD_RELOC_PPC64_REL24_P9NOTOC 1168@deffnx {} BFD_RELOC_PPC64_D34 1169@deffnx {} BFD_RELOC_PPC64_D34_LO 1170@deffnx {} BFD_RELOC_PPC64_D34_HI30 1171@deffnx {} BFD_RELOC_PPC64_D34_HA30 1172@deffnx {} BFD_RELOC_PPC64_PCREL34 1173@deffnx {} BFD_RELOC_PPC64_GOT_PCREL34 1174@deffnx {} BFD_RELOC_PPC64_PLT_PCREL34 1175@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHER34 1176@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHERA34 1177@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHEST34 1178@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHESTA34 1179@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER34 1180@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA34 1181@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST34 1182@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA34 1183@deffnx {} BFD_RELOC_PPC64_D28 1184@deffnx {} BFD_RELOC_PPC64_PCREL28 1185Power(rs6000) and PowerPC relocations. 1186@end deffn 1187@deffn {} BFD_RELOC_PPC_TLS 1188@deffnx {} BFD_RELOC_PPC_TLSGD 1189@deffnx {} BFD_RELOC_PPC_TLSLD 1190@deffnx {} BFD_RELOC_PPC_TLSLE 1191@deffnx {} BFD_RELOC_PPC_TLSIE 1192@deffnx {} BFD_RELOC_PPC_TLSM 1193@deffnx {} BFD_RELOC_PPC_TLSML 1194@deffnx {} BFD_RELOC_PPC_DTPMOD 1195@deffnx {} BFD_RELOC_PPC_TPREL16 1196@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1197@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1198@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1199@deffnx {} BFD_RELOC_PPC_TPREL 1200@deffnx {} BFD_RELOC_PPC_DTPREL16 1201@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1202@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1203@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1204@deffnx {} BFD_RELOC_PPC_DTPREL 1205@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1206@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1207@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1208@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1209@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1210@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1211@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1212@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1213@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1214@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1215@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1216@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1217@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1218@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1219@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1220@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1221@deffnx {} BFD_RELOC_PPC64_TLSGD 1222@deffnx {} BFD_RELOC_PPC64_TLSLD 1223@deffnx {} BFD_RELOC_PPC64_TLSLE 1224@deffnx {} BFD_RELOC_PPC64_TLSIE 1225@deffnx {} BFD_RELOC_PPC64_TLSM 1226@deffnx {} BFD_RELOC_PPC64_TLSML 1227@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1228@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1229@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1230@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1231@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1232@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1233@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1234@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1235@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1236@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1237@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1238@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1239@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1240@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1241@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1242@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1243@deffnx {} BFD_RELOC_PPC64_TPREL34 1244@deffnx {} BFD_RELOC_PPC64_DTPREL34 1245@deffnx {} BFD_RELOC_PPC64_GOT_TLSGD_PCREL34 1246@deffnx {} BFD_RELOC_PPC64_GOT_TLSLD_PCREL34 1247@deffnx {} BFD_RELOC_PPC64_GOT_TPREL_PCREL34 1248@deffnx {} BFD_RELOC_PPC64_GOT_DTPREL_PCREL34 1249@deffnx {} BFD_RELOC_PPC64_TLS_PCREL 1250PowerPC and PowerPC64 thread-local storage relocations. 1251@end deffn 1252@deffn {} BFD_RELOC_I370_D12 1253IBM 370/390 relocations. 1254@end deffn 1255@deffn {} BFD_RELOC_CTOR 1256The type of reloc used to build a constructor table - at the moment 1257probably a 32 bit wide absolute relocation, but the target can choose. 1258It generally does map to one of the other relocation types. 1259@end deffn 1260@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1261ARM 26 bit pc-relative branch. The lowest two bits must be zero and 1262are not stored in the instruction. 1263@end deffn 1264@deffn {} BFD_RELOC_ARM_PCREL_BLX 1265ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1266not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1267field in the instruction. 1268@end deffn 1269@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1270Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1271not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1272field in the instruction. 1273@end deffn 1274@deffn {} BFD_RELOC_ARM_PCREL_CALL 1275ARM 26-bit pc-relative branch for an unconditional BL or BLX 1276instruction. 1277@end deffn 1278@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1279ARM 26-bit pc-relative branch for B or conditional BL instruction. 1280@end deffn 1281@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH5 1282ARM 5-bit pc-relative branch for Branch Future instructions. 1283@end deffn 1284@deffn {} BFD_RELOC_THUMB_PCREL_BFCSEL 1285ARM 6-bit pc-relative branch for BFCSEL instruction. 1286@end deffn 1287@deffn {} BFD_RELOC_ARM_THUMB_BF17 1288ARM 17-bit pc-relative branch for Branch Future instructions. 1289@end deffn 1290@deffn {} BFD_RELOC_ARM_THUMB_BF13 1291ARM 13-bit pc-relative branch for BFCSEL instruction. 1292@end deffn 1293@deffn {} BFD_RELOC_ARM_THUMB_BF19 1294ARM 19-bit pc-relative branch for Branch Future Link instruction. 1295@end deffn 1296@deffn {} BFD_RELOC_ARM_THUMB_LOOP12 1297ARM 12-bit pc-relative branch for Low Overhead Loop instructions. 1298@end deffn 1299@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1300@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1301@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1302@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1303@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1304@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1305Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1306The lowest bit must be zero and is not stored in the instruction. 1307Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1308"nn" one smaller in all cases. Note further that BRANCH23 1309corresponds to R_ARM_THM_CALL. 1310@end deffn 1311@deffn {} BFD_RELOC_ARM_OFFSET_IMM 131212-bit immediate offset, used in ARM-format ldr and str instructions. 1313@end deffn 1314@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13155-bit immediate offset, used in Thumb-format ldr and str instructions. 1316@end deffn 1317@deffn {} BFD_RELOC_ARM_TARGET1 1318Pc-relative or absolute relocation depending on target. Used for 1319entries in .init_array sections. 1320@end deffn 1321@deffn {} BFD_RELOC_ARM_ROSEGREL32 1322Read-only segment base relative address. 1323@end deffn 1324@deffn {} BFD_RELOC_ARM_SBREL32 1325Data segment base relative address. 1326@end deffn 1327@deffn {} BFD_RELOC_ARM_TARGET2 1328This reloc is used for references to RTTI data from exception 1329handling tables. The actual definition depends on the target. It 1330may be a pc-relative or some form of GOT-indirect relocation. 1331@end deffn 1332@deffn {} BFD_RELOC_ARM_PREL31 133331-bit PC relative address. 1334@end deffn 1335@deffn {} BFD_RELOC_ARM_MOVW 1336@deffnx {} BFD_RELOC_ARM_MOVT 1337@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1338@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1339@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1340@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1341@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1342@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1343Low and High halfword relocations for MOVW and MOVT instructions. 1344@end deffn 1345@deffn {} BFD_RELOC_ARM_GOTFUNCDESC 1346@deffnx {} BFD_RELOC_ARM_GOTOFFFUNCDESC 1347@deffnx {} BFD_RELOC_ARM_FUNCDESC 1348@deffnx {} BFD_RELOC_ARM_FUNCDESC_VALUE 1349@deffnx {} BFD_RELOC_ARM_TLS_GD32_FDPIC 1350@deffnx {} BFD_RELOC_ARM_TLS_LDM32_FDPIC 1351@deffnx {} BFD_RELOC_ARM_TLS_IE32_FDPIC 1352ARM FDPIC specific relocations. 1353@end deffn 1354@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1355@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1356@deffnx {} BFD_RELOC_ARM_GOT32 1357@deffnx {} BFD_RELOC_ARM_PLT32 1358@deffnx {} BFD_RELOC_ARM_RELATIVE 1359@deffnx {} BFD_RELOC_ARM_GOTOFF 1360@deffnx {} BFD_RELOC_ARM_GOTPC 1361@deffnx {} BFD_RELOC_ARM_GOT_PREL 1362Relocations for setting up GOTs and PLTs for shared libraries. 1363@end deffn 1364@deffn {} BFD_RELOC_ARM_TLS_GD32 1365@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1366@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1367@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1368@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1369@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1370@deffnx {} BFD_RELOC_ARM_TLS_IE32 1371@deffnx {} BFD_RELOC_ARM_TLS_LE32 1372@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1373@deffnx {} BFD_RELOC_ARM_TLS_CALL 1374@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1375@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1376@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1377@deffnx {} BFD_RELOC_ARM_TLS_DESC 1378ARM thread-local storage relocations. 1379@end deffn 1380@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1381@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1382@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1383@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1384@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1385@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1386@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1387@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1388@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1389@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1390@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1391@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1392@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1393@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1394@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1395@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1396@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1397@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1398@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1399@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1400@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1401@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1402@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1403@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1404@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1405@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1406@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1407@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1408ARM group relocations. 1409@end deffn 1410@deffn {} BFD_RELOC_ARM_V4BX 1411Annotation of BX instructions. 1412@end deffn 1413@deffn {} BFD_RELOC_ARM_IRELATIVE 1414ARM support for STT_GNU_IFUNC. 1415@end deffn 1416@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1417@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1418@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1419@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1420Thumb1 relocations to support execute-only code. 1421@end deffn 1422@deffn {} BFD_RELOC_ARM_IMMEDIATE 1423@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1424@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1425@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1426@deffnx {} BFD_RELOC_ARM_T32_IMM12 1427@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1428@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1429@deffnx {} BFD_RELOC_ARM_SMC 1430@deffnx {} BFD_RELOC_ARM_HVC 1431@deffnx {} BFD_RELOC_ARM_SWI 1432@deffnx {} BFD_RELOC_ARM_MULTI 1433@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1434@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1435@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1436@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1437@deffnx {} BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM 1438@deffnx {} BFD_RELOC_ARM_ADR_IMM 1439@deffnx {} BFD_RELOC_ARM_LDR_IMM 1440@deffnx {} BFD_RELOC_ARM_LITERAL 1441@deffnx {} BFD_RELOC_ARM_IN_POOL 1442@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1443@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1444@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1445@deffnx {} BFD_RELOC_ARM_HWLITERAL 1446@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1447@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1448@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1449These relocs are only used within the ARM assembler. They are not 1450(at present) written to any object files. 1451@end deffn 1452@deffn {} BFD_RELOC_SH_PCDISP8BY2 1453@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1454@deffnx {} BFD_RELOC_SH_IMM3 1455@deffnx {} BFD_RELOC_SH_IMM3U 1456@deffnx {} BFD_RELOC_SH_DISP12 1457@deffnx {} BFD_RELOC_SH_DISP12BY2 1458@deffnx {} BFD_RELOC_SH_DISP12BY4 1459@deffnx {} BFD_RELOC_SH_DISP12BY8 1460@deffnx {} BFD_RELOC_SH_DISP20 1461@deffnx {} BFD_RELOC_SH_DISP20BY8 1462@deffnx {} BFD_RELOC_SH_IMM4 1463@deffnx {} BFD_RELOC_SH_IMM4BY2 1464@deffnx {} BFD_RELOC_SH_IMM4BY4 1465@deffnx {} BFD_RELOC_SH_IMM8 1466@deffnx {} BFD_RELOC_SH_IMM8BY2 1467@deffnx {} BFD_RELOC_SH_IMM8BY4 1468@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1469@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1470@deffnx {} BFD_RELOC_SH_SWITCH16 1471@deffnx {} BFD_RELOC_SH_SWITCH32 1472@deffnx {} BFD_RELOC_SH_USES 1473@deffnx {} BFD_RELOC_SH_COUNT 1474@deffnx {} BFD_RELOC_SH_ALIGN 1475@deffnx {} BFD_RELOC_SH_CODE 1476@deffnx {} BFD_RELOC_SH_DATA 1477@deffnx {} BFD_RELOC_SH_LABEL 1478@deffnx {} BFD_RELOC_SH_LOOP_START 1479@deffnx {} BFD_RELOC_SH_LOOP_END 1480@deffnx {} BFD_RELOC_SH_COPY 1481@deffnx {} BFD_RELOC_SH_GLOB_DAT 1482@deffnx {} BFD_RELOC_SH_JMP_SLOT 1483@deffnx {} BFD_RELOC_SH_RELATIVE 1484@deffnx {} BFD_RELOC_SH_GOTPC 1485@deffnx {} BFD_RELOC_SH_GOT_LOW16 1486@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1487@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1488@deffnx {} BFD_RELOC_SH_GOT_HI16 1489@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1490@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1491@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1492@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1493@deffnx {} BFD_RELOC_SH_PLT_LOW16 1494@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1495@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1496@deffnx {} BFD_RELOC_SH_PLT_HI16 1497@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1498@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1499@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1500@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1501@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1502@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1503@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1504@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1505@deffnx {} BFD_RELOC_SH_COPY64 1506@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1507@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1508@deffnx {} BFD_RELOC_SH_RELATIVE64 1509@deffnx {} BFD_RELOC_SH_GOT10BY4 1510@deffnx {} BFD_RELOC_SH_GOT10BY8 1511@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1512@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1513@deffnx {} BFD_RELOC_SH_GOTPLT32 1514@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1515@deffnx {} BFD_RELOC_SH_IMMU5 1516@deffnx {} BFD_RELOC_SH_IMMS6 1517@deffnx {} BFD_RELOC_SH_IMMS6BY32 1518@deffnx {} BFD_RELOC_SH_IMMU6 1519@deffnx {} BFD_RELOC_SH_IMMS10 1520@deffnx {} BFD_RELOC_SH_IMMS10BY2 1521@deffnx {} BFD_RELOC_SH_IMMS10BY4 1522@deffnx {} BFD_RELOC_SH_IMMS10BY8 1523@deffnx {} BFD_RELOC_SH_IMMS16 1524@deffnx {} BFD_RELOC_SH_IMMU16 1525@deffnx {} BFD_RELOC_SH_IMM_LOW16 1526@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1527@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1528@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1529@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1530@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1531@deffnx {} BFD_RELOC_SH_IMM_HI16 1532@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1533@deffnx {} BFD_RELOC_SH_PT_16 1534@deffnx {} BFD_RELOC_SH_TLS_GD_32 1535@deffnx {} BFD_RELOC_SH_TLS_LD_32 1536@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1537@deffnx {} BFD_RELOC_SH_TLS_IE_32 1538@deffnx {} BFD_RELOC_SH_TLS_LE_32 1539@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1540@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1541@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1542@deffnx {} BFD_RELOC_SH_GOT20 1543@deffnx {} BFD_RELOC_SH_GOTOFF20 1544@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1545@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1546@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1547@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1548@deffnx {} BFD_RELOC_SH_FUNCDESC 1549Renesas / SuperH SH relocs. Not all of these appear in object files. 1550@end deffn 1551@deffn {} BFD_RELOC_ARC_NONE 1552@deffnx {} BFD_RELOC_ARC_8 1553@deffnx {} BFD_RELOC_ARC_16 1554@deffnx {} BFD_RELOC_ARC_24 1555@deffnx {} BFD_RELOC_ARC_32 1556@deffnx {} BFD_RELOC_ARC_N8 1557@deffnx {} BFD_RELOC_ARC_N16 1558@deffnx {} BFD_RELOC_ARC_N24 1559@deffnx {} BFD_RELOC_ARC_N32 1560@deffnx {} BFD_RELOC_ARC_SDA 1561@deffnx {} BFD_RELOC_ARC_SECTOFF 1562@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1563@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1564@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1565@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1566@deffnx {} BFD_RELOC_ARC_SDA32 1567@deffnx {} BFD_RELOC_ARC_SDA_LDST 1568@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1569@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1570@deffnx {} BFD_RELOC_ARC_SDA16_LD 1571@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1572@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1573@deffnx {} BFD_RELOC_ARC_S13_PCREL 1574@deffnx {} BFD_RELOC_ARC_W 1575@deffnx {} BFD_RELOC_ARC_32_ME 1576@deffnx {} BFD_RELOC_ARC_32_ME_S 1577@deffnx {} BFD_RELOC_ARC_N32_ME 1578@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1579@deffnx {} BFD_RELOC_ARC_SDA32_ME 1580@deffnx {} BFD_RELOC_ARC_W_ME 1581@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1582@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1583@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1584@deffnx {} BFD_RELOC_AC_SECTOFF_S9 1585@deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1586@deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1587@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1588@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1589@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1590@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1591@deffnx {} BFD_RELOC_ARC_SDA_12 1592@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1593@deffnx {} BFD_RELOC_ARC_32_PCREL 1594@deffnx {} BFD_RELOC_ARC_PC32 1595@deffnx {} BFD_RELOC_ARC_GOT32 1596@deffnx {} BFD_RELOC_ARC_GOTPC32 1597@deffnx {} BFD_RELOC_ARC_PLT32 1598@deffnx {} BFD_RELOC_ARC_COPY 1599@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1600@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1601@deffnx {} BFD_RELOC_ARC_RELATIVE 1602@deffnx {} BFD_RELOC_ARC_GOTOFF 1603@deffnx {} BFD_RELOC_ARC_GOTPC 1604@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1605@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1606@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1607@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1608@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1609@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1610@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1611@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1612@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1613@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1614@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1615@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1616@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1617@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1618@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1619@deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1620ARC relocs. 1621@end deffn 1622@deffn {} BFD_RELOC_BFIN_16_IMM 1623ADI Blackfin 16 bit immediate absolute reloc. 1624@end deffn 1625@deffn {} BFD_RELOC_BFIN_16_HIGH 1626ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1627@end deffn 1628@deffn {} BFD_RELOC_BFIN_4_PCREL 1629ADI Blackfin 'a' part of LSETUP. 1630@end deffn 1631@deffn {} BFD_RELOC_BFIN_5_PCREL 1632ADI Blackfin. 1633@end deffn 1634@deffn {} BFD_RELOC_BFIN_16_LOW 1635ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1636@end deffn 1637@deffn {} BFD_RELOC_BFIN_10_PCREL 1638ADI Blackfin. 1639@end deffn 1640@deffn {} BFD_RELOC_BFIN_11_PCREL 1641ADI Blackfin 'b' part of LSETUP. 1642@end deffn 1643@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1644ADI Blackfin. 1645@end deffn 1646@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1647ADI Blackfin Short jump, pcrel. 1648@end deffn 1649@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1650ADI Blackfin Call.x not implemented. 1651@end deffn 1652@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1653ADI Blackfin Long Jump pcrel. 1654@end deffn 1655@deffn {} BFD_RELOC_BFIN_GOT17M4 1656@deffnx {} BFD_RELOC_BFIN_GOTHI 1657@deffnx {} BFD_RELOC_BFIN_GOTLO 1658@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1659@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1660@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1661@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1662@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1663@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1664@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1665@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1666@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1667@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1668@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1669ADI Blackfin FD-PIC relocations. 1670@end deffn 1671@deffn {} BFD_RELOC_BFIN_GOT 1672ADI Blackfin GOT relocation. 1673@end deffn 1674@deffn {} BFD_RELOC_BFIN_PLTPC 1675ADI Blackfin PLTPC relocation. 1676@end deffn 1677@deffn {} BFD_ARELOC_BFIN_PUSH 1678ADI Blackfin arithmetic relocation. 1679@end deffn 1680@deffn {} BFD_ARELOC_BFIN_CONST 1681ADI Blackfin arithmetic relocation. 1682@end deffn 1683@deffn {} BFD_ARELOC_BFIN_ADD 1684ADI Blackfin arithmetic relocation. 1685@end deffn 1686@deffn {} BFD_ARELOC_BFIN_SUB 1687ADI Blackfin arithmetic relocation. 1688@end deffn 1689@deffn {} BFD_ARELOC_BFIN_MULT 1690ADI Blackfin arithmetic relocation. 1691@end deffn 1692@deffn {} BFD_ARELOC_BFIN_DIV 1693ADI Blackfin arithmetic relocation. 1694@end deffn 1695@deffn {} BFD_ARELOC_BFIN_MOD 1696ADI Blackfin arithmetic relocation. 1697@end deffn 1698@deffn {} BFD_ARELOC_BFIN_LSHIFT 1699ADI Blackfin arithmetic relocation. 1700@end deffn 1701@deffn {} BFD_ARELOC_BFIN_RSHIFT 1702ADI Blackfin arithmetic relocation. 1703@end deffn 1704@deffn {} BFD_ARELOC_BFIN_AND 1705ADI Blackfin arithmetic relocation. 1706@end deffn 1707@deffn {} BFD_ARELOC_BFIN_OR 1708ADI Blackfin arithmetic relocation. 1709@end deffn 1710@deffn {} BFD_ARELOC_BFIN_XOR 1711ADI Blackfin arithmetic relocation. 1712@end deffn 1713@deffn {} BFD_ARELOC_BFIN_LAND 1714ADI Blackfin arithmetic relocation. 1715@end deffn 1716@deffn {} BFD_ARELOC_BFIN_LOR 1717ADI Blackfin arithmetic relocation. 1718@end deffn 1719@deffn {} BFD_ARELOC_BFIN_LEN 1720ADI Blackfin arithmetic relocation. 1721@end deffn 1722@deffn {} BFD_ARELOC_BFIN_NEG 1723ADI Blackfin arithmetic relocation. 1724@end deffn 1725@deffn {} BFD_ARELOC_BFIN_COMP 1726ADI Blackfin arithmetic relocation. 1727@end deffn 1728@deffn {} BFD_ARELOC_BFIN_PAGE 1729ADI Blackfin arithmetic relocation. 1730@end deffn 1731@deffn {} BFD_ARELOC_BFIN_HWPAGE 1732ADI Blackfin arithmetic relocation. 1733@end deffn 1734@deffn {} BFD_ARELOC_BFIN_ADDR 1735ADI Blackfin arithmetic relocation. 1736@end deffn 1737@deffn {} BFD_RELOC_D10V_10_PCREL_R 1738Mitsubishi D10V relocs. 1739This is a 10-bit reloc with the right 2 bits assumed to be 0. 1740@end deffn 1741@deffn {} BFD_RELOC_D10V_10_PCREL_L 1742Mitsubishi D10V relocs. 1743This is a 10-bit reloc with the right 2 bits assumed to be 0. This 1744is the same as the previous reloc except it is in the left 1745container, i.e., shifted left 15 bits. 1746@end deffn 1747@deffn {} BFD_RELOC_D10V_18 1748This is an 18-bit reloc with the right 2 bits assumed to be 0. 1749@end deffn 1750@deffn {} BFD_RELOC_D10V_18_PCREL 1751This is an 18-bit reloc with the right 2 bits assumed to be 0. 1752@end deffn 1753@deffn {} BFD_RELOC_D30V_6 1754Mitsubishi D30V relocs. 1755This is a 6-bit absolute reloc. 1756@end deffn 1757@deffn {} BFD_RELOC_D30V_9_PCREL 1758This is a 6-bit pc-relative reloc with the right 3 bits assumed to 1759be 0. 1760@end deffn 1761@deffn {} BFD_RELOC_D30V_9_PCREL_R 1762This is a 6-bit pc-relative reloc with the right 3 bits assumed to 1763be 0. Same as the previous reloc but on the right side of the 1764container. 1765@end deffn 1766@deffn {} BFD_RELOC_D30V_15 1767This is a 12-bit absolute reloc with the right 3 bitsassumed to 1768be 0. 1769@end deffn 1770@deffn {} BFD_RELOC_D30V_15_PCREL 1771This is a 12-bit pc-relative reloc with the right 3 bits assumed to 1772be 0. 1773@end deffn 1774@deffn {} BFD_RELOC_D30V_15_PCREL_R 1775This is a 12-bit pc-relative reloc with the right 3 bits assumed to 1776be 0. Same as the previous reloc but on the right side of the 1777container. 1778@end deffn 1779@deffn {} BFD_RELOC_D30V_21 1780This is an 18-bit absolute reloc with the right 3 bits assumed to 1781be 0. 1782@end deffn 1783@deffn {} BFD_RELOC_D30V_21_PCREL 1784This is an 18-bit pc-relative reloc with the right 3 bits assumed to 1785be 0. 1786@end deffn 1787@deffn {} BFD_RELOC_D30V_21_PCREL_R 1788This is an 18-bit pc-relative reloc with the right 3 bits assumed to 1789be 0. Same as the previous reloc but on the right side of the 1790container. 1791@end deffn 1792@deffn {} BFD_RELOC_D30V_32 1793This is a 32-bit absolute reloc. 1794@end deffn 1795@deffn {} BFD_RELOC_D30V_32_PCREL 1796This is a 32-bit pc-relative reloc. 1797@end deffn 1798@deffn {} BFD_RELOC_DLX_HI16_S 1799@deffnx {} BFD_RELOC_DLX_LO16 1800@deffnx {} BFD_RELOC_DLX_JMP26 1801DLX relocs. 1802@end deffn 1803@deffn {} BFD_RELOC_M32C_HI8 1804@deffnx {} BFD_RELOC_M32C_RL_JUMP 1805@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1806@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1807Renesas M16C/M32C Relocations. 1808@end deffn 1809@deffn {} BFD_RELOC_M32R_24 1810Renesas M32R (formerly Mitsubishi M32R) relocs. 1811This is a 24 bit absolute address. 1812@end deffn 1813@deffn {} BFD_RELOC_M32R_10_PCREL 1814This is a 10-bit pc-relative reloc with the right 2 bits assumed to 1815be 0. 1816@end deffn 1817@deffn {} BFD_RELOC_M32R_18_PCREL 1818This is an 18-bit reloc with the right 2 bits assumed to be 0. 1819@end deffn 1820@deffn {} BFD_RELOC_M32R_26_PCREL 1821This is a 26-bit reloc with the right 2 bits assumed to be 0. 1822@end deffn 1823@deffn {} BFD_RELOC_M32R_HI16_ULO 1824This is a 16-bit reloc containing the high 16 bits of an address 1825used when the lower 16 bits are treated as unsigned. 1826@end deffn 1827@deffn {} BFD_RELOC_M32R_HI16_SLO 1828This is a 16-bit reloc containing the high 16 bits of an address 1829used when the lower 16 bits are treated as signed. 1830@end deffn 1831@deffn {} BFD_RELOC_M32R_LO16 1832This is a 16-bit reloc containing the lower 16 bits of an address. 1833@end deffn 1834@deffn {} BFD_RELOC_M32R_SDA16 1835This is a 16-bit reloc containing the small data area offset for use 1836in add3, load, and store instructions. 1837@end deffn 1838@deffn {} BFD_RELOC_M32R_GOT24 1839@deffnx {} BFD_RELOC_M32R_26_PLTREL 1840@deffnx {} BFD_RELOC_M32R_COPY 1841@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1842@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1843@deffnx {} BFD_RELOC_M32R_RELATIVE 1844@deffnx {} BFD_RELOC_M32R_GOTOFF 1845@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1846@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1847@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1848@deffnx {} BFD_RELOC_M32R_GOTPC24 1849@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1850@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1851@deffnx {} BFD_RELOC_M32R_GOT16_LO 1852@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1853@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1854@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1855For PIC. 1856@end deffn 1857@deffn {} BFD_RELOC_NDS32_20 1858NDS32 relocs. 1859This is a 20 bit absolute address. 1860@end deffn 1861@deffn {} BFD_RELOC_NDS32_9_PCREL 1862This is a 9-bit pc-relative reloc with the right 1 bit assumed to 1863be 0. 1864@end deffn 1865@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1866This is a 9-bit pc-relative reloc with the right 1 bit assumed to 1867be 0. 1868@end deffn 1869@deffn {} BFD_RELOC_NDS32_15_PCREL 1870This is an 15-bit reloc with the right 1 bit assumed to be 0. 1871@end deffn 1872@deffn {} BFD_RELOC_NDS32_17_PCREL 1873This is an 17-bit reloc with the right 1 bit assumed to be 0. 1874@end deffn 1875@deffn {} BFD_RELOC_NDS32_25_PCREL 1876This is a 25-bit reloc with the right 1 bit assumed to be 0. 1877@end deffn 1878@deffn {} BFD_RELOC_NDS32_HI20 1879This is a 20-bit reloc containing the high 20 bits of an address 1880used with the lower 12 bits. 1881@end deffn 1882@deffn {} BFD_RELOC_NDS32_LO12S3 1883This is a 12-bit reloc containing the lower 12 bits of an address 1884then shift right by 3. This is used with ldi,sdi. 1885@end deffn 1886@deffn {} BFD_RELOC_NDS32_LO12S2 1887This is a 12-bit reloc containing the lower 12 bits of an address 1888then shift left by 2. This is used with lwi,swi. 1889@end deffn 1890@deffn {} BFD_RELOC_NDS32_LO12S1 1891This is a 12-bit reloc containing the lower 12 bits of an address 1892then shift left by 1. This is used with lhi,shi. 1893@end deffn 1894@deffn {} BFD_RELOC_NDS32_LO12S0 1895This is a 12-bit reloc containing the lower 12 bits of an address 1896then shift left by 0. This is used with lbisbi. 1897@end deffn 1898@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1899This is a 12-bit reloc containing the lower 12 bits of an address 1900then shift left by 0. This is only used with branch relaxations. 1901@end deffn 1902@deffn {} BFD_RELOC_NDS32_SDA15S3 1903This is a 15-bit reloc containing the small data area 18-bit signed 1904offset and shift left by 3 for use in ldi, sdi. 1905@end deffn 1906@deffn {} BFD_RELOC_NDS32_SDA15S2 1907This is a 15-bit reloc containing the small data area 17-bit signed 1908offset and shift left by 2 for use in lwi, swi. 1909@end deffn 1910@deffn {} BFD_RELOC_NDS32_SDA15S1 1911This is a 15-bit reloc containing the small data area 16-bit signed 1912offset and shift left by 1 for use in lhi, shi. 1913@end deffn 1914@deffn {} BFD_RELOC_NDS32_SDA15S0 1915This is a 15-bit reloc containing the small data area 15-bit signed 1916offset and shift left by 0 for use in lbi, sbi. 1917@end deffn 1918@deffn {} BFD_RELOC_NDS32_SDA16S3 1919This is a 16-bit reloc containing the small data area 16-bit signed 1920offset and shift left by 3. 1921@end deffn 1922@deffn {} BFD_RELOC_NDS32_SDA17S2 1923This is a 17-bit reloc containing the small data area 17-bit signed 1924offset and shift left by 2 for use in lwi.gp, swi.gp. 1925@end deffn 1926@deffn {} BFD_RELOC_NDS32_SDA18S1 1927This is a 18-bit reloc containing the small data area 18-bit signed 1928offset and shift left by 1 for use in lhi.gp, shi.gp. 1929@end deffn 1930@deffn {} BFD_RELOC_NDS32_SDA19S0 1931This is a 19-bit reloc containing the small data area 19-bit signed 1932offset and shift left by 0 for use in lbi.gp, sbi.gp. 1933@end deffn 1934@deffn {} BFD_RELOC_NDS32_GOT20 1935@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1936@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1937@deffnx {} BFD_RELOC_NDS32_COPY 1938@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1939@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1940@deffnx {} BFD_RELOC_NDS32_RELATIVE 1941@deffnx {} BFD_RELOC_NDS32_GOTOFF 1942@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1943@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1944@deffnx {} BFD_RELOC_NDS32_GOTPC20 1945@deffnx {} BFD_RELOC_NDS32_GOT_HI20 1946@deffnx {} BFD_RELOC_NDS32_GOT_LO12 1947@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1948@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1949For PIC. 1950@end deffn 1951@deffn {} BFD_RELOC_NDS32_INSN16 1952@deffnx {} BFD_RELOC_NDS32_LABEL 1953@deffnx {} BFD_RELOC_NDS32_LONGCALL1 1954@deffnx {} BFD_RELOC_NDS32_LONGCALL2 1955@deffnx {} BFD_RELOC_NDS32_LONGCALL3 1956@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1957@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1958@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1959@deffnx {} BFD_RELOC_NDS32_LOADSTORE 1960@deffnx {} BFD_RELOC_NDS32_9_FIXED 1961@deffnx {} BFD_RELOC_NDS32_15_FIXED 1962@deffnx {} BFD_RELOC_NDS32_17_FIXED 1963@deffnx {} BFD_RELOC_NDS32_25_FIXED 1964@deffnx {} BFD_RELOC_NDS32_LONGCALL4 1965@deffnx {} BFD_RELOC_NDS32_LONGCALL5 1966@deffnx {} BFD_RELOC_NDS32_LONGCALL6 1967@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 1968@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 1969@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 1970@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 1971For relax. 1972@end deffn 1973@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 1974@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 1975@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 1976@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 1977For PIC. 1978@end deffn 1979@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 1980@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 1981@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 1982@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 1983For floating point. 1984@end deffn 1985@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 1986@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 1987@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 1988For dwarf2 debug_line. 1989@end deffn 1990@deffn {} BFD_RELOC_NDS32_UPDATE_TA 1991For eliminating 16-bit instructions. 1992@end deffn 1993@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 1994@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 1995@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 1996@deffnx {} BFD_RELOC_NDS32_GOT_LO15 1997@deffnx {} BFD_RELOC_NDS32_GOT_LO19 1998@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 1999@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2000@deffnx {} BFD_RELOC_NDS32_GOT15S2 2001@deffnx {} BFD_RELOC_NDS32_GOT17S2 2002For PIC object relaxation. 2003@end deffn 2004@deffn {} BFD_RELOC_NDS32_5 2005NDS32 relocs. 2006This is a 5 bit absolute address. 2007@end deffn 2008@deffn {} BFD_RELOC_NDS32_10_UPCREL 2009This is a 10-bit unsigned pc-relative reloc with the right 1 bit 2010assumed to be 0. 2011@end deffn 2012@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2013If fp were omitted, fp can used as another gp. 2014@end deffn 2015@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2016@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2017@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2018@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2019@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2020@deffnx {} BFD_RELOC_NDS32_PTR 2021@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2022@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2023@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2024@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2025@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2026@deffnx {} BFD_RELOC_NDS32_MINUEND 2027@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2028@deffnx {} BFD_RELOC_NDS32_DIFF8 2029@deffnx {} BFD_RELOC_NDS32_DIFF16 2030@deffnx {} BFD_RELOC_NDS32_DIFF32 2031@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2032@deffnx {} BFD_RELOC_NDS32_EMPTY 2033Relaxation relative relocation types. 2034@end deffn 2035@deffn {} BFD_RELOC_NDS32_25_ABS 2036This is a 25 bit absolute address. 2037@end deffn 2038@deffn {} BFD_RELOC_NDS32_DATA 2039@deffnx {} BFD_RELOC_NDS32_TRAN 2040@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2041@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2042For ex9 and ifc using. 2043@end deffn 2044@deffn {} BFD_RELOC_NDS32_TPOFF 2045@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2046@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2047@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2048@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2049@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2050@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2051@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2052@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2053@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2054@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2055@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12 2056@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2057@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_HI20 2058@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12 2059@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12S2 2060@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LW 2061@deffnx {} BFD_RELOC_NDS32_TLS_DESC 2062@deffnx {} BFD_RELOC_NDS32_TLS_DESC_HI20 2063@deffnx {} BFD_RELOC_NDS32_TLS_DESC_LO12 2064@deffnx {} BFD_RELOC_NDS32_TLS_DESC_20 2065@deffnx {} BFD_RELOC_NDS32_TLS_DESC_SDA17S2 2066@deffnx {} BFD_RELOC_NDS32_TLS_DESC_ADD 2067@deffnx {} BFD_RELOC_NDS32_TLS_DESC_FUNC 2068@deffnx {} BFD_RELOC_NDS32_TLS_DESC_CALL 2069@deffnx {} BFD_RELOC_NDS32_TLS_DESC_MEM 2070@deffnx {} BFD_RELOC_NDS32_REMOVE 2071@deffnx {} BFD_RELOC_NDS32_GROUP 2072For TLS. 2073@end deffn 2074@deffn {} BFD_RELOC_NDS32_LSI 2075For floating load store relaxation. 2076@end deffn 2077@deffn {} BFD_RELOC_V850_9_PCREL 2078This is a 9-bit reloc. 2079@end deffn 2080@deffn {} BFD_RELOC_V850_22_PCREL 2081This is a 22-bit reloc. 2082@end deffn 2083@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2084This is a 16 bit offset from the short data area pointer. 2085@end deffn 2086@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2087This is a 16 bit offset (of which only 15 bits are used) from the 2088short data area pointer. 2089@end deffn 2090@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2091This is a 16 bit offset from the zero data area pointer. 2092@end deffn 2093@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2094This is a 16 bit offset (of which only 15 bits are used) from the 2095zero data area pointer. 2096@end deffn 2097@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2098This is an 8 bit offset (of which only 6 bits are used) from the 2099tiny data area pointer. 2100@end deffn 2101@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2102This is an 8bit offset (of which only 7 bits are used) from the tiny 2103data area pointer. 2104@end deffn 2105@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2106This is a 7 bit offset from the tiny data area pointer. 2107@end deffn 2108@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2109This is a 16 bit offset from the tiny data area pointer. 2110@end deffn 2111@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2112This is a 5 bit offset (of which only 4 bits are used) from the tiny 2113data area pointer. 2114@end deffn 2115@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2116This is a 4 bit offset from the tiny data area pointer. 2117@end deffn 2118@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2119This is a 16 bit offset from the short data area pointer, with the 2120bits placed non-contiguously in the instruction. 2121@end deffn 2122@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2123This is a 16 bit offset from the zero data area pointer, with the 2124bits placed non-contiguously in the instruction. 2125@end deffn 2126@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2127This is a 6 bit offset from the call table base pointer. 2128@end deffn 2129@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2130This is a 16 bit offset from the call table base pointer. 2131@end deffn 2132@deffn {} BFD_RELOC_V850_LONGCALL 2133Used for relaxing indirect function calls. 2134@end deffn 2135@deffn {} BFD_RELOC_V850_LONGJUMP 2136Used for relaxing indirect jumps. 2137@end deffn 2138@deffn {} BFD_RELOC_V850_ALIGN 2139Used to maintain alignment whilst relaxing. 2140@end deffn 2141@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2142This is a variation of BFD_RELOC_LO16 that can be used in v850e 2143ld.bu instructions. 2144@end deffn 2145@deffn {} BFD_RELOC_V850_16_PCREL 2146This is a 16-bit reloc. 2147@end deffn 2148@deffn {} BFD_RELOC_V850_17_PCREL 2149This is a 17-bit reloc. 2150@end deffn 2151@deffn {} BFD_RELOC_V850_23 2152This is a 23-bit reloc. 2153@end deffn 2154@deffn {} BFD_RELOC_V850_32_PCREL 2155This is a 32-bit reloc. 2156@end deffn 2157@deffn {} BFD_RELOC_V850_32_ABS 2158This is a 32-bit reloc. 2159@end deffn 2160@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2161This is a 16-bit reloc. 2162@end deffn 2163@deffn {} BFD_RELOC_V850_16_S1 2164This is a 16-bit reloc. 2165@end deffn 2166@deffn {} BFD_RELOC_V850_LO16_S1 2167Low 16 bits. 16 bit shifted by 1. 2168@end deffn 2169@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2170This is a 16 bit offset from the call table base pointer. 2171@end deffn 2172@deffn {} BFD_RELOC_V850_32_GOTPCREL 2173@deffnx {} BFD_RELOC_V850_16_GOT 2174@deffnx {} BFD_RELOC_V850_32_GOT 2175@deffnx {} BFD_RELOC_V850_22_PLT_PCREL 2176@deffnx {} BFD_RELOC_V850_32_PLT_PCREL 2177@deffnx {} BFD_RELOC_V850_COPY 2178@deffnx {} BFD_RELOC_V850_GLOB_DAT 2179@deffnx {} BFD_RELOC_V850_JMP_SLOT 2180@deffnx {} BFD_RELOC_V850_RELATIVE 2181@deffnx {} BFD_RELOC_V850_16_GOTOFF 2182@deffnx {} BFD_RELOC_V850_32_GOTOFF 2183DSO relocations. 2184@end deffn 2185@deffn {} BFD_RELOC_V850_CODE 2186Start code. 2187@end deffn 2188@deffn {} BFD_RELOC_V850_DATA 2189Start data in text. 2190@end deffn 2191@deffn {} BFD_RELOC_TIC30_LDP 2192This is a 8bit DP reloc for the tms320c30, where the most 2193significant 8 bits of a 24 bit word are placed into the least 2194significant 8 bits of the opcode. 2195@end deffn 2196@deffn {} BFD_RELOC_TIC54X_PARTLS7 2197This is a 7bit reloc for the tms320c54x, where the least 2198significant 7 bits of a 16 bit word are placed into the least 2199significant 7 bits of the opcode. 2200@end deffn 2201@deffn {} BFD_RELOC_TIC54X_PARTMS9 2202This is a 9bit DP reloc for the tms320c54x, where the most 2203significant 9 bits of a 16 bit word are placed into the least 2204significant 9 bits of the opcode. 2205@end deffn 2206@deffn {} BFD_RELOC_TIC54X_23 2207This is an extended address 23-bit reloc for the tms320c54x. 2208@end deffn 2209@deffn {} BFD_RELOC_TIC54X_16_OF_23 2210This is a 16-bit reloc for the tms320c54x, where the least 2211significant 16 bits of a 23-bit extended address are placed into 2212the opcode. 2213@end deffn 2214@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2215This is a reloc for the tms320c54x, where the most 2216significant 7 bits of a 23-bit extended address are placed into 2217the opcode. 2218@end deffn 2219@deffn {} BFD_RELOC_C6000_PCR_S21 2220@deffnx {} BFD_RELOC_C6000_PCR_S12 2221@deffnx {} BFD_RELOC_C6000_PCR_S10 2222@deffnx {} BFD_RELOC_C6000_PCR_S7 2223@deffnx {} BFD_RELOC_C6000_ABS_S16 2224@deffnx {} BFD_RELOC_C6000_ABS_L16 2225@deffnx {} BFD_RELOC_C6000_ABS_H16 2226@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2227@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2228@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2229@deffnx {} BFD_RELOC_C6000_SBR_S16 2230@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2231@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2232@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2233@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2234@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2235@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2236@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2237@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2238@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2239@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2240@deffnx {} BFD_RELOC_C6000_PREL31 2241@deffnx {} BFD_RELOC_C6000_COPY 2242@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2243@deffnx {} BFD_RELOC_C6000_EHTYPE 2244@deffnx {} BFD_RELOC_C6000_PCR_H16 2245@deffnx {} BFD_RELOC_C6000_PCR_L16 2246@deffnx {} BFD_RELOC_C6000_ALIGN 2247@deffnx {} BFD_RELOC_C6000_FPHEAD 2248@deffnx {} BFD_RELOC_C6000_NOCMP 2249TMS320C6000 relocations. 2250@end deffn 2251@deffn {} BFD_RELOC_FR30_48 2252This is a 48 bit reloc for the FR30 that stores 32 bits. 2253@end deffn 2254@deffn {} BFD_RELOC_FR30_20 2255This is a 32 bit reloc for the FR30 that stores 20 bits split up 2256into two sections. 2257@end deffn 2258@deffn {} BFD_RELOC_FR30_6_IN_4 2259This is a 16 bit reloc for the FR30 that stores a 6 bit word offset 2260in 4 bits. 2261@end deffn 2262@deffn {} BFD_RELOC_FR30_8_IN_8 2263This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2264into 8 bits. 2265@end deffn 2266@deffn {} BFD_RELOC_FR30_9_IN_8 2267This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2268into 8 bits. 2269@end deffn 2270@deffn {} BFD_RELOC_FR30_10_IN_8 2271This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2272into 8 bits. 2273@end deffn 2274@deffn {} BFD_RELOC_FR30_9_PCREL 2275This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2276short offset into 8 bits. 2277@end deffn 2278@deffn {} BFD_RELOC_FR30_12_PCREL 2279This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2280short offset into 11 bits. 2281@end deffn 2282@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2283@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2284@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2285@deffnx {} BFD_RELOC_MCORE_PCREL_32 2286@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2287@deffnx {} BFD_RELOC_MCORE_RVA 2288Motorola Mcore relocations. 2289@end deffn 2290@deffn {} BFD_RELOC_MEP_8 2291@deffnx {} BFD_RELOC_MEP_16 2292@deffnx {} BFD_RELOC_MEP_32 2293@deffnx {} BFD_RELOC_MEP_PCREL8A2 2294@deffnx {} BFD_RELOC_MEP_PCREL12A2 2295@deffnx {} BFD_RELOC_MEP_PCREL17A2 2296@deffnx {} BFD_RELOC_MEP_PCREL24A2 2297@deffnx {} BFD_RELOC_MEP_PCABS24A2 2298@deffnx {} BFD_RELOC_MEP_LOW16 2299@deffnx {} BFD_RELOC_MEP_HI16U 2300@deffnx {} BFD_RELOC_MEP_HI16S 2301@deffnx {} BFD_RELOC_MEP_GPREL 2302@deffnx {} BFD_RELOC_MEP_TPREL 2303@deffnx {} BFD_RELOC_MEP_TPREL7 2304@deffnx {} BFD_RELOC_MEP_TPREL7A2 2305@deffnx {} BFD_RELOC_MEP_TPREL7A4 2306@deffnx {} BFD_RELOC_MEP_UIMM24 2307@deffnx {} BFD_RELOC_MEP_ADDR24A4 2308@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2309@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2310Toshiba Media Processor Relocations. 2311@end deffn 2312@deffn {} BFD_RELOC_METAG_HIADDR16 2313@deffnx {} BFD_RELOC_METAG_LOADDR16 2314@deffnx {} BFD_RELOC_METAG_RELBRANCH 2315@deffnx {} BFD_RELOC_METAG_GETSETOFF 2316@deffnx {} BFD_RELOC_METAG_HIOG 2317@deffnx {} BFD_RELOC_METAG_LOOG 2318@deffnx {} BFD_RELOC_METAG_REL8 2319@deffnx {} BFD_RELOC_METAG_REL16 2320@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2321@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2322@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2323@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2324@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2325@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2326@deffnx {} BFD_RELOC_METAG_HI16_PLT 2327@deffnx {} BFD_RELOC_METAG_LO16_PLT 2328@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2329@deffnx {} BFD_RELOC_METAG_GOTOFF 2330@deffnx {} BFD_RELOC_METAG_PLT 2331@deffnx {} BFD_RELOC_METAG_COPY 2332@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2333@deffnx {} BFD_RELOC_METAG_RELATIVE 2334@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2335@deffnx {} BFD_RELOC_METAG_TLS_GD 2336@deffnx {} BFD_RELOC_METAG_TLS_LDM 2337@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2338@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2339@deffnx {} BFD_RELOC_METAG_TLS_LDO 2340@deffnx {} BFD_RELOC_METAG_TLS_IE 2341@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2342@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2343@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2344@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2345@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2346@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2347@deffnx {} BFD_RELOC_METAG_TLS_LE 2348@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2349@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2350Imagination Technologies Meta relocations. 2351@end deffn 2352@deffn {} BFD_RELOC_MMIX_GETA 2353@deffnx {} BFD_RELOC_MMIX_GETA_1 2354@deffnx {} BFD_RELOC_MMIX_GETA_2 2355@deffnx {} BFD_RELOC_MMIX_GETA_3 2356These are relocations for the GETA instruction. 2357@end deffn 2358@deffn {} BFD_RELOC_MMIX_CBRANCH 2359@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2360@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2361@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2362@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2363These are relocations for a conditional branch instruction. 2364@end deffn 2365@deffn {} BFD_RELOC_MMIX_PUSHJ 2366@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2367@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2368@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2369@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2370These are relocations for the PUSHJ instruction. 2371@end deffn 2372@deffn {} BFD_RELOC_MMIX_JMP 2373@deffnx {} BFD_RELOC_MMIX_JMP_1 2374@deffnx {} BFD_RELOC_MMIX_JMP_2 2375@deffnx {} BFD_RELOC_MMIX_JMP_3 2376These are relocations for the JMP instruction. 2377@end deffn 2378@deffn {} BFD_RELOC_MMIX_ADDR19 2379This is a relocation for a relative address as in a GETA instruction 2380or a branch. 2381@end deffn 2382@deffn {} BFD_RELOC_MMIX_ADDR27 2383This is a relocation for a relative address as in a JMP instruction. 2384@end deffn 2385@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2386This is a relocation for an instruction field that may be a general 2387register or a value 0..255. 2388@end deffn 2389@deffn {} BFD_RELOC_MMIX_REG 2390This is a relocation for an instruction field that may be a general 2391register. 2392@end deffn 2393@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2394This is a relocation for two instruction fields holding a register 2395and an offset, the equivalent of the relocation. 2396@end deffn 2397@deffn {} BFD_RELOC_MMIX_LOCAL 2398This relocation is an assertion that the expression is not allocated 2399as a global register. It does not modify contents. 2400@end deffn 2401@deffn {} BFD_RELOC_AVR_7_PCREL 2402This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2403short offset into 7 bits. 2404@end deffn 2405@deffn {} BFD_RELOC_AVR_13_PCREL 2406This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2407short offset into 12 bits. 2408@end deffn 2409@deffn {} BFD_RELOC_AVR_16_PM 2410This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2411program memory address) into 16 bits. 2412@end deffn 2413@deffn {} BFD_RELOC_AVR_LO8_LDI 2414This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2415data memory address) into 8 bit immediate value of LDI insn. 2416@end deffn 2417@deffn {} BFD_RELOC_AVR_HI8_LDI 2418This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2419of data memory address) into 8 bit immediate value of LDI insn. 2420@end deffn 2421@deffn {} BFD_RELOC_AVR_HH8_LDI 2422This is a 16 bit reloc for the AVR that stores 8 bit value (most 2423high 8 bit of program memory address) into 8 bit immediate value of 2424LDI insn. 2425@end deffn 2426@deffn {} BFD_RELOC_AVR_MS8_LDI 2427This is a 16 bit reloc for the AVR that stores 8 bit value (most 2428high 8 bit of 32 bit value) into 8 bit immediate value of LDI insn. 2429@end deffn 2430@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2431This is a 16 bit reloc for the AVR that stores negated 8 bit value 2432(usually data memory address) into 8 bit immediate value of SUBI insn. 2433@end deffn 2434@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2435This is a 16 bit reloc for the AVR that stores negated 8 bit value 2436(high 8 bit of data memory address) into 8 bit immediate value of 2437SUBI insn. 2438@end deffn 2439@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2440This is a 16 bit reloc for the AVR that stores negated 8 bit value 2441(most high 8 bit of program memory address) into 8 bit immediate 2442value of LDI or SUBI insn. 2443@end deffn 2444@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2445This is a 16 bit reloc for the AVR that stores negated 8 bit value 2446(msb of 32 bit value) into 8 bit immediate value of LDI insn. 2447@end deffn 2448@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2449This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2450command address) into 8 bit immediate value of LDI insn. 2451@end deffn 2452@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2453This is a 16 bit reloc for the AVR that stores 8 bit value 2454(command address) into 8 bit immediate value of LDI insn. If the 2455address is beyond the 128k boundary, the linker inserts a jump stub 2456for this reloc in the lower 128k. 2457@end deffn 2458@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2459This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2460of command address) into 8 bit immediate value of LDI insn. 2461@end deffn 2462@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2463This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2464of command address) into 8 bit immediate value of LDI insn. If the 2465address is beyond the 128k boundary, the linker inserts a jump stub 2466for this reloc below 128k. 2467@end deffn 2468@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2469This is a 16 bit reloc for the AVR that stores 8 bit value (most 2470high 8 bit of command address) into 8 bit immediate value of LDI 2471insn. 2472@end deffn 2473@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2474This is a 16 bit reloc for the AVR that stores negated 8 bit value 2475(usually command address) into 8 bit immediate value of SUBI insn. 2476@end deffn 2477@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2478This is a 16 bit reloc for the AVR that stores negated 8 bit value 2479(high 8 bit of 16 bit command address) into 8 bit immediate value 2480of SUBI insn. 2481@end deffn 2482@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2483This is a 16 bit reloc for the AVR that stores negated 8 bit value 2484(high 6 bit of 22 bit command address) into 8 bit immediate 2485value of SUBI insn. 2486@end deffn 2487@deffn {} BFD_RELOC_AVR_CALL 2488This is a 32 bit reloc for the AVR that stores 23 bit value 2489into 22 bits. 2490@end deffn 2491@deffn {} BFD_RELOC_AVR_LDI 2492This is a 16 bit reloc for the AVR that stores all needed bits 2493for absolute addressing with ldi with overflow check to linktime. 2494@end deffn 2495@deffn {} BFD_RELOC_AVR_6 2496This is a 6 bit reloc for the AVR that stores offset for ldd/std 2497instructions. 2498@end deffn 2499@deffn {} BFD_RELOC_AVR_6_ADIW 2500This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2501instructions. 2502@end deffn 2503@deffn {} BFD_RELOC_AVR_8_LO 2504This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2505in .byte lo8(symbol). 2506@end deffn 2507@deffn {} BFD_RELOC_AVR_8_HI 2508This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2509in .byte hi8(symbol). 2510@end deffn 2511@deffn {} BFD_RELOC_AVR_8_HLO 2512This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2513in .byte hlo8(symbol). 2514@end deffn 2515@deffn {} BFD_RELOC_AVR_DIFF8 2516@deffnx {} BFD_RELOC_AVR_DIFF16 2517@deffnx {} BFD_RELOC_AVR_DIFF32 2518AVR relocations to mark the difference of two local symbols. 2519These are only needed to support linker relaxation and can be ignored 2520when not relaxing. The field is set to the value of the difference 2521assuming no relaxation. The relocation encodes the position of the 2522second symbol so the linker can determine whether to adjust the field 2523value. 2524@end deffn 2525@deffn {} BFD_RELOC_AVR_LDS_STS_16 2526This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2527lds and sts instructions supported only tiny core. 2528@end deffn 2529@deffn {} BFD_RELOC_AVR_PORT6 2530This is a 6 bit reloc for the AVR that stores an I/O register 2531number for the IN and OUT instructions. 2532@end deffn 2533@deffn {} BFD_RELOC_AVR_PORT5 2534This is a 5 bit reloc for the AVR that stores an I/O register 2535number for the SBIC, SBIS, SBI and CBI instructions. 2536@end deffn 2537@deffn {} BFD_RELOC_RISCV_HI20 2538@deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2539@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2540@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2541@deffnx {} BFD_RELOC_RISCV_LO12_I 2542@deffnx {} BFD_RELOC_RISCV_LO12_S 2543@deffnx {} BFD_RELOC_RISCV_GPREL12_I 2544@deffnx {} BFD_RELOC_RISCV_GPREL12_S 2545@deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2546@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2547@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2548@deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2549@deffnx {} BFD_RELOC_RISCV_CALL 2550@deffnx {} BFD_RELOC_RISCV_CALL_PLT 2551@deffnx {} BFD_RELOC_RISCV_ADD8 2552@deffnx {} BFD_RELOC_RISCV_ADD16 2553@deffnx {} BFD_RELOC_RISCV_ADD32 2554@deffnx {} BFD_RELOC_RISCV_ADD64 2555@deffnx {} BFD_RELOC_RISCV_SUB8 2556@deffnx {} BFD_RELOC_RISCV_SUB16 2557@deffnx {} BFD_RELOC_RISCV_SUB32 2558@deffnx {} BFD_RELOC_RISCV_SUB64 2559@deffnx {} BFD_RELOC_RISCV_GOT_HI20 2560@deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2561@deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2562@deffnx {} BFD_RELOC_RISCV_JMP 2563@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2564@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2565@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2566@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2567@deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2568@deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2569@deffnx {} BFD_RELOC_RISCV_ALIGN 2570@deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2571@deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2572@deffnx {} BFD_RELOC_RISCV_RELAX 2573@deffnx {} BFD_RELOC_RISCV_CFA 2574@deffnx {} BFD_RELOC_RISCV_SUB6 2575@deffnx {} BFD_RELOC_RISCV_SET6 2576@deffnx {} BFD_RELOC_RISCV_SET8 2577@deffnx {} BFD_RELOC_RISCV_SET16 2578@deffnx {} BFD_RELOC_RISCV_SET32 2579@deffnx {} BFD_RELOC_RISCV_32_PCREL 2580@deffnx {} BFD_RELOC_RISCV_SET_ULEB128 2581@deffnx {} BFD_RELOC_RISCV_SUB_ULEB128 2582RISC-V relocations. 2583@end deffn 2584@deffn {} BFD_RELOC_RL78_NEG8 2585@deffnx {} BFD_RELOC_RL78_NEG16 2586@deffnx {} BFD_RELOC_RL78_NEG24 2587@deffnx {} BFD_RELOC_RL78_NEG32 2588@deffnx {} BFD_RELOC_RL78_16_OP 2589@deffnx {} BFD_RELOC_RL78_24_OP 2590@deffnx {} BFD_RELOC_RL78_32_OP 2591@deffnx {} BFD_RELOC_RL78_8U 2592@deffnx {} BFD_RELOC_RL78_16U 2593@deffnx {} BFD_RELOC_RL78_24U 2594@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2595@deffnx {} BFD_RELOC_RL78_DIFF 2596@deffnx {} BFD_RELOC_RL78_GPRELB 2597@deffnx {} BFD_RELOC_RL78_GPRELW 2598@deffnx {} BFD_RELOC_RL78_GPRELL 2599@deffnx {} BFD_RELOC_RL78_SYM 2600@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2601@deffnx {} BFD_RELOC_RL78_OP_NEG 2602@deffnx {} BFD_RELOC_RL78_OP_AND 2603@deffnx {} BFD_RELOC_RL78_OP_SHRA 2604@deffnx {} BFD_RELOC_RL78_ABS8 2605@deffnx {} BFD_RELOC_RL78_ABS16 2606@deffnx {} BFD_RELOC_RL78_ABS16_REV 2607@deffnx {} BFD_RELOC_RL78_ABS32 2608@deffnx {} BFD_RELOC_RL78_ABS32_REV 2609@deffnx {} BFD_RELOC_RL78_ABS16U 2610@deffnx {} BFD_RELOC_RL78_ABS16UW 2611@deffnx {} BFD_RELOC_RL78_ABS16UL 2612@deffnx {} BFD_RELOC_RL78_RELAX 2613@deffnx {} BFD_RELOC_RL78_HI16 2614@deffnx {} BFD_RELOC_RL78_HI8 2615@deffnx {} BFD_RELOC_RL78_LO16 2616@deffnx {} BFD_RELOC_RL78_CODE 2617@deffnx {} BFD_RELOC_RL78_SADDR 2618Renesas RL78 Relocations. 2619@end deffn 2620@deffn {} BFD_RELOC_RX_NEG8 2621@deffnx {} BFD_RELOC_RX_NEG16 2622@deffnx {} BFD_RELOC_RX_NEG24 2623@deffnx {} BFD_RELOC_RX_NEG32 2624@deffnx {} BFD_RELOC_RX_16_OP 2625@deffnx {} BFD_RELOC_RX_24_OP 2626@deffnx {} BFD_RELOC_RX_32_OP 2627@deffnx {} BFD_RELOC_RX_8U 2628@deffnx {} BFD_RELOC_RX_16U 2629@deffnx {} BFD_RELOC_RX_24U 2630@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2631@deffnx {} BFD_RELOC_RX_DIFF 2632@deffnx {} BFD_RELOC_RX_GPRELB 2633@deffnx {} BFD_RELOC_RX_GPRELW 2634@deffnx {} BFD_RELOC_RX_GPRELL 2635@deffnx {} BFD_RELOC_RX_SYM 2636@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2637@deffnx {} BFD_RELOC_RX_OP_NEG 2638@deffnx {} BFD_RELOC_RX_ABS8 2639@deffnx {} BFD_RELOC_RX_ABS16 2640@deffnx {} BFD_RELOC_RX_ABS16_REV 2641@deffnx {} BFD_RELOC_RX_ABS32 2642@deffnx {} BFD_RELOC_RX_ABS32_REV 2643@deffnx {} BFD_RELOC_RX_ABS16U 2644@deffnx {} BFD_RELOC_RX_ABS16UW 2645@deffnx {} BFD_RELOC_RX_ABS16UL 2646@deffnx {} BFD_RELOC_RX_RELAX 2647Renesas RX Relocations. 2648@end deffn 2649@deffn {} BFD_RELOC_390_12 2650Direct 12 bit. 2651@end deffn 2652@deffn {} BFD_RELOC_390_GOT12 265312 bit GOT offset. 2654@end deffn 2655@deffn {} BFD_RELOC_390_PLT32 265632 bit PC relative PLT address. 2657@end deffn 2658@deffn {} BFD_RELOC_390_COPY 2659Copy symbol at runtime. 2660@end deffn 2661@deffn {} BFD_RELOC_390_GLOB_DAT 2662Create GOT entry. 2663@end deffn 2664@deffn {} BFD_RELOC_390_JMP_SLOT 2665Create PLT entry. 2666@end deffn 2667@deffn {} BFD_RELOC_390_RELATIVE 2668Adjust by program base. 2669@end deffn 2670@deffn {} BFD_RELOC_390_GOTPC 267132 bit PC relative offset to GOT. 2672@end deffn 2673@deffn {} BFD_RELOC_390_GOT16 267416 bit GOT offset. 2675@end deffn 2676@deffn {} BFD_RELOC_390_PC12DBL 2677PC relative 12 bit shifted by 1. 2678@end deffn 2679@deffn {} BFD_RELOC_390_PLT12DBL 268012 bit PC rel. PLT shifted by 1. 2681@end deffn 2682@deffn {} BFD_RELOC_390_PC16DBL 2683PC relative 16 bit shifted by 1. 2684@end deffn 2685@deffn {} BFD_RELOC_390_PLT16DBL 268616 bit PC rel. PLT shifted by 1. 2687@end deffn 2688@deffn {} BFD_RELOC_390_PC24DBL 2689PC relative 24 bit shifted by 1. 2690@end deffn 2691@deffn {} BFD_RELOC_390_PLT24DBL 269224 bit PC rel. PLT shifted by 1. 2693@end deffn 2694@deffn {} BFD_RELOC_390_PC32DBL 2695PC relative 32 bit shifted by 1. 2696@end deffn 2697@deffn {} BFD_RELOC_390_PLT32DBL 269832 bit PC rel. PLT shifted by 1. 2699@end deffn 2700@deffn {} BFD_RELOC_390_GOTPCDBL 270132 bit PC rel. GOT shifted by 1. 2702@end deffn 2703@deffn {} BFD_RELOC_390_GOT64 270464 bit GOT offset. 2705@end deffn 2706@deffn {} BFD_RELOC_390_PLT64 270764 bit PC relative PLT address. 2708@end deffn 2709@deffn {} BFD_RELOC_390_GOTENT 271032 bit rel. offset to GOT entry. 2711@end deffn 2712@deffn {} BFD_RELOC_390_GOTOFF64 271364 bit offset to GOT. 2714@end deffn 2715@deffn {} BFD_RELOC_390_GOTPLT12 271612-bit offset to symbol-entry within GOT, with PLT handling. 2717@end deffn 2718@deffn {} BFD_RELOC_390_GOTPLT16 271916-bit offset to symbol-entry within GOT, with PLT handling. 2720@end deffn 2721@deffn {} BFD_RELOC_390_GOTPLT32 272232-bit offset to symbol-entry within GOT, with PLT handling. 2723@end deffn 2724@deffn {} BFD_RELOC_390_GOTPLT64 272564-bit offset to symbol-entry within GOT, with PLT handling. 2726@end deffn 2727@deffn {} BFD_RELOC_390_GOTPLTENT 272832-bit rel. offset to symbol-entry within GOT, with PLT handling. 2729@end deffn 2730@deffn {} BFD_RELOC_390_PLTOFF16 273116-bit rel. offset from the GOT to a PLT entry. 2732@end deffn 2733@deffn {} BFD_RELOC_390_PLTOFF32 273432-bit rel. offset from the GOT to a PLT entry. 2735@end deffn 2736@deffn {} BFD_RELOC_390_PLTOFF64 273764-bit rel. offset from the GOT to a PLT entry. 2738@end deffn 2739@deffn {} BFD_RELOC_390_TLS_LOAD 2740@deffnx {} BFD_RELOC_390_TLS_GDCALL 2741@deffnx {} BFD_RELOC_390_TLS_LDCALL 2742@deffnx {} BFD_RELOC_390_TLS_GD32 2743@deffnx {} BFD_RELOC_390_TLS_GD64 2744@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2745@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2746@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2747@deffnx {} BFD_RELOC_390_TLS_LDM32 2748@deffnx {} BFD_RELOC_390_TLS_LDM64 2749@deffnx {} BFD_RELOC_390_TLS_IE32 2750@deffnx {} BFD_RELOC_390_TLS_IE64 2751@deffnx {} BFD_RELOC_390_TLS_IEENT 2752@deffnx {} BFD_RELOC_390_TLS_LE32 2753@deffnx {} BFD_RELOC_390_TLS_LE64 2754@deffnx {} BFD_RELOC_390_TLS_LDO32 2755@deffnx {} BFD_RELOC_390_TLS_LDO64 2756@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2757@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2758@deffnx {} BFD_RELOC_390_TLS_TPOFF 2759s390 tls relocations. 2760@end deffn 2761@deffn {} BFD_RELOC_390_20 2762@deffnx {} BFD_RELOC_390_GOT20 2763@deffnx {} BFD_RELOC_390_GOTPLT20 2764@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2765Long displacement extension. 2766@end deffn 2767@deffn {} BFD_RELOC_390_IRELATIVE 2768STT_GNU_IFUNC relocation. 2769@end deffn 2770@deffn {} BFD_RELOC_SCORE_GPREL15 2771Score relocations. 2772Low 16 bit for load/store. 2773@end deffn 2774@deffn {} BFD_RELOC_SCORE_DUMMY2 2775@deffnx {} BFD_RELOC_SCORE_JMP 2776This is a 24-bit reloc with the right 1 bit assumed to be 0. 2777@end deffn 2778@deffn {} BFD_RELOC_SCORE_BRANCH 2779This is a 19-bit reloc with the right 1 bit assumed to be 0. 2780@end deffn 2781@deffn {} BFD_RELOC_SCORE_IMM30 2782This is a 32-bit reloc for 48-bit instructions. 2783@end deffn 2784@deffn {} BFD_RELOC_SCORE_IMM32 2785This is a 32-bit reloc for 48-bit instructions. 2786@end deffn 2787@deffn {} BFD_RELOC_SCORE16_JMP 2788This is a 11-bit reloc with the right 1 bit assumed to be 0. 2789@end deffn 2790@deffn {} BFD_RELOC_SCORE16_BRANCH 2791This is a 8-bit reloc with the right 1 bit assumed to be 0. 2792@end deffn 2793@deffn {} BFD_RELOC_SCORE_BCMP 2794This is a 9-bit reloc with the right 1 bit assumed to be 0. 2795@end deffn 2796@deffn {} BFD_RELOC_SCORE_GOT15 2797@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2798@deffnx {} BFD_RELOC_SCORE_CALL15 2799@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2800Undocumented Score relocs. 2801@end deffn 2802@deffn {} BFD_RELOC_IP2K_FR9 2803Scenix IP2K - 9-bit register number / data address. 2804@end deffn 2805@deffn {} BFD_RELOC_IP2K_BANK 2806Scenix IP2K - 4-bit register/data bank number. 2807@end deffn 2808@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2809Scenix IP2K - low 13 bits of instruction word address. 2810@end deffn 2811@deffn {} BFD_RELOC_IP2K_PAGE3 2812Scenix IP2K - high 3 bits of instruction word address. 2813@end deffn 2814@deffn {} BFD_RELOC_IP2K_LO8DATA 2815@deffnx {} BFD_RELOC_IP2K_HI8DATA 2816@deffnx {} BFD_RELOC_IP2K_EX8DATA 2817Scenix IP2K - ext/low/high 8 bits of data address. 2818@end deffn 2819@deffn {} BFD_RELOC_IP2K_LO8INSN 2820@deffnx {} BFD_RELOC_IP2K_HI8INSN 2821Scenix IP2K - low/high 8 bits of instruction word address. 2822@end deffn 2823@deffn {} BFD_RELOC_IP2K_PC_SKIP 2824Scenix IP2K - even/odd PC modifier to modify snb pcl.0. 2825@end deffn 2826@deffn {} BFD_RELOC_IP2K_TEXT 2827Scenix IP2K - 16 bit word address in text section. 2828@end deffn 2829@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2830Scenix IP2K - 7-bit sp or dp offset. 2831@end deffn 2832@deffn {} BFD_RELOC_VPE4KMATH_DATA 2833@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2834Scenix VPE4K coprocessor - data/insn-space addressing. 2835@end deffn 2836@deffn {} BFD_RELOC_VTABLE_INHERIT 2837@deffnx {} BFD_RELOC_VTABLE_ENTRY 2838These two relocations are used by the linker to determine which of 2839the entries in a C++ virtual function table are actually used. When 2840the --gc-sections option is given, the linker will zero out the 2841entries that are not used, so that the code for those functions need 2842not be included in the output. 2843 2844VTABLE_INHERIT is a zero-space relocation used to describe to the 2845linker the inheritance tree of a C++ virtual function table. The 2846relocation's symbol should be the parent class' vtable, and the 2847relocation should be located at the child vtable. 2848 2849VTABLE_ENTRY is a zero-space relocation that describes the use of a 2850virtual function table entry. The reloc's symbol should refer to 2851the table of the class mentioned in the code. Off of that base, an 2852offset describes the entry that is being used. For Rela hosts, this 2853offset is stored in the reloc's addend. For Rel hosts, we are 2854forced to put this offset in the reloc's section offset. 2855@end deffn 2856@deffn {} BFD_RELOC_IA64_IMM14 2857@deffnx {} BFD_RELOC_IA64_IMM22 2858@deffnx {} BFD_RELOC_IA64_IMM64 2859@deffnx {} BFD_RELOC_IA64_DIR32MSB 2860@deffnx {} BFD_RELOC_IA64_DIR32LSB 2861@deffnx {} BFD_RELOC_IA64_DIR64MSB 2862@deffnx {} BFD_RELOC_IA64_DIR64LSB 2863@deffnx {} BFD_RELOC_IA64_GPREL22 2864@deffnx {} BFD_RELOC_IA64_GPREL64I 2865@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2866@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2867@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2868@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2869@deffnx {} BFD_RELOC_IA64_LTOFF22 2870@deffnx {} BFD_RELOC_IA64_LTOFF64I 2871@deffnx {} BFD_RELOC_IA64_PLTOFF22 2872@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2873@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2874@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2875@deffnx {} BFD_RELOC_IA64_FPTR64I 2876@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2877@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2878@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2879@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2880@deffnx {} BFD_RELOC_IA64_PCREL21B 2881@deffnx {} BFD_RELOC_IA64_PCREL21BI 2882@deffnx {} BFD_RELOC_IA64_PCREL21M 2883@deffnx {} BFD_RELOC_IA64_PCREL21F 2884@deffnx {} BFD_RELOC_IA64_PCREL22 2885@deffnx {} BFD_RELOC_IA64_PCREL60B 2886@deffnx {} BFD_RELOC_IA64_PCREL64I 2887@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2888@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2889@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2890@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2891@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2892@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2893@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2894@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2895@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2896@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2897@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2898@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2899@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2900@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2901@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2902@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2903@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2904@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2905@deffnx {} BFD_RELOC_IA64_REL32MSB 2906@deffnx {} BFD_RELOC_IA64_REL32LSB 2907@deffnx {} BFD_RELOC_IA64_REL64MSB 2908@deffnx {} BFD_RELOC_IA64_REL64LSB 2909@deffnx {} BFD_RELOC_IA64_LTV32MSB 2910@deffnx {} BFD_RELOC_IA64_LTV32LSB 2911@deffnx {} BFD_RELOC_IA64_LTV64MSB 2912@deffnx {} BFD_RELOC_IA64_LTV64LSB 2913@deffnx {} BFD_RELOC_IA64_IPLTMSB 2914@deffnx {} BFD_RELOC_IA64_IPLTLSB 2915@deffnx {} BFD_RELOC_IA64_COPY 2916@deffnx {} BFD_RELOC_IA64_LTOFF22X 2917@deffnx {} BFD_RELOC_IA64_LDXMOV 2918@deffnx {} BFD_RELOC_IA64_TPREL14 2919@deffnx {} BFD_RELOC_IA64_TPREL22 2920@deffnx {} BFD_RELOC_IA64_TPREL64I 2921@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2922@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2923@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2924@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2925@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2926@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2927@deffnx {} BFD_RELOC_IA64_DTPREL14 2928@deffnx {} BFD_RELOC_IA64_DTPREL22 2929@deffnx {} BFD_RELOC_IA64_DTPREL64I 2930@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2931@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2932@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2933@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2934@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2935Intel IA64 Relocations. 2936@end deffn 2937@deffn {} BFD_RELOC_M68HC11_HI8 2938Motorola 68HC11 reloc. 2939This is the 8 bit high part of an absolute address. 2940@end deffn 2941@deffn {} BFD_RELOC_M68HC11_LO8 2942Motorola 68HC11 reloc. 2943This is the 8 bit low part of an absolute address. 2944@end deffn 2945@deffn {} BFD_RELOC_M68HC11_3B 2946Motorola 68HC11 reloc. 2947This is the 3 bit of a value. 2948@end deffn 2949@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2950Motorola 68HC11 reloc. 2951This reloc marks the beginning of a jump/call instruction. 2952It is used for linker relaxation to correctly identify beginning 2953of instruction and change some branches to use PC-relative 2954addressing mode. 2955@end deffn 2956@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2957Motorola 68HC11 reloc. 2958This reloc marks a group of several instructions that gcc generates 2959and for which the linker relaxation pass can modify and/or remove 2960some of them. 2961@end deffn 2962@deffn {} BFD_RELOC_M68HC11_LO16 2963Motorola 68HC11 reloc. 2964This is the 16-bit lower part of an address. It is used for 'call' 2965instruction to specify the symbol address without any special 2966transformation (due to memory bank window). 2967@end deffn 2968@deffn {} BFD_RELOC_M68HC11_PAGE 2969Motorola 68HC11 reloc. 2970This is a 8-bit reloc that specifies the page number of an address. 2971It is used by 'call' instruction to specify the page number of 2972the symbol. 2973@end deffn 2974@deffn {} BFD_RELOC_M68HC11_24 2975Motorola 68HC11 reloc. 2976This is a 24-bit reloc that represents the address with a 16-bit 2977value and a 8-bit page number. The symbol address is transformed 2978to follow the 16K memory bank of 68HC12 (seen as mapped in the 2979window). 2980@end deffn 2981@deffn {} BFD_RELOC_M68HC12_5B 2982Motorola 68HC12 reloc. 2983This is the 5 bits of a value. 2984@end deffn 2985@deffn {} BFD_RELOC_XGATE_RL_JUMP 2986Freescale XGATE reloc. 2987This reloc marks the beginning of a bra/jal instruction. 2988@end deffn 2989@deffn {} BFD_RELOC_XGATE_RL_GROUP 2990Freescale XGATE reloc. 2991This reloc marks a group of several instructions that gcc generates 2992and for which the linker relaxation pass can modify and/or remove 2993some of them. 2994@end deffn 2995@deffn {} BFD_RELOC_XGATE_LO16 2996Freescale XGATE reloc. 2997This is the 16-bit lower part of an address. It is used for the 2998'16-bit' instructions. 2999@end deffn 3000@deffn {} BFD_RELOC_XGATE_GPAGE 3001Freescale XGATE reloc. 3002@end deffn 3003@deffn {} BFD_RELOC_XGATE_24 3004Freescale XGATE reloc. 3005@end deffn 3006@deffn {} BFD_RELOC_XGATE_PCREL_9 3007Freescale XGATE reloc. 3008This is a 9-bit pc-relative reloc. 3009@end deffn 3010@deffn {} BFD_RELOC_XGATE_PCREL_10 3011Freescale XGATE reloc. 3012This is a 10-bit pc-relative reloc. 3013@end deffn 3014@deffn {} BFD_RELOC_XGATE_IMM8_LO 3015Freescale XGATE reloc. 3016This is the 16-bit lower part of an address. It is used for the 3017'16-bit' instructions. 3018@end deffn 3019@deffn {} BFD_RELOC_XGATE_IMM8_HI 3020Freescale XGATE reloc. 3021This is the 16-bit higher part of an address. It is used for the 3022'16-bit' instructions. 3023@end deffn 3024@deffn {} BFD_RELOC_XGATE_IMM3 3025Freescale XGATE reloc. 3026This is a 3-bit pc-relative reloc. 3027@end deffn 3028@deffn {} BFD_RELOC_XGATE_IMM4 3029Freescale XGATE reloc. 3030This is a 4-bit pc-relative reloc. 3031@end deffn 3032@deffn {} BFD_RELOC_XGATE_IMM5 3033Freescale XGATE reloc. 3034This is a 5-bit pc-relative reloc. 3035@end deffn 3036@deffn {} BFD_RELOC_M68HC12_9B 3037Motorola 68HC12 reloc. 3038This is the 9 bits of a value. 3039@end deffn 3040@deffn {} BFD_RELOC_M68HC12_16B 3041Motorola 68HC12 reloc. 3042This is the 16 bits of a value. 3043@end deffn 3044@deffn {} BFD_RELOC_M68HC12_9_PCREL 3045Motorola 68HC12/XGATE reloc. 3046This is a PCREL9 branch. 3047@end deffn 3048@deffn {} BFD_RELOC_M68HC12_10_PCREL 3049Motorola 68HC12/XGATE reloc. 3050This is a PCREL10 branch. 3051@end deffn 3052@deffn {} BFD_RELOC_M68HC12_LO8XG 3053Motorola 68HC12/XGATE reloc. 3054This is the 8 bit low part of an absolute address and immediately 3055precedes a matching HI8XG part. 3056@end deffn 3057@deffn {} BFD_RELOC_M68HC12_HI8XG 3058Motorola 68HC12/XGATE reloc. 3059This is the 8 bit high part of an absolute address and immediately 3060follows a matching LO8XG part. 3061@end deffn 3062@deffn {} BFD_RELOC_S12Z_15_PCREL 3063Freescale S12Z reloc. 3064This is a 15 bit relative address. If the most significant bits are 3065all zero then it may be truncated to 8 bits. 3066@end deffn 3067@deffn {} BFD_RELOC_CR16_NUM8 3068@deffnx {} BFD_RELOC_CR16_NUM16 3069@deffnx {} BFD_RELOC_CR16_NUM32 3070@deffnx {} BFD_RELOC_CR16_NUM32a 3071@deffnx {} BFD_RELOC_CR16_REGREL0 3072@deffnx {} BFD_RELOC_CR16_REGREL4 3073@deffnx {} BFD_RELOC_CR16_REGREL4a 3074@deffnx {} BFD_RELOC_CR16_REGREL14 3075@deffnx {} BFD_RELOC_CR16_REGREL14a 3076@deffnx {} BFD_RELOC_CR16_REGREL16 3077@deffnx {} BFD_RELOC_CR16_REGREL20 3078@deffnx {} BFD_RELOC_CR16_REGREL20a 3079@deffnx {} BFD_RELOC_CR16_ABS20 3080@deffnx {} BFD_RELOC_CR16_ABS24 3081@deffnx {} BFD_RELOC_CR16_IMM4 3082@deffnx {} BFD_RELOC_CR16_IMM8 3083@deffnx {} BFD_RELOC_CR16_IMM16 3084@deffnx {} BFD_RELOC_CR16_IMM20 3085@deffnx {} BFD_RELOC_CR16_IMM24 3086@deffnx {} BFD_RELOC_CR16_IMM32 3087@deffnx {} BFD_RELOC_CR16_IMM32a 3088@deffnx {} BFD_RELOC_CR16_DISP4 3089@deffnx {} BFD_RELOC_CR16_DISP8 3090@deffnx {} BFD_RELOC_CR16_DISP16 3091@deffnx {} BFD_RELOC_CR16_DISP20 3092@deffnx {} BFD_RELOC_CR16_DISP24 3093@deffnx {} BFD_RELOC_CR16_DISP24a 3094@deffnx {} BFD_RELOC_CR16_SWITCH8 3095@deffnx {} BFD_RELOC_CR16_SWITCH16 3096@deffnx {} BFD_RELOC_CR16_SWITCH32 3097@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3098@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3099@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3100NS CR16 Relocations. 3101@end deffn 3102@deffn {} BFD_RELOC_CRX_REL4 3103@deffnx {} BFD_RELOC_CRX_REL8 3104@deffnx {} BFD_RELOC_CRX_REL8_CMP 3105@deffnx {} BFD_RELOC_CRX_REL16 3106@deffnx {} BFD_RELOC_CRX_REL24 3107@deffnx {} BFD_RELOC_CRX_REL32 3108@deffnx {} BFD_RELOC_CRX_REGREL12 3109@deffnx {} BFD_RELOC_CRX_REGREL22 3110@deffnx {} BFD_RELOC_CRX_REGREL28 3111@deffnx {} BFD_RELOC_CRX_REGREL32 3112@deffnx {} BFD_RELOC_CRX_ABS16 3113@deffnx {} BFD_RELOC_CRX_ABS32 3114@deffnx {} BFD_RELOC_CRX_NUM8 3115@deffnx {} BFD_RELOC_CRX_NUM16 3116@deffnx {} BFD_RELOC_CRX_NUM32 3117@deffnx {} BFD_RELOC_CRX_IMM16 3118@deffnx {} BFD_RELOC_CRX_IMM32 3119@deffnx {} BFD_RELOC_CRX_SWITCH8 3120@deffnx {} BFD_RELOC_CRX_SWITCH16 3121@deffnx {} BFD_RELOC_CRX_SWITCH32 3122NS CRX Relocations. 3123@end deffn 3124@deffn {} BFD_RELOC_CRIS_BDISP8 3125@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3126@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3127@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3128@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3129@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3130@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3131@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3132@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3133@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3134These relocs are only used within the CRIS assembler. They are not 3135(at present) written to any object files. 3136@end deffn 3137@deffn {} BFD_RELOC_CRIS_COPY 3138@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3139@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3140@deffnx {} BFD_RELOC_CRIS_RELATIVE 3141Relocs used in ELF shared libraries for CRIS. 3142@end deffn 3143@deffn {} BFD_RELOC_CRIS_32_GOT 314432-bit offset to symbol-entry within GOT. 3145@end deffn 3146@deffn {} BFD_RELOC_CRIS_16_GOT 314716-bit offset to symbol-entry within GOT. 3148@end deffn 3149@deffn {} BFD_RELOC_CRIS_32_GOTPLT 315032-bit offset to symbol-entry within GOT, with PLT handling. 3151@end deffn 3152@deffn {} BFD_RELOC_CRIS_16_GOTPLT 315316-bit offset to symbol-entry within GOT, with PLT handling. 3154@end deffn 3155@deffn {} BFD_RELOC_CRIS_32_GOTREL 315632-bit offset to symbol, relative to GOT. 3157@end deffn 3158@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 315932-bit offset to symbol with PLT entry, relative to GOT. 3160@end deffn 3161@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 316232-bit offset to symbol with PLT entry, relative to this 3163relocation. 3164@end deffn 3165@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3166@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3167@deffnx {} BFD_RELOC_CRIS_32_GD 3168@deffnx {} BFD_RELOC_CRIS_DTP 3169@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3170@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3171@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3172@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3173@deffnx {} BFD_RELOC_CRIS_32_TPREL 3174@deffnx {} BFD_RELOC_CRIS_16_TPREL 3175@deffnx {} BFD_RELOC_CRIS_DTPMOD 3176@deffnx {} BFD_RELOC_CRIS_32_IE 3177Relocs used in TLS code for CRIS. 3178@end deffn 3179@deffn {} BFD_RELOC_OR1K_REL_26 3180@deffnx {} BFD_RELOC_OR1K_SLO16 3181@deffnx {} BFD_RELOC_OR1K_PCREL_PG21 3182@deffnx {} BFD_RELOC_OR1K_LO13 3183@deffnx {} BFD_RELOC_OR1K_SLO13 3184@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3185@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3186@deffnx {} BFD_RELOC_OR1K_GOT_AHI16 3187@deffnx {} BFD_RELOC_OR1K_GOT16 3188@deffnx {} BFD_RELOC_OR1K_GOT_PG21 3189@deffnx {} BFD_RELOC_OR1K_GOT_LO13 3190@deffnx {} BFD_RELOC_OR1K_PLT26 3191@deffnx {} BFD_RELOC_OR1K_PLTA26 3192@deffnx {} BFD_RELOC_OR1K_GOTOFF_SLO16 3193@deffnx {} BFD_RELOC_OR1K_COPY 3194@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3195@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3196@deffnx {} BFD_RELOC_OR1K_RELATIVE 3197@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3198@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3199@deffnx {} BFD_RELOC_OR1K_TLS_GD_PG21 3200@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO13 3201@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3202@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3203@deffnx {} BFD_RELOC_OR1K_TLS_LDM_PG21 3204@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO13 3205@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3206@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3207@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3208@deffnx {} BFD_RELOC_OR1K_TLS_IE_AHI16 3209@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3210@deffnx {} BFD_RELOC_OR1K_TLS_IE_PG21 3211@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO13 3212@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3213@deffnx {} BFD_RELOC_OR1K_TLS_LE_AHI16 3214@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3215@deffnx {} BFD_RELOC_OR1K_TLS_LE_SLO16 3216@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3217@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3218@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3219OpenRISC 1000 Relocations. 3220@end deffn 3221@deffn {} BFD_RELOC_H8_DIR16A8 3222@deffnx {} BFD_RELOC_H8_DIR16R8 3223@deffnx {} BFD_RELOC_H8_DIR24A8 3224@deffnx {} BFD_RELOC_H8_DIR24R8 3225@deffnx {} BFD_RELOC_H8_DIR32A16 3226@deffnx {} BFD_RELOC_H8_DISP32A16 3227H8 elf Relocations. 3228@end deffn 3229@deffn {} BFD_RELOC_XSTORMY16_REL_12 3230@deffnx {} BFD_RELOC_XSTORMY16_12 3231@deffnx {} BFD_RELOC_XSTORMY16_24 3232@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3233Sony Xstormy16 Relocations. 3234@end deffn 3235@deffn {} BFD_RELOC_RELC 3236Self-describing complex relocations. 3237@end deffn 3238@deffn {} BFD_RELOC_VAX_GLOB_DAT 3239@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3240@deffnx {} BFD_RELOC_VAX_RELATIVE 3241Relocations used by VAX ELF. 3242@end deffn 3243@deffn {} BFD_RELOC_MT_PC16 3244Morpho MT - 16 bit immediate relocation. 3245@end deffn 3246@deffn {} BFD_RELOC_MT_HI16 3247Morpho MT - Hi 16 bits of an address. 3248@end deffn 3249@deffn {} BFD_RELOC_MT_LO16 3250Morpho MT - Low 16 bits of an address. 3251@end deffn 3252@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3253Morpho MT - Used to tell the linker which vtable entries are used. 3254@end deffn 3255@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3256Morpho MT - Used to tell the linker which vtable entries are used. 3257@end deffn 3258@deffn {} BFD_RELOC_MT_PCINSN8 3259Morpho MT - 8 bit immediate relocation. 3260@end deffn 3261@deffn {} BFD_RELOC_MSP430_10_PCREL 3262@deffnx {} BFD_RELOC_MSP430_16_PCREL 3263@deffnx {} BFD_RELOC_MSP430_16 3264@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3265@deffnx {} BFD_RELOC_MSP430_16_BYTE 3266@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3267@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3268@deffnx {} BFD_RELOC_MSP430_ABS8 3269@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3270@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3271@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3272@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3273@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3274@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3275@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3276@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3277@deffnx {} BFD_RELOC_MSP430X_PCR16 3278@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3279@deffnx {} BFD_RELOC_MSP430X_ABS16 3280@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3281@deffnx {} BFD_RELOC_MSP430_PREL31 3282@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3283@deffnx {} BFD_RELOC_MSP430_SET_ULEB128 3284@deffnx {} BFD_RELOC_MSP430_SUB_ULEB128 3285msp430 specific relocation codes. 3286@end deffn 3287@deffn {} BFD_RELOC_NIOS2_S16 3288@deffnx {} BFD_RELOC_NIOS2_U16 3289@deffnx {} BFD_RELOC_NIOS2_CALL26 3290@deffnx {} BFD_RELOC_NIOS2_IMM5 3291@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3292@deffnx {} BFD_RELOC_NIOS2_IMM6 3293@deffnx {} BFD_RELOC_NIOS2_IMM8 3294@deffnx {} BFD_RELOC_NIOS2_HI16 3295@deffnx {} BFD_RELOC_NIOS2_LO16 3296@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3297@deffnx {} BFD_RELOC_NIOS2_GPREL 3298@deffnx {} BFD_RELOC_NIOS2_UJMP 3299@deffnx {} BFD_RELOC_NIOS2_CJMP 3300@deffnx {} BFD_RELOC_NIOS2_CALLR 3301@deffnx {} BFD_RELOC_NIOS2_ALIGN 3302@deffnx {} BFD_RELOC_NIOS2_GOT16 3303@deffnx {} BFD_RELOC_NIOS2_CALL16 3304@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3305@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3306@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3307@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3308@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3309@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3310@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3311@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3312@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3313@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3314@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3315@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3316@deffnx {} BFD_RELOC_NIOS2_COPY 3317@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3318@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3319@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3320@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3321@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3322@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3323@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3324@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3325@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3326@deffnx {} BFD_RELOC_NIOS2_R2_S12 3327@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3328@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3329@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3330@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3331@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3332@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3333@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3334@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3335@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3336@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3337@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3338@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3339Relocations used by the Altera Nios II core. 3340@end deffn 3341@deffn {} BFD_RELOC_PRU_U16 3342PRU LDI 16-bit unsigned data-memory relocation. 3343@end deffn 3344@deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3345PRU LDI 16-bit unsigned instruction-memory relocation. 3346@end deffn 3347@deffn {} BFD_RELOC_PRU_LDI32 3348PRU relocation for two consecutive LDI load instructions that load a 334932 bit value into a register. If the higher bits are all zero, then 3350the second instruction may be relaxed. 3351@end deffn 3352@deffn {} BFD_RELOC_PRU_S10_PCREL 3353PRU QBBx 10-bit signed PC-relative relocation. 3354@end deffn 3355@deffn {} BFD_RELOC_PRU_U8_PCREL 3356PRU 8-bit unsigned relocation used for the LOOP instruction. 3357@end deffn 3358@deffn {} BFD_RELOC_PRU_32_PMEM 3359@deffnx {} BFD_RELOC_PRU_16_PMEM 3360PRU Program Memory relocations. Used to convert from byte 3361addressing to 32-bit word addressing. 3362@end deffn 3363@deffn {} BFD_RELOC_PRU_GNU_DIFF8 3364@deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3365@deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3366@deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3367@deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3368PRU relocations to mark the difference of two local symbols. 3369These are only needed to support linker relaxation and can be 3370ignored when not relaxing. The field is set to the value of the 3371difference assuming no relaxation. The relocation encodes the 3372position of the second symbol so the linker can determine whether to 3373adjust the field value. The PMEM variants encode the word 3374difference, instead of byte difference between symbols. 3375@end deffn 3376@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3377@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3378@deffnx {} BFD_RELOC_IQ2000_UHI16 3379IQ2000 Relocations. 3380@end deffn 3381@deffn {} BFD_RELOC_XTENSA_RTLD 3382Special Xtensa relocation used only by PLT entries in ELF shared 3383objects to indicate that the runtime linker should set the value 3384to one of its own internal functions or data structures. 3385@end deffn 3386@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3387@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3388@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3389Xtensa relocations for ELF shared objects. 3390@end deffn 3391@deffn {} BFD_RELOC_XTENSA_PLT 3392Xtensa relocation used in ELF object files for symbols that may 3393require PLT entries. Otherwise, this is just a generic 32-bit 3394relocation. 3395@end deffn 3396@deffn {} BFD_RELOC_XTENSA_DIFF8 3397@deffnx {} BFD_RELOC_XTENSA_DIFF16 3398@deffnx {} BFD_RELOC_XTENSA_DIFF32 3399Xtensa relocations for backward compatibility. These have been 3400replaced by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF. 3401Xtensa relocations to mark the difference of two local symbols. 3402These are only needed to support linker relaxation and can be 3403ignored when not relaxing. The field is set to the value of the 3404difference assuming no relaxation. The relocation encodes the 3405position of the first symbol so the linker can determine whether to 3406adjust the field value. 3407@end deffn 3408@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3409@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3410@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3411@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3412@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3413@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3414@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3415@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3416@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3417@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3418@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3419@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3420@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3421@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3422@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3423Generic Xtensa relocations for instruction operands. Only the slot 3424number is encoded in the relocation. The relocation applies to the 3425last PC-relative immediate operand, or if there are no PC-relative 3426immediates, to the last immediate operand. 3427@end deffn 3428@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3429@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3430@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3431@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3432@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3433@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3434@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3435@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3436@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3437@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3438@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3439@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3440@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3441@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3442@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3443Alternate Xtensa relocations. Only the slot is encoded in the 3444relocation. The meaning of these relocations is opcode-specific. 3445@end deffn 3446@deffn {} BFD_RELOC_XTENSA_OP0 3447@deffnx {} BFD_RELOC_XTENSA_OP1 3448@deffnx {} BFD_RELOC_XTENSA_OP2 3449Xtensa relocations for backward compatibility. These have all been 3450replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3451@end deffn 3452@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3453Xtensa relocation to mark that the assembler expanded the 3454instructions from an original target. The expansion size is 3455encoded in the reloc size. 3456@end deffn 3457@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3458Xtensa relocation to mark that the linker should simplify 3459assembler-expanded instructions. This is commonly used 3460internally by the linker after analysis of a 3461BFD_RELOC_XTENSA_ASM_EXPAND. 3462@end deffn 3463@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3464@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3465@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3466@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3467@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3468@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3469@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3470Xtensa TLS relocations. 3471@end deffn 3472@deffn {} BFD_RELOC_XTENSA_PDIFF8 3473@deffnx {} BFD_RELOC_XTENSA_PDIFF16 3474@deffnx {} BFD_RELOC_XTENSA_PDIFF32 3475@deffnx {} BFD_RELOC_XTENSA_NDIFF8 3476@deffnx {} BFD_RELOC_XTENSA_NDIFF16 3477@deffnx {} BFD_RELOC_XTENSA_NDIFF32 3478Xtensa relocations to mark the difference of two local symbols. 3479These are only needed to support linker relaxation and can be 3480ignored when not relaxing. The field is set to the value of the 3481difference assuming no relaxation. The relocation encodes the 3482position of the subtracted symbol so the linker can determine 3483whether to adjust the field value. PDIFF relocations are used for 3484positive differences, NDIFF relocations are used for negative 3485differences. The difference value is treated as unsigned with these 3486relocation types, giving full 8/16 value ranges. 3487@end deffn 3488@deffn {} BFD_RELOC_Z80_DISP8 34898 bit signed offset in (ix+d) or (iy+d). 3490@end deffn 3491@deffn {} BFD_RELOC_Z80_BYTE0 3492First 8 bits of multibyte (32, 24 or 16 bit) value. 3493@end deffn 3494@deffn {} BFD_RELOC_Z80_BYTE1 3495Second 8 bits of multibyte (32, 24 or 16 bit) value. 3496@end deffn 3497@deffn {} BFD_RELOC_Z80_BYTE2 3498Third 8 bits of multibyte (32 or 24 bit) value. 3499@end deffn 3500@deffn {} BFD_RELOC_Z80_BYTE3 3501Fourth 8 bits of multibyte (32 bit) value. 3502@end deffn 3503@deffn {} BFD_RELOC_Z80_WORD0 3504Lowest 16 bits of multibyte (32 or 24 bit) value. 3505@end deffn 3506@deffn {} BFD_RELOC_Z80_WORD1 3507Highest 16 bits of multibyte (32 or 24 bit) value. 3508@end deffn 3509@deffn {} BFD_RELOC_Z80_16_BE 3510Like BFD_RELOC_16 but big-endian. 3511@end deffn 3512@deffn {} BFD_RELOC_Z8K_DISP7 3513DJNZ offset. 3514@end deffn 3515@deffn {} BFD_RELOC_Z8K_CALLR 3516CALR offset. 3517@end deffn 3518@deffn {} BFD_RELOC_Z8K_IMM4L 35194 bit value. 3520@end deffn 3521@deffn {} BFD_RELOC_LM32_CALL 3522@deffnx {} BFD_RELOC_LM32_BRANCH 3523@deffnx {} BFD_RELOC_LM32_16_GOT 3524@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3525@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3526@deffnx {} BFD_RELOC_LM32_COPY 3527@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3528@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3529@deffnx {} BFD_RELOC_LM32_RELATIVE 3530Lattice Mico32 relocations. 3531@end deffn 3532@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3533Difference between two section addreses. Must be followed by a 3534BFD_RELOC_MACH_O_PAIR. 3535@end deffn 3536@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3537Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3538@end deffn 3539@deffn {} BFD_RELOC_MACH_O_PAIR 3540Pair of relocation. Contains the first symbol. 3541@end deffn 3542@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3543Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3544@end deffn 3545@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3546Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3547@end deffn 3548@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3549@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3550PCREL relocations. They are marked as branch to create PLT entry if 3551required. 3552@end deffn 3553@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3554Used when referencing a GOT entry. 3555@end deffn 3556@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3557Used when loading a GOT entry with movq. It is specially marked so 3558that the linker could optimize the movq to a leaq if possible. 3559@end deffn 3560@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3561Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3562@end deffn 3563@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3564Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3565@end deffn 3566@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3567Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3568@end deffn 3569@deffn {} BFD_RELOC_MACH_O_X86_64_TLV 3570Used when referencing a TLV entry. 3571@end deffn 3572@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3573Addend for PAGE or PAGEOFF. 3574@end deffn 3575@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3576Relative offset to page of GOT slot. 3577@end deffn 3578@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3579Relative offset within page of GOT slot. 3580@end deffn 3581@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3582Address of a GOT entry. 3583@end deffn 3584@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3585This is a 32 bit reloc for the microblaze that stores the low 16 3586bits of a value. 3587@end deffn 3588@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3589This is a 32 bit pc-relative reloc for the microblaze that stores 3590the low 16 bits of a value. 3591@end deffn 3592@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3593This is a 32 bit reloc for the microblaze that stores a value 3594relative to the read-only small data area anchor. 3595@end deffn 3596@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3597This is a 32 bit reloc for the microblaze that stores a value 3598relative to the read-write small data area anchor. 3599@end deffn 3600@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3601This is a 32 bit reloc for the microblaze to handle expressions of 3602the form "Symbol Op Symbol". 3603@end deffn 3604@deffn {} BFD_RELOC_MICROBLAZE_32_NONE 3605This is a 32 bit reloc that stores the 32 bit pc relative value in 3606two words (with an imm instruction). No relocation is done here - 3607only used for relaxing. 3608@end deffn 3609@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3610This is a 64 bit reloc that stores the 32 bit pc relative value in 3611two words (with an imm instruction). No relocation is done here - 3612only used for relaxing. 3613@end deffn 3614@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3615This is a 64 bit reloc that stores the 32 bit pc relative value in 3616two words (with an imm instruction). The relocation is PC-relative 3617GOT offset. 3618@end deffn 3619@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3620This is a 64 bit reloc that stores the 32 bit pc relative value in 3621two words (with an imm instruction). The relocation is GOT offset. 3622@end deffn 3623@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3624This is a 64 bit reloc that stores the 32 bit pc relative value in 3625two words (with an imm instruction). The relocation is PC-relative 3626offset into PLT. 3627@end deffn 3628@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3629This is a 64 bit reloc that stores the 32 bit GOT relative value in 3630two words (with an imm instruction). The relocation is relative 3631offset from _GLOBAL_OFFSET_TABLE_. 3632@end deffn 3633@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3634This is a 32 bit reloc that stores the 32 bit GOT relative value in 3635a word. The relocation is relative offset from 3636_GLOBAL_OFFSET_TABLE_. 3637@end deffn 3638@deffn {} BFD_RELOC_MICROBLAZE_COPY 3639This is used to tell the dynamic linker to copy the value out of 3640the dynamic object into the runtime process image. 3641@end deffn 3642@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3643Unused Reloc. 3644@end deffn 3645@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3646This is a 64 bit reloc that stores the 32 bit GOT relative value 3647of the GOT TLS GD info entry in two words (with an imm instruction). 3648The relocation is GOT offset. 3649@end deffn 3650@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3651This is a 64 bit reloc that stores the 32 bit GOT relative value 3652of the GOT TLS LD info entry in two words (with an imm instruction). 3653The relocation is GOT offset. 3654@end deffn 3655@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3656This is a 32 bit reloc that stores the Module ID to GOT(n). 3657@end deffn 3658@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3659This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3660@end deffn 3661@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3662This is a 32 bit reloc for storing TLS offset to two words (uses imm 3663instruction). 3664@end deffn 3665@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3666This is a 64 bit reloc that stores 32-bit thread pointer relative 3667offset to two words (uses imm instruction). 3668@end deffn 3669@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3670This is a 64 bit reloc that stores 32-bit thread pointer relative 3671offset to two words (uses imm instruction). 3672@end deffn 3673@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTPCREL 3674This is a 64 bit reloc that stores the 32 bit pc relative value in 3675two words (with an imm instruction). The relocation is PC-relative 3676offset from start of TEXT. 3677@end deffn 3678@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTREL 3679This is a 64 bit reloc that stores the 32 bit offset value in two 3680words (with an imm instruction). The relocation is relative offset 3681from start of TEXT. 3682@end deffn 3683@deffn {} BFD_RELOC_KVX_RELOC_START 3684KVX pseudo relocation code to mark the start of the KVX relocation 3685enumerators. N.B. the order of the enumerators is important as 3686several tables in the KVX bfd backend are indexed by these 3687enumerators; make sure they are all synced. 3688@end deffn 3689@deffn {} BFD_RELOC_KVX_NONE 3690KVX null relocation code. 3691@end deffn 3692@deffn {} BFD_RELOC_KVX_16 3693@deffnx {} BFD_RELOC_KVX_32 3694@deffnx {} BFD_RELOC_KVX_64 3695@deffnx {} BFD_RELOC_KVX_S16_PCREL 3696@deffnx {} BFD_RELOC_KVX_PCREL17 3697@deffnx {} BFD_RELOC_KVX_PCREL27 3698@deffnx {} BFD_RELOC_KVX_32_PCREL 3699@deffnx {} BFD_RELOC_KVX_S37_PCREL_LO10 3700@deffnx {} BFD_RELOC_KVX_S37_PCREL_UP27 3701@deffnx {} BFD_RELOC_KVX_S43_PCREL_LO10 3702@deffnx {} BFD_RELOC_KVX_S43_PCREL_UP27 3703@deffnx {} BFD_RELOC_KVX_S43_PCREL_EX6 3704@deffnx {} BFD_RELOC_KVX_S64_PCREL_LO10 3705@deffnx {} BFD_RELOC_KVX_S64_PCREL_UP27 3706@deffnx {} BFD_RELOC_KVX_S64_PCREL_EX27 3707@deffnx {} BFD_RELOC_KVX_64_PCREL 3708@deffnx {} BFD_RELOC_KVX_S16 3709@deffnx {} BFD_RELOC_KVX_S32_LO5 3710@deffnx {} BFD_RELOC_KVX_S32_UP27 3711@deffnx {} BFD_RELOC_KVX_S37_LO10 3712@deffnx {} BFD_RELOC_KVX_S37_UP27 3713@deffnx {} BFD_RELOC_KVX_S37_GOTOFF_LO10 3714@deffnx {} BFD_RELOC_KVX_S37_GOTOFF_UP27 3715@deffnx {} BFD_RELOC_KVX_S43_GOTOFF_LO10 3716@deffnx {} BFD_RELOC_KVX_S43_GOTOFF_UP27 3717@deffnx {} BFD_RELOC_KVX_S43_GOTOFF_EX6 3718@deffnx {} BFD_RELOC_KVX_32_GOTOFF 3719@deffnx {} BFD_RELOC_KVX_64_GOTOFF 3720@deffnx {} BFD_RELOC_KVX_32_GOT 3721@deffnx {} BFD_RELOC_KVX_S37_GOT_LO10 3722@deffnx {} BFD_RELOC_KVX_S37_GOT_UP27 3723@deffnx {} BFD_RELOC_KVX_S43_GOT_LO10 3724@deffnx {} BFD_RELOC_KVX_S43_GOT_UP27 3725@deffnx {} BFD_RELOC_KVX_S43_GOT_EX6 3726@deffnx {} BFD_RELOC_KVX_64_GOT 3727@deffnx {} BFD_RELOC_KVX_GLOB_DAT 3728@deffnx {} BFD_RELOC_KVX_COPY 3729@deffnx {} BFD_RELOC_KVX_JMP_SLOT 3730@deffnx {} BFD_RELOC_KVX_RELATIVE 3731@deffnx {} BFD_RELOC_KVX_S43_LO10 3732@deffnx {} BFD_RELOC_KVX_S43_UP27 3733@deffnx {} BFD_RELOC_KVX_S43_EX6 3734@deffnx {} BFD_RELOC_KVX_S64_LO10 3735@deffnx {} BFD_RELOC_KVX_S64_UP27 3736@deffnx {} BFD_RELOC_KVX_S64_EX27 3737@deffnx {} BFD_RELOC_KVX_S37_GOTADDR_LO10 3738@deffnx {} BFD_RELOC_KVX_S37_GOTADDR_UP27 3739@deffnx {} BFD_RELOC_KVX_S43_GOTADDR_LO10 3740@deffnx {} BFD_RELOC_KVX_S43_GOTADDR_UP27 3741@deffnx {} BFD_RELOC_KVX_S43_GOTADDR_EX6 3742@deffnx {} BFD_RELOC_KVX_S64_GOTADDR_LO10 3743@deffnx {} BFD_RELOC_KVX_S64_GOTADDR_UP27 3744@deffnx {} BFD_RELOC_KVX_S64_GOTADDR_EX27 3745@deffnx {} BFD_RELOC_KVX_64_DTPMOD 3746@deffnx {} BFD_RELOC_KVX_64_DTPOFF 3747@deffnx {} BFD_RELOC_KVX_S37_TLS_DTPOFF_LO10 3748@deffnx {} BFD_RELOC_KVX_S37_TLS_DTPOFF_UP27 3749@deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_LO10 3750@deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_UP27 3751@deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_EX6 3752@deffnx {} BFD_RELOC_KVX_S37_TLS_GD_LO10 3753@deffnx {} BFD_RELOC_KVX_S37_TLS_GD_UP27 3754@deffnx {} BFD_RELOC_KVX_S43_TLS_GD_LO10 3755@deffnx {} BFD_RELOC_KVX_S43_TLS_GD_UP27 3756@deffnx {} BFD_RELOC_KVX_S43_TLS_GD_EX6 3757@deffnx {} BFD_RELOC_KVX_S37_TLS_LD_LO10 3758@deffnx {} BFD_RELOC_KVX_S37_TLS_LD_UP27 3759@deffnx {} BFD_RELOC_KVX_S43_TLS_LD_LO10 3760@deffnx {} BFD_RELOC_KVX_S43_TLS_LD_UP27 3761@deffnx {} BFD_RELOC_KVX_S43_TLS_LD_EX6 3762@deffnx {} BFD_RELOC_KVX_64_TPOFF 3763@deffnx {} BFD_RELOC_KVX_S37_TLS_IE_LO10 3764@deffnx {} BFD_RELOC_KVX_S37_TLS_IE_UP27 3765@deffnx {} BFD_RELOC_KVX_S43_TLS_IE_LO10 3766@deffnx {} BFD_RELOC_KVX_S43_TLS_IE_UP27 3767@deffnx {} BFD_RELOC_KVX_S43_TLS_IE_EX6 3768@deffnx {} BFD_RELOC_KVX_S37_TLS_LE_LO10 3769@deffnx {} BFD_RELOC_KVX_S37_TLS_LE_UP27 3770@deffnx {} BFD_RELOC_KVX_S43_TLS_LE_LO10 3771@deffnx {} BFD_RELOC_KVX_S43_TLS_LE_UP27 3772@deffnx {} BFD_RELOC_KVX_S43_TLS_LE_EX6 3773@deffnx {} BFD_RELOC_KVX_8 3774KVX Relocations. 3775@end deffn 3776@deffn {} BFD_RELOC_KVX_RELOC_END 3777KVX pseudo relocation code to mark the end of the KVX relocation 3778enumerators that have direct mapping to ELF reloc codes. There are 3779a few more enumerators after this one; those are mainly used by the 3780KVX assembler for the internal fixup or to select one of the above 3781enumerators. 3782@end deffn 3783@deffn {} BFD_RELOC_AARCH64_RELOC_START 3784AArch64 pseudo relocation code to mark the start of the AArch64 3785relocation enumerators. N.B. the order of the enumerators is 3786important as several tables in the AArch64 bfd backend are indexed 3787by these enumerators; make sure they are all synced. 3788@end deffn 3789@deffn {} BFD_RELOC_AARCH64_NULL 3790Deprecated AArch64 null relocation code. 3791@end deffn 3792@deffn {} BFD_RELOC_AARCH64_NONE 3793AArch64 null relocation code. 3794@end deffn 3795@deffn {} BFD_RELOC_AARCH64_64 3796@deffnx {} BFD_RELOC_AARCH64_32 3797@deffnx {} BFD_RELOC_AARCH64_16 3798Basic absolute relocations of N bits. These are equivalent to 3799BFD_RELOC_N and they were added to assist the indexing of the howto 3800table. 3801@end deffn 3802@deffn {} BFD_RELOC_AARCH64_64_PCREL 3803@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3804@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3805PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3806and they were added to assist the indexing of the howto table. 3807@end deffn 3808@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3809AArch64 MOV[NZK] instruction with most significant bits 0 to 15 of 3810an unsigned address/value. 3811@end deffn 3812@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3813AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3814an address/value. No overflow checking. 3815@end deffn 3816@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3817AArch64 MOV[NZK] instruction with most significant bits 16 to 31 of 3818an unsigned address/value. 3819@end deffn 3820@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3821AArch64 MOV[NZK] instruction with less significant bits 16 to 31 of 3822an address/value. No overflow checking. 3823@end deffn 3824@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3825AArch64 MOV[NZK] instruction with most significant bits 32 to 47 of 3826an unsigned address/value. 3827@end deffn 3828@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3829AArch64 MOV[NZK] instruction with less significant bits 32 to 47 of 3830an address/value. No overflow checking. 3831@end deffn 3832@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3833AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 of a 3834signed or unsigned address/value. 3835@end deffn 3836@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3837AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3838signed value. Changes instruction to MOVZ or MOVN depending on the 3839value's sign. 3840@end deffn 3841@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3842AArch64 MOV[NZ] instruction with most significant bits 16 to 31 of a 3843signed value. Changes instruction to MOVZ or MOVN depending on the 3844value's sign. 3845@end deffn 3846@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3847AArch64 MOV[NZ] instruction with most significant bits 32 to 47 of a 3848signed value. Changes instruction to MOVZ or MOVN depending on the 3849value's sign. 3850@end deffn 3851@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0 3852AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3853signed value. Changes instruction to MOVZ or MOVN depending on the 3854value's sign. 3855@end deffn 3856@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0_NC 3857AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3858signed value. Changes instruction to MOVZ or MOVN depending on the 3859value's sign. 3860@end deffn 3861@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1 3862AArch64 MOVK instruction with most significant bits 16 to 31 of a 3863signed value. 3864@end deffn 3865@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1_NC 3866AArch64 MOVK instruction with most significant bits 16 to 31 of a 3867signed value. 3868@end deffn 3869@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2 3870AArch64 MOVK instruction with most significant bits 32 to 47 of a 3871signed value. 3872@end deffn 3873@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2_NC 3874AArch64 MOVK instruction with most significant bits 32 to 47 of a 3875signed value. 3876@end deffn 3877@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G3 3878AArch64 MOVK instruction with most significant bits 47 to 63 of a 3879signed value. 3880@end deffn 3881@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3882AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3883offset. The lowest two bits must be zero and are not stored in the 3884instruction, giving a 21 bit signed byte offset. 3885@end deffn 3886@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3887AArch64 ADR instruction, holding a simple 21 bit pc-relative byte 3888offset. 3889@end deffn 3890@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3891AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3892offset, giving a 4KB aligned page base address. 3893@end deffn 3894@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3895AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3896offset, giving a 4KB aligned page base address, but with no overflow 3897checking. 3898@end deffn 3899@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3900AArch64 ADD immediate instruction, holding bits 0 to 11 of the 3901address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3902@end deffn 3903@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3904AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3905address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3906@end deffn 3907@deffn {} BFD_RELOC_AARCH64_TSTBR14 3908AArch64 14 bit pc-relative test bit and branch. 3909The lowest two bits must be zero and are not stored in the 3910instruction, giving a 16 bit signed byte offset. 3911@end deffn 3912@deffn {} BFD_RELOC_AARCH64_BRANCH19 3913AArch64 19 bit pc-relative conditional branch and compare & branch. 3914The lowest two bits must be zero and are not stored in the 3915instruction, giving a 21 bit signed byte offset. 3916@end deffn 3917@deffn {} BFD_RELOC_AARCH64_JUMP26 3918AArch64 26 bit pc-relative unconditional branch. 3919The lowest two bits must be zero and are not stored in the 3920instruction, giving a 28 bit signed byte offset. 3921@end deffn 3922@deffn {} BFD_RELOC_AARCH64_CALL26 3923AArch64 26 bit pc-relative unconditional branch and link. 3924The lowest two bits must be zero and are not stored in the 3925instruction, giving a 28 bit signed byte offset. 3926@end deffn 3927@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3928AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3929address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3930@end deffn 3931@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3932AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3933address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3934@end deffn 3935@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3936AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3937address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3938@end deffn 3939@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3940AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3941address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3942@end deffn 3943@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3944AArch64 Load Literal instruction, holding a 19 bit PC relative word 3945offset of the global offset table entry for a symbol. The lowest 3946two bits must be zero and are not stored in the instruction, giving 3947a 21 bit signed byte offset. This relocation type requires signed 3948overflow checking. 3949@end deffn 3950@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3951Get to the page base of the global offset table entry for a symbol 3952as part of an ADRP instruction using a 21 bit PC relative value. 3953Used in conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3954@end deffn 3955@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3956Unsigned 12 bit byte offset for 64 bit load/store from the page of 3957the GOT entry for this symbol. Used in conjunction with 3958BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3959@end deffn 3960@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3961Unsigned 12 bit byte offset for 32 bit load/store from the page of 3962the GOT entry for this symbol. Used in conjunction with 3963BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3964@end deffn 3965@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3966Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3967for this symbol. Valid in LP64 ABI only. 3968@end deffn 3969@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3970Unsigned 16 bit byte higher offset for 64 bit load/store from the 3971GOT entry for this symbol. Valid in LP64 ABI only. 3972@end deffn 3973@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3974Unsigned 15 bit byte offset for 64 bit load/store from the page of 3975the GOT entry for this symbol. Valid in LP64 ABI only. 3976@end deffn 3977@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3978Scaled 14 bit byte offset to the page base of the global offset 3979table. 3980@end deffn 3981@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3982Scaled 15 bit byte offset to the page base of the global offset 3983table. 3984@end deffn 3985@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3986Get to the page base of the global offset table entry for a symbols 3987tls_index structure as part of an adrp instruction using a 21 bit PC 3988relative value. Used in conjunction with 3989BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3990@end deffn 3991@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3992AArch64 TLS General Dynamic. 3993@end deffn 3994@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3995Unsigned 12 bit byte offset to global offset table entry for a 3996symbol's tls_index structure. Used in conjunction with 3997BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3998@end deffn 3999@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 4000AArch64 TLS General Dynamic relocation. 4001@end deffn 4002@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 4003AArch64 TLS General Dynamic relocation. 4004@end deffn 4005@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 4006AArch64 TLS INITIAL EXEC relocation. 4007@end deffn 4008@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 4009AArch64 TLS INITIAL EXEC relocation. 4010@end deffn 4011@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 4012AArch64 TLS INITIAL EXEC relocation. 4013@end deffn 4014@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 4015AArch64 TLS INITIAL EXEC relocation. 4016@end deffn 4017@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 4018AArch64 TLS INITIAL EXEC relocation. 4019@end deffn 4020@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 4021AArch64 TLS INITIAL EXEC relocation. 4022@end deffn 4023@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 4024bit[23:12] of byte offset to module TLS base address. 4025@end deffn 4026@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 4027Unsigned 12 bit byte offset to module TLS base address. 4028@end deffn 4029@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 4030No overflow check version of 4031BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 4032@end deffn 4033@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 4034Unsigned 12 bit byte offset to global offset table entry for a 4035symbol's tls_index structure. Used in conjunction with 4036BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 4037@end deffn 4038@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 4039GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 4040instruction. 4041@end deffn 4042@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 4043GOT entry address for AArch64 TLS Local Dynamic, used with ADR 4044instruction. 4045@end deffn 4046@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 4047bit[11:1] of byte offset to module TLS base address, encoded in ldst 4048instructions. 4049@end deffn 4050@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 4051Similar to BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no 4052overflow check. 4053@end deffn 4054@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 4055bit[11:2] of byte offset to module TLS base address, encoded in ldst 4056instructions. 4057@end deffn 4058@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 4059Similar to BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no 4060overflow check. 4061@end deffn 4062@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 4063bit[11:3] of byte offset to module TLS base address, encoded in ldst 4064instructions. 4065@end deffn 4066@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 4067Similar to BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no 4068overflow check. 4069@end deffn 4070@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 4071bit[11:0] of byte offset to module TLS base address, encoded in ldst 4072instructions. 4073@end deffn 4074@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 4075Similar to BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no 4076overflow check. 4077@end deffn 4078@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4079bit[15:0] of byte offset to module TLS base address. 4080@end deffn 4081@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 4082No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. 4083@end deffn 4084@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4085bit[31:16] of byte offset to module TLS base address. 4086@end deffn 4087@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 4088No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. 4089@end deffn 4090@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 4091bit[47:32] of byte offset to module TLS base address. 4092@end deffn 4093@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 4094AArch64 TLS LOCAL EXEC relocation. 4095@end deffn 4096@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 4097AArch64 TLS LOCAL EXEC relocation. 4098@end deffn 4099@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 4100AArch64 TLS LOCAL EXEC relocation. 4101@end deffn 4102@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4103AArch64 TLS LOCAL EXEC relocation. 4104@end deffn 4105@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4106AArch64 TLS LOCAL EXEC relocation. 4107@end deffn 4108@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4109AArch64 TLS LOCAL EXEC relocation. 4110@end deffn 4111@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4112AArch64 TLS LOCAL EXEC relocation. 4113@end deffn 4114@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4115AArch64 TLS LOCAL EXEC relocation. 4116@end deffn 4117@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 4118bit[11:1] of byte offset to module TLS base address, encoded in ldst 4119instructions. 4120@end deffn 4121@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 4122Similar to BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no 4123overflow check. 4124@end deffn 4125@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 4126bit[11:2] of byte offset to module TLS base address, encoded in ldst 4127instructions. 4128@end deffn 4129@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 4130Similar to BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no 4131overflow check. 4132@end deffn 4133@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 4134bit[11:3] of byte offset to module TLS base address, encoded in ldst 4135instructions. 4136@end deffn 4137@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 4138Similar to BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no 4139overflow check. 4140@end deffn 4141@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 4142bit[11:0] of byte offset to module TLS base address, encoded in ldst 4143instructions. 4144@end deffn 4145@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 4146Similar to BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow 4147check. 4148@end deffn 4149@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4150@deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4151@deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4152@deffnx {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4153@deffnx {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4154@deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4155@deffnx {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4156@deffnx {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4157@deffnx {} BFD_RELOC_AARCH64_TLSDESC_LDR 4158@deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADD 4159@deffnx {} BFD_RELOC_AARCH64_TLSDESC_CALL 4160AArch64 TLS DESC relocations. 4161@end deffn 4162@deffn {} BFD_RELOC_AARCH64_COPY 4163@deffnx {} BFD_RELOC_AARCH64_GLOB_DAT 4164@deffnx {} BFD_RELOC_AARCH64_JUMP_SLOT 4165@deffnx {} BFD_RELOC_AARCH64_RELATIVE 4166AArch64 DSO relocations. 4167@end deffn 4168@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4169@deffnx {} BFD_RELOC_AARCH64_TLS_DTPREL 4170@deffnx {} BFD_RELOC_AARCH64_TLS_TPREL 4171@deffnx {} BFD_RELOC_AARCH64_TLSDESC 4172AArch64 TLS relocations. 4173@end deffn 4174@deffn {} BFD_RELOC_AARCH64_IRELATIVE 4175AArch64 support for STT_GNU_IFUNC. 4176@end deffn 4177@deffn {} BFD_RELOC_AARCH64_RELOC_END 4178AArch64 pseudo relocation code to mark the end of the AArch64 4179relocation enumerators that have direct mapping to ELF reloc codes. 4180There are a few more enumerators after this one; those are mainly 4181used by the AArch64 assembler for the internal fixup or to select 4182one of the above enumerators. 4183@end deffn 4184@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4185AArch64 pseudo relocation code to be used internally by the AArch64 4186assembler and not (currently) written to any object files. 4187@end deffn 4188@deffn {} BFD_RELOC_AARCH64_LDST_LO12 4189AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4190address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4191@end deffn 4192@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4193AArch64 pseudo relocation code for TLS local dynamic mode. It's to 4194be used internally by the AArch64 assembler and not (currently) 4195written to any object files. 4196@end deffn 4197@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4198Similar to BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow 4199check. 4200@end deffn 4201@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 4202AArch64 pseudo relocation code for TLS local exec mode. It's to be 4203used internally by the AArch64 assembler and not (currently) written 4204to any object files. 4205@end deffn 4206@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC 4207Similar to BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow 4208check. 4209@end deffn 4210@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4211AArch64 pseudo relocation code to be used internally by the AArch64 4212assembler and not (currently) written to any object files. 4213@end deffn 4214@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4215AArch64 pseudo relocation code to be used internally by the AArch64 4216assembler and not (currently) written to any object files. 4217@end deffn 4218@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4219AArch64 pseudo relocation code to be used internally by the AArch64 4220assembler and not (currently) written to any object files. 4221@end deffn 4222@deffn {} BFD_RELOC_TILEPRO_COPY 4223@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4224@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4225@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4226@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4227@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4228@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4229@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4230@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4231@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4232@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4233@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4234@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4235@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4236@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4237@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4238@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4239@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4240@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4241@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4242@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4243@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4244@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4245@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4246@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4247@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4248@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4249@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4250@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4251@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4252@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4253@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4254@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4255@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4256@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4257@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4258@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4259@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4260@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4261@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4262@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4263@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4264@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4265@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4266@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4267@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4268@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4269@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4270@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4271@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4272@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4273@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4274@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4275@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4276@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4277@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4278@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4279@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4280@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4281@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4282@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4283@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4284@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4285@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4286@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4287@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4288@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4289@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4290@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4291@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4292@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4293@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4294@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4295@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4296@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4297@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4298@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4299@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4300@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4301Tilera TILEPro Relocations. 4302@end deffn 4303@deffn {} BFD_RELOC_TILEGX_HW0 4304@deffnx {} BFD_RELOC_TILEGX_HW1 4305@deffnx {} BFD_RELOC_TILEGX_HW2 4306@deffnx {} BFD_RELOC_TILEGX_HW3 4307@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4308@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4309@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4310@deffnx {} BFD_RELOC_TILEGX_COPY 4311@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4312@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4313@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4314@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4315@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4316@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4317@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4318@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4319@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4320@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4321@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4322@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4323@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4324@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4325@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4326@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4327@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4328@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4329@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4330@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4331@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4332@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4333@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4334@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4335@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4336@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4337@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4338@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4339@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4340@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4341@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4342@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4343@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4344@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4345@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4346@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4347@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4348@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4349@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4350@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4351@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4352@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4353@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4354@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4355@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4356@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4357@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4358@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4359@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4360@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4361@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4362@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4363@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4364@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4365@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4366@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4367@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4368@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4369@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4370@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4371@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4372@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4373@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4374@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4375@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4376@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4377@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4378@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4379@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4380@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4381@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4382@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4383@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4384@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4385@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4386@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4387@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4388@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4389@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4390@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4391@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4392@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4393@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4394@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4395@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4396@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4397@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4398@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4399@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4400@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4401@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4402@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4403@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4404@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4405@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4406@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4407@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4408@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4409@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4410@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4411@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4412Tilera TILE-Gx Relocations. 4413@end deffn 4414@deffn {} BFD_RELOC_BPF_64 4415@deffnx {} BFD_RELOC_BPF_DISP32 4416@deffnx {} BFD_RELOC_BPF_DISPCALL32 4417@deffnx {} BFD_RELOC_BPF_DISP16 4418Linux eBPF relocations. 4419@end deffn 4420@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4421Adapteva EPIPHANY - 8 bit signed pc-relative displacement. 4422@end deffn 4423@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4424Adapteva EPIPHANY - 24 bit signed pc-relative displacement. 4425@end deffn 4426@deffn {} BFD_RELOC_EPIPHANY_HIGH 4427Adapteva EPIPHANY - 16 most-significant bits of absolute address. 4428@end deffn 4429@deffn {} BFD_RELOC_EPIPHANY_LOW 4430Adapteva EPIPHANY - 16 least-significant bits of absolute address. 4431@end deffn 4432@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4433Adapteva EPIPHANY - 11 bit signed number - add/sub immediate. 4434@end deffn 4435@deffn {} BFD_RELOC_EPIPHANY_IMM11 4436Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st 4437displacement). 4438@end deffn 4439@deffn {} BFD_RELOC_EPIPHANY_IMM8 4440Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4441@end deffn 4442@deffn {} BFD_RELOC_VISIUM_HI16 4443@deffnx {} BFD_RELOC_VISIUM_LO16 4444@deffnx {} BFD_RELOC_VISIUM_IM16 4445@deffnx {} BFD_RELOC_VISIUM_REL16 4446@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4447@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4448@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4449Visium Relocations. 4450@end deffn 4451@deffn {} BFD_RELOC_WASM32_LEB128 4452@deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4453@deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4454@deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4455@deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4456@deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4457@deffnx {} BFD_RELOC_WASM32_COPY 4458@deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4459@deffnx {} BFD_RELOC_WASM32_INDEX 4460@deffnx {} BFD_RELOC_WASM32_PLT_SIG 4461WebAssembly relocations. 4462@end deffn 4463@deffn {} BFD_RELOC_CKCORE_NONE 4464@deffnx {} BFD_RELOC_CKCORE_ADDR32 4465@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM8BY4 4466@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM11BY2 4467@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM4BY2 4468@deffnx {} BFD_RELOC_CKCORE_PCREL32 4469@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2 4470@deffnx {} BFD_RELOC_CKCORE_GNU_VTINHERIT 4471@deffnx {} BFD_RELOC_CKCORE_GNU_VTENTRY 4472@deffnx {} BFD_RELOC_CKCORE_RELATIVE 4473@deffnx {} BFD_RELOC_CKCORE_COPY 4474@deffnx {} BFD_RELOC_CKCORE_GLOB_DAT 4475@deffnx {} BFD_RELOC_CKCORE_JUMP_SLOT 4476@deffnx {} BFD_RELOC_CKCORE_GOTOFF 4477@deffnx {} BFD_RELOC_CKCORE_GOTPC 4478@deffnx {} BFD_RELOC_CKCORE_GOT32 4479@deffnx {} BFD_RELOC_CKCORE_PLT32 4480@deffnx {} BFD_RELOC_CKCORE_ADDRGOT 4481@deffnx {} BFD_RELOC_CKCORE_ADDRPLT 4482@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM26BY2 4483@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY2 4484@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY4 4485@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY2 4486@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY4 4487@deffnx {} BFD_RELOC_CKCORE_ADDR_HI16 4488@deffnx {} BFD_RELOC_CKCORE_ADDR_LO16 4489@deffnx {} BFD_RELOC_CKCORE_GOTPC_HI16 4490@deffnx {} BFD_RELOC_CKCORE_GOTPC_LO16 4491@deffnx {} BFD_RELOC_CKCORE_GOTOFF_HI16 4492@deffnx {} BFD_RELOC_CKCORE_GOTOFF_LO16 4493@deffnx {} BFD_RELOC_CKCORE_GOT12 4494@deffnx {} BFD_RELOC_CKCORE_GOT_HI16 4495@deffnx {} BFD_RELOC_CKCORE_GOT_LO16 4496@deffnx {} BFD_RELOC_CKCORE_PLT12 4497@deffnx {} BFD_RELOC_CKCORE_PLT_HI16 4498@deffnx {} BFD_RELOC_CKCORE_PLT_LO16 4499@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_HI16 4500@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_LO16 4501@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_HI16 4502@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_LO16 4503@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2 4504@deffnx {} BFD_RELOC_CKCORE_TOFFSET_LO16 4505@deffnx {} BFD_RELOC_CKCORE_DOFFSET_LO16 4506@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM18BY2 4507@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18 4508@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 4509@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 4510@deffnx {} BFD_RELOC_CKCORE_GOTOFF_IMM18 4511@deffnx {} BFD_RELOC_CKCORE_GOT_IMM18BY4 4512@deffnx {} BFD_RELOC_CKCORE_PLT_IMM18BY4 4513@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM7BY4 4514@deffnx {} BFD_RELOC_CKCORE_TLS_LE32 4515@deffnx {} BFD_RELOC_CKCORE_TLS_IE32 4516@deffnx {} BFD_RELOC_CKCORE_TLS_GD32 4517@deffnx {} BFD_RELOC_CKCORE_TLS_LDM32 4518@deffnx {} BFD_RELOC_CKCORE_TLS_LDO32 4519@deffnx {} BFD_RELOC_CKCORE_TLS_DTPMOD32 4520@deffnx {} BFD_RELOC_CKCORE_TLS_DTPOFF32 4521@deffnx {} BFD_RELOC_CKCORE_TLS_TPOFF32 4522@deffnx {} BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 4523@deffnx {} BFD_RELOC_CKCORE_NOJSRI 4524@deffnx {} BFD_RELOC_CKCORE_CALLGRAPH 4525@deffnx {} BFD_RELOC_CKCORE_IRELATIVE 4526@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4 4527@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4 4528C-SKY relocations. 4529@end deffn 4530@deffn {} BFD_RELOC_S12Z_OPR 4531S12Z relocations. 4532@end deffn 4533@deffn {} BFD_RELOC_LARCH_TLS_DTPMOD32 4534@deffnx {} BFD_RELOC_LARCH_TLS_DTPREL32 4535@deffnx {} BFD_RELOC_LARCH_TLS_DTPMOD64 4536@deffnx {} BFD_RELOC_LARCH_TLS_DTPREL64 4537@deffnx {} BFD_RELOC_LARCH_TLS_TPREL32 4538@deffnx {} BFD_RELOC_LARCH_TLS_TPREL64 4539@deffnx {} BFD_RELOC_LARCH_TLS_DESC32 4540@deffnx {} BFD_RELOC_LARCH_TLS_DESC64 4541@deffnx {} BFD_RELOC_LARCH_MARK_LA 4542@deffnx {} BFD_RELOC_LARCH_MARK_PCREL 4543@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PCREL 4544@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE 4545@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_DUP 4546@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_GPREL 4547@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL 4548@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT 4549@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GD 4550@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL 4551@deffnx {} BFD_RELOC_LARCH_SOP_ASSERT 4552@deffnx {} BFD_RELOC_LARCH_SOP_NOT 4553@deffnx {} BFD_RELOC_LARCH_SOP_SUB 4554@deffnx {} BFD_RELOC_LARCH_SOP_SL 4555@deffnx {} BFD_RELOC_LARCH_SOP_SR 4556@deffnx {} BFD_RELOC_LARCH_SOP_ADD 4557@deffnx {} BFD_RELOC_LARCH_SOP_AND 4558@deffnx {} BFD_RELOC_LARCH_SOP_IF_ELSE 4559@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_5 4560@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U_10_12 4561@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_12 4562@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16 4563@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2 4564@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_5_20 4565@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2 4566@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2 4567@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U 4568@deffnx {} BFD_RELOC_LARCH_ADD8 4569@deffnx {} BFD_RELOC_LARCH_ADD16 4570@deffnx {} BFD_RELOC_LARCH_ADD24 4571@deffnx {} BFD_RELOC_LARCH_ADD32 4572@deffnx {} BFD_RELOC_LARCH_ADD64 4573@deffnx {} BFD_RELOC_LARCH_SUB8 4574@deffnx {} BFD_RELOC_LARCH_SUB16 4575@deffnx {} BFD_RELOC_LARCH_SUB24 4576@deffnx {} BFD_RELOC_LARCH_SUB32 4577@deffnx {} BFD_RELOC_LARCH_SUB64 4578@deffnx {} BFD_RELOC_LARCH_B16 4579@deffnx {} BFD_RELOC_LARCH_B21 4580@deffnx {} BFD_RELOC_LARCH_B26 4581@deffnx {} BFD_RELOC_LARCH_ABS_HI20 4582@deffnx {} BFD_RELOC_LARCH_ABS_LO12 4583@deffnx {} BFD_RELOC_LARCH_ABS64_LO20 4584@deffnx {} BFD_RELOC_LARCH_ABS64_HI12 4585@deffnx {} BFD_RELOC_LARCH_PCALA_HI20 4586@deffnx {} BFD_RELOC_LARCH_PCALA_LO12 4587@deffnx {} BFD_RELOC_LARCH_PCALA64_LO20 4588@deffnx {} BFD_RELOC_LARCH_PCALA64_HI12 4589@deffnx {} BFD_RELOC_LARCH_GOT_PC_HI20 4590@deffnx {} BFD_RELOC_LARCH_GOT_PC_LO12 4591@deffnx {} BFD_RELOC_LARCH_GOT64_PC_LO20 4592@deffnx {} BFD_RELOC_LARCH_GOT64_PC_HI12 4593@deffnx {} BFD_RELOC_LARCH_GOT_HI20 4594@deffnx {} BFD_RELOC_LARCH_GOT_LO12 4595@deffnx {} BFD_RELOC_LARCH_GOT64_LO20 4596@deffnx {} BFD_RELOC_LARCH_GOT64_HI12 4597@deffnx {} BFD_RELOC_LARCH_TLS_LE_HI20 4598@deffnx {} BFD_RELOC_LARCH_TLS_LE_LO12 4599@deffnx {} BFD_RELOC_LARCH_TLS_LE64_LO20 4600@deffnx {} BFD_RELOC_LARCH_TLS_LE64_HI12 4601@deffnx {} BFD_RELOC_LARCH_TLS_IE_PC_HI20 4602@deffnx {} BFD_RELOC_LARCH_TLS_IE_PC_LO12 4603@deffnx {} BFD_RELOC_LARCH_TLS_IE64_PC_LO20 4604@deffnx {} BFD_RELOC_LARCH_TLS_IE64_PC_HI12 4605@deffnx {} BFD_RELOC_LARCH_TLS_IE_HI20 4606@deffnx {} BFD_RELOC_LARCH_TLS_IE_LO12 4607@deffnx {} BFD_RELOC_LARCH_TLS_IE64_LO20 4608@deffnx {} BFD_RELOC_LARCH_TLS_IE64_HI12 4609@deffnx {} BFD_RELOC_LARCH_TLS_LD_PC_HI20 4610@deffnx {} BFD_RELOC_LARCH_TLS_LD_HI20 4611@deffnx {} BFD_RELOC_LARCH_TLS_GD_PC_HI20 4612@deffnx {} BFD_RELOC_LARCH_TLS_GD_HI20 4613@deffnx {} BFD_RELOC_LARCH_32_PCREL 4614@deffnx {} BFD_RELOC_LARCH_RELAX 4615@deffnx {} BFD_RELOC_LARCH_DELETE 4616@deffnx {} BFD_RELOC_LARCH_ALIGN 4617@deffnx {} BFD_RELOC_LARCH_PCREL20_S2 4618@deffnx {} BFD_RELOC_LARCH_CFA 4619@deffnx {} BFD_RELOC_LARCH_ADD6 4620@deffnx {} BFD_RELOC_LARCH_SUB6 4621@deffnx {} BFD_RELOC_LARCH_ADD_ULEB128 4622@deffnx {} BFD_RELOC_LARCH_SUB_ULEB128 4623@deffnx {} BFD_RELOC_LARCH_64_PCREL 4624@deffnx {} BFD_RELOC_LARCH_CALL36 4625@deffnx {} BFD_RELOC_LARCH_TLS_DESC_PC_HI20 4626@deffnx {} BFD_RELOC_LARCH_TLS_DESC_PC_LO12 4627@deffnx {} BFD_RELOC_LARCH_TLS_DESC64_PC_LO20 4628@deffnx {} BFD_RELOC_LARCH_TLS_DESC64_PC_HI12 4629@deffnx {} BFD_RELOC_LARCH_TLS_DESC_HI20 4630@deffnx {} BFD_RELOC_LARCH_TLS_DESC_LO12 4631@deffnx {} BFD_RELOC_LARCH_TLS_DESC64_LO20 4632@deffnx {} BFD_RELOC_LARCH_TLS_DESC64_HI12 4633@deffnx {} BFD_RELOC_LARCH_TLS_DESC_LD 4634@deffnx {} BFD_RELOC_LARCH_TLS_DESC_CALL 4635@deffnx {} BFD_RELOC_LARCH_TLS_LE_HI20_R 4636@deffnx {} BFD_RELOC_LARCH_TLS_LE_ADD_R 4637@deffnx {} BFD_RELOC_LARCH_TLS_LE_LO12_R 4638@deffnx {} BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 4639@deffnx {} BFD_RELOC_LARCH_TLS_GD_PCREL20_S2 4640@deffnx {} BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2 4641LARCH relocations. 4642@end deffn 4643 4644@example 4645typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4646 4647@end example 4648@findex bfd_reloc_type_lookup 4649@subsubsection @code{bfd_reloc_type_lookup} 4650@deftypefn {Function} reloc_howto_type *bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); reloc_howto_type *bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name); 4651Return a pointer to a howto structure which, when 4652invoked, will perform the relocation @var{code} on data from the 4653architecture noted. 4654 4655@end deftypefn 4656@findex bfd_default_reloc_type_lookup 4657@subsubsection @code{bfd_default_reloc_type_lookup} 4658@deftypefn {Function} reloc_howto_type *bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); 4659Provides a default relocation lookup routine for any architecture. 4660 4661@end deftypefn 4662@findex bfd_get_reloc_code_name 4663@subsubsection @code{bfd_get_reloc_code_name} 4664@deftypefn {Function} const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4665Provides a printable name for the supplied relocation code. 4666Useful mainly for printing error messages. 4667 4668@end deftypefn 4669@findex bfd_generic_relax_section 4670@subsubsection @code{bfd_generic_relax_section} 4671@deftypefn {Function} bool bfd_generic_relax_section (bfd *abfd, asection *section, struct bfd_link_info *, bool *); 4672Provides default handling for relaxing for back ends which 4673don't do relaxing. 4674 4675@end deftypefn 4676@findex bfd_generic_gc_sections 4677@subsubsection @code{bfd_generic_gc_sections} 4678@deftypefn {Function} bool bfd_generic_gc_sections (bfd *, struct bfd_link_info *); 4679Provides default handling for relaxing for back ends which 4680don't do section gc -- i.e., does nothing. 4681 4682@end deftypefn 4683@findex bfd_generic_lookup_section_flags 4684@subsubsection @code{bfd_generic_lookup_section_flags} 4685@deftypefn {Function} bool bfd_generic_lookup_section_flags (struct bfd_link_info *, struct flag_info *, asection *); 4686Provides default handling for section flags lookup 4687-- i.e., does nothing. 4688Returns FALSE if the section should be omitted, otherwise TRUE. 4689 4690@end deftypefn 4691@findex bfd_generic_merge_sections 4692@subsubsection @code{bfd_generic_merge_sections} 4693@deftypefn {Function} bool bfd_generic_merge_sections (bfd *, struct bfd_link_info *); 4694Provides default handling for SEC_MERGE section merging for back ends 4695which don't have SEC_MERGE support -- i.e., does nothing. 4696 4697@end deftypefn 4698@findex bfd_generic_get_relocated_section_contents 4699@subsubsection @code{bfd_generic_get_relocated_section_contents} 4700@deftypefn {Function} bfd_byte *bfd_generic_get_relocated_section_contents (bfd *abfd, struct bfd_link_info *link_info, struct bfd_link_order *link_order, bfd_byte *data, bool relocatable, asymbol **symbols); 4701Provides default handling of relocation effort for back ends 4702which can't be bothered to do it efficiently. 4703 4704@end deftypefn 4705@findex _bfd_generic_set_reloc 4706@subsubsection @code{_bfd_generic_set_reloc} 4707@deftypefn {Function} void _bfd_generic_set_reloc (bfd *abfd, sec_ptr section, arelent **relptr, unsigned int count); 4708Installs a new set of internal relocations in SECTION. 4709 4710@end deftypefn 4711@findex _bfd_unrecognized_reloc 4712@subsubsection @code{_bfd_unrecognized_reloc} 4713@deftypefn {Function} bool _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type); 4714Reports an unrecognized reloc. 4715Written as a function in order to reduce code duplication. 4716Returns FALSE so that it can be called from a return statement. 4717 4718@end deftypefn 4719