reloc.texi revision 1.6
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. Note - the value 2 is used so that it 31 will not be mistaken for the boolean TRUE or FALSE values. */ 32 bfd_reloc_ok = 2, 33 34 /* The relocation was performed, but there was an overflow. */ 35 bfd_reloc_overflow, 36 37 /* The address to relocate was not within the section supplied. */ 38 bfd_reloc_outofrange, 39 40 /* Used by special functions. */ 41 bfd_reloc_continue, 42 43 /* Unsupported relocation size requested. */ 44 bfd_reloc_notsupported, 45 46 /* Unused. */ 47 bfd_reloc_other, 48 49 /* The symbol to relocate against was undefined. */ 50 bfd_reloc_undefined, 51 52 /* The relocation was performed, but may not be ok - presently 53 generated only when linking i960 coff files with i960 b.out 54 symbols. If this type is returned, the error_message argument 55 to bfd_perform_relocation will be set. */ 56 bfd_reloc_dangerous 57 @} 58 bfd_reloc_status_type; 59 60 61typedef struct reloc_cache_entry 62@{ 63 /* A pointer into the canonical table of pointers. */ 64 struct bfd_symbol **sym_ptr_ptr; 65 66 /* offset in section. */ 67 bfd_size_type address; 68 69 /* addend for relocation value. */ 70 bfd_vma addend; 71 72 /* Pointer to how to perform the required relocation. */ 73 reloc_howto_type *howto; 74 75@} 76arelent; 77 78@end example 79@strong{Description}@* 80Here is a description of each of the fields within an @code{arelent}: 81 82@itemize @bullet 83 84@item 85@code{sym_ptr_ptr} 86@end itemize 87The symbol table pointer points to a pointer to the symbol 88associated with the relocation request. It is the pointer 89into the table returned by the back end's 90@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 91referenced through a pointer to a pointer so that tools like 92the linker can fix up all the symbols of the same name by 93modifying only one pointer. The relocation routine looks in 94the symbol and uses the base of the section the symbol is 95attached to and the value of the symbol as the initial 96relocation offset. If the symbol pointer is zero, then the 97section provided is looked up. 98 99@itemize @bullet 100 101@item 102@code{address} 103@end itemize 104The @code{address} field gives the offset in bytes from the base of 105the section data which owns the relocation record to the first 106byte of relocatable information. The actual data relocated 107will be relative to this point; for example, a relocation 108type which modifies the bottom two bytes of a four byte word 109would not touch the first byte pointed to in a big endian 110world. 111 112@itemize @bullet 113 114@item 115@code{addend} 116@end itemize 117The @code{addend} is a value provided by the back end to be added (!) 118to the relocation offset. Its interpretation is dependent upon 119the howto. For example, on the 68k the code: 120 121@example 122 char foo[]; 123 main() 124 @{ 125 return foo[0x12345678]; 126 @} 127@end example 128 129Could be compiled into: 130 131@example 132 linkw fp,#-4 133 moveb @@#12345678,d0 134 extbl d0 135 unlk fp 136 rts 137@end example 138 139This could create a reloc pointing to @code{foo}, but leave the 140offset in the data, something like: 141 142@example 143RELOCATION RECORDS FOR [.text]: 144offset type value 14500000006 32 _foo 146 14700000000 4e56 fffc ; linkw fp,#-4 14800000004 1039 1234 5678 ; moveb @@#12345678,d0 1490000000a 49c0 ; extbl d0 1500000000c 4e5e ; unlk fp 1510000000e 4e75 ; rts 152@end example 153 154Using coff and an 88k, some instructions don't have enough 155space in them to represent the full address range, and 156pointers have to be loaded in two parts. So you'd get something like: 157 158@example 159 or.u r13,r0,hi16(_foo+0x12345678) 160 ld.b r2,r13,lo16(_foo+0x12345678) 161 jmp r1 162@end example 163 164This should create two relocs, both pointing to @code{_foo}, and with 1650x12340000 in their addend field. The data would consist of: 166 167@example 168RELOCATION RECORDS FOR [.text]: 169offset type value 17000000002 HVRT16 _foo+0x12340000 17100000006 LVRT16 _foo+0x12340000 172 17300000000 5da05678 ; or.u r13,r0,0x5678 17400000004 1c4d5678 ; ld.b r2,r13,0x5678 17500000008 f400c001 ; jmp r1 176@end example 177 178The relocation routine digs out the value from the data, adds 179it to the addend to get the original offset, and then adds the 180value of @code{_foo}. Note that all 32 bits have to be kept around 181somewhere, to cope with carry from bit 15 to bit 16. 182 183One further example is the sparc and the a.out format. The 184sparc has a similar problem to the 88k, in that some 185instructions don't have room for an entire offset, but on the 186sparc the parts are created in odd sized lumps. The designers of 187the a.out format chose to not use the data within the section 188for storing part of the offset; all the offset is kept within 189the reloc. Anything in the data should be ignored. 190 191@example 192 save %sp,-112,%sp 193 sethi %hi(_foo+0x12345678),%g2 194 ldsb [%g2+%lo(_foo+0x12345678)],%i0 195 ret 196 restore 197@end example 198 199Both relocs contain a pointer to @code{foo}, and the offsets 200contain junk. 201 202@example 203RELOCATION RECORDS FOR [.text]: 204offset type value 20500000004 HI22 _foo+0x12345678 20600000008 LO10 _foo+0x12345678 207 20800000000 9de3bf90 ; save %sp,-112,%sp 20900000004 05000000 ; sethi %hi(_foo+0),%g2 21000000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2110000000c 81c7e008 ; ret 21200000010 81e80000 ; restore 213@end example 214 215@itemize @bullet 216 217@item 218@code{howto} 219@end itemize 220The @code{howto} field can be imagined as a 221relocation instruction. It is a pointer to a structure which 222contains information on what to do with all of the other 223information in the reloc record and data section. A back end 224would normally have a relocation instruction set and turn 225relocations into pointers to the correct structure on input - 226but it would be possible to create each howto field on demand. 227 228@subsubsection @code{enum complain_overflow} 229Indicates what sort of overflow checking should be done when 230performing a relocation. 231 232 233@example 234 235enum complain_overflow 236@{ 237 /* Do not complain on overflow. */ 238 complain_overflow_dont, 239 240 /* Complain if the value overflows when considered as a signed 241 number one bit larger than the field. ie. A bitfield of N bits 242 is allowed to represent -2**n to 2**n-1. */ 243 complain_overflow_bitfield, 244 245 /* Complain if the value overflows when considered as a signed 246 number. */ 247 complain_overflow_signed, 248 249 /* Complain if the value overflows when considered as an 250 unsigned number. */ 251 complain_overflow_unsigned 252@}; 253@end example 254@subsubsection @code{reloc_howto_type} 255The @code{reloc_howto_type} is a structure which contains all the 256information that libbfd needs to know to tie up a back end's data. 257 258 259@example 260struct bfd_symbol; /* Forward declaration. */ 261 262struct reloc_howto_struct 263@{ 264 /* The type field has mainly a documentary use - the back end can 265 do what it wants with it, though normally the back end's 266 external idea of what a reloc number is stored 267 in this field. For example, a PC relative word relocation 268 in a coff environment has the type 023 - because that's 269 what the outside world calls a R_PCRWORD reloc. */ 270 unsigned int type; 271 272 /* The value the final relocation is shifted right by. This drops 273 unwanted data from the relocation. */ 274 unsigned int rightshift; 275 276 /* The size of the item to be relocated. This is *not* a 277 power-of-two measure. To get the number of bytes operated 278 on by a type of relocation, use bfd_get_reloc_size. */ 279 int size; 280 281 /* The number of bits in the item to be relocated. This is used 282 when doing overflow checking. */ 283 unsigned int bitsize; 284 285 /* The relocation is relative to the field being relocated. */ 286 bfd_boolean pc_relative; 287 288 /* The bit position of the reloc value in the destination. 289 The relocated value is left shifted by this amount. */ 290 unsigned int bitpos; 291 292 /* What type of overflow error should be checked for when 293 relocating. */ 294 enum complain_overflow complain_on_overflow; 295 296 /* If this field is non null, then the supplied function is 297 called rather than the normal function. This allows really 298 strange relocation methods to be accommodated (e.g., i960 callj 299 instructions). */ 300 bfd_reloc_status_type (*special_function) 301 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 302 bfd *, char **); 303 304 /* The textual name of the relocation type. */ 305 char *name; 306 307 /* Some formats record a relocation addend in the section contents 308 rather than with the relocation. For ELF formats this is the 309 distinction between USE_REL and USE_RELA (though the code checks 310 for USE_REL == 1/0). The value of this field is TRUE if the 311 addend is recorded with the section contents; when performing a 312 partial link (ld -r) the section contents (the data) will be 313 modified. The value of this field is FALSE if addends are 314 recorded with the relocation (in arelent.addend); when performing 315 a partial link the relocation will be modified. 316 All relocations for all ELF USE_RELA targets should set this field 317 to FALSE (values of TRUE should be looked on with suspicion). 318 However, the converse is not true: not all relocations of all ELF 319 USE_REL targets set this field to TRUE. Why this is so is peculiar 320 to each particular target. For relocs that aren't used in partial 321 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 322 bfd_boolean partial_inplace; 323 324 /* src_mask selects the part of the instruction (or data) to be used 325 in the relocation sum. If the target relocations don't have an 326 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 327 dst_mask to extract the addend from the section contents. If 328 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 329 field should be zero. Non-zero values for ELF USE_RELA targets are 330 bogus as in those cases the value in the dst_mask part of the 331 section contents should be treated as garbage. */ 332 bfd_vma src_mask; 333 334 /* dst_mask selects which parts of the instruction (or data) are 335 replaced with a relocated value. */ 336 bfd_vma dst_mask; 337 338 /* When some formats create PC relative instructions, they leave 339 the value of the pc of the place being relocated in the offset 340 slot of the instruction, so that a PC relative relocation can 341 be made just by adding in an ordinary offset (e.g., sun3 a.out). 342 Some formats leave the displacement part of an instruction 343 empty (e.g., m88k bcs); this flag signals the fact. */ 344 bfd_boolean pcrel_offset; 345@}; 346 347@end example 348@findex The HOWTO Macro 349@subsubsection @code{The HOWTO Macro} 350@strong{Description}@* 351The HOWTO define is horrible and will go away. 352@example 353#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 354 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 355@end example 356 357@strong{Description}@* 358And will be replaced with the totally magic way. But for the 359moment, we are compatible, so do it this way. 360@example 361#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 362 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 363 NAME, FALSE, 0, 0, IN) 364 365@end example 366 367@strong{Description}@* 368This is used to fill in an empty howto entry in an array. 369@example 370#define EMPTY_HOWTO(C) \ 371 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 372 NULL, FALSE, 0, 0, FALSE) 373 374@end example 375 376@strong{Description}@* 377Helper routine to turn a symbol into a relocation value. 378@example 379#define HOWTO_PREPARE(relocation, symbol) \ 380 @{ \ 381 if (symbol != NULL) \ 382 @{ \ 383 if (bfd_is_com_section (symbol->section)) \ 384 @{ \ 385 relocation = 0; \ 386 @} \ 387 else \ 388 @{ \ 389 relocation = symbol->value; \ 390 @} \ 391 @} \ 392 @} 393 394@end example 395 396@findex bfd_get_reloc_size 397@subsubsection @code{bfd_get_reloc_size} 398@strong{Synopsis} 399@example 400unsigned int bfd_get_reloc_size (reloc_howto_type *); 401@end example 402@strong{Description}@* 403For a reloc_howto_type that operates on a fixed number of bytes, 404this returns the number of bytes operated on. 405 406@findex arelent_chain 407@subsubsection @code{arelent_chain} 408@strong{Description}@* 409How relocs are tied together in an @code{asection}: 410@example 411typedef struct relent_chain 412@{ 413 arelent relent; 414 struct relent_chain *next; 415@} 416arelent_chain; 417 418@end example 419 420@findex bfd_check_overflow 421@subsubsection @code{bfd_check_overflow} 422@strong{Synopsis} 423@example 424bfd_reloc_status_type bfd_check_overflow 425 (enum complain_overflow how, 426 unsigned int bitsize, 427 unsigned int rightshift, 428 unsigned int addrsize, 429 bfd_vma relocation); 430@end example 431@strong{Description}@* 432Perform overflow checking on @var{relocation} which has 433@var{bitsize} significant bits and will be shifted right by 434@var{rightshift} bits, on a machine with addresses containing 435@var{addrsize} significant bits. The result is either of 436@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 437 438@findex bfd_reloc_offset_in_range 439@subsubsection @code{bfd_reloc_offset_in_range} 440@strong{Synopsis} 441@example 442bfd_boolean bfd_reloc_offset_in_range 443 (reloc_howto_type *howto, 444 bfd *abfd, 445 asection *section, 446 bfd_size_type offset); 447@end example 448@strong{Description}@* 449Returns TRUE if the reloc described by @var{HOWTO} can be 450applied at @var{OFFSET} octets in @var{SECTION}. 451 452@findex bfd_perform_relocation 453@subsubsection @code{bfd_perform_relocation} 454@strong{Synopsis} 455@example 456bfd_reloc_status_type bfd_perform_relocation 457 (bfd *abfd, 458 arelent *reloc_entry, 459 void *data, 460 asection *input_section, 461 bfd *output_bfd, 462 char **error_message); 463@end example 464@strong{Description}@* 465If @var{output_bfd} is supplied to this function, the 466generated image will be relocatable; the relocations are 467copied to the output file after they have been changed to 468reflect the new state of the world. There are two ways of 469reflecting the results of partial linkage in an output file: 470by modifying the output data in place, and by modifying the 471relocation record. Some native formats (e.g., basic a.out and 472basic coff) have no way of specifying an addend in the 473relocation type, so the addend has to go in the output data. 474This is no big deal since in these formats the output data 475slot will always be big enough for the addend. Complex reloc 476types with addends were invented to solve just this problem. 477The @var{error_message} argument is set to an error message if 478this return @code{bfd_reloc_dangerous}. 479 480@findex bfd_install_relocation 481@subsubsection @code{bfd_install_relocation} 482@strong{Synopsis} 483@example 484bfd_reloc_status_type bfd_install_relocation 485 (bfd *abfd, 486 arelent *reloc_entry, 487 void *data, bfd_vma data_start, 488 asection *input_section, 489 char **error_message); 490@end example 491@strong{Description}@* 492This looks remarkably like @code{bfd_perform_relocation}, except it 493does not expect that the section contents have been filled in. 494I.e., it's suitable for use when creating, rather than applying 495a relocation. 496 497For now, this function should be considered reserved for the 498assembler. 499 500 501@node howto manager, , typedef arelent, Relocations 502@subsection The howto manager 503When an application wants to create a relocation, but doesn't 504know what the target machine might call it, it can find out by 505using this bit of code. 506 507@findex bfd_reloc_code_type 508@subsubsection @code{bfd_reloc_code_type} 509@strong{Description}@* 510The insides of a reloc code. The idea is that, eventually, there 511will be one enumerator for every type of relocation we ever do. 512Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 513return a howto pointer. 514 515This does mean that the application must determine the correct 516enumerator value; you can't get a howto pointer from a random set 517of attributes. 518 519Here are the possible values for @code{enum bfd_reloc_code_real}: 520 521@deffn {} BFD_RELOC_64 522@deffnx {} BFD_RELOC_32 523@deffnx {} BFD_RELOC_26 524@deffnx {} BFD_RELOC_24 525@deffnx {} BFD_RELOC_16 526@deffnx {} BFD_RELOC_14 527@deffnx {} BFD_RELOC_8 528Basic absolute relocations of N bits. 529@end deffn 530@deffn {} BFD_RELOC_64_PCREL 531@deffnx {} BFD_RELOC_32_PCREL 532@deffnx {} BFD_RELOC_24_PCREL 533@deffnx {} BFD_RELOC_16_PCREL 534@deffnx {} BFD_RELOC_12_PCREL 535@deffnx {} BFD_RELOC_8_PCREL 536PC-relative relocations. Sometimes these are relative to the address 537of the relocation itself; sometimes they are relative to the start of 538the section containing the relocation. It depends on the specific target. 539 540The 24-bit relocation is used in some Intel 960 configurations. 541@end deffn 542@deffn {} BFD_RELOC_32_SECREL 543Section relative relocations. Some targets need this for DWARF2. 544@end deffn 545@deffn {} BFD_RELOC_32_GOT_PCREL 546@deffnx {} BFD_RELOC_16_GOT_PCREL 547@deffnx {} BFD_RELOC_8_GOT_PCREL 548@deffnx {} BFD_RELOC_32_GOTOFF 549@deffnx {} BFD_RELOC_16_GOTOFF 550@deffnx {} BFD_RELOC_LO16_GOTOFF 551@deffnx {} BFD_RELOC_HI16_GOTOFF 552@deffnx {} BFD_RELOC_HI16_S_GOTOFF 553@deffnx {} BFD_RELOC_8_GOTOFF 554@deffnx {} BFD_RELOC_64_PLT_PCREL 555@deffnx {} BFD_RELOC_32_PLT_PCREL 556@deffnx {} BFD_RELOC_24_PLT_PCREL 557@deffnx {} BFD_RELOC_16_PLT_PCREL 558@deffnx {} BFD_RELOC_8_PLT_PCREL 559@deffnx {} BFD_RELOC_64_PLTOFF 560@deffnx {} BFD_RELOC_32_PLTOFF 561@deffnx {} BFD_RELOC_16_PLTOFF 562@deffnx {} BFD_RELOC_LO16_PLTOFF 563@deffnx {} BFD_RELOC_HI16_PLTOFF 564@deffnx {} BFD_RELOC_HI16_S_PLTOFF 565@deffnx {} BFD_RELOC_8_PLTOFF 566For ELF. 567@end deffn 568@deffn {} BFD_RELOC_SIZE32 569@deffnx {} BFD_RELOC_SIZE64 570Size relocations. 571@end deffn 572@deffn {} BFD_RELOC_68K_GLOB_DAT 573@deffnx {} BFD_RELOC_68K_JMP_SLOT 574@deffnx {} BFD_RELOC_68K_RELATIVE 575@deffnx {} BFD_RELOC_68K_TLS_GD32 576@deffnx {} BFD_RELOC_68K_TLS_GD16 577@deffnx {} BFD_RELOC_68K_TLS_GD8 578@deffnx {} BFD_RELOC_68K_TLS_LDM32 579@deffnx {} BFD_RELOC_68K_TLS_LDM16 580@deffnx {} BFD_RELOC_68K_TLS_LDM8 581@deffnx {} BFD_RELOC_68K_TLS_LDO32 582@deffnx {} BFD_RELOC_68K_TLS_LDO16 583@deffnx {} BFD_RELOC_68K_TLS_LDO8 584@deffnx {} BFD_RELOC_68K_TLS_IE32 585@deffnx {} BFD_RELOC_68K_TLS_IE16 586@deffnx {} BFD_RELOC_68K_TLS_IE8 587@deffnx {} BFD_RELOC_68K_TLS_LE32 588@deffnx {} BFD_RELOC_68K_TLS_LE16 589@deffnx {} BFD_RELOC_68K_TLS_LE8 590Relocations used by 68K ELF. 591@end deffn 592@deffn {} BFD_RELOC_VAX_GLOB_DAT 593@deffnx {} BFD_RELOC_VAX_GLOB_REF 594@deffnx {} BFD_RELOC_VAX_JMP_SLOT 595@deffnx {} BFD_RELOC_VAX_RELATIVE 596Relocations used by VAX ELF. 597@end deffn 598@deffn {} BFD_RELOC_32_BASEREL 599@deffnx {} BFD_RELOC_16_BASEREL 600@deffnx {} BFD_RELOC_LO16_BASEREL 601@deffnx {} BFD_RELOC_HI16_BASEREL 602@deffnx {} BFD_RELOC_HI16_S_BASEREL 603@deffnx {} BFD_RELOC_8_BASEREL 604@deffnx {} BFD_RELOC_RVA 605Linkage-table relative. 606@end deffn 607@deffn {} BFD_RELOC_8_FFnn 608Absolute 8-bit relocation, but used to form an address like 0xFFnn. 609@end deffn 610@deffn {} BFD_RELOC_32_PCREL_S2 611@deffnx {} BFD_RELOC_16_PCREL_S2 612@deffnx {} BFD_RELOC_23_PCREL_S2 613These PC-relative relocations are stored as word displacements -- 614i.e., byte displacements shifted right two bits. The 30-bit word 615displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 616SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 617signed 16-bit displacement is used on the MIPS, and the 23-bit 618displacement is used on the Alpha. 619@end deffn 620@deffn {} BFD_RELOC_HI22 621@deffnx {} BFD_RELOC_LO10 622High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 623the target word. These are used on the SPARC. 624@end deffn 625@deffn {} BFD_RELOC_GPREL16 626@deffnx {} BFD_RELOC_GPREL32 627For systems that allocate a Global Pointer register, these are 628displacements off that register. These relocation types are 629handled specially, because the value the register will have is 630decided relatively late. 631@end deffn 632@deffn {} BFD_RELOC_I960_CALLJ 633Reloc types used for i960/b.out. 634@end deffn 635@deffn {} BFD_RELOC_NONE 636@deffnx {} BFD_RELOC_SPARC_WDISP22 637@deffnx {} BFD_RELOC_SPARC22 638@deffnx {} BFD_RELOC_SPARC13 639@deffnx {} BFD_RELOC_SPARC_GOT10 640@deffnx {} BFD_RELOC_SPARC_GOT13 641@deffnx {} BFD_RELOC_SPARC_GOT22 642@deffnx {} BFD_RELOC_SPARC_PC10 643@deffnx {} BFD_RELOC_SPARC_PC22 644@deffnx {} BFD_RELOC_SPARC_WPLT30 645@deffnx {} BFD_RELOC_SPARC_COPY 646@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 647@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 648@deffnx {} BFD_RELOC_SPARC_RELATIVE 649@deffnx {} BFD_RELOC_SPARC_UA16 650@deffnx {} BFD_RELOC_SPARC_UA32 651@deffnx {} BFD_RELOC_SPARC_UA64 652@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 653@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 654@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 655@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 656@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 657@deffnx {} BFD_RELOC_SPARC_JMP_IREL 658@deffnx {} BFD_RELOC_SPARC_IRELATIVE 659SPARC ELF relocations. There is probably some overlap with other 660relocation types already defined. 661@end deffn 662@deffn {} BFD_RELOC_SPARC_BASE13 663@deffnx {} BFD_RELOC_SPARC_BASE22 664I think these are specific to SPARC a.out (e.g., Sun 4). 665@end deffn 666@deffn {} BFD_RELOC_SPARC_64 667@deffnx {} BFD_RELOC_SPARC_10 668@deffnx {} BFD_RELOC_SPARC_11 669@deffnx {} BFD_RELOC_SPARC_OLO10 670@deffnx {} BFD_RELOC_SPARC_HH22 671@deffnx {} BFD_RELOC_SPARC_HM10 672@deffnx {} BFD_RELOC_SPARC_LM22 673@deffnx {} BFD_RELOC_SPARC_PC_HH22 674@deffnx {} BFD_RELOC_SPARC_PC_HM10 675@deffnx {} BFD_RELOC_SPARC_PC_LM22 676@deffnx {} BFD_RELOC_SPARC_WDISP16 677@deffnx {} BFD_RELOC_SPARC_WDISP19 678@deffnx {} BFD_RELOC_SPARC_7 679@deffnx {} BFD_RELOC_SPARC_6 680@deffnx {} BFD_RELOC_SPARC_5 681@deffnx {} BFD_RELOC_SPARC_DISP64 682@deffnx {} BFD_RELOC_SPARC_PLT32 683@deffnx {} BFD_RELOC_SPARC_PLT64 684@deffnx {} BFD_RELOC_SPARC_HIX22 685@deffnx {} BFD_RELOC_SPARC_LOX10 686@deffnx {} BFD_RELOC_SPARC_H44 687@deffnx {} BFD_RELOC_SPARC_M44 688@deffnx {} BFD_RELOC_SPARC_L44 689@deffnx {} BFD_RELOC_SPARC_REGISTER 690@deffnx {} BFD_RELOC_SPARC_H34 691@deffnx {} BFD_RELOC_SPARC_SIZE32 692@deffnx {} BFD_RELOC_SPARC_SIZE64 693@deffnx {} BFD_RELOC_SPARC_WDISP10 694SPARC64 relocations 695@end deffn 696@deffn {} BFD_RELOC_SPARC_REV32 697SPARC little endian relocation 698@end deffn 699@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 700@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 701@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 702@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 703@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 704@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 705@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 706@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 707@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 708@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 709@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 710@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 711@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 712@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 713@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 714@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 715@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 716@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 717@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 718@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 719@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 720@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 721@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 722@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 723SPARC TLS relocations 724@end deffn 725@deffn {} BFD_RELOC_SPU_IMM7 726@deffnx {} BFD_RELOC_SPU_IMM8 727@deffnx {} BFD_RELOC_SPU_IMM10 728@deffnx {} BFD_RELOC_SPU_IMM10W 729@deffnx {} BFD_RELOC_SPU_IMM16 730@deffnx {} BFD_RELOC_SPU_IMM16W 731@deffnx {} BFD_RELOC_SPU_IMM18 732@deffnx {} BFD_RELOC_SPU_PCREL9a 733@deffnx {} BFD_RELOC_SPU_PCREL9b 734@deffnx {} BFD_RELOC_SPU_PCREL16 735@deffnx {} BFD_RELOC_SPU_LO16 736@deffnx {} BFD_RELOC_SPU_HI16 737@deffnx {} BFD_RELOC_SPU_PPU32 738@deffnx {} BFD_RELOC_SPU_PPU64 739@deffnx {} BFD_RELOC_SPU_ADD_PIC 740SPU Relocations. 741@end deffn 742@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 743Alpha ECOFF and ELF relocations. Some of these treat the symbol or 744"addend" in some special way. 745For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 746writing; when reading, it will be the absolute section symbol. The 747addend is the displacement in bytes of the "lda" instruction from 748the "ldah" instruction (which is at the address of this reloc). 749@end deffn 750@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 751For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 752with GPDISP_HI16 relocs. The addend is ignored when writing the 753relocations out, and is filled in with the file's GP value on 754reading, for convenience. 755@end deffn 756@deffn {} BFD_RELOC_ALPHA_GPDISP 757The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 758relocation except that there is no accompanying GPDISP_LO16 759relocation. 760@end deffn 761@deffn {} BFD_RELOC_ALPHA_LITERAL 762@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 763@deffnx {} BFD_RELOC_ALPHA_LITUSE 764The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 765the assembler turns it into a LDQ instruction to load the address of 766the symbol, and then fills in a register in the real instruction. 767 768The LITERAL reloc, at the LDQ instruction, refers to the .lita 769section symbol. The addend is ignored when writing, but is filled 770in with the file's GP value on reading, for convenience, as with the 771GPDISP_LO16 reloc. 772 773The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 774It should refer to the symbol to be referenced, as with 16_GOTOFF, 775but it generates output not based on the position within the .got 776section, but relative to the GP value chosen for the file during the 777final link stage. 778 779The LITUSE reloc, on the instruction using the loaded address, gives 780information to the linker that it might be able to use to optimize 781away some literal section references. The symbol is ignored (read 782as the absolute section symbol), and the "addend" indicates the type 783of instruction using the register: 7841 - "memory" fmt insn 7852 - byte-manipulation (byte offset reg) 7863 - jsr (target of branch) 787@end deffn 788@deffn {} BFD_RELOC_ALPHA_HINT 789The HINT relocation indicates a value that should be filled into the 790"hint" field of a jmp/jsr/ret instruction, for possible branch- 791prediction logic which may be provided on some processors. 792@end deffn 793@deffn {} BFD_RELOC_ALPHA_LINKAGE 794The LINKAGE relocation outputs a linkage pair in the object file, 795which is filled by the linker. 796@end deffn 797@deffn {} BFD_RELOC_ALPHA_CODEADDR 798The CODEADDR relocation outputs a STO_CA in the object file, 799which is filled by the linker. 800@end deffn 801@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 802@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 803The GPREL_HI/LO relocations together form a 32-bit offset from the 804GP register. 805@end deffn 806@deffn {} BFD_RELOC_ALPHA_BRSGP 807Like BFD_RELOC_23_PCREL_S2, except that the source and target must 808share a common GP, and the target address is adjusted for 809STO_ALPHA_STD_GPLOAD. 810@end deffn 811@deffn {} BFD_RELOC_ALPHA_NOP 812The NOP relocation outputs a NOP if the longword displacement 813between two procedure entry points is < 2^21. 814@end deffn 815@deffn {} BFD_RELOC_ALPHA_BSR 816The BSR relocation outputs a BSR if the longword displacement 817between two procedure entry points is < 2^21. 818@end deffn 819@deffn {} BFD_RELOC_ALPHA_LDA 820The LDA relocation outputs a LDA if the longword displacement 821between two procedure entry points is < 2^16. 822@end deffn 823@deffn {} BFD_RELOC_ALPHA_BOH 824The BOH relocation outputs a BSR if the longword displacement 825between two procedure entry points is < 2^21, or else a hint. 826@end deffn 827@deffn {} BFD_RELOC_ALPHA_TLSGD 828@deffnx {} BFD_RELOC_ALPHA_TLSLDM 829@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 830@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 831@deffnx {} BFD_RELOC_ALPHA_DTPREL64 832@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 833@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 834@deffnx {} BFD_RELOC_ALPHA_DTPREL16 835@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 836@deffnx {} BFD_RELOC_ALPHA_TPREL64 837@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 838@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 839@deffnx {} BFD_RELOC_ALPHA_TPREL16 840Alpha thread-local storage relocations. 841@end deffn 842@deffn {} BFD_RELOC_MIPS_JMP 843@deffnx {} BFD_RELOC_MICROMIPS_JMP 844The MIPS jump instruction. 845@end deffn 846@deffn {} BFD_RELOC_MIPS16_JMP 847The MIPS16 jump instruction. 848@end deffn 849@deffn {} BFD_RELOC_MIPS16_GPREL 850MIPS16 GP relative reloc. 851@end deffn 852@deffn {} BFD_RELOC_HI16 853High 16 bits of 32-bit value; simple reloc. 854@end deffn 855@deffn {} BFD_RELOC_HI16_S 856High 16 bits of 32-bit value but the low 16 bits will be sign 857extended and added to form the final result. If the low 16 858bits form a negative number, we need to add one to the high value 859to compensate for the borrow when the low bits are added. 860@end deffn 861@deffn {} BFD_RELOC_LO16 862Low 16 bits. 863@end deffn 864@deffn {} BFD_RELOC_HI16_PCREL 865High 16 bits of 32-bit pc-relative value 866@end deffn 867@deffn {} BFD_RELOC_HI16_S_PCREL 868High 16 bits of 32-bit pc-relative value, adjusted 869@end deffn 870@deffn {} BFD_RELOC_LO16_PCREL 871Low 16 bits of pc-relative value 872@end deffn 873@deffn {} BFD_RELOC_MIPS16_GOT16 874@deffnx {} BFD_RELOC_MIPS16_CALL16 875Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 87616-bit immediate fields 877@end deffn 878@deffn {} BFD_RELOC_MIPS16_HI16 879MIPS16 high 16 bits of 32-bit value. 880@end deffn 881@deffn {} BFD_RELOC_MIPS16_HI16_S 882MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 883extended and added to form the final result. If the low 16 884bits form a negative number, we need to add one to the high value 885to compensate for the borrow when the low bits are added. 886@end deffn 887@deffn {} BFD_RELOC_MIPS16_LO16 888MIPS16 low 16 bits. 889@end deffn 890@deffn {} BFD_RELOC_MIPS16_TLS_GD 891@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 892@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 893@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 894@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 895@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 896@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 897MIPS16 TLS relocations 898@end deffn 899@deffn {} BFD_RELOC_MIPS_LITERAL 900@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 901Relocation against a MIPS literal section. 902@end deffn 903@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 904@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 905@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 906microMIPS PC-relative relocations. 907@end deffn 908@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 909MIPS16 PC-relative relocation. 910@end deffn 911@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 912@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 913@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 914@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 915MIPS PC-relative relocations. 916@end deffn 917@deffn {} BFD_RELOC_MICROMIPS_GPREL16 918@deffnx {} BFD_RELOC_MICROMIPS_HI16 919@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 920@deffnx {} BFD_RELOC_MICROMIPS_LO16 921microMIPS versions of generic BFD relocs. 922@end deffn 923@deffn {} BFD_RELOC_MIPS_GOT16 924@deffnx {} BFD_RELOC_MICROMIPS_GOT16 925@deffnx {} BFD_RELOC_MIPS_CALL16 926@deffnx {} BFD_RELOC_MICROMIPS_CALL16 927@deffnx {} BFD_RELOC_MIPS_GOT_HI16 928@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 929@deffnx {} BFD_RELOC_MIPS_GOT_LO16 930@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 931@deffnx {} BFD_RELOC_MIPS_CALL_HI16 932@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 933@deffnx {} BFD_RELOC_MIPS_CALL_LO16 934@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 935@deffnx {} BFD_RELOC_MIPS_SUB 936@deffnx {} BFD_RELOC_MICROMIPS_SUB 937@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 938@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 939@deffnx {} BFD_RELOC_MIPS_GOT_OFST 940@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 941@deffnx {} BFD_RELOC_MIPS_GOT_DISP 942@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 943@deffnx {} BFD_RELOC_MIPS_SHIFT5 944@deffnx {} BFD_RELOC_MIPS_SHIFT6 945@deffnx {} BFD_RELOC_MIPS_INSERT_A 946@deffnx {} BFD_RELOC_MIPS_INSERT_B 947@deffnx {} BFD_RELOC_MIPS_DELETE 948@deffnx {} BFD_RELOC_MIPS_HIGHEST 949@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 950@deffnx {} BFD_RELOC_MIPS_HIGHER 951@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 952@deffnx {} BFD_RELOC_MIPS_SCN_DISP 953@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 954@deffnx {} BFD_RELOC_MIPS_REL16 955@deffnx {} BFD_RELOC_MIPS_RELGOT 956@deffnx {} BFD_RELOC_MIPS_JALR 957@deffnx {} BFD_RELOC_MICROMIPS_JALR 958@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 959@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 960@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 961@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 962@deffnx {} BFD_RELOC_MIPS_TLS_GD 963@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 964@deffnx {} BFD_RELOC_MIPS_TLS_LDM 965@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 966@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 967@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 968@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 969@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 970@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 971@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 972@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 973@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 974@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 975@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 976@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 977@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 978@deffnx {} BFD_RELOC_MIPS_EH 979MIPS ELF relocations. 980@end deffn 981@deffn {} BFD_RELOC_MIPS_COPY 982@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 983MIPS ELF relocations (VxWorks and PLT extensions). 984@end deffn 985@deffn {} BFD_RELOC_MOXIE_10_PCREL 986Moxie ELF relocations. 987@end deffn 988@deffn {} BFD_RELOC_FT32_10 989@deffnx {} BFD_RELOC_FT32_20 990@deffnx {} BFD_RELOC_FT32_17 991@deffnx {} BFD_RELOC_FT32_18 992@deffnx {} BFD_RELOC_FT32_RELAX 993@deffnx {} BFD_RELOC_FT32_SC0 994@deffnx {} BFD_RELOC_FT32_SC1 995@deffnx {} BFD_RELOC_FT32_15 996@deffnx {} BFD_RELOC_FT32_DIFF32 997FT32 ELF relocations. 998@end deffn 999@deffn {} BFD_RELOC_FRV_LABEL16 1000@deffnx {} BFD_RELOC_FRV_LABEL24 1001@deffnx {} BFD_RELOC_FRV_LO16 1002@deffnx {} BFD_RELOC_FRV_HI16 1003@deffnx {} BFD_RELOC_FRV_GPREL12 1004@deffnx {} BFD_RELOC_FRV_GPRELU12 1005@deffnx {} BFD_RELOC_FRV_GPREL32 1006@deffnx {} BFD_RELOC_FRV_GPRELHI 1007@deffnx {} BFD_RELOC_FRV_GPRELLO 1008@deffnx {} BFD_RELOC_FRV_GOT12 1009@deffnx {} BFD_RELOC_FRV_GOTHI 1010@deffnx {} BFD_RELOC_FRV_GOTLO 1011@deffnx {} BFD_RELOC_FRV_FUNCDESC 1012@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 1013@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 1014@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 1015@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 1016@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 1017@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 1018@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 1019@deffnx {} BFD_RELOC_FRV_GOTOFF12 1020@deffnx {} BFD_RELOC_FRV_GOTOFFHI 1021@deffnx {} BFD_RELOC_FRV_GOTOFFLO 1022@deffnx {} BFD_RELOC_FRV_GETTLSOFF 1023@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 1024@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 1025@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 1026@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 1027@deffnx {} BFD_RELOC_FRV_TLSMOFF12 1028@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 1029@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 1030@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 1031@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 1032@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 1033@deffnx {} BFD_RELOC_FRV_TLSOFF 1034@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 1035@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 1036@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 1037@deffnx {} BFD_RELOC_FRV_TLSMOFF 1038Fujitsu Frv Relocations. 1039@end deffn 1040@deffn {} BFD_RELOC_MN10300_GOTOFF24 1041This is a 24bit GOT-relative reloc for the mn10300. 1042@end deffn 1043@deffn {} BFD_RELOC_MN10300_GOT32 1044This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1045in the instruction. 1046@end deffn 1047@deffn {} BFD_RELOC_MN10300_GOT24 1048This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1049in the instruction. 1050@end deffn 1051@deffn {} BFD_RELOC_MN10300_GOT16 1052This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1053in the instruction. 1054@end deffn 1055@deffn {} BFD_RELOC_MN10300_COPY 1056Copy symbol at runtime. 1057@end deffn 1058@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1059Create GOT entry. 1060@end deffn 1061@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1062Create PLT entry. 1063@end deffn 1064@deffn {} BFD_RELOC_MN10300_RELATIVE 1065Adjust by program base. 1066@end deffn 1067@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1068Together with another reloc targeted at the same location, 1069allows for a value that is the difference of two symbols 1070in the same section. 1071@end deffn 1072@deffn {} BFD_RELOC_MN10300_ALIGN 1073The addend of this reloc is an alignment power that must 1074be honoured at the offset's location, regardless of linker 1075relaxation. 1076@end deffn 1077@deffn {} BFD_RELOC_MN10300_TLS_GD 1078@deffnx {} BFD_RELOC_MN10300_TLS_LD 1079@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1080@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1081@deffnx {} BFD_RELOC_MN10300_TLS_IE 1082@deffnx {} BFD_RELOC_MN10300_TLS_LE 1083@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1084@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1085@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1086Various TLS-related relocations. 1087@end deffn 1088@deffn {} BFD_RELOC_MN10300_32_PCREL 1089This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1090instruction. 1091@end deffn 1092@deffn {} BFD_RELOC_MN10300_16_PCREL 1093This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1094instruction. 1095@end deffn 1096@deffn {} BFD_RELOC_386_GOT32 1097@deffnx {} BFD_RELOC_386_PLT32 1098@deffnx {} BFD_RELOC_386_COPY 1099@deffnx {} BFD_RELOC_386_GLOB_DAT 1100@deffnx {} BFD_RELOC_386_JUMP_SLOT 1101@deffnx {} BFD_RELOC_386_RELATIVE 1102@deffnx {} BFD_RELOC_386_GOTOFF 1103@deffnx {} BFD_RELOC_386_GOTPC 1104@deffnx {} BFD_RELOC_386_TLS_TPOFF 1105@deffnx {} BFD_RELOC_386_TLS_IE 1106@deffnx {} BFD_RELOC_386_TLS_GOTIE 1107@deffnx {} BFD_RELOC_386_TLS_LE 1108@deffnx {} BFD_RELOC_386_TLS_GD 1109@deffnx {} BFD_RELOC_386_TLS_LDM 1110@deffnx {} BFD_RELOC_386_TLS_LDO_32 1111@deffnx {} BFD_RELOC_386_TLS_IE_32 1112@deffnx {} BFD_RELOC_386_TLS_LE_32 1113@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1114@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1115@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1116@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1117@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1118@deffnx {} BFD_RELOC_386_TLS_DESC 1119@deffnx {} BFD_RELOC_386_IRELATIVE 1120@deffnx {} BFD_RELOC_386_GOT32X 1121i386/elf relocations 1122@end deffn 1123@deffn {} BFD_RELOC_X86_64_GOT32 1124@deffnx {} BFD_RELOC_X86_64_PLT32 1125@deffnx {} BFD_RELOC_X86_64_COPY 1126@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1127@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1128@deffnx {} BFD_RELOC_X86_64_RELATIVE 1129@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1130@deffnx {} BFD_RELOC_X86_64_32S 1131@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1132@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1133@deffnx {} BFD_RELOC_X86_64_TPOFF64 1134@deffnx {} BFD_RELOC_X86_64_TLSGD 1135@deffnx {} BFD_RELOC_X86_64_TLSLD 1136@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1137@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1138@deffnx {} BFD_RELOC_X86_64_TPOFF32 1139@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1140@deffnx {} BFD_RELOC_X86_64_GOTPC32 1141@deffnx {} BFD_RELOC_X86_64_GOT64 1142@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1143@deffnx {} BFD_RELOC_X86_64_GOTPC64 1144@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1145@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1146@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1147@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1148@deffnx {} BFD_RELOC_X86_64_TLSDESC 1149@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1150@deffnx {} BFD_RELOC_X86_64_PC32_BND 1151@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1152@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1153@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1154x86-64/elf relocations 1155@end deffn 1156@deffn {} BFD_RELOC_NS32K_IMM_8 1157@deffnx {} BFD_RELOC_NS32K_IMM_16 1158@deffnx {} BFD_RELOC_NS32K_IMM_32 1159@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1160@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1161@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1162@deffnx {} BFD_RELOC_NS32K_DISP_8 1163@deffnx {} BFD_RELOC_NS32K_DISP_16 1164@deffnx {} BFD_RELOC_NS32K_DISP_32 1165@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1166@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1167@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1168ns32k relocations 1169@end deffn 1170@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1171@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1172PDP11 relocations 1173@end deffn 1174@deffn {} BFD_RELOC_PJ_CODE_HI16 1175@deffnx {} BFD_RELOC_PJ_CODE_LO16 1176@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1177@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1178@deffnx {} BFD_RELOC_PJ_CODE_REL16 1179@deffnx {} BFD_RELOC_PJ_CODE_REL32 1180Picojava relocs. Not all of these appear in object files. 1181@end deffn 1182@deffn {} BFD_RELOC_PPC_B26 1183@deffnx {} BFD_RELOC_PPC_BA26 1184@deffnx {} BFD_RELOC_PPC_TOC16 1185@deffnx {} BFD_RELOC_PPC_B16 1186@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1187@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1188@deffnx {} BFD_RELOC_PPC_BA16 1189@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1190@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1191@deffnx {} BFD_RELOC_PPC_COPY 1192@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1193@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1194@deffnx {} BFD_RELOC_PPC_RELATIVE 1195@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1196@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1197@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1198@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1199@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1200@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1201@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1202@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1203@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1204@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1205@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1206@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1207@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1208@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1209@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1210@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1211@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1212@deffnx {} BFD_RELOC_PPC_VLE_REL8 1213@deffnx {} BFD_RELOC_PPC_VLE_REL15 1214@deffnx {} BFD_RELOC_PPC_VLE_REL24 1215@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1216@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1217@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1218@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1219@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1220@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1221@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1222@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1223@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1224@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1225@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1226@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1227@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1228@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1229@deffnx {} BFD_RELOC_PPC_16DX_HA 1230@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1231@deffnx {} BFD_RELOC_PPC64_HIGHER 1232@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1233@deffnx {} BFD_RELOC_PPC64_HIGHEST 1234@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1235@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1236@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1237@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1238@deffnx {} BFD_RELOC_PPC64_TOC 1239@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1240@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1241@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1242@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1243@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1244@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1245@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1246@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1247@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1248@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1249@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1250@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1251@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1252@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1253@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1254@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1255@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1256@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1257@deffnx {} BFD_RELOC_PPC64_ENTRY 1258Power(rs6000) and PowerPC relocations. 1259@end deffn 1260@deffn {} BFD_RELOC_PPC_TLS 1261@deffnx {} BFD_RELOC_PPC_TLSGD 1262@deffnx {} BFD_RELOC_PPC_TLSLD 1263@deffnx {} BFD_RELOC_PPC_DTPMOD 1264@deffnx {} BFD_RELOC_PPC_TPREL16 1265@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1266@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1267@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1268@deffnx {} BFD_RELOC_PPC_TPREL 1269@deffnx {} BFD_RELOC_PPC_DTPREL16 1270@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1271@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1272@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1273@deffnx {} BFD_RELOC_PPC_DTPREL 1274@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1275@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1276@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1277@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1278@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1279@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1280@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1281@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1282@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1283@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1284@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1285@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1286@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1287@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1288@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1289@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1290@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1291@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1292@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1293@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1294@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1295@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1296@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1297@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1298@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1299@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1300@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1301@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1302@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1303@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1304@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1305@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1306PowerPC and PowerPC64 thread-local storage relocations. 1307@end deffn 1308@deffn {} BFD_RELOC_I370_D12 1309IBM 370/390 relocations 1310@end deffn 1311@deffn {} BFD_RELOC_CTOR 1312The type of reloc used to build a constructor table - at the moment 1313probably a 32 bit wide absolute relocation, but the target can choose. 1314It generally does map to one of the other relocation types. 1315@end deffn 1316@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1317ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1318not stored in the instruction. 1319@end deffn 1320@deffn {} BFD_RELOC_ARM_PCREL_BLX 1321ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1322not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1323field in the instruction. 1324@end deffn 1325@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1326Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1327not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1328field in the instruction. 1329@end deffn 1330@deffn {} BFD_RELOC_ARM_PCREL_CALL 1331ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1332@end deffn 1333@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1334ARM 26-bit pc-relative branch for B or conditional BL instruction. 1335@end deffn 1336@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1337@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1338@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1339@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1340@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1341@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1342Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1343The lowest bit must be zero and is not stored in the instruction. 1344Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1345"nn" one smaller in all cases. Note further that BRANCH23 1346corresponds to R_ARM_THM_CALL. 1347@end deffn 1348@deffn {} BFD_RELOC_ARM_OFFSET_IMM 134912-bit immediate offset, used in ARM-format ldr and str instructions. 1350@end deffn 1351@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13525-bit immediate offset, used in Thumb-format ldr and str instructions. 1353@end deffn 1354@deffn {} BFD_RELOC_ARM_TARGET1 1355Pc-relative or absolute relocation depending on target. Used for 1356entries in .init_array sections. 1357@end deffn 1358@deffn {} BFD_RELOC_ARM_ROSEGREL32 1359Read-only segment base relative address. 1360@end deffn 1361@deffn {} BFD_RELOC_ARM_SBREL32 1362Data segment base relative address. 1363@end deffn 1364@deffn {} BFD_RELOC_ARM_TARGET2 1365This reloc is used for references to RTTI data from exception handling 1366tables. The actual definition depends on the target. It may be a 1367pc-relative or some form of GOT-indirect relocation. 1368@end deffn 1369@deffn {} BFD_RELOC_ARM_PREL31 137031-bit PC relative address. 1371@end deffn 1372@deffn {} BFD_RELOC_ARM_MOVW 1373@deffnx {} BFD_RELOC_ARM_MOVT 1374@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1375@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1376@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1377@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1378@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1379@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1380Low and High halfword relocations for MOVW and MOVT instructions. 1381@end deffn 1382@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1383@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1384@deffnx {} BFD_RELOC_ARM_GOT32 1385@deffnx {} BFD_RELOC_ARM_PLT32 1386@deffnx {} BFD_RELOC_ARM_RELATIVE 1387@deffnx {} BFD_RELOC_ARM_GOTOFF 1388@deffnx {} BFD_RELOC_ARM_GOTPC 1389@deffnx {} BFD_RELOC_ARM_GOT_PREL 1390Relocations for setting up GOTs and PLTs for shared libraries. 1391@end deffn 1392@deffn {} BFD_RELOC_ARM_TLS_GD32 1393@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1394@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1395@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1396@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1397@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1398@deffnx {} BFD_RELOC_ARM_TLS_IE32 1399@deffnx {} BFD_RELOC_ARM_TLS_LE32 1400@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1401@deffnx {} BFD_RELOC_ARM_TLS_CALL 1402@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1403@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1404@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1405@deffnx {} BFD_RELOC_ARM_TLS_DESC 1406ARM thread-local storage relocations. 1407@end deffn 1408@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1409@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1410@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1411@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1412@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1413@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1414@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1415@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1416@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1417@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1418@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1419@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1420@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1421@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1422@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1423@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1424@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1425@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1426@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1427@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1428@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1429@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1430@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1431@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1432@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1433@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1434@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1435@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1436ARM group relocations. 1437@end deffn 1438@deffn {} BFD_RELOC_ARM_V4BX 1439Annotation of BX instructions. 1440@end deffn 1441@deffn {} BFD_RELOC_ARM_IRELATIVE 1442ARM support for STT_GNU_IFUNC. 1443@end deffn 1444@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1445@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1446@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1447@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1448Thumb1 relocations to support execute-only code. 1449@end deffn 1450@deffn {} BFD_RELOC_ARM_IMMEDIATE 1451@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1452@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1453@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1454@deffnx {} BFD_RELOC_ARM_T32_IMM12 1455@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1456@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1457@deffnx {} BFD_RELOC_ARM_SMC 1458@deffnx {} BFD_RELOC_ARM_HVC 1459@deffnx {} BFD_RELOC_ARM_SWI 1460@deffnx {} BFD_RELOC_ARM_MULTI 1461@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1462@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1463@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1464@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1465@deffnx {} BFD_RELOC_ARM_ADR_IMM 1466@deffnx {} BFD_RELOC_ARM_LDR_IMM 1467@deffnx {} BFD_RELOC_ARM_LITERAL 1468@deffnx {} BFD_RELOC_ARM_IN_POOL 1469@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1470@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1471@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1472@deffnx {} BFD_RELOC_ARM_HWLITERAL 1473@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1474@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1475@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1476These relocs are only used within the ARM assembler. They are not 1477(at present) written to any object files. 1478@end deffn 1479@deffn {} BFD_RELOC_SH_PCDISP8BY2 1480@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1481@deffnx {} BFD_RELOC_SH_IMM3 1482@deffnx {} BFD_RELOC_SH_IMM3U 1483@deffnx {} BFD_RELOC_SH_DISP12 1484@deffnx {} BFD_RELOC_SH_DISP12BY2 1485@deffnx {} BFD_RELOC_SH_DISP12BY4 1486@deffnx {} BFD_RELOC_SH_DISP12BY8 1487@deffnx {} BFD_RELOC_SH_DISP20 1488@deffnx {} BFD_RELOC_SH_DISP20BY8 1489@deffnx {} BFD_RELOC_SH_IMM4 1490@deffnx {} BFD_RELOC_SH_IMM4BY2 1491@deffnx {} BFD_RELOC_SH_IMM4BY4 1492@deffnx {} BFD_RELOC_SH_IMM8 1493@deffnx {} BFD_RELOC_SH_IMM8BY2 1494@deffnx {} BFD_RELOC_SH_IMM8BY4 1495@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1496@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1497@deffnx {} BFD_RELOC_SH_SWITCH16 1498@deffnx {} BFD_RELOC_SH_SWITCH32 1499@deffnx {} BFD_RELOC_SH_USES 1500@deffnx {} BFD_RELOC_SH_COUNT 1501@deffnx {} BFD_RELOC_SH_ALIGN 1502@deffnx {} BFD_RELOC_SH_CODE 1503@deffnx {} BFD_RELOC_SH_DATA 1504@deffnx {} BFD_RELOC_SH_LABEL 1505@deffnx {} BFD_RELOC_SH_LOOP_START 1506@deffnx {} BFD_RELOC_SH_LOOP_END 1507@deffnx {} BFD_RELOC_SH_COPY 1508@deffnx {} BFD_RELOC_SH_GLOB_DAT 1509@deffnx {} BFD_RELOC_SH_JMP_SLOT 1510@deffnx {} BFD_RELOC_SH_RELATIVE 1511@deffnx {} BFD_RELOC_SH_GOTPC 1512@deffnx {} BFD_RELOC_SH_GOT_LOW16 1513@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1514@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1515@deffnx {} BFD_RELOC_SH_GOT_HI16 1516@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1517@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1518@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1519@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1520@deffnx {} BFD_RELOC_SH_PLT_LOW16 1521@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1522@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1523@deffnx {} BFD_RELOC_SH_PLT_HI16 1524@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1525@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1526@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1527@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1528@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1529@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1530@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1531@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1532@deffnx {} BFD_RELOC_SH_COPY64 1533@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1534@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1535@deffnx {} BFD_RELOC_SH_RELATIVE64 1536@deffnx {} BFD_RELOC_SH_GOT10BY4 1537@deffnx {} BFD_RELOC_SH_GOT10BY8 1538@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1539@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1540@deffnx {} BFD_RELOC_SH_GOTPLT32 1541@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1542@deffnx {} BFD_RELOC_SH_IMMU5 1543@deffnx {} BFD_RELOC_SH_IMMS6 1544@deffnx {} BFD_RELOC_SH_IMMS6BY32 1545@deffnx {} BFD_RELOC_SH_IMMU6 1546@deffnx {} BFD_RELOC_SH_IMMS10 1547@deffnx {} BFD_RELOC_SH_IMMS10BY2 1548@deffnx {} BFD_RELOC_SH_IMMS10BY4 1549@deffnx {} BFD_RELOC_SH_IMMS10BY8 1550@deffnx {} BFD_RELOC_SH_IMMS16 1551@deffnx {} BFD_RELOC_SH_IMMU16 1552@deffnx {} BFD_RELOC_SH_IMM_LOW16 1553@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1554@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1555@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1556@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1557@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1558@deffnx {} BFD_RELOC_SH_IMM_HI16 1559@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1560@deffnx {} BFD_RELOC_SH_PT_16 1561@deffnx {} BFD_RELOC_SH_TLS_GD_32 1562@deffnx {} BFD_RELOC_SH_TLS_LD_32 1563@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1564@deffnx {} BFD_RELOC_SH_TLS_IE_32 1565@deffnx {} BFD_RELOC_SH_TLS_LE_32 1566@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1567@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1568@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1569@deffnx {} BFD_RELOC_SH_GOT20 1570@deffnx {} BFD_RELOC_SH_GOTOFF20 1571@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1572@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1573@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1574@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1575@deffnx {} BFD_RELOC_SH_FUNCDESC 1576Renesas / SuperH SH relocs. Not all of these appear in object files. 1577@end deffn 1578@deffn {} BFD_RELOC_ARC_NONE 1579@deffnx {} BFD_RELOC_ARC_8 1580@deffnx {} BFD_RELOC_ARC_16 1581@deffnx {} BFD_RELOC_ARC_24 1582@deffnx {} BFD_RELOC_ARC_32 1583@deffnx {} BFD_RELOC_ARC_N8 1584@deffnx {} BFD_RELOC_ARC_N16 1585@deffnx {} BFD_RELOC_ARC_N24 1586@deffnx {} BFD_RELOC_ARC_N32 1587@deffnx {} BFD_RELOC_ARC_SDA 1588@deffnx {} BFD_RELOC_ARC_SECTOFF 1589@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1590@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1591@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1592@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1593@deffnx {} BFD_RELOC_ARC_SDA32 1594@deffnx {} BFD_RELOC_ARC_SDA_LDST 1595@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1596@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1597@deffnx {} BFD_RELOC_ARC_SDA16_LD 1598@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1599@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1600@deffnx {} BFD_RELOC_ARC_S13_PCREL 1601@deffnx {} BFD_RELOC_ARC_W 1602@deffnx {} BFD_RELOC_ARC_32_ME 1603@deffnx {} BFD_RELOC_ARC_32_ME_S 1604@deffnx {} BFD_RELOC_ARC_N32_ME 1605@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1606@deffnx {} BFD_RELOC_ARC_SDA32_ME 1607@deffnx {} BFD_RELOC_ARC_W_ME 1608@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1609@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1610@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1611@deffnx {} BFD_RELOC_AC_SECTOFF_S9 1612@deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1613@deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1614@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1615@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1616@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1617@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1618@deffnx {} BFD_RELOC_ARC_SDA_12 1619@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1620@deffnx {} BFD_RELOC_ARC_32_PCREL 1621@deffnx {} BFD_RELOC_ARC_PC32 1622@deffnx {} BFD_RELOC_ARC_GOT32 1623@deffnx {} BFD_RELOC_ARC_GOTPC32 1624@deffnx {} BFD_RELOC_ARC_PLT32 1625@deffnx {} BFD_RELOC_ARC_COPY 1626@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1627@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1628@deffnx {} BFD_RELOC_ARC_RELATIVE 1629@deffnx {} BFD_RELOC_ARC_GOTOFF 1630@deffnx {} BFD_RELOC_ARC_GOTPC 1631@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1632@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1633@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1634@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1635@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1636@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1637@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1638@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1639@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1640@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1641@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1642@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1643@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1644@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1645@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1646@deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1647ARC relocs. 1648@end deffn 1649@deffn {} BFD_RELOC_BFIN_16_IMM 1650ADI Blackfin 16 bit immediate absolute reloc. 1651@end deffn 1652@deffn {} BFD_RELOC_BFIN_16_HIGH 1653ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1654@end deffn 1655@deffn {} BFD_RELOC_BFIN_4_PCREL 1656ADI Blackfin 'a' part of LSETUP. 1657@end deffn 1658@deffn {} BFD_RELOC_BFIN_5_PCREL 1659ADI Blackfin. 1660@end deffn 1661@deffn {} BFD_RELOC_BFIN_16_LOW 1662ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1663@end deffn 1664@deffn {} BFD_RELOC_BFIN_10_PCREL 1665ADI Blackfin. 1666@end deffn 1667@deffn {} BFD_RELOC_BFIN_11_PCREL 1668ADI Blackfin 'b' part of LSETUP. 1669@end deffn 1670@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1671ADI Blackfin. 1672@end deffn 1673@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1674ADI Blackfin Short jump, pcrel. 1675@end deffn 1676@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1677ADI Blackfin Call.x not implemented. 1678@end deffn 1679@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1680ADI Blackfin Long Jump pcrel. 1681@end deffn 1682@deffn {} BFD_RELOC_BFIN_GOT17M4 1683@deffnx {} BFD_RELOC_BFIN_GOTHI 1684@deffnx {} BFD_RELOC_BFIN_GOTLO 1685@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1686@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1687@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1688@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1689@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1690@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1691@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1692@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1693@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1694@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1695@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1696ADI Blackfin FD-PIC relocations. 1697@end deffn 1698@deffn {} BFD_RELOC_BFIN_GOT 1699ADI Blackfin GOT relocation. 1700@end deffn 1701@deffn {} BFD_RELOC_BFIN_PLTPC 1702ADI Blackfin PLTPC relocation. 1703@end deffn 1704@deffn {} BFD_ARELOC_BFIN_PUSH 1705ADI Blackfin arithmetic relocation. 1706@end deffn 1707@deffn {} BFD_ARELOC_BFIN_CONST 1708ADI Blackfin arithmetic relocation. 1709@end deffn 1710@deffn {} BFD_ARELOC_BFIN_ADD 1711ADI Blackfin arithmetic relocation. 1712@end deffn 1713@deffn {} BFD_ARELOC_BFIN_SUB 1714ADI Blackfin arithmetic relocation. 1715@end deffn 1716@deffn {} BFD_ARELOC_BFIN_MULT 1717ADI Blackfin arithmetic relocation. 1718@end deffn 1719@deffn {} BFD_ARELOC_BFIN_DIV 1720ADI Blackfin arithmetic relocation. 1721@end deffn 1722@deffn {} BFD_ARELOC_BFIN_MOD 1723ADI Blackfin arithmetic relocation. 1724@end deffn 1725@deffn {} BFD_ARELOC_BFIN_LSHIFT 1726ADI Blackfin arithmetic relocation. 1727@end deffn 1728@deffn {} BFD_ARELOC_BFIN_RSHIFT 1729ADI Blackfin arithmetic relocation. 1730@end deffn 1731@deffn {} BFD_ARELOC_BFIN_AND 1732ADI Blackfin arithmetic relocation. 1733@end deffn 1734@deffn {} BFD_ARELOC_BFIN_OR 1735ADI Blackfin arithmetic relocation. 1736@end deffn 1737@deffn {} BFD_ARELOC_BFIN_XOR 1738ADI Blackfin arithmetic relocation. 1739@end deffn 1740@deffn {} BFD_ARELOC_BFIN_LAND 1741ADI Blackfin arithmetic relocation. 1742@end deffn 1743@deffn {} BFD_ARELOC_BFIN_LOR 1744ADI Blackfin arithmetic relocation. 1745@end deffn 1746@deffn {} BFD_ARELOC_BFIN_LEN 1747ADI Blackfin arithmetic relocation. 1748@end deffn 1749@deffn {} BFD_ARELOC_BFIN_NEG 1750ADI Blackfin arithmetic relocation. 1751@end deffn 1752@deffn {} BFD_ARELOC_BFIN_COMP 1753ADI Blackfin arithmetic relocation. 1754@end deffn 1755@deffn {} BFD_ARELOC_BFIN_PAGE 1756ADI Blackfin arithmetic relocation. 1757@end deffn 1758@deffn {} BFD_ARELOC_BFIN_HWPAGE 1759ADI Blackfin arithmetic relocation. 1760@end deffn 1761@deffn {} BFD_ARELOC_BFIN_ADDR 1762ADI Blackfin arithmetic relocation. 1763@end deffn 1764@deffn {} BFD_RELOC_D10V_10_PCREL_R 1765Mitsubishi D10V relocs. 1766This is a 10-bit reloc with the right 2 bits 1767assumed to be 0. 1768@end deffn 1769@deffn {} BFD_RELOC_D10V_10_PCREL_L 1770Mitsubishi D10V relocs. 1771This is a 10-bit reloc with the right 2 bits 1772assumed to be 0. This is the same as the previous reloc 1773except it is in the left container, i.e., 1774shifted left 15 bits. 1775@end deffn 1776@deffn {} BFD_RELOC_D10V_18 1777This is an 18-bit reloc with the right 2 bits 1778assumed to be 0. 1779@end deffn 1780@deffn {} BFD_RELOC_D10V_18_PCREL 1781This is an 18-bit reloc with the right 2 bits 1782assumed to be 0. 1783@end deffn 1784@deffn {} BFD_RELOC_D30V_6 1785Mitsubishi D30V relocs. 1786This is a 6-bit absolute reloc. 1787@end deffn 1788@deffn {} BFD_RELOC_D30V_9_PCREL 1789This is a 6-bit pc-relative reloc with 1790the right 3 bits assumed to be 0. 1791@end deffn 1792@deffn {} BFD_RELOC_D30V_9_PCREL_R 1793This is a 6-bit pc-relative reloc with 1794the right 3 bits assumed to be 0. Same 1795as the previous reloc but on the right side 1796of the container. 1797@end deffn 1798@deffn {} BFD_RELOC_D30V_15 1799This is a 12-bit absolute reloc with the 1800right 3 bitsassumed to be 0. 1801@end deffn 1802@deffn {} BFD_RELOC_D30V_15_PCREL 1803This is a 12-bit pc-relative reloc with 1804the right 3 bits assumed to be 0. 1805@end deffn 1806@deffn {} BFD_RELOC_D30V_15_PCREL_R 1807This is a 12-bit pc-relative reloc with 1808the right 3 bits assumed to be 0. Same 1809as the previous reloc but on the right side 1810of the container. 1811@end deffn 1812@deffn {} BFD_RELOC_D30V_21 1813This is an 18-bit absolute reloc with 1814the right 3 bits assumed to be 0. 1815@end deffn 1816@deffn {} BFD_RELOC_D30V_21_PCREL 1817This is an 18-bit pc-relative reloc with 1818the right 3 bits assumed to be 0. 1819@end deffn 1820@deffn {} BFD_RELOC_D30V_21_PCREL_R 1821This is an 18-bit pc-relative reloc with 1822the right 3 bits assumed to be 0. Same 1823as the previous reloc but on the right side 1824of the container. 1825@end deffn 1826@deffn {} BFD_RELOC_D30V_32 1827This is a 32-bit absolute reloc. 1828@end deffn 1829@deffn {} BFD_RELOC_D30V_32_PCREL 1830This is a 32-bit pc-relative reloc. 1831@end deffn 1832@deffn {} BFD_RELOC_DLX_HI16_S 1833DLX relocs 1834@end deffn 1835@deffn {} BFD_RELOC_DLX_LO16 1836DLX relocs 1837@end deffn 1838@deffn {} BFD_RELOC_DLX_JMP26 1839DLX relocs 1840@end deffn 1841@deffn {} BFD_RELOC_M32C_HI8 1842@deffnx {} BFD_RELOC_M32C_RL_JUMP 1843@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1844@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1845Renesas M16C/M32C Relocations. 1846@end deffn 1847@deffn {} BFD_RELOC_M32R_24 1848Renesas M32R (formerly Mitsubishi M32R) relocs. 1849This is a 24 bit absolute address. 1850@end deffn 1851@deffn {} BFD_RELOC_M32R_10_PCREL 1852This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1853@end deffn 1854@deffn {} BFD_RELOC_M32R_18_PCREL 1855This is an 18-bit reloc with the right 2 bits assumed to be 0. 1856@end deffn 1857@deffn {} BFD_RELOC_M32R_26_PCREL 1858This is a 26-bit reloc with the right 2 bits assumed to be 0. 1859@end deffn 1860@deffn {} BFD_RELOC_M32R_HI16_ULO 1861This is a 16-bit reloc containing the high 16 bits of an address 1862used when the lower 16 bits are treated as unsigned. 1863@end deffn 1864@deffn {} BFD_RELOC_M32R_HI16_SLO 1865This is a 16-bit reloc containing the high 16 bits of an address 1866used when the lower 16 bits are treated as signed. 1867@end deffn 1868@deffn {} BFD_RELOC_M32R_LO16 1869This is a 16-bit reloc containing the lower 16 bits of an address. 1870@end deffn 1871@deffn {} BFD_RELOC_M32R_SDA16 1872This is a 16-bit reloc containing the small data area offset for use in 1873add3, load, and store instructions. 1874@end deffn 1875@deffn {} BFD_RELOC_M32R_GOT24 1876@deffnx {} BFD_RELOC_M32R_26_PLTREL 1877@deffnx {} BFD_RELOC_M32R_COPY 1878@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1879@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1880@deffnx {} BFD_RELOC_M32R_RELATIVE 1881@deffnx {} BFD_RELOC_M32R_GOTOFF 1882@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1883@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1884@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1885@deffnx {} BFD_RELOC_M32R_GOTPC24 1886@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1887@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1888@deffnx {} BFD_RELOC_M32R_GOT16_LO 1889@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1890@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1891@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1892For PIC. 1893@end deffn 1894@deffn {} BFD_RELOC_NDS32_20 1895NDS32 relocs. 1896This is a 20 bit absolute address. 1897@end deffn 1898@deffn {} BFD_RELOC_NDS32_9_PCREL 1899This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1900@end deffn 1901@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1902This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1903@end deffn 1904@deffn {} BFD_RELOC_NDS32_15_PCREL 1905This is an 15-bit reloc with the right 1 bit assumed to be 0. 1906@end deffn 1907@deffn {} BFD_RELOC_NDS32_17_PCREL 1908This is an 17-bit reloc with the right 1 bit assumed to be 0. 1909@end deffn 1910@deffn {} BFD_RELOC_NDS32_25_PCREL 1911This is a 25-bit reloc with the right 1 bit assumed to be 0. 1912@end deffn 1913@deffn {} BFD_RELOC_NDS32_HI20 1914This is a 20-bit reloc containing the high 20 bits of an address 1915used with the lower 12 bits 1916@end deffn 1917@deffn {} BFD_RELOC_NDS32_LO12S3 1918This is a 12-bit reloc containing the lower 12 bits of an address 1919then shift right by 3. This is used with ldi,sdi... 1920@end deffn 1921@deffn {} BFD_RELOC_NDS32_LO12S2 1922This is a 12-bit reloc containing the lower 12 bits of an address 1923then shift left by 2. This is used with lwi,swi... 1924@end deffn 1925@deffn {} BFD_RELOC_NDS32_LO12S1 1926This is a 12-bit reloc containing the lower 12 bits of an address 1927then shift left by 1. This is used with lhi,shi... 1928@end deffn 1929@deffn {} BFD_RELOC_NDS32_LO12S0 1930This is a 12-bit reloc containing the lower 12 bits of an address 1931then shift left by 0. This is used with lbisbi... 1932@end deffn 1933@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1934This is a 12-bit reloc containing the lower 12 bits of an address 1935then shift left by 0. This is only used with branch relaxations 1936@end deffn 1937@deffn {} BFD_RELOC_NDS32_SDA15S3 1938This is a 15-bit reloc containing the small data area 18-bit signed offset 1939and shift left by 3 for use in ldi, sdi... 1940@end deffn 1941@deffn {} BFD_RELOC_NDS32_SDA15S2 1942This is a 15-bit reloc containing the small data area 17-bit signed offset 1943and shift left by 2 for use in lwi, swi... 1944@end deffn 1945@deffn {} BFD_RELOC_NDS32_SDA15S1 1946This is a 15-bit reloc containing the small data area 16-bit signed offset 1947and shift left by 1 for use in lhi, shi... 1948@end deffn 1949@deffn {} BFD_RELOC_NDS32_SDA15S0 1950This is a 15-bit reloc containing the small data area 15-bit signed offset 1951and shift left by 0 for use in lbi, sbi... 1952@end deffn 1953@deffn {} BFD_RELOC_NDS32_SDA16S3 1954This is a 16-bit reloc containing the small data area 16-bit signed offset 1955and shift left by 3 1956@end deffn 1957@deffn {} BFD_RELOC_NDS32_SDA17S2 1958This is a 17-bit reloc containing the small data area 17-bit signed offset 1959and shift left by 2 for use in lwi.gp, swi.gp... 1960@end deffn 1961@deffn {} BFD_RELOC_NDS32_SDA18S1 1962This is a 18-bit reloc containing the small data area 18-bit signed offset 1963and shift left by 1 for use in lhi.gp, shi.gp... 1964@end deffn 1965@deffn {} BFD_RELOC_NDS32_SDA19S0 1966This is a 19-bit reloc containing the small data area 19-bit signed offset 1967and shift left by 0 for use in lbi.gp, sbi.gp... 1968@end deffn 1969@deffn {} BFD_RELOC_NDS32_GOT20 1970@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1971@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1972@deffnx {} BFD_RELOC_NDS32_COPY 1973@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1974@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1975@deffnx {} BFD_RELOC_NDS32_RELATIVE 1976@deffnx {} BFD_RELOC_NDS32_GOTOFF 1977@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1978@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1979@deffnx {} BFD_RELOC_NDS32_GOTPC20 1980@deffnx {} BFD_RELOC_NDS32_GOT_HI20 1981@deffnx {} BFD_RELOC_NDS32_GOT_LO12 1982@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1983@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1984for PIC 1985@end deffn 1986@deffn {} BFD_RELOC_NDS32_INSN16 1987@deffnx {} BFD_RELOC_NDS32_LABEL 1988@deffnx {} BFD_RELOC_NDS32_LONGCALL1 1989@deffnx {} BFD_RELOC_NDS32_LONGCALL2 1990@deffnx {} BFD_RELOC_NDS32_LONGCALL3 1991@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1992@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1993@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1994@deffnx {} BFD_RELOC_NDS32_LOADSTORE 1995@deffnx {} BFD_RELOC_NDS32_9_FIXED 1996@deffnx {} BFD_RELOC_NDS32_15_FIXED 1997@deffnx {} BFD_RELOC_NDS32_17_FIXED 1998@deffnx {} BFD_RELOC_NDS32_25_FIXED 1999@deffnx {} BFD_RELOC_NDS32_LONGCALL4 2000@deffnx {} BFD_RELOC_NDS32_LONGCALL5 2001@deffnx {} BFD_RELOC_NDS32_LONGCALL6 2002@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 2003@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 2004@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 2005@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 2006for relax 2007@end deffn 2008@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 2009@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 2010@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 2011@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 2012for PIC 2013@end deffn 2014@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 2015@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 2016@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 2017@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 2018for floating point 2019@end deffn 2020@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 2021@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 2022@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 2023for dwarf2 debug_line. 2024@end deffn 2025@deffn {} BFD_RELOC_NDS32_UPDATE_TA 2026for eliminate 16-bit instructions 2027@end deffn 2028@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2029@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2030@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2031@deffnx {} BFD_RELOC_NDS32_GOT_LO15 2032@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2033@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2034@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2035@deffnx {} BFD_RELOC_NDS32_GOT15S2 2036@deffnx {} BFD_RELOC_NDS32_GOT17S2 2037for PIC object relaxation 2038@end deffn 2039@deffn {} BFD_RELOC_NDS32_5 2040NDS32 relocs. 2041This is a 5 bit absolute address. 2042@end deffn 2043@deffn {} BFD_RELOC_NDS32_10_UPCREL 2044This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2045@end deffn 2046@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2047If fp were omitted, fp can used as another gp. 2048@end deffn 2049@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2050@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2051@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2052@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2053@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2054@deffnx {} BFD_RELOC_NDS32_PTR 2055@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2056@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2057@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2058@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2059@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2060@deffnx {} BFD_RELOC_NDS32_MINUEND 2061@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2062@deffnx {} BFD_RELOC_NDS32_DIFF8 2063@deffnx {} BFD_RELOC_NDS32_DIFF16 2064@deffnx {} BFD_RELOC_NDS32_DIFF32 2065@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2066@deffnx {} BFD_RELOC_NDS32_EMPTY 2067relaxation relative relocation types 2068@end deffn 2069@deffn {} BFD_RELOC_NDS32_25_ABS 2070This is a 25 bit absolute address. 2071@end deffn 2072@deffn {} BFD_RELOC_NDS32_DATA 2073@deffnx {} BFD_RELOC_NDS32_TRAN 2074@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2075@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2076For ex9 and ifc using. 2077@end deffn 2078@deffn {} BFD_RELOC_NDS32_TPOFF 2079@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2080@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2081@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2082@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2083@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2084@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2085@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2086@deffnx {} BFD_RELOC_NDS32_TLS_TPOFF 2087@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2088@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2089@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2090@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2091For TLS. 2092@end deffn 2093@deffn {} BFD_RELOC_V850_9_PCREL 2094This is a 9-bit reloc 2095@end deffn 2096@deffn {} BFD_RELOC_V850_22_PCREL 2097This is a 22-bit reloc 2098@end deffn 2099@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2100This is a 16 bit offset from the short data area pointer. 2101@end deffn 2102@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2103This is a 16 bit offset (of which only 15 bits are used) from the 2104short data area pointer. 2105@end deffn 2106@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2107This is a 16 bit offset from the zero data area pointer. 2108@end deffn 2109@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2110This is a 16 bit offset (of which only 15 bits are used) from the 2111zero data area pointer. 2112@end deffn 2113@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2114This is an 8 bit offset (of which only 6 bits are used) from the 2115tiny data area pointer. 2116@end deffn 2117@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2118This is an 8bit offset (of which only 7 bits are used) from the tiny 2119data area pointer. 2120@end deffn 2121@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2122This is a 7 bit offset from the tiny data area pointer. 2123@end deffn 2124@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2125This is a 16 bit offset from the tiny data area pointer. 2126@end deffn 2127@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2128This is a 5 bit offset (of which only 4 bits are used) from the tiny 2129data area pointer. 2130@end deffn 2131@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2132This is a 4 bit offset from the tiny data area pointer. 2133@end deffn 2134@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2135This is a 16 bit offset from the short data area pointer, with the 2136bits placed non-contiguously in the instruction. 2137@end deffn 2138@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2139This is a 16 bit offset from the zero data area pointer, with the 2140bits placed non-contiguously in the instruction. 2141@end deffn 2142@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2143This is a 6 bit offset from the call table base pointer. 2144@end deffn 2145@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2146This is a 16 bit offset from the call table base pointer. 2147@end deffn 2148@deffn {} BFD_RELOC_V850_LONGCALL 2149Used for relaxing indirect function calls. 2150@end deffn 2151@deffn {} BFD_RELOC_V850_LONGJUMP 2152Used for relaxing indirect jumps. 2153@end deffn 2154@deffn {} BFD_RELOC_V850_ALIGN 2155Used to maintain alignment whilst relaxing. 2156@end deffn 2157@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2158This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2159instructions. 2160@end deffn 2161@deffn {} BFD_RELOC_V850_16_PCREL 2162This is a 16-bit reloc. 2163@end deffn 2164@deffn {} BFD_RELOC_V850_17_PCREL 2165This is a 17-bit reloc. 2166@end deffn 2167@deffn {} BFD_RELOC_V850_23 2168This is a 23-bit reloc. 2169@end deffn 2170@deffn {} BFD_RELOC_V850_32_PCREL 2171This is a 32-bit reloc. 2172@end deffn 2173@deffn {} BFD_RELOC_V850_32_ABS 2174This is a 32-bit reloc. 2175@end deffn 2176@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2177This is a 16-bit reloc. 2178@end deffn 2179@deffn {} BFD_RELOC_V850_16_S1 2180This is a 16-bit reloc. 2181@end deffn 2182@deffn {} BFD_RELOC_V850_LO16_S1 2183Low 16 bits. 16 bit shifted by 1. 2184@end deffn 2185@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2186This is a 16 bit offset from the call table base pointer. 2187@end deffn 2188@deffn {} BFD_RELOC_V850_32_GOTPCREL 2189DSO relocations. 2190@end deffn 2191@deffn {} BFD_RELOC_V850_16_GOT 2192DSO relocations. 2193@end deffn 2194@deffn {} BFD_RELOC_V850_32_GOT 2195DSO relocations. 2196@end deffn 2197@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2198DSO relocations. 2199@end deffn 2200@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2201DSO relocations. 2202@end deffn 2203@deffn {} BFD_RELOC_V850_COPY 2204DSO relocations. 2205@end deffn 2206@deffn {} BFD_RELOC_V850_GLOB_DAT 2207DSO relocations. 2208@end deffn 2209@deffn {} BFD_RELOC_V850_JMP_SLOT 2210DSO relocations. 2211@end deffn 2212@deffn {} BFD_RELOC_V850_RELATIVE 2213DSO relocations. 2214@end deffn 2215@deffn {} BFD_RELOC_V850_16_GOTOFF 2216DSO relocations. 2217@end deffn 2218@deffn {} BFD_RELOC_V850_32_GOTOFF 2219DSO relocations. 2220@end deffn 2221@deffn {} BFD_RELOC_V850_CODE 2222start code. 2223@end deffn 2224@deffn {} BFD_RELOC_V850_DATA 2225start data in text. 2226@end deffn 2227@deffn {} BFD_RELOC_TIC30_LDP 2228This is a 8bit DP reloc for the tms320c30, where the most 2229significant 8 bits of a 24 bit word are placed into the least 2230significant 8 bits of the opcode. 2231@end deffn 2232@deffn {} BFD_RELOC_TIC54X_PARTLS7 2233This is a 7bit reloc for the tms320c54x, where the least 2234significant 7 bits of a 16 bit word are placed into the least 2235significant 7 bits of the opcode. 2236@end deffn 2237@deffn {} BFD_RELOC_TIC54X_PARTMS9 2238This is a 9bit DP reloc for the tms320c54x, where the most 2239significant 9 bits of a 16 bit word are placed into the least 2240significant 9 bits of the opcode. 2241@end deffn 2242@deffn {} BFD_RELOC_TIC54X_23 2243This is an extended address 23-bit reloc for the tms320c54x. 2244@end deffn 2245@deffn {} BFD_RELOC_TIC54X_16_OF_23 2246This is a 16-bit reloc for the tms320c54x, where the least 2247significant 16 bits of a 23-bit extended address are placed into 2248the opcode. 2249@end deffn 2250@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2251This is a reloc for the tms320c54x, where the most 2252significant 7 bits of a 23-bit extended address are placed into 2253the opcode. 2254@end deffn 2255@deffn {} BFD_RELOC_C6000_PCR_S21 2256@deffnx {} BFD_RELOC_C6000_PCR_S12 2257@deffnx {} BFD_RELOC_C6000_PCR_S10 2258@deffnx {} BFD_RELOC_C6000_PCR_S7 2259@deffnx {} BFD_RELOC_C6000_ABS_S16 2260@deffnx {} BFD_RELOC_C6000_ABS_L16 2261@deffnx {} BFD_RELOC_C6000_ABS_H16 2262@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2263@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2264@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2265@deffnx {} BFD_RELOC_C6000_SBR_S16 2266@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2267@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2268@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2269@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2270@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2271@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2272@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2273@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2274@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2275@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2276@deffnx {} BFD_RELOC_C6000_PREL31 2277@deffnx {} BFD_RELOC_C6000_COPY 2278@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2279@deffnx {} BFD_RELOC_C6000_EHTYPE 2280@deffnx {} BFD_RELOC_C6000_PCR_H16 2281@deffnx {} BFD_RELOC_C6000_PCR_L16 2282@deffnx {} BFD_RELOC_C6000_ALIGN 2283@deffnx {} BFD_RELOC_C6000_FPHEAD 2284@deffnx {} BFD_RELOC_C6000_NOCMP 2285TMS320C6000 relocations. 2286@end deffn 2287@deffn {} BFD_RELOC_FR30_48 2288This is a 48 bit reloc for the FR30 that stores 32 bits. 2289@end deffn 2290@deffn {} BFD_RELOC_FR30_20 2291This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2292two sections. 2293@end deffn 2294@deffn {} BFD_RELOC_FR30_6_IN_4 2295This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 22964 bits. 2297@end deffn 2298@deffn {} BFD_RELOC_FR30_8_IN_8 2299This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2300into 8 bits. 2301@end deffn 2302@deffn {} BFD_RELOC_FR30_9_IN_8 2303This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2304into 8 bits. 2305@end deffn 2306@deffn {} BFD_RELOC_FR30_10_IN_8 2307This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2308into 8 bits. 2309@end deffn 2310@deffn {} BFD_RELOC_FR30_9_PCREL 2311This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2312short offset into 8 bits. 2313@end deffn 2314@deffn {} BFD_RELOC_FR30_12_PCREL 2315This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2316short offset into 11 bits. 2317@end deffn 2318@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2319@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2320@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2321@deffnx {} BFD_RELOC_MCORE_PCREL_32 2322@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2323@deffnx {} BFD_RELOC_MCORE_RVA 2324Motorola Mcore relocations. 2325@end deffn 2326@deffn {} BFD_RELOC_MEP_8 2327@deffnx {} BFD_RELOC_MEP_16 2328@deffnx {} BFD_RELOC_MEP_32 2329@deffnx {} BFD_RELOC_MEP_PCREL8A2 2330@deffnx {} BFD_RELOC_MEP_PCREL12A2 2331@deffnx {} BFD_RELOC_MEP_PCREL17A2 2332@deffnx {} BFD_RELOC_MEP_PCREL24A2 2333@deffnx {} BFD_RELOC_MEP_PCABS24A2 2334@deffnx {} BFD_RELOC_MEP_LOW16 2335@deffnx {} BFD_RELOC_MEP_HI16U 2336@deffnx {} BFD_RELOC_MEP_HI16S 2337@deffnx {} BFD_RELOC_MEP_GPREL 2338@deffnx {} BFD_RELOC_MEP_TPREL 2339@deffnx {} BFD_RELOC_MEP_TPREL7 2340@deffnx {} BFD_RELOC_MEP_TPREL7A2 2341@deffnx {} BFD_RELOC_MEP_TPREL7A4 2342@deffnx {} BFD_RELOC_MEP_UIMM24 2343@deffnx {} BFD_RELOC_MEP_ADDR24A4 2344@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2345@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2346Toshiba Media Processor Relocations. 2347@end deffn 2348@deffn {} BFD_RELOC_METAG_HIADDR16 2349@deffnx {} BFD_RELOC_METAG_LOADDR16 2350@deffnx {} BFD_RELOC_METAG_RELBRANCH 2351@deffnx {} BFD_RELOC_METAG_GETSETOFF 2352@deffnx {} BFD_RELOC_METAG_HIOG 2353@deffnx {} BFD_RELOC_METAG_LOOG 2354@deffnx {} BFD_RELOC_METAG_REL8 2355@deffnx {} BFD_RELOC_METAG_REL16 2356@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2357@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2358@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2359@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2360@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2361@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2362@deffnx {} BFD_RELOC_METAG_HI16_PLT 2363@deffnx {} BFD_RELOC_METAG_LO16_PLT 2364@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2365@deffnx {} BFD_RELOC_METAG_GOTOFF 2366@deffnx {} BFD_RELOC_METAG_PLT 2367@deffnx {} BFD_RELOC_METAG_COPY 2368@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2369@deffnx {} BFD_RELOC_METAG_RELATIVE 2370@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2371@deffnx {} BFD_RELOC_METAG_TLS_GD 2372@deffnx {} BFD_RELOC_METAG_TLS_LDM 2373@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2374@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2375@deffnx {} BFD_RELOC_METAG_TLS_LDO 2376@deffnx {} BFD_RELOC_METAG_TLS_IE 2377@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2378@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2379@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2380@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2381@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2382@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2383@deffnx {} BFD_RELOC_METAG_TLS_LE 2384@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2385@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2386Imagination Technologies Meta relocations. 2387@end deffn 2388@deffn {} BFD_RELOC_MMIX_GETA 2389@deffnx {} BFD_RELOC_MMIX_GETA_1 2390@deffnx {} BFD_RELOC_MMIX_GETA_2 2391@deffnx {} BFD_RELOC_MMIX_GETA_3 2392These are relocations for the GETA instruction. 2393@end deffn 2394@deffn {} BFD_RELOC_MMIX_CBRANCH 2395@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2396@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2397@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2398@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2399These are relocations for a conditional branch instruction. 2400@end deffn 2401@deffn {} BFD_RELOC_MMIX_PUSHJ 2402@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2403@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2404@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2405@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2406These are relocations for the PUSHJ instruction. 2407@end deffn 2408@deffn {} BFD_RELOC_MMIX_JMP 2409@deffnx {} BFD_RELOC_MMIX_JMP_1 2410@deffnx {} BFD_RELOC_MMIX_JMP_2 2411@deffnx {} BFD_RELOC_MMIX_JMP_3 2412These are relocations for the JMP instruction. 2413@end deffn 2414@deffn {} BFD_RELOC_MMIX_ADDR19 2415This is a relocation for a relative address as in a GETA instruction or 2416a branch. 2417@end deffn 2418@deffn {} BFD_RELOC_MMIX_ADDR27 2419This is a relocation for a relative address as in a JMP instruction. 2420@end deffn 2421@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2422This is a relocation for an instruction field that may be a general 2423register or a value 0..255. 2424@end deffn 2425@deffn {} BFD_RELOC_MMIX_REG 2426This is a relocation for an instruction field that may be a general 2427register. 2428@end deffn 2429@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2430This is a relocation for two instruction fields holding a register and 2431an offset, the equivalent of the relocation. 2432@end deffn 2433@deffn {} BFD_RELOC_MMIX_LOCAL 2434This relocation is an assertion that the expression is not allocated as 2435a global register. It does not modify contents. 2436@end deffn 2437@deffn {} BFD_RELOC_AVR_7_PCREL 2438This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2439short offset into 7 bits. 2440@end deffn 2441@deffn {} BFD_RELOC_AVR_13_PCREL 2442This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2443short offset into 12 bits. 2444@end deffn 2445@deffn {} BFD_RELOC_AVR_16_PM 2446This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2447program memory address) into 16 bits. 2448@end deffn 2449@deffn {} BFD_RELOC_AVR_LO8_LDI 2450This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2451data memory address) into 8 bit immediate value of LDI insn. 2452@end deffn 2453@deffn {} BFD_RELOC_AVR_HI8_LDI 2454This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2455of data memory address) into 8 bit immediate value of LDI insn. 2456@end deffn 2457@deffn {} BFD_RELOC_AVR_HH8_LDI 2458This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2459of program memory address) into 8 bit immediate value of LDI insn. 2460@end deffn 2461@deffn {} BFD_RELOC_AVR_MS8_LDI 2462This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2463of 32 bit value) into 8 bit immediate value of LDI insn. 2464@end deffn 2465@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2466This is a 16 bit reloc for the AVR that stores negated 8 bit value 2467(usually data memory address) into 8 bit immediate value of SUBI insn. 2468@end deffn 2469@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2470This is a 16 bit reloc for the AVR that stores negated 8 bit value 2471(high 8 bit of data memory address) into 8 bit immediate value of 2472SUBI insn. 2473@end deffn 2474@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2475This is a 16 bit reloc for the AVR that stores negated 8 bit value 2476(most high 8 bit of program memory address) into 8 bit immediate value 2477of LDI or SUBI insn. 2478@end deffn 2479@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2480This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2481of 32 bit value) into 8 bit immediate value of LDI insn. 2482@end deffn 2483@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2484This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2485command address) into 8 bit immediate value of LDI insn. 2486@end deffn 2487@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2488This is a 16 bit reloc for the AVR that stores 8 bit value 2489(command address) into 8 bit immediate value of LDI insn. If the address 2490is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2491in the lower 128k. 2492@end deffn 2493@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2494This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2495of command address) into 8 bit immediate value of LDI insn. 2496@end deffn 2497@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2498This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2499of command address) into 8 bit immediate value of LDI insn. If the address 2500is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2501below 128k. 2502@end deffn 2503@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2504This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2505of command address) into 8 bit immediate value of LDI insn. 2506@end deffn 2507@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2508This is a 16 bit reloc for the AVR that stores negated 8 bit value 2509(usually command address) into 8 bit immediate value of SUBI insn. 2510@end deffn 2511@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2512This is a 16 bit reloc for the AVR that stores negated 8 bit value 2513(high 8 bit of 16 bit command address) into 8 bit immediate value 2514of SUBI insn. 2515@end deffn 2516@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2517This is a 16 bit reloc for the AVR that stores negated 8 bit value 2518(high 6 bit of 22 bit command address) into 8 bit immediate 2519value of SUBI insn. 2520@end deffn 2521@deffn {} BFD_RELOC_AVR_CALL 2522This is a 32 bit reloc for the AVR that stores 23 bit value 2523into 22 bits. 2524@end deffn 2525@deffn {} BFD_RELOC_AVR_LDI 2526This is a 16 bit reloc for the AVR that stores all needed bits 2527for absolute addressing with ldi with overflow check to linktime 2528@end deffn 2529@deffn {} BFD_RELOC_AVR_6 2530This is a 6 bit reloc for the AVR that stores offset for ldd/std 2531instructions 2532@end deffn 2533@deffn {} BFD_RELOC_AVR_6_ADIW 2534This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2535instructions 2536@end deffn 2537@deffn {} BFD_RELOC_AVR_8_LO 2538This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2539in .byte lo8(symbol) 2540@end deffn 2541@deffn {} BFD_RELOC_AVR_8_HI 2542This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2543in .byte hi8(symbol) 2544@end deffn 2545@deffn {} BFD_RELOC_AVR_8_HLO 2546This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2547in .byte hlo8(symbol) 2548@end deffn 2549@deffn {} BFD_RELOC_AVR_DIFF8 2550@deffnx {} BFD_RELOC_AVR_DIFF16 2551@deffnx {} BFD_RELOC_AVR_DIFF32 2552AVR relocations to mark the difference of two local symbols. 2553These are only needed to support linker relaxation and can be ignored 2554when not relaxing. The field is set to the value of the difference 2555assuming no relaxation. The relocation encodes the position of the 2556second symbol so the linker can determine whether to adjust the field 2557value. 2558@end deffn 2559@deffn {} BFD_RELOC_AVR_LDS_STS_16 2560This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2561lds and sts instructions supported only tiny core. 2562@end deffn 2563@deffn {} BFD_RELOC_AVR_PORT6 2564This is a 6 bit reloc for the AVR that stores an I/O register 2565number for the IN and OUT instructions 2566@end deffn 2567@deffn {} BFD_RELOC_AVR_PORT5 2568This is a 5 bit reloc for the AVR that stores an I/O register 2569number for the SBIC, SBIS, SBI and CBI instructions 2570@end deffn 2571@deffn {} BFD_RELOC_RISCV_HI20 2572@deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2573@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2574@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2575@deffnx {} BFD_RELOC_RISCV_LO12_I 2576@deffnx {} BFD_RELOC_RISCV_LO12_S 2577@deffnx {} BFD_RELOC_RISCV_GPREL12_I 2578@deffnx {} BFD_RELOC_RISCV_GPREL12_S 2579@deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2580@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2581@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2582@deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2583@deffnx {} BFD_RELOC_RISCV_CALL 2584@deffnx {} BFD_RELOC_RISCV_CALL_PLT 2585@deffnx {} BFD_RELOC_RISCV_ADD8 2586@deffnx {} BFD_RELOC_RISCV_ADD16 2587@deffnx {} BFD_RELOC_RISCV_ADD32 2588@deffnx {} BFD_RELOC_RISCV_ADD64 2589@deffnx {} BFD_RELOC_RISCV_SUB8 2590@deffnx {} BFD_RELOC_RISCV_SUB16 2591@deffnx {} BFD_RELOC_RISCV_SUB32 2592@deffnx {} BFD_RELOC_RISCV_SUB64 2593@deffnx {} BFD_RELOC_RISCV_GOT_HI20 2594@deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2595@deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2596@deffnx {} BFD_RELOC_RISCV_JMP 2597@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2598@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2599@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2600@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2601@deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2602@deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2603@deffnx {} BFD_RELOC_RISCV_ALIGN 2604@deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2605@deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2606@deffnx {} BFD_RELOC_RISCV_RVC_LUI 2607@deffnx {} BFD_RELOC_RISCV_GPREL_I 2608@deffnx {} BFD_RELOC_RISCV_GPREL_S 2609@deffnx {} BFD_RELOC_RISCV_TPREL_I 2610@deffnx {} BFD_RELOC_RISCV_TPREL_S 2611@deffnx {} BFD_RELOC_RISCV_RELAX 2612@deffnx {} BFD_RELOC_RISCV_CFA 2613@deffnx {} BFD_RELOC_RISCV_SUB6 2614@deffnx {} BFD_RELOC_RISCV_SET6 2615@deffnx {} BFD_RELOC_RISCV_SET8 2616@deffnx {} BFD_RELOC_RISCV_SET16 2617@deffnx {} BFD_RELOC_RISCV_SET32 2618@deffnx {} BFD_RELOC_RISCV_32_PCREL 2619RISC-V relocations. 2620@end deffn 2621@deffn {} BFD_RELOC_RL78_NEG8 2622@deffnx {} BFD_RELOC_RL78_NEG16 2623@deffnx {} BFD_RELOC_RL78_NEG24 2624@deffnx {} BFD_RELOC_RL78_NEG32 2625@deffnx {} BFD_RELOC_RL78_16_OP 2626@deffnx {} BFD_RELOC_RL78_24_OP 2627@deffnx {} BFD_RELOC_RL78_32_OP 2628@deffnx {} BFD_RELOC_RL78_8U 2629@deffnx {} BFD_RELOC_RL78_16U 2630@deffnx {} BFD_RELOC_RL78_24U 2631@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2632@deffnx {} BFD_RELOC_RL78_DIFF 2633@deffnx {} BFD_RELOC_RL78_GPRELB 2634@deffnx {} BFD_RELOC_RL78_GPRELW 2635@deffnx {} BFD_RELOC_RL78_GPRELL 2636@deffnx {} BFD_RELOC_RL78_SYM 2637@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2638@deffnx {} BFD_RELOC_RL78_OP_NEG 2639@deffnx {} BFD_RELOC_RL78_OP_AND 2640@deffnx {} BFD_RELOC_RL78_OP_SHRA 2641@deffnx {} BFD_RELOC_RL78_ABS8 2642@deffnx {} BFD_RELOC_RL78_ABS16 2643@deffnx {} BFD_RELOC_RL78_ABS16_REV 2644@deffnx {} BFD_RELOC_RL78_ABS32 2645@deffnx {} BFD_RELOC_RL78_ABS32_REV 2646@deffnx {} BFD_RELOC_RL78_ABS16U 2647@deffnx {} BFD_RELOC_RL78_ABS16UW 2648@deffnx {} BFD_RELOC_RL78_ABS16UL 2649@deffnx {} BFD_RELOC_RL78_RELAX 2650@deffnx {} BFD_RELOC_RL78_HI16 2651@deffnx {} BFD_RELOC_RL78_HI8 2652@deffnx {} BFD_RELOC_RL78_LO16 2653@deffnx {} BFD_RELOC_RL78_CODE 2654@deffnx {} BFD_RELOC_RL78_SADDR 2655Renesas RL78 Relocations. 2656@end deffn 2657@deffn {} BFD_RELOC_RX_NEG8 2658@deffnx {} BFD_RELOC_RX_NEG16 2659@deffnx {} BFD_RELOC_RX_NEG24 2660@deffnx {} BFD_RELOC_RX_NEG32 2661@deffnx {} BFD_RELOC_RX_16_OP 2662@deffnx {} BFD_RELOC_RX_24_OP 2663@deffnx {} BFD_RELOC_RX_32_OP 2664@deffnx {} BFD_RELOC_RX_8U 2665@deffnx {} BFD_RELOC_RX_16U 2666@deffnx {} BFD_RELOC_RX_24U 2667@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2668@deffnx {} BFD_RELOC_RX_DIFF 2669@deffnx {} BFD_RELOC_RX_GPRELB 2670@deffnx {} BFD_RELOC_RX_GPRELW 2671@deffnx {} BFD_RELOC_RX_GPRELL 2672@deffnx {} BFD_RELOC_RX_SYM 2673@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2674@deffnx {} BFD_RELOC_RX_OP_NEG 2675@deffnx {} BFD_RELOC_RX_ABS8 2676@deffnx {} BFD_RELOC_RX_ABS16 2677@deffnx {} BFD_RELOC_RX_ABS16_REV 2678@deffnx {} BFD_RELOC_RX_ABS32 2679@deffnx {} BFD_RELOC_RX_ABS32_REV 2680@deffnx {} BFD_RELOC_RX_ABS16U 2681@deffnx {} BFD_RELOC_RX_ABS16UW 2682@deffnx {} BFD_RELOC_RX_ABS16UL 2683@deffnx {} BFD_RELOC_RX_RELAX 2684Renesas RX Relocations. 2685@end deffn 2686@deffn {} BFD_RELOC_390_12 2687Direct 12 bit. 2688@end deffn 2689@deffn {} BFD_RELOC_390_GOT12 269012 bit GOT offset. 2691@end deffn 2692@deffn {} BFD_RELOC_390_PLT32 269332 bit PC relative PLT address. 2694@end deffn 2695@deffn {} BFD_RELOC_390_COPY 2696Copy symbol at runtime. 2697@end deffn 2698@deffn {} BFD_RELOC_390_GLOB_DAT 2699Create GOT entry. 2700@end deffn 2701@deffn {} BFD_RELOC_390_JMP_SLOT 2702Create PLT entry. 2703@end deffn 2704@deffn {} BFD_RELOC_390_RELATIVE 2705Adjust by program base. 2706@end deffn 2707@deffn {} BFD_RELOC_390_GOTPC 270832 bit PC relative offset to GOT. 2709@end deffn 2710@deffn {} BFD_RELOC_390_GOT16 271116 bit GOT offset. 2712@end deffn 2713@deffn {} BFD_RELOC_390_PC12DBL 2714PC relative 12 bit shifted by 1. 2715@end deffn 2716@deffn {} BFD_RELOC_390_PLT12DBL 271712 bit PC rel. PLT shifted by 1. 2718@end deffn 2719@deffn {} BFD_RELOC_390_PC16DBL 2720PC relative 16 bit shifted by 1. 2721@end deffn 2722@deffn {} BFD_RELOC_390_PLT16DBL 272316 bit PC rel. PLT shifted by 1. 2724@end deffn 2725@deffn {} BFD_RELOC_390_PC24DBL 2726PC relative 24 bit shifted by 1. 2727@end deffn 2728@deffn {} BFD_RELOC_390_PLT24DBL 272924 bit PC rel. PLT shifted by 1. 2730@end deffn 2731@deffn {} BFD_RELOC_390_PC32DBL 2732PC relative 32 bit shifted by 1. 2733@end deffn 2734@deffn {} BFD_RELOC_390_PLT32DBL 273532 bit PC rel. PLT shifted by 1. 2736@end deffn 2737@deffn {} BFD_RELOC_390_GOTPCDBL 273832 bit PC rel. GOT shifted by 1. 2739@end deffn 2740@deffn {} BFD_RELOC_390_GOT64 274164 bit GOT offset. 2742@end deffn 2743@deffn {} BFD_RELOC_390_PLT64 274464 bit PC relative PLT address. 2745@end deffn 2746@deffn {} BFD_RELOC_390_GOTENT 274732 bit rel. offset to GOT entry. 2748@end deffn 2749@deffn {} BFD_RELOC_390_GOTOFF64 275064 bit offset to GOT. 2751@end deffn 2752@deffn {} BFD_RELOC_390_GOTPLT12 275312-bit offset to symbol-entry within GOT, with PLT handling. 2754@end deffn 2755@deffn {} BFD_RELOC_390_GOTPLT16 275616-bit offset to symbol-entry within GOT, with PLT handling. 2757@end deffn 2758@deffn {} BFD_RELOC_390_GOTPLT32 275932-bit offset to symbol-entry within GOT, with PLT handling. 2760@end deffn 2761@deffn {} BFD_RELOC_390_GOTPLT64 276264-bit offset to symbol-entry within GOT, with PLT handling. 2763@end deffn 2764@deffn {} BFD_RELOC_390_GOTPLTENT 276532-bit rel. offset to symbol-entry within GOT, with PLT handling. 2766@end deffn 2767@deffn {} BFD_RELOC_390_PLTOFF16 276816-bit rel. offset from the GOT to a PLT entry. 2769@end deffn 2770@deffn {} BFD_RELOC_390_PLTOFF32 277132-bit rel. offset from the GOT to a PLT entry. 2772@end deffn 2773@deffn {} BFD_RELOC_390_PLTOFF64 277464-bit rel. offset from the GOT to a PLT entry. 2775@end deffn 2776@deffn {} BFD_RELOC_390_TLS_LOAD 2777@deffnx {} BFD_RELOC_390_TLS_GDCALL 2778@deffnx {} BFD_RELOC_390_TLS_LDCALL 2779@deffnx {} BFD_RELOC_390_TLS_GD32 2780@deffnx {} BFD_RELOC_390_TLS_GD64 2781@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2782@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2783@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2784@deffnx {} BFD_RELOC_390_TLS_LDM32 2785@deffnx {} BFD_RELOC_390_TLS_LDM64 2786@deffnx {} BFD_RELOC_390_TLS_IE32 2787@deffnx {} BFD_RELOC_390_TLS_IE64 2788@deffnx {} BFD_RELOC_390_TLS_IEENT 2789@deffnx {} BFD_RELOC_390_TLS_LE32 2790@deffnx {} BFD_RELOC_390_TLS_LE64 2791@deffnx {} BFD_RELOC_390_TLS_LDO32 2792@deffnx {} BFD_RELOC_390_TLS_LDO64 2793@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2794@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2795@deffnx {} BFD_RELOC_390_TLS_TPOFF 2796s390 tls relocations. 2797@end deffn 2798@deffn {} BFD_RELOC_390_20 2799@deffnx {} BFD_RELOC_390_GOT20 2800@deffnx {} BFD_RELOC_390_GOTPLT20 2801@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2802Long displacement extension. 2803@end deffn 2804@deffn {} BFD_RELOC_390_IRELATIVE 2805STT_GNU_IFUNC relocation. 2806@end deffn 2807@deffn {} BFD_RELOC_SCORE_GPREL15 2808Score relocations 2809Low 16 bit for load/store 2810@end deffn 2811@deffn {} BFD_RELOC_SCORE_DUMMY2 2812@deffnx {} BFD_RELOC_SCORE_JMP 2813This is a 24-bit reloc with the right 1 bit assumed to be 0 2814@end deffn 2815@deffn {} BFD_RELOC_SCORE_BRANCH 2816This is a 19-bit reloc with the right 1 bit assumed to be 0 2817@end deffn 2818@deffn {} BFD_RELOC_SCORE_IMM30 2819This is a 32-bit reloc for 48-bit instructions. 2820@end deffn 2821@deffn {} BFD_RELOC_SCORE_IMM32 2822This is a 32-bit reloc for 48-bit instructions. 2823@end deffn 2824@deffn {} BFD_RELOC_SCORE16_JMP 2825This is a 11-bit reloc with the right 1 bit assumed to be 0 2826@end deffn 2827@deffn {} BFD_RELOC_SCORE16_BRANCH 2828This is a 8-bit reloc with the right 1 bit assumed to be 0 2829@end deffn 2830@deffn {} BFD_RELOC_SCORE_BCMP 2831This is a 9-bit reloc with the right 1 bit assumed to be 0 2832@end deffn 2833@deffn {} BFD_RELOC_SCORE_GOT15 2834@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2835@deffnx {} BFD_RELOC_SCORE_CALL15 2836@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2837Undocumented Score relocs 2838@end deffn 2839@deffn {} BFD_RELOC_IP2K_FR9 2840Scenix IP2K - 9-bit register number / data address 2841@end deffn 2842@deffn {} BFD_RELOC_IP2K_BANK 2843Scenix IP2K - 4-bit register/data bank number 2844@end deffn 2845@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2846Scenix IP2K - low 13 bits of instruction word address 2847@end deffn 2848@deffn {} BFD_RELOC_IP2K_PAGE3 2849Scenix IP2K - high 3 bits of instruction word address 2850@end deffn 2851@deffn {} BFD_RELOC_IP2K_LO8DATA 2852@deffnx {} BFD_RELOC_IP2K_HI8DATA 2853@deffnx {} BFD_RELOC_IP2K_EX8DATA 2854Scenix IP2K - ext/low/high 8 bits of data address 2855@end deffn 2856@deffn {} BFD_RELOC_IP2K_LO8INSN 2857@deffnx {} BFD_RELOC_IP2K_HI8INSN 2858Scenix IP2K - low/high 8 bits of instruction word address 2859@end deffn 2860@deffn {} BFD_RELOC_IP2K_PC_SKIP 2861Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2862@end deffn 2863@deffn {} BFD_RELOC_IP2K_TEXT 2864Scenix IP2K - 16 bit word address in text section. 2865@end deffn 2866@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2867Scenix IP2K - 7-bit sp or dp offset 2868@end deffn 2869@deffn {} BFD_RELOC_VPE4KMATH_DATA 2870@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2871Scenix VPE4K coprocessor - data/insn-space addressing 2872@end deffn 2873@deffn {} BFD_RELOC_VTABLE_INHERIT 2874@deffnx {} BFD_RELOC_VTABLE_ENTRY 2875These two relocations are used by the linker to determine which of 2876the entries in a C++ virtual function table are actually used. When 2877the --gc-sections option is given, the linker will zero out the entries 2878that are not used, so that the code for those functions need not be 2879included in the output. 2880 2881VTABLE_INHERIT is a zero-space relocation used to describe to the 2882linker the inheritance tree of a C++ virtual function table. The 2883relocation's symbol should be the parent class' vtable, and the 2884relocation should be located at the child vtable. 2885 2886VTABLE_ENTRY is a zero-space relocation that describes the use of a 2887virtual function table entry. The reloc's symbol should refer to the 2888table of the class mentioned in the code. Off of that base, an offset 2889describes the entry that is being used. For Rela hosts, this offset 2890is stored in the reloc's addend. For Rel hosts, we are forced to put 2891this offset in the reloc's section offset. 2892@end deffn 2893@deffn {} BFD_RELOC_IA64_IMM14 2894@deffnx {} BFD_RELOC_IA64_IMM22 2895@deffnx {} BFD_RELOC_IA64_IMM64 2896@deffnx {} BFD_RELOC_IA64_DIR32MSB 2897@deffnx {} BFD_RELOC_IA64_DIR32LSB 2898@deffnx {} BFD_RELOC_IA64_DIR64MSB 2899@deffnx {} BFD_RELOC_IA64_DIR64LSB 2900@deffnx {} BFD_RELOC_IA64_GPREL22 2901@deffnx {} BFD_RELOC_IA64_GPREL64I 2902@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2903@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2904@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2905@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2906@deffnx {} BFD_RELOC_IA64_LTOFF22 2907@deffnx {} BFD_RELOC_IA64_LTOFF64I 2908@deffnx {} BFD_RELOC_IA64_PLTOFF22 2909@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2910@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2911@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2912@deffnx {} BFD_RELOC_IA64_FPTR64I 2913@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2914@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2915@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2916@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2917@deffnx {} BFD_RELOC_IA64_PCREL21B 2918@deffnx {} BFD_RELOC_IA64_PCREL21BI 2919@deffnx {} BFD_RELOC_IA64_PCREL21M 2920@deffnx {} BFD_RELOC_IA64_PCREL21F 2921@deffnx {} BFD_RELOC_IA64_PCREL22 2922@deffnx {} BFD_RELOC_IA64_PCREL60B 2923@deffnx {} BFD_RELOC_IA64_PCREL64I 2924@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2925@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2926@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2927@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2928@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2929@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2930@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2931@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2932@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2933@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2934@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2935@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2936@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2937@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2938@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2939@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2940@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2941@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2942@deffnx {} BFD_RELOC_IA64_REL32MSB 2943@deffnx {} BFD_RELOC_IA64_REL32LSB 2944@deffnx {} BFD_RELOC_IA64_REL64MSB 2945@deffnx {} BFD_RELOC_IA64_REL64LSB 2946@deffnx {} BFD_RELOC_IA64_LTV32MSB 2947@deffnx {} BFD_RELOC_IA64_LTV32LSB 2948@deffnx {} BFD_RELOC_IA64_LTV64MSB 2949@deffnx {} BFD_RELOC_IA64_LTV64LSB 2950@deffnx {} BFD_RELOC_IA64_IPLTMSB 2951@deffnx {} BFD_RELOC_IA64_IPLTLSB 2952@deffnx {} BFD_RELOC_IA64_COPY 2953@deffnx {} BFD_RELOC_IA64_LTOFF22X 2954@deffnx {} BFD_RELOC_IA64_LDXMOV 2955@deffnx {} BFD_RELOC_IA64_TPREL14 2956@deffnx {} BFD_RELOC_IA64_TPREL22 2957@deffnx {} BFD_RELOC_IA64_TPREL64I 2958@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2959@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2960@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2961@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2962@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2963@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2964@deffnx {} BFD_RELOC_IA64_DTPREL14 2965@deffnx {} BFD_RELOC_IA64_DTPREL22 2966@deffnx {} BFD_RELOC_IA64_DTPREL64I 2967@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2968@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2969@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2970@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2971@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2972Intel IA64 Relocations. 2973@end deffn 2974@deffn {} BFD_RELOC_M68HC11_HI8 2975Motorola 68HC11 reloc. 2976This is the 8 bit high part of an absolute address. 2977@end deffn 2978@deffn {} BFD_RELOC_M68HC11_LO8 2979Motorola 68HC11 reloc. 2980This is the 8 bit low part of an absolute address. 2981@end deffn 2982@deffn {} BFD_RELOC_M68HC11_3B 2983Motorola 68HC11 reloc. 2984This is the 3 bit of a value. 2985@end deffn 2986@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2987Motorola 68HC11 reloc. 2988This reloc marks the beginning of a jump/call instruction. 2989It is used for linker relaxation to correctly identify beginning 2990of instruction and change some branches to use PC-relative 2991addressing mode. 2992@end deffn 2993@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2994Motorola 68HC11 reloc. 2995This reloc marks a group of several instructions that gcc generates 2996and for which the linker relaxation pass can modify and/or remove 2997some of them. 2998@end deffn 2999@deffn {} BFD_RELOC_M68HC11_LO16 3000Motorola 68HC11 reloc. 3001This is the 16-bit lower part of an address. It is used for 'call' 3002instruction to specify the symbol address without any special 3003transformation (due to memory bank window). 3004@end deffn 3005@deffn {} BFD_RELOC_M68HC11_PAGE 3006Motorola 68HC11 reloc. 3007This is a 8-bit reloc that specifies the page number of an address. 3008It is used by 'call' instruction to specify the page number of 3009the symbol. 3010@end deffn 3011@deffn {} BFD_RELOC_M68HC11_24 3012Motorola 68HC11 reloc. 3013This is a 24-bit reloc that represents the address with a 16-bit 3014value and a 8-bit page number. The symbol address is transformed 3015to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 3016@end deffn 3017@deffn {} BFD_RELOC_M68HC12_5B 3018Motorola 68HC12 reloc. 3019This is the 5 bits of a value. 3020@end deffn 3021@deffn {} BFD_RELOC_XGATE_RL_JUMP 3022Freescale XGATE reloc. 3023This reloc marks the beginning of a bra/jal instruction. 3024@end deffn 3025@deffn {} BFD_RELOC_XGATE_RL_GROUP 3026Freescale XGATE reloc. 3027This reloc marks a group of several instructions that gcc generates 3028and for which the linker relaxation pass can modify and/or remove 3029some of them. 3030@end deffn 3031@deffn {} BFD_RELOC_XGATE_LO16 3032Freescale XGATE reloc. 3033This is the 16-bit lower part of an address. It is used for the '16-bit' 3034instructions. 3035@end deffn 3036@deffn {} BFD_RELOC_XGATE_GPAGE 3037Freescale XGATE reloc. 3038@end deffn 3039@deffn {} BFD_RELOC_XGATE_24 3040Freescale XGATE reloc. 3041@end deffn 3042@deffn {} BFD_RELOC_XGATE_PCREL_9 3043Freescale XGATE reloc. 3044This is a 9-bit pc-relative reloc. 3045@end deffn 3046@deffn {} BFD_RELOC_XGATE_PCREL_10 3047Freescale XGATE reloc. 3048This is a 10-bit pc-relative reloc. 3049@end deffn 3050@deffn {} BFD_RELOC_XGATE_IMM8_LO 3051Freescale XGATE reloc. 3052This is the 16-bit lower part of an address. It is used for the '16-bit' 3053instructions. 3054@end deffn 3055@deffn {} BFD_RELOC_XGATE_IMM8_HI 3056Freescale XGATE reloc. 3057This is the 16-bit higher part of an address. It is used for the '16-bit' 3058instructions. 3059@end deffn 3060@deffn {} BFD_RELOC_XGATE_IMM3 3061Freescale XGATE reloc. 3062This is a 3-bit pc-relative reloc. 3063@end deffn 3064@deffn {} BFD_RELOC_XGATE_IMM4 3065Freescale XGATE reloc. 3066This is a 4-bit pc-relative reloc. 3067@end deffn 3068@deffn {} BFD_RELOC_XGATE_IMM5 3069Freescale XGATE reloc. 3070This is a 5-bit pc-relative reloc. 3071@end deffn 3072@deffn {} BFD_RELOC_M68HC12_9B 3073Motorola 68HC12 reloc. 3074This is the 9 bits of a value. 3075@end deffn 3076@deffn {} BFD_RELOC_M68HC12_16B 3077Motorola 68HC12 reloc. 3078This is the 16 bits of a value. 3079@end deffn 3080@deffn {} BFD_RELOC_M68HC12_9_PCREL 3081Motorola 68HC12/XGATE reloc. 3082This is a PCREL9 branch. 3083@end deffn 3084@deffn {} BFD_RELOC_M68HC12_10_PCREL 3085Motorola 68HC12/XGATE reloc. 3086This is a PCREL10 branch. 3087@end deffn 3088@deffn {} BFD_RELOC_M68HC12_LO8XG 3089Motorola 68HC12/XGATE reloc. 3090This is the 8 bit low part of an absolute address and immediately precedes 3091a matching HI8XG part. 3092@end deffn 3093@deffn {} BFD_RELOC_M68HC12_HI8XG 3094Motorola 68HC12/XGATE reloc. 3095This is the 8 bit high part of an absolute address and immediately follows 3096a matching LO8XG part. 3097@end deffn 3098@deffn {} BFD_RELOC_16C_NUM08 3099@deffnx {} BFD_RELOC_16C_NUM08_C 3100@deffnx {} BFD_RELOC_16C_NUM16 3101@deffnx {} BFD_RELOC_16C_NUM16_C 3102@deffnx {} BFD_RELOC_16C_NUM32 3103@deffnx {} BFD_RELOC_16C_NUM32_C 3104@deffnx {} BFD_RELOC_16C_DISP04 3105@deffnx {} BFD_RELOC_16C_DISP04_C 3106@deffnx {} BFD_RELOC_16C_DISP08 3107@deffnx {} BFD_RELOC_16C_DISP08_C 3108@deffnx {} BFD_RELOC_16C_DISP16 3109@deffnx {} BFD_RELOC_16C_DISP16_C 3110@deffnx {} BFD_RELOC_16C_DISP24 3111@deffnx {} BFD_RELOC_16C_DISP24_C 3112@deffnx {} BFD_RELOC_16C_DISP24a 3113@deffnx {} BFD_RELOC_16C_DISP24a_C 3114@deffnx {} BFD_RELOC_16C_REG04 3115@deffnx {} BFD_RELOC_16C_REG04_C 3116@deffnx {} BFD_RELOC_16C_REG04a 3117@deffnx {} BFD_RELOC_16C_REG04a_C 3118@deffnx {} BFD_RELOC_16C_REG14 3119@deffnx {} BFD_RELOC_16C_REG14_C 3120@deffnx {} BFD_RELOC_16C_REG16 3121@deffnx {} BFD_RELOC_16C_REG16_C 3122@deffnx {} BFD_RELOC_16C_REG20 3123@deffnx {} BFD_RELOC_16C_REG20_C 3124@deffnx {} BFD_RELOC_16C_ABS20 3125@deffnx {} BFD_RELOC_16C_ABS20_C 3126@deffnx {} BFD_RELOC_16C_ABS24 3127@deffnx {} BFD_RELOC_16C_ABS24_C 3128@deffnx {} BFD_RELOC_16C_IMM04 3129@deffnx {} BFD_RELOC_16C_IMM04_C 3130@deffnx {} BFD_RELOC_16C_IMM16 3131@deffnx {} BFD_RELOC_16C_IMM16_C 3132@deffnx {} BFD_RELOC_16C_IMM20 3133@deffnx {} BFD_RELOC_16C_IMM20_C 3134@deffnx {} BFD_RELOC_16C_IMM24 3135@deffnx {} BFD_RELOC_16C_IMM24_C 3136@deffnx {} BFD_RELOC_16C_IMM32 3137@deffnx {} BFD_RELOC_16C_IMM32_C 3138NS CR16C Relocations. 3139@end deffn 3140@deffn {} BFD_RELOC_CR16_NUM8 3141@deffnx {} BFD_RELOC_CR16_NUM16 3142@deffnx {} BFD_RELOC_CR16_NUM32 3143@deffnx {} BFD_RELOC_CR16_NUM32a 3144@deffnx {} BFD_RELOC_CR16_REGREL0 3145@deffnx {} BFD_RELOC_CR16_REGREL4 3146@deffnx {} BFD_RELOC_CR16_REGREL4a 3147@deffnx {} BFD_RELOC_CR16_REGREL14 3148@deffnx {} BFD_RELOC_CR16_REGREL14a 3149@deffnx {} BFD_RELOC_CR16_REGREL16 3150@deffnx {} BFD_RELOC_CR16_REGREL20 3151@deffnx {} BFD_RELOC_CR16_REGREL20a 3152@deffnx {} BFD_RELOC_CR16_ABS20 3153@deffnx {} BFD_RELOC_CR16_ABS24 3154@deffnx {} BFD_RELOC_CR16_IMM4 3155@deffnx {} BFD_RELOC_CR16_IMM8 3156@deffnx {} BFD_RELOC_CR16_IMM16 3157@deffnx {} BFD_RELOC_CR16_IMM20 3158@deffnx {} BFD_RELOC_CR16_IMM24 3159@deffnx {} BFD_RELOC_CR16_IMM32 3160@deffnx {} BFD_RELOC_CR16_IMM32a 3161@deffnx {} BFD_RELOC_CR16_DISP4 3162@deffnx {} BFD_RELOC_CR16_DISP8 3163@deffnx {} BFD_RELOC_CR16_DISP16 3164@deffnx {} BFD_RELOC_CR16_DISP20 3165@deffnx {} BFD_RELOC_CR16_DISP24 3166@deffnx {} BFD_RELOC_CR16_DISP24a 3167@deffnx {} BFD_RELOC_CR16_SWITCH8 3168@deffnx {} BFD_RELOC_CR16_SWITCH16 3169@deffnx {} BFD_RELOC_CR16_SWITCH32 3170@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3171@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3172@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3173NS CR16 Relocations. 3174@end deffn 3175@deffn {} BFD_RELOC_CRX_REL4 3176@deffnx {} BFD_RELOC_CRX_REL8 3177@deffnx {} BFD_RELOC_CRX_REL8_CMP 3178@deffnx {} BFD_RELOC_CRX_REL16 3179@deffnx {} BFD_RELOC_CRX_REL24 3180@deffnx {} BFD_RELOC_CRX_REL32 3181@deffnx {} BFD_RELOC_CRX_REGREL12 3182@deffnx {} BFD_RELOC_CRX_REGREL22 3183@deffnx {} BFD_RELOC_CRX_REGREL28 3184@deffnx {} BFD_RELOC_CRX_REGREL32 3185@deffnx {} BFD_RELOC_CRX_ABS16 3186@deffnx {} BFD_RELOC_CRX_ABS32 3187@deffnx {} BFD_RELOC_CRX_NUM8 3188@deffnx {} BFD_RELOC_CRX_NUM16 3189@deffnx {} BFD_RELOC_CRX_NUM32 3190@deffnx {} BFD_RELOC_CRX_IMM16 3191@deffnx {} BFD_RELOC_CRX_IMM32 3192@deffnx {} BFD_RELOC_CRX_SWITCH8 3193@deffnx {} BFD_RELOC_CRX_SWITCH16 3194@deffnx {} BFD_RELOC_CRX_SWITCH32 3195NS CRX Relocations. 3196@end deffn 3197@deffn {} BFD_RELOC_CRIS_BDISP8 3198@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3199@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3200@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3201@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3202@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3203@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3204@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3205@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3206@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3207These relocs are only used within the CRIS assembler. They are not 3208(at present) written to any object files. 3209@end deffn 3210@deffn {} BFD_RELOC_CRIS_COPY 3211@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3212@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3213@deffnx {} BFD_RELOC_CRIS_RELATIVE 3214Relocs used in ELF shared libraries for CRIS. 3215@end deffn 3216@deffn {} BFD_RELOC_CRIS_32_GOT 321732-bit offset to symbol-entry within GOT. 3218@end deffn 3219@deffn {} BFD_RELOC_CRIS_16_GOT 322016-bit offset to symbol-entry within GOT. 3221@end deffn 3222@deffn {} BFD_RELOC_CRIS_32_GOTPLT 322332-bit offset to symbol-entry within GOT, with PLT handling. 3224@end deffn 3225@deffn {} BFD_RELOC_CRIS_16_GOTPLT 322616-bit offset to symbol-entry within GOT, with PLT handling. 3227@end deffn 3228@deffn {} BFD_RELOC_CRIS_32_GOTREL 322932-bit offset to symbol, relative to GOT. 3230@end deffn 3231@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 323232-bit offset to symbol with PLT entry, relative to GOT. 3233@end deffn 3234@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 323532-bit offset to symbol with PLT entry, relative to this relocation. 3236@end deffn 3237@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3238@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3239@deffnx {} BFD_RELOC_CRIS_32_GD 3240@deffnx {} BFD_RELOC_CRIS_DTP 3241@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3242@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3243@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3244@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3245@deffnx {} BFD_RELOC_CRIS_32_TPREL 3246@deffnx {} BFD_RELOC_CRIS_16_TPREL 3247@deffnx {} BFD_RELOC_CRIS_DTPMOD 3248@deffnx {} BFD_RELOC_CRIS_32_IE 3249Relocs used in TLS code for CRIS. 3250@end deffn 3251@deffn {} BFD_RELOC_860_COPY 3252@deffnx {} BFD_RELOC_860_GLOB_DAT 3253@deffnx {} BFD_RELOC_860_JUMP_SLOT 3254@deffnx {} BFD_RELOC_860_RELATIVE 3255@deffnx {} BFD_RELOC_860_PC26 3256@deffnx {} BFD_RELOC_860_PLT26 3257@deffnx {} BFD_RELOC_860_PC16 3258@deffnx {} BFD_RELOC_860_LOW0 3259@deffnx {} BFD_RELOC_860_SPLIT0 3260@deffnx {} BFD_RELOC_860_LOW1 3261@deffnx {} BFD_RELOC_860_SPLIT1 3262@deffnx {} BFD_RELOC_860_LOW2 3263@deffnx {} BFD_RELOC_860_SPLIT2 3264@deffnx {} BFD_RELOC_860_LOW3 3265@deffnx {} BFD_RELOC_860_LOGOT0 3266@deffnx {} BFD_RELOC_860_SPGOT0 3267@deffnx {} BFD_RELOC_860_LOGOT1 3268@deffnx {} BFD_RELOC_860_SPGOT1 3269@deffnx {} BFD_RELOC_860_LOGOTOFF0 3270@deffnx {} BFD_RELOC_860_SPGOTOFF0 3271@deffnx {} BFD_RELOC_860_LOGOTOFF1 3272@deffnx {} BFD_RELOC_860_SPGOTOFF1 3273@deffnx {} BFD_RELOC_860_LOGOTOFF2 3274@deffnx {} BFD_RELOC_860_LOGOTOFF3 3275@deffnx {} BFD_RELOC_860_LOPC 3276@deffnx {} BFD_RELOC_860_HIGHADJ 3277@deffnx {} BFD_RELOC_860_HAGOT 3278@deffnx {} BFD_RELOC_860_HAGOTOFF 3279@deffnx {} BFD_RELOC_860_HAPC 3280@deffnx {} BFD_RELOC_860_HIGH 3281@deffnx {} BFD_RELOC_860_HIGOT 3282@deffnx {} BFD_RELOC_860_HIGOTOFF 3283Intel i860 Relocations. 3284@end deffn 3285@deffn {} BFD_RELOC_OR1K_REL_26 3286@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3287@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3288@deffnx {} BFD_RELOC_OR1K_GOT16 3289@deffnx {} BFD_RELOC_OR1K_PLT26 3290@deffnx {} BFD_RELOC_OR1K_GOTOFF_HI16 3291@deffnx {} BFD_RELOC_OR1K_GOTOFF_LO16 3292@deffnx {} BFD_RELOC_OR1K_COPY 3293@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3294@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3295@deffnx {} BFD_RELOC_OR1K_RELATIVE 3296@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3297@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3298@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3299@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3300@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3301@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3302@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3303@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3304@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3305@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3306@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3307@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3308@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3309OpenRISC 1000 Relocations. 3310@end deffn 3311@deffn {} BFD_RELOC_H8_DIR16A8 3312@deffnx {} BFD_RELOC_H8_DIR16R8 3313@deffnx {} BFD_RELOC_H8_DIR24A8 3314@deffnx {} BFD_RELOC_H8_DIR24R8 3315@deffnx {} BFD_RELOC_H8_DIR32A16 3316@deffnx {} BFD_RELOC_H8_DISP32A16 3317H8 elf Relocations. 3318@end deffn 3319@deffn {} BFD_RELOC_XSTORMY16_REL_12 3320@deffnx {} BFD_RELOC_XSTORMY16_12 3321@deffnx {} BFD_RELOC_XSTORMY16_24 3322@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3323Sony Xstormy16 Relocations. 3324@end deffn 3325@deffn {} BFD_RELOC_RELC 3326Self-describing complex relocations. 3327@end deffn 3328@deffn {} BFD_RELOC_XC16X_PAG 3329@deffnx {} BFD_RELOC_XC16X_POF 3330@deffnx {} BFD_RELOC_XC16X_SEG 3331@deffnx {} BFD_RELOC_XC16X_SOF 3332Infineon Relocations. 3333@end deffn 3334@deffn {} BFD_RELOC_VAX_GLOB_DAT 3335@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3336@deffnx {} BFD_RELOC_VAX_RELATIVE 3337Relocations used by VAX ELF. 3338@end deffn 3339@deffn {} BFD_RELOC_MT_PC16 3340Morpho MT - 16 bit immediate relocation. 3341@end deffn 3342@deffn {} BFD_RELOC_MT_HI16 3343Morpho MT - Hi 16 bits of an address. 3344@end deffn 3345@deffn {} BFD_RELOC_MT_LO16 3346Morpho MT - Low 16 bits of an address. 3347@end deffn 3348@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3349Morpho MT - Used to tell the linker which vtable entries are used. 3350@end deffn 3351@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3352Morpho MT - Used to tell the linker which vtable entries are used. 3353@end deffn 3354@deffn {} BFD_RELOC_MT_PCINSN8 3355Morpho MT - 8 bit immediate relocation. 3356@end deffn 3357@deffn {} BFD_RELOC_MSP430_10_PCREL 3358@deffnx {} BFD_RELOC_MSP430_16_PCREL 3359@deffnx {} BFD_RELOC_MSP430_16 3360@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3361@deffnx {} BFD_RELOC_MSP430_16_BYTE 3362@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3363@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3364@deffnx {} BFD_RELOC_MSP430_ABS8 3365@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3366@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3367@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3368@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3369@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3370@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3371@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3372@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3373@deffnx {} BFD_RELOC_MSP430X_PCR16 3374@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3375@deffnx {} BFD_RELOC_MSP430X_ABS16 3376@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3377@deffnx {} BFD_RELOC_MSP430_PREL31 3378@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3379msp430 specific relocation codes 3380@end deffn 3381@deffn {} BFD_RELOC_NIOS2_S16 3382@deffnx {} BFD_RELOC_NIOS2_U16 3383@deffnx {} BFD_RELOC_NIOS2_CALL26 3384@deffnx {} BFD_RELOC_NIOS2_IMM5 3385@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3386@deffnx {} BFD_RELOC_NIOS2_IMM6 3387@deffnx {} BFD_RELOC_NIOS2_IMM8 3388@deffnx {} BFD_RELOC_NIOS2_HI16 3389@deffnx {} BFD_RELOC_NIOS2_LO16 3390@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3391@deffnx {} BFD_RELOC_NIOS2_GPREL 3392@deffnx {} BFD_RELOC_NIOS2_UJMP 3393@deffnx {} BFD_RELOC_NIOS2_CJMP 3394@deffnx {} BFD_RELOC_NIOS2_CALLR 3395@deffnx {} BFD_RELOC_NIOS2_ALIGN 3396@deffnx {} BFD_RELOC_NIOS2_GOT16 3397@deffnx {} BFD_RELOC_NIOS2_CALL16 3398@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3399@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3400@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3401@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3402@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3403@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3404@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3405@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3406@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3407@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3408@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3409@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3410@deffnx {} BFD_RELOC_NIOS2_COPY 3411@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3412@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3413@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3414@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3415@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3416@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3417@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3418@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3419@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3420@deffnx {} BFD_RELOC_NIOS2_R2_S12 3421@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3422@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3423@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3424@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3425@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3426@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3427@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3428@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3429@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3430@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3431@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3432@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3433Relocations used by the Altera Nios II core. 3434@end deffn 3435@deffn {} BFD_RELOC_PRU_U16 3436PRU LDI 16-bit unsigned data-memory relocation. 3437@end deffn 3438@deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3439PRU LDI 16-bit unsigned instruction-memory relocation. 3440@end deffn 3441@deffn {} BFD_RELOC_PRU_LDI32 3442PRU relocation for two consecutive LDI load instructions that load a 344332 bit value into a register. If the higher bits are all zero, then 3444the second instruction may be relaxed. 3445@end deffn 3446@deffn {} BFD_RELOC_PRU_S10_PCREL 3447PRU QBBx 10-bit signed PC-relative relocation. 3448@end deffn 3449@deffn {} BFD_RELOC_PRU_U8_PCREL 3450PRU 8-bit unsigned relocation used for the LOOP instruction. 3451@end deffn 3452@deffn {} BFD_RELOC_PRU_32_PMEM 3453@deffnx {} BFD_RELOC_PRU_16_PMEM 3454PRU Program Memory relocations. Used to convert from byte addressing to 345532-bit word addressing. 3456@end deffn 3457@deffn {} BFD_RELOC_PRU_GNU_DIFF8 3458@deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3459@deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3460@deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3461@deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3462PRU relocations to mark the difference of two local symbols. 3463These are only needed to support linker relaxation and can be ignored 3464when not relaxing. The field is set to the value of the difference 3465assuming no relaxation. The relocation encodes the position of the 3466second symbol so the linker can determine whether to adjust the field 3467value. The PMEM variants encode the word difference, instead of byte 3468difference between symbols. 3469@end deffn 3470@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3471@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3472@deffnx {} BFD_RELOC_IQ2000_UHI16 3473IQ2000 Relocations. 3474@end deffn 3475@deffn {} BFD_RELOC_XTENSA_RTLD 3476Special Xtensa relocation used only by PLT entries in ELF shared 3477objects to indicate that the runtime linker should set the value 3478to one of its own internal functions or data structures. 3479@end deffn 3480@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3481@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3482@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3483Xtensa relocations for ELF shared objects. 3484@end deffn 3485@deffn {} BFD_RELOC_XTENSA_PLT 3486Xtensa relocation used in ELF object files for symbols that may require 3487PLT entries. Otherwise, this is just a generic 32-bit relocation. 3488@end deffn 3489@deffn {} BFD_RELOC_XTENSA_DIFF8 3490@deffnx {} BFD_RELOC_XTENSA_DIFF16 3491@deffnx {} BFD_RELOC_XTENSA_DIFF32 3492Xtensa relocations to mark the difference of two local symbols. 3493These are only needed to support linker relaxation and can be ignored 3494when not relaxing. The field is set to the value of the difference 3495assuming no relaxation. The relocation encodes the position of the 3496first symbol so the linker can determine whether to adjust the field 3497value. 3498@end deffn 3499@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3500@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3501@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3502@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3503@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3504@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3505@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3506@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3507@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3508@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3509@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3510@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3511@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3512@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3513@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3514Generic Xtensa relocations for instruction operands. Only the slot 3515number is encoded in the relocation. The relocation applies to the 3516last PC-relative immediate operand, or if there are no PC-relative 3517immediates, to the last immediate operand. 3518@end deffn 3519@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3520@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3521@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3522@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3523@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3524@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3525@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3526@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3527@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3528@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3529@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3530@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3531@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3532@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3533@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3534Alternate Xtensa relocations. Only the slot is encoded in the 3535relocation. The meaning of these relocations is opcode-specific. 3536@end deffn 3537@deffn {} BFD_RELOC_XTENSA_OP0 3538@deffnx {} BFD_RELOC_XTENSA_OP1 3539@deffnx {} BFD_RELOC_XTENSA_OP2 3540Xtensa relocations for backward compatibility. These have all been 3541replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3542@end deffn 3543@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3544Xtensa relocation to mark that the assembler expanded the 3545instructions from an original target. The expansion size is 3546encoded in the reloc size. 3547@end deffn 3548@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3549Xtensa relocation to mark that the linker should simplify 3550assembler-expanded instructions. This is commonly used 3551internally by the linker after analysis of a 3552BFD_RELOC_XTENSA_ASM_EXPAND. 3553@end deffn 3554@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3555@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3556@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3557@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3558@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3559@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3560@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3561Xtensa TLS relocations. 3562@end deffn 3563@deffn {} BFD_RELOC_Z80_DISP8 35648 bit signed offset in (ix+d) or (iy+d). 3565@end deffn 3566@deffn {} BFD_RELOC_Z8K_DISP7 3567DJNZ offset. 3568@end deffn 3569@deffn {} BFD_RELOC_Z8K_CALLR 3570CALR offset. 3571@end deffn 3572@deffn {} BFD_RELOC_Z8K_IMM4L 35734 bit value. 3574@end deffn 3575@deffn {} BFD_RELOC_LM32_CALL 3576@deffnx {} BFD_RELOC_LM32_BRANCH 3577@deffnx {} BFD_RELOC_LM32_16_GOT 3578@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3579@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3580@deffnx {} BFD_RELOC_LM32_COPY 3581@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3582@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3583@deffnx {} BFD_RELOC_LM32_RELATIVE 3584Lattice Mico32 relocations. 3585@end deffn 3586@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3587Difference between two section addreses. Must be followed by a 3588BFD_RELOC_MACH_O_PAIR. 3589@end deffn 3590@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3591Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3592@end deffn 3593@deffn {} BFD_RELOC_MACH_O_PAIR 3594Pair of relocation. Contains the first symbol. 3595@end deffn 3596@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3597Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3598@end deffn 3599@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3600Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3601@end deffn 3602@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3603@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3604PCREL relocations. They are marked as branch to create PLT entry if 3605required. 3606@end deffn 3607@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3608Used when referencing a GOT entry. 3609@end deffn 3610@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3611Used when loading a GOT entry with movq. It is specially marked so that 3612the linker could optimize the movq to a leaq if possible. 3613@end deffn 3614@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3615Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3616@end deffn 3617@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3618Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3619@end deffn 3620@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3621Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3622@end deffn 3623@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3624Addend for PAGE or PAGEOFF. 3625@end deffn 3626@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3627Relative offset to page of GOT slot. 3628@end deffn 3629@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3630Relative offset within page of GOT slot. 3631@end deffn 3632@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3633Address of a GOT entry. 3634@end deffn 3635@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3636This is a 32 bit reloc for the microblaze that stores the 3637low 16 bits of a value 3638@end deffn 3639@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3640This is a 32 bit pc-relative reloc for the microblaze that 3641stores the low 16 bits of a value 3642@end deffn 3643@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3644This is a 32 bit reloc for the microblaze that stores a 3645value relative to the read-only small data area anchor 3646@end deffn 3647@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3648This is a 32 bit reloc for the microblaze that stores a 3649value relative to the read-write small data area anchor 3650@end deffn 3651@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3652This is a 32 bit reloc for the microblaze to handle 3653expressions of the form "Symbol Op Symbol" 3654@end deffn 3655@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3656This is a 64 bit reloc that stores the 32 bit pc relative 3657value in two words (with an imm instruction). No relocation is 3658done here - only used for relaxing 3659@end deffn 3660@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3661This is a 64 bit reloc that stores the 32 bit pc relative 3662value in two words (with an imm instruction). The relocation is 3663PC-relative GOT offset 3664@end deffn 3665@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3666This is a 64 bit reloc that stores the 32 bit pc relative 3667value in two words (with an imm instruction). The relocation is 3668GOT offset 3669@end deffn 3670@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3671This is a 64 bit reloc that stores the 32 bit pc relative 3672value in two words (with an imm instruction). The relocation is 3673PC-relative offset into PLT 3674@end deffn 3675@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3676This is a 64 bit reloc that stores the 32 bit GOT relative 3677value in two words (with an imm instruction). The relocation is 3678relative offset from _GLOBAL_OFFSET_TABLE_ 3679@end deffn 3680@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3681This is a 32 bit reloc that stores the 32 bit GOT relative 3682value in a word. The relocation is relative offset from 3683@end deffn 3684@deffn {} BFD_RELOC_MICROBLAZE_COPY 3685This is used to tell the dynamic linker to copy the value out of 3686the dynamic object into the runtime process image. 3687@end deffn 3688@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3689Unused Reloc 3690@end deffn 3691@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3692This is a 64 bit reloc that stores the 32 bit GOT relative value 3693of the GOT TLS GD info entry in two words (with an imm instruction). The 3694relocation is GOT offset. 3695@end deffn 3696@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3697This is a 64 bit reloc that stores the 32 bit GOT relative value 3698of the GOT TLS LD info entry in two words (with an imm instruction). The 3699relocation is GOT offset. 3700@end deffn 3701@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3702This is a 32 bit reloc that stores the Module ID to GOT(n). 3703@end deffn 3704@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3705This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3706@end deffn 3707@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3708This is a 32 bit reloc for storing TLS offset to two words (uses imm 3709instruction) 3710@end deffn 3711@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3712This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3713to two words (uses imm instruction). 3714@end deffn 3715@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3716This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3717to two words (uses imm instruction). 3718@end deffn 3719@deffn {} BFD_RELOC_AARCH64_RELOC_START 3720AArch64 pseudo relocation code to mark the start of the AArch64 3721relocation enumerators. N.B. the order of the enumerators is 3722important as several tables in the AArch64 bfd backend are indexed 3723by these enumerators; make sure they are all synced. 3724@end deffn 3725@deffn {} BFD_RELOC_AARCH64_NULL 3726Deprecated AArch64 null relocation code. 3727@end deffn 3728@deffn {} BFD_RELOC_AARCH64_NONE 3729AArch64 null relocation code. 3730@end deffn 3731@deffn {} BFD_RELOC_AARCH64_64 3732@deffnx {} BFD_RELOC_AARCH64_32 3733@deffnx {} BFD_RELOC_AARCH64_16 3734Basic absolute relocations of N bits. These are equivalent to 3735BFD_RELOC_N and they were added to assist the indexing of the howto 3736table. 3737@end deffn 3738@deffn {} BFD_RELOC_AARCH64_64_PCREL 3739@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3740@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3741PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3742and they were added to assist the indexing of the howto table. 3743@end deffn 3744@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3745AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3746of an unsigned address/value. 3747@end deffn 3748@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3749AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3750an address/value. No overflow checking. 3751@end deffn 3752@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3753AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3754of an unsigned address/value. 3755@end deffn 3756@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3757AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3758of an address/value. No overflow checking. 3759@end deffn 3760@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3761AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3762of an unsigned address/value. 3763@end deffn 3764@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3765AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3766of an address/value. No overflow checking. 3767@end deffn 3768@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3769AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3770of a signed or unsigned address/value. 3771@end deffn 3772@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3773AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3774of a signed value. Changes instruction to MOVZ or MOVN depending on the 3775value's sign. 3776@end deffn 3777@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3778AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3779of a signed value. Changes instruction to MOVZ or MOVN depending on the 3780value's sign. 3781@end deffn 3782@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3783AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3784of a signed value. Changes instruction to MOVZ or MOVN depending on the 3785value's sign. 3786@end deffn 3787@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3788AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3789offset. The lowest two bits must be zero and are not stored in the 3790instruction, giving a 21 bit signed byte offset. 3791@end deffn 3792@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3793AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3794@end deffn 3795@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3796AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3797offset, giving a 4KB aligned page base address. 3798@end deffn 3799@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3800AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3801offset, giving a 4KB aligned page base address, but with no overflow 3802checking. 3803@end deffn 3804@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3805AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3806Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3807@end deffn 3808@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3809AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3810address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3811@end deffn 3812@deffn {} BFD_RELOC_AARCH64_TSTBR14 3813AArch64 14 bit pc-relative test bit and branch. 3814The lowest two bits must be zero and are not stored in the instruction, 3815giving a 16 bit signed byte offset. 3816@end deffn 3817@deffn {} BFD_RELOC_AARCH64_BRANCH19 3818AArch64 19 bit pc-relative conditional branch and compare & branch. 3819The lowest two bits must be zero and are not stored in the instruction, 3820giving a 21 bit signed byte offset. 3821@end deffn 3822@deffn {} BFD_RELOC_AARCH64_JUMP26 3823AArch64 26 bit pc-relative unconditional branch. 3824The lowest two bits must be zero and are not stored in the instruction, 3825giving a 28 bit signed byte offset. 3826@end deffn 3827@deffn {} BFD_RELOC_AARCH64_CALL26 3828AArch64 26 bit pc-relative unconditional branch and link. 3829The lowest two bits must be zero and are not stored in the instruction, 3830giving a 28 bit signed byte offset. 3831@end deffn 3832@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3833AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3834address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3835@end deffn 3836@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3837AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3838address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3839@end deffn 3840@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3841AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3842address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3843@end deffn 3844@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3845AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3846address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3847@end deffn 3848@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3849AArch64 Load Literal instruction, holding a 19 bit PC relative word 3850offset of the global offset table entry for a symbol. The lowest two 3851bits must be zero and are not stored in the instruction, giving a 21 3852bit signed byte offset. This relocation type requires signed overflow 3853checking. 3854@end deffn 3855@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3856Get to the page base of the global offset table entry for a symbol as 3857part of an ADRP instruction using a 21 bit PC relative value.Used in 3858conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3859@end deffn 3860@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3861Unsigned 12 bit byte offset for 64 bit load/store from the page of 3862the GOT entry for this symbol. Used in conjunction with 3863BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3864@end deffn 3865@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3866Unsigned 12 bit byte offset for 32 bit load/store from the page of 3867the GOT entry for this symbol. Used in conjunction with 3868BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3869@end deffn 3870@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3871Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3872for this symbol. Valid in LP64 ABI only. 3873@end deffn 3874@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3875Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3876for this symbol. Valid in LP64 ABI only. 3877@end deffn 3878@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3879Unsigned 15 bit byte offset for 64 bit load/store from the page of 3880the GOT entry for this symbol. Valid in LP64 ABI only. 3881@end deffn 3882@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3883Scaled 14 bit byte offset to the page base of the global offset table. 3884@end deffn 3885@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3886Scaled 15 bit byte offset to the page base of the global offset table. 3887@end deffn 3888@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3889Get to the page base of the global offset table entry for a symbols 3890tls_index structure as part of an adrp instruction using a 21 bit PC 3891relative value. Used in conjunction with 3892BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3893@end deffn 3894@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3895AArch64 TLS General Dynamic 3896@end deffn 3897@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3898Unsigned 12 bit byte offset to global offset table entry for a symbols 3899tls_index structure. Used in conjunction with 3900BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3901@end deffn 3902@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3903AArch64 TLS General Dynamic relocation. 3904@end deffn 3905@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3906AArch64 TLS General Dynamic relocation. 3907@end deffn 3908@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3909AArch64 TLS INITIAL EXEC relocation. 3910@end deffn 3911@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3912AArch64 TLS INITIAL EXEC relocation. 3913@end deffn 3914@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3915AArch64 TLS INITIAL EXEC relocation. 3916@end deffn 3917@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3918AArch64 TLS INITIAL EXEC relocation. 3919@end deffn 3920@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3921AArch64 TLS INITIAL EXEC relocation. 3922@end deffn 3923@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3924AArch64 TLS INITIAL EXEC relocation. 3925@end deffn 3926@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3927bit[23:12] of byte offset to module TLS base address. 3928@end deffn 3929@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3930Unsigned 12 bit byte offset to module TLS base address. 3931@end deffn 3932@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3933No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3934@end deffn 3935@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3936Unsigned 12 bit byte offset to global offset table entry for a symbols 3937tls_index structure. Used in conjunction with 3938BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3939@end deffn 3940@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3941GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3942instruction. 3943@end deffn 3944@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3945GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 3946@end deffn 3947@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 3948bit[11:1] of byte offset to module TLS base address, encoded in ldst 3949instructions. 3950@end deffn 3951@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 3952Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 3953@end deffn 3954@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 3955bit[11:2] of byte offset to module TLS base address, encoded in ldst 3956instructions. 3957@end deffn 3958@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 3959Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 3960@end deffn 3961@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 3962bit[11:3] of byte offset to module TLS base address, encoded in ldst 3963instructions. 3964@end deffn 3965@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 3966Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 3967@end deffn 3968@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 3969bit[11:0] of byte offset to module TLS base address, encoded in ldst 3970instructions. 3971@end deffn 3972@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 3973Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 3974@end deffn 3975@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3976bit[15:0] of byte offset to module TLS base address. 3977@end deffn 3978@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 3979No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3980@end deffn 3981@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3982bit[31:16] of byte offset to module TLS base address. 3983@end deffn 3984@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 3985No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3986@end deffn 3987@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 3988bit[47:32] of byte offset to module TLS base address. 3989@end deffn 3990@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 3991AArch64 TLS LOCAL EXEC relocation. 3992@end deffn 3993@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 3994AArch64 TLS LOCAL EXEC relocation. 3995@end deffn 3996@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 3997AArch64 TLS LOCAL EXEC relocation. 3998@end deffn 3999@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4000AArch64 TLS LOCAL EXEC relocation. 4001@end deffn 4002@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4003AArch64 TLS LOCAL EXEC relocation. 4004@end deffn 4005@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4006AArch64 TLS LOCAL EXEC relocation. 4007@end deffn 4008@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4009AArch64 TLS LOCAL EXEC relocation. 4010@end deffn 4011@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4012AArch64 TLS LOCAL EXEC relocation. 4013@end deffn 4014@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4015AArch64 TLS DESC relocation. 4016@end deffn 4017@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4018AArch64 TLS DESC relocation. 4019@end deffn 4020@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4021AArch64 TLS DESC relocation. 4022@end deffn 4023@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4024AArch64 TLS DESC relocation. 4025@end deffn 4026@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4027AArch64 TLS DESC relocation. 4028@end deffn 4029@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4030AArch64 TLS DESC relocation. 4031@end deffn 4032@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4033AArch64 TLS DESC relocation. 4034@end deffn 4035@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4036AArch64 TLS DESC relocation. 4037@end deffn 4038@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 4039AArch64 TLS DESC relocation. 4040@end deffn 4041@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 4042AArch64 TLS DESC relocation. 4043@end deffn 4044@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 4045AArch64 TLS DESC relocation. 4046@end deffn 4047@deffn {} BFD_RELOC_AARCH64_COPY 4048AArch64 TLS relocation. 4049@end deffn 4050@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 4051AArch64 TLS relocation. 4052@end deffn 4053@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 4054AArch64 TLS relocation. 4055@end deffn 4056@deffn {} BFD_RELOC_AARCH64_RELATIVE 4057AArch64 TLS relocation. 4058@end deffn 4059@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4060AArch64 TLS relocation. 4061@end deffn 4062@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 4063AArch64 TLS relocation. 4064@end deffn 4065@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 4066AArch64 TLS relocation. 4067@end deffn 4068@deffn {} BFD_RELOC_AARCH64_TLSDESC 4069AArch64 TLS relocation. 4070@end deffn 4071@deffn {} BFD_RELOC_AARCH64_IRELATIVE 4072AArch64 support for STT_GNU_IFUNC. 4073@end deffn 4074@deffn {} BFD_RELOC_AARCH64_RELOC_END 4075AArch64 pseudo relocation code to mark the end of the AArch64 4076relocation enumerators that have direct mapping to ELF reloc codes. 4077There are a few more enumerators after this one; those are mainly 4078used by the AArch64 assembler for the internal fixup or to select 4079one of the above enumerators. 4080@end deffn 4081@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4082AArch64 pseudo relocation code to be used internally by the AArch64 4083assembler and not (currently) written to any object files. 4084@end deffn 4085@deffn {} BFD_RELOC_AARCH64_LDST_LO12 4086AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4087address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4088@end deffn 4089@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4090AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 4091used internally by the AArch64 assembler and not (currently) written to 4092any object files. 4093@end deffn 4094@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4095Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 4096@end deffn 4097@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4098AArch64 pseudo relocation code to be used internally by the AArch64 4099assembler and not (currently) written to any object files. 4100@end deffn 4101@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4102AArch64 pseudo relocation code to be used internally by the AArch64 4103assembler and not (currently) written to any object files. 4104@end deffn 4105@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4106AArch64 pseudo relocation code to be used internally by the AArch64 4107assembler and not (currently) written to any object files. 4108@end deffn 4109@deffn {} BFD_RELOC_TILEPRO_COPY 4110@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4111@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4112@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4113@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4114@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4115@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4116@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4117@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4118@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4119@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4120@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4121@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4122@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4123@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4124@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4125@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4126@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4127@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4128@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4129@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4130@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4131@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4132@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4133@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4134@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4135@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4136@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4137@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4138@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4139@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4140@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4141@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4142@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4143@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4144@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4145@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4146@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4147@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4148@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4149@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4150@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4151@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4152@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4153@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4154@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4155@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4156@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4157@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4158@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4159@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4160@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4161@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4162@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4163@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4164@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4165@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4166@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4167@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4168@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4169@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4170@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4171@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4172@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4173@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4174@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4175@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4176@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4177@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4178@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4179@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4180@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4181@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4182@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4183@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4184@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4185@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4186@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4187@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4188Tilera TILEPro Relocations. 4189@end deffn 4190@deffn {} BFD_RELOC_TILEGX_HW0 4191@deffnx {} BFD_RELOC_TILEGX_HW1 4192@deffnx {} BFD_RELOC_TILEGX_HW2 4193@deffnx {} BFD_RELOC_TILEGX_HW3 4194@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4195@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4196@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4197@deffnx {} BFD_RELOC_TILEGX_COPY 4198@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4199@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4200@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4201@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4202@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4203@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4204@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4205@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4206@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4207@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4208@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4209@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4210@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4211@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4212@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4213@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4214@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4215@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4216@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4217@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4218@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4219@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4220@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4221@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4222@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4223@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4224@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4225@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4226@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4227@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4228@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4229@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4230@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4231@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4232@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4233@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4234@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4235@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4236@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4237@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4238@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4239@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4240@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4241@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4242@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4243@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4244@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4245@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4246@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4247@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4248@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4249@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4250@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4251@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4252@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4253@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4254@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4255@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4256@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4257@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4258@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4259@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4260@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4261@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4262@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4263@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4264@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4265@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4266@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4267@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4268@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4269@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4270@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4271@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4272@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4273@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4274@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4275@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4276@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4277@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4278@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4279@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4280@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4281@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4282@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4283@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4284@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4285@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4286@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4287@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4288@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4289@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4290@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4291@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4292@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4293@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4294@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4295@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4296@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4297@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4298@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4299Tilera TILE-Gx Relocations. 4300@end deffn 4301@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4302Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4303@end deffn 4304@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4305Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4306@end deffn 4307@deffn {} BFD_RELOC_EPIPHANY_HIGH 4308Adapteva EPIPHANY - 16 most-significant bits of absolute address 4309@end deffn 4310@deffn {} BFD_RELOC_EPIPHANY_LOW 4311Adapteva EPIPHANY - 16 least-significant bits of absolute address 4312@end deffn 4313@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4314Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4315@end deffn 4316@deffn {} BFD_RELOC_EPIPHANY_IMM11 4317Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4318@end deffn 4319@deffn {} BFD_RELOC_EPIPHANY_IMM8 4320Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4321@end deffn 4322@deffn {} BFD_RELOC_VISIUM_HI16 4323@deffnx {} BFD_RELOC_VISIUM_LO16 4324@deffnx {} BFD_RELOC_VISIUM_IM16 4325@deffnx {} BFD_RELOC_VISIUM_REL16 4326@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4327@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4328@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4329Visium Relocations. 4330@end deffn 4331@deffn {} BFD_RELOC_WASM32_LEB128 4332@deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4333@deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4334@deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4335@deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4336@deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4337@deffnx {} BFD_RELOC_WASM32_COPY 4338@deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4339@deffnx {} BFD_RELOC_WASM32_INDEX 4340@deffnx {} BFD_RELOC_WASM32_PLT_SIG 4341WebAssembly relocations. 4342@end deffn 4343 4344@example 4345 4346typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4347@end example 4348@findex bfd_reloc_type_lookup 4349@subsubsection @code{bfd_reloc_type_lookup} 4350@strong{Synopsis} 4351@example 4352reloc_howto_type *bfd_reloc_type_lookup 4353 (bfd *abfd, bfd_reloc_code_real_type code); 4354reloc_howto_type *bfd_reloc_name_lookup 4355 (bfd *abfd, const char *reloc_name); 4356@end example 4357@strong{Description}@* 4358Return a pointer to a howto structure which, when 4359invoked, will perform the relocation @var{code} on data from the 4360architecture noted. 4361 4362@findex bfd_default_reloc_type_lookup 4363@subsubsection @code{bfd_default_reloc_type_lookup} 4364@strong{Synopsis} 4365@example 4366reloc_howto_type *bfd_default_reloc_type_lookup 4367 (bfd *abfd, bfd_reloc_code_real_type code); 4368@end example 4369@strong{Description}@* 4370Provides a default relocation lookup routine for any architecture. 4371 4372@findex bfd_get_reloc_code_name 4373@subsubsection @code{bfd_get_reloc_code_name} 4374@strong{Synopsis} 4375@example 4376const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4377@end example 4378@strong{Description}@* 4379Provides a printable name for the supplied relocation code. 4380Useful mainly for printing error messages. 4381 4382@findex bfd_generic_relax_section 4383@subsubsection @code{bfd_generic_relax_section} 4384@strong{Synopsis} 4385@example 4386bfd_boolean bfd_generic_relax_section 4387 (bfd *abfd, 4388 asection *section, 4389 struct bfd_link_info *, 4390 bfd_boolean *); 4391@end example 4392@strong{Description}@* 4393Provides default handling for relaxing for back ends which 4394don't do relaxing. 4395 4396@findex bfd_generic_gc_sections 4397@subsubsection @code{bfd_generic_gc_sections} 4398@strong{Synopsis} 4399@example 4400bfd_boolean bfd_generic_gc_sections 4401 (bfd *, struct bfd_link_info *); 4402@end example 4403@strong{Description}@* 4404Provides default handling for relaxing for back ends which 4405don't do section gc -- i.e., does nothing. 4406 4407@findex bfd_generic_lookup_section_flags 4408@subsubsection @code{bfd_generic_lookup_section_flags} 4409@strong{Synopsis} 4410@example 4411bfd_boolean bfd_generic_lookup_section_flags 4412 (struct bfd_link_info *, struct flag_info *, asection *); 4413@end example 4414@strong{Description}@* 4415Provides default handling for section flags lookup 4416-- i.e., does nothing. 4417Returns FALSE if the section should be omitted, otherwise TRUE. 4418 4419@findex bfd_generic_merge_sections 4420@subsubsection @code{bfd_generic_merge_sections} 4421@strong{Synopsis} 4422@example 4423bfd_boolean bfd_generic_merge_sections 4424 (bfd *, struct bfd_link_info *); 4425@end example 4426@strong{Description}@* 4427Provides default handling for SEC_MERGE section merging for back ends 4428which don't have SEC_MERGE support -- i.e., does nothing. 4429 4430@findex bfd_generic_get_relocated_section_contents 4431@subsubsection @code{bfd_generic_get_relocated_section_contents} 4432@strong{Synopsis} 4433@example 4434bfd_byte *bfd_generic_get_relocated_section_contents 4435 (bfd *abfd, 4436 struct bfd_link_info *link_info, 4437 struct bfd_link_order *link_order, 4438 bfd_byte *data, 4439 bfd_boolean relocatable, 4440 asymbol **symbols); 4441@end example 4442@strong{Description}@* 4443Provides default handling of relocation effort for back ends 4444which can't be bothered to do it efficiently. 4445 4446@findex _bfd_generic_set_reloc 4447@subsubsection @code{_bfd_generic_set_reloc} 4448@strong{Synopsis} 4449@example 4450void _bfd_generic_set_reloc 4451 (bfd *abfd, 4452 sec_ptr section, 4453 arelent **relptr, 4454 unsigned int count); 4455@end example 4456@strong{Description}@* 4457Installs a new set of internal relocations in SECTION. 4458 4459@findex _bfd_unrecognized_reloc 4460@subsubsection @code{_bfd_unrecognized_reloc} 4461@strong{Synopsis} 4462@example 4463bfd_boolean _bfd_unrecognized_reloc 4464 (bfd * abfd, 4465 sec_ptr section, 4466 unsigned int r_type); 4467@end example 4468@strong{Description}@* 4469Reports an unrecognized reloc. 4470Written as a function in order to reduce code duplication. 4471Returns FALSE so that it can be called from a return statement. 4472 4473