reloc.texi revision 1.3
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* The relocation is relative to the field being relocated. */ 285 bfd_boolean pc_relative; 286 287 /* The bit position of the reloc value in the destination. 288 The relocated value is left shifted by this amount. */ 289 unsigned int bitpos; 290 291 /* What type of overflow error should be checked for when 292 relocating. */ 293 enum complain_overflow complain_on_overflow; 294 295 /* If this field is non null, then the supplied function is 296 called rather than the normal function. This allows really 297 strange relocation methods to be accommodated (e.g., i960 callj 298 instructions). */ 299 bfd_reloc_status_type (*special_function) 300 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 301 bfd *, char **); 302 303 /* The textual name of the relocation type. */ 304 char *name; 305 306 /* Some formats record a relocation addend in the section contents 307 rather than with the relocation. For ELF formats this is the 308 distinction between USE_REL and USE_RELA (though the code checks 309 for USE_REL == 1/0). The value of this field is TRUE if the 310 addend is recorded with the section contents; when performing a 311 partial link (ld -r) the section contents (the data) will be 312 modified. The value of this field is FALSE if addends are 313 recorded with the relocation (in arelent.addend); when performing 314 a partial link the relocation will be modified. 315 All relocations for all ELF USE_RELA targets should set this field 316 to FALSE (values of TRUE should be looked on with suspicion). 317 However, the converse is not true: not all relocations of all ELF 318 USE_REL targets set this field to TRUE. Why this is so is peculiar 319 to each particular target. For relocs that aren't used in partial 320 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 321 bfd_boolean partial_inplace; 322 323 /* src_mask selects the part of the instruction (or data) to be used 324 in the relocation sum. If the target relocations don't have an 325 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 326 dst_mask to extract the addend from the section contents. If 327 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 328 field should be zero. Non-zero values for ELF USE_RELA targets are 329 bogus as in those cases the value in the dst_mask part of the 330 section contents should be treated as garbage. */ 331 bfd_vma src_mask; 332 333 /* dst_mask selects which parts of the instruction (or data) are 334 replaced with a relocated value. */ 335 bfd_vma dst_mask; 336 337 /* When some formats create PC relative instructions, they leave 338 the value of the pc of the place being relocated in the offset 339 slot of the instruction, so that a PC relative relocation can 340 be made just by adding in an ordinary offset (e.g., sun3 a.out). 341 Some formats leave the displacement part of an instruction 342 empty (e.g., m88k bcs); this flag signals the fact. */ 343 bfd_boolean pcrel_offset; 344@}; 345 346@end example 347@findex The HOWTO Macro 348@subsubsection @code{The HOWTO Macro} 349@strong{Description}@* 350The HOWTO define is horrible and will go away. 351@example 352#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 353 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 354@end example 355 356@strong{Description}@* 357And will be replaced with the totally magic way. But for the 358moment, we are compatible, so do it this way. 359@example 360#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 361 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 362 NAME, FALSE, 0, 0, IN) 363 364@end example 365 366@strong{Description}@* 367This is used to fill in an empty howto entry in an array. 368@example 369#define EMPTY_HOWTO(C) \ 370 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 371 NULL, FALSE, 0, 0, FALSE) 372 373@end example 374 375@strong{Description}@* 376Helper routine to turn a symbol into a relocation value. 377@example 378#define HOWTO_PREPARE(relocation, symbol) \ 379 @{ \ 380 if (symbol != NULL) \ 381 @{ \ 382 if (bfd_is_com_section (symbol->section)) \ 383 @{ \ 384 relocation = 0; \ 385 @} \ 386 else \ 387 @{ \ 388 relocation = symbol->value; \ 389 @} \ 390 @} \ 391 @} 392 393@end example 394 395@findex bfd_get_reloc_size 396@subsubsection @code{bfd_get_reloc_size} 397@strong{Synopsis} 398@example 399unsigned int bfd_get_reloc_size (reloc_howto_type *); 400@end example 401@strong{Description}@* 402For a reloc_howto_type that operates on a fixed number of bytes, 403this returns the number of bytes operated on. 404 405@findex arelent_chain 406@subsubsection @code{arelent_chain} 407@strong{Description}@* 408How relocs are tied together in an @code{asection}: 409@example 410typedef struct relent_chain 411@{ 412 arelent relent; 413 struct relent_chain *next; 414@} 415arelent_chain; 416 417@end example 418 419@findex bfd_check_overflow 420@subsubsection @code{bfd_check_overflow} 421@strong{Synopsis} 422@example 423bfd_reloc_status_type bfd_check_overflow 424 (enum complain_overflow how, 425 unsigned int bitsize, 426 unsigned int rightshift, 427 unsigned int addrsize, 428 bfd_vma relocation); 429@end example 430@strong{Description}@* 431Perform overflow checking on @var{relocation} which has 432@var{bitsize} significant bits and will be shifted right by 433@var{rightshift} bits, on a machine with addresses containing 434@var{addrsize} significant bits. The result is either of 435@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 436 437@findex bfd_perform_relocation 438@subsubsection @code{bfd_perform_relocation} 439@strong{Synopsis} 440@example 441bfd_reloc_status_type bfd_perform_relocation 442 (bfd *abfd, 443 arelent *reloc_entry, 444 void *data, 445 asection *input_section, 446 bfd *output_bfd, 447 char **error_message); 448@end example 449@strong{Description}@* 450If @var{output_bfd} is supplied to this function, the 451generated image will be relocatable; the relocations are 452copied to the output file after they have been changed to 453reflect the new state of the world. There are two ways of 454reflecting the results of partial linkage in an output file: 455by modifying the output data in place, and by modifying the 456relocation record. Some native formats (e.g., basic a.out and 457basic coff) have no way of specifying an addend in the 458relocation type, so the addend has to go in the output data. 459This is no big deal since in these formats the output data 460slot will always be big enough for the addend. Complex reloc 461types with addends were invented to solve just this problem. 462The @var{error_message} argument is set to an error message if 463this return @code{bfd_reloc_dangerous}. 464 465@findex bfd_install_relocation 466@subsubsection @code{bfd_install_relocation} 467@strong{Synopsis} 468@example 469bfd_reloc_status_type bfd_install_relocation 470 (bfd *abfd, 471 arelent *reloc_entry, 472 void *data, bfd_vma data_start, 473 asection *input_section, 474 char **error_message); 475@end example 476@strong{Description}@* 477This looks remarkably like @code{bfd_perform_relocation}, except it 478does not expect that the section contents have been filled in. 479I.e., it's suitable for use when creating, rather than applying 480a relocation. 481 482For now, this function should be considered reserved for the 483assembler. 484 485 486@node howto manager, , typedef arelent, Relocations 487@subsection The howto manager 488When an application wants to create a relocation, but doesn't 489know what the target machine might call it, it can find out by 490using this bit of code. 491 492@findex bfd_reloc_code_type 493@subsubsection @code{bfd_reloc_code_type} 494@strong{Description}@* 495The insides of a reloc code. The idea is that, eventually, there 496will be one enumerator for every type of relocation we ever do. 497Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 498return a howto pointer. 499 500This does mean that the application must determine the correct 501enumerator value; you can't get a howto pointer from a random set 502of attributes. 503 504Here are the possible values for @code{enum bfd_reloc_code_real}: 505 506@deffn {} BFD_RELOC_64 507@deffnx {} BFD_RELOC_32 508@deffnx {} BFD_RELOC_26 509@deffnx {} BFD_RELOC_24 510@deffnx {} BFD_RELOC_16 511@deffnx {} BFD_RELOC_14 512@deffnx {} BFD_RELOC_8 513Basic absolute relocations of N bits. 514@end deffn 515@deffn {} BFD_RELOC_64_PCREL 516@deffnx {} BFD_RELOC_32_PCREL 517@deffnx {} BFD_RELOC_24_PCREL 518@deffnx {} BFD_RELOC_16_PCREL 519@deffnx {} BFD_RELOC_12_PCREL 520@deffnx {} BFD_RELOC_8_PCREL 521PC-relative relocations. Sometimes these are relative to the address 522of the relocation itself; sometimes they are relative to the start of 523the section containing the relocation. It depends on the specific target. 524 525The 24-bit relocation is used in some Intel 960 configurations. 526@end deffn 527@deffn {} BFD_RELOC_32_SECREL 528Section relative relocations. Some targets need this for DWARF2. 529@end deffn 530@deffn {} BFD_RELOC_32_GOT_PCREL 531@deffnx {} BFD_RELOC_16_GOT_PCREL 532@deffnx {} BFD_RELOC_8_GOT_PCREL 533@deffnx {} BFD_RELOC_32_GOTOFF 534@deffnx {} BFD_RELOC_16_GOTOFF 535@deffnx {} BFD_RELOC_LO16_GOTOFF 536@deffnx {} BFD_RELOC_HI16_GOTOFF 537@deffnx {} BFD_RELOC_HI16_S_GOTOFF 538@deffnx {} BFD_RELOC_8_GOTOFF 539@deffnx {} BFD_RELOC_64_PLT_PCREL 540@deffnx {} BFD_RELOC_32_PLT_PCREL 541@deffnx {} BFD_RELOC_24_PLT_PCREL 542@deffnx {} BFD_RELOC_16_PLT_PCREL 543@deffnx {} BFD_RELOC_8_PLT_PCREL 544@deffnx {} BFD_RELOC_64_PLTOFF 545@deffnx {} BFD_RELOC_32_PLTOFF 546@deffnx {} BFD_RELOC_16_PLTOFF 547@deffnx {} BFD_RELOC_LO16_PLTOFF 548@deffnx {} BFD_RELOC_HI16_PLTOFF 549@deffnx {} BFD_RELOC_HI16_S_PLTOFF 550@deffnx {} BFD_RELOC_8_PLTOFF 551For ELF. 552@end deffn 553@deffn {} BFD_RELOC_68K_GLOB_DAT 554@deffnx {} BFD_RELOC_68K_JMP_SLOT 555@deffnx {} BFD_RELOC_68K_RELATIVE 556@deffnx {} BFD_RELOC_68K_TLS_GD32 557@deffnx {} BFD_RELOC_68K_TLS_GD16 558@deffnx {} BFD_RELOC_68K_TLS_GD8 559@deffnx {} BFD_RELOC_68K_TLS_LDM32 560@deffnx {} BFD_RELOC_68K_TLS_LDM16 561@deffnx {} BFD_RELOC_68K_TLS_LDM8 562@deffnx {} BFD_RELOC_68K_TLS_LDO32 563@deffnx {} BFD_RELOC_68K_TLS_LDO16 564@deffnx {} BFD_RELOC_68K_TLS_LDO8 565@deffnx {} BFD_RELOC_68K_TLS_IE32 566@deffnx {} BFD_RELOC_68K_TLS_IE16 567@deffnx {} BFD_RELOC_68K_TLS_IE8 568@deffnx {} BFD_RELOC_68K_TLS_LE32 569@deffnx {} BFD_RELOC_68K_TLS_LE16 570@deffnx {} BFD_RELOC_68K_TLS_LE8 571Relocations used by 68K ELF. 572@end deffn 573@deffn {} BFD_RELOC_VAX_GLOB_DAT 574@deffnx {} BFD_RELOC_VAX_GLOB_REF 575@deffnx {} BFD_RELOC_VAX_JMP_SLOT 576@deffnx {} BFD_RELOC_VAX_RELATIVE 577Relocations used by VAX ELF. 578@end deffn 579@deffn {} BFD_RELOC_32_BASEREL 580@deffnx {} BFD_RELOC_16_BASEREL 581@deffnx {} BFD_RELOC_LO16_BASEREL 582@deffnx {} BFD_RELOC_HI16_BASEREL 583@deffnx {} BFD_RELOC_HI16_S_BASEREL 584@deffnx {} BFD_RELOC_8_BASEREL 585@deffnx {} BFD_RELOC_RVA 586Linkage-table relative. 587@end deffn 588@deffn {} BFD_RELOC_8_FFnn 589Absolute 8-bit relocation, but used to form an address like 0xFFnn. 590@end deffn 591@deffn {} BFD_RELOC_32_PCREL_S2 592@deffnx {} BFD_RELOC_16_PCREL_S2 593@deffnx {} BFD_RELOC_23_PCREL_S2 594These PC-relative relocations are stored as word displacements -- 595i.e., byte displacements shifted right two bits. The 30-bit word 596displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 597SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 598signed 16-bit displacement is used on the MIPS, and the 23-bit 599displacement is used on the Alpha. 600@end deffn 601@deffn {} BFD_RELOC_HI22 602@deffnx {} BFD_RELOC_LO10 603High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 604the target word. These are used on the SPARC. 605@end deffn 606@deffn {} BFD_RELOC_GPREL16 607@deffnx {} BFD_RELOC_GPREL32 608For systems that allocate a Global Pointer register, these are 609displacements off that register. These relocation types are 610handled specially, because the value the register will have is 611decided relatively late. 612@end deffn 613@deffn {} BFD_RELOC_I960_CALLJ 614Reloc types used for i960/b.out. 615@end deffn 616@deffn {} BFD_RELOC_NONE 617@deffnx {} BFD_RELOC_SPARC_WDISP22 618@deffnx {} BFD_RELOC_SPARC22 619@deffnx {} BFD_RELOC_SPARC13 620@deffnx {} BFD_RELOC_SPARC_GOT10 621@deffnx {} BFD_RELOC_SPARC_GOT13 622@deffnx {} BFD_RELOC_SPARC_GOT22 623@deffnx {} BFD_RELOC_SPARC_PC10 624@deffnx {} BFD_RELOC_SPARC_PC22 625@deffnx {} BFD_RELOC_SPARC_WPLT30 626@deffnx {} BFD_RELOC_SPARC_COPY 627@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 628@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 629@deffnx {} BFD_RELOC_SPARC_RELATIVE 630@deffnx {} BFD_RELOC_SPARC_UA16 631@deffnx {} BFD_RELOC_SPARC_UA32 632@deffnx {} BFD_RELOC_SPARC_UA64 633@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 634@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 635@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 636@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 637@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 638@deffnx {} BFD_RELOC_SPARC_JMP_IREL 639@deffnx {} BFD_RELOC_SPARC_IRELATIVE 640SPARC ELF relocations. There is probably some overlap with other 641relocation types already defined. 642@end deffn 643@deffn {} BFD_RELOC_SPARC_BASE13 644@deffnx {} BFD_RELOC_SPARC_BASE22 645I think these are specific to SPARC a.out (e.g., Sun 4). 646@end deffn 647@deffn {} BFD_RELOC_SPARC_64 648@deffnx {} BFD_RELOC_SPARC_10 649@deffnx {} BFD_RELOC_SPARC_11 650@deffnx {} BFD_RELOC_SPARC_OLO10 651@deffnx {} BFD_RELOC_SPARC_HH22 652@deffnx {} BFD_RELOC_SPARC_HM10 653@deffnx {} BFD_RELOC_SPARC_LM22 654@deffnx {} BFD_RELOC_SPARC_PC_HH22 655@deffnx {} BFD_RELOC_SPARC_PC_HM10 656@deffnx {} BFD_RELOC_SPARC_PC_LM22 657@deffnx {} BFD_RELOC_SPARC_WDISP16 658@deffnx {} BFD_RELOC_SPARC_WDISP19 659@deffnx {} BFD_RELOC_SPARC_7 660@deffnx {} BFD_RELOC_SPARC_6 661@deffnx {} BFD_RELOC_SPARC_5 662@deffnx {} BFD_RELOC_SPARC_DISP64 663@deffnx {} BFD_RELOC_SPARC_PLT32 664@deffnx {} BFD_RELOC_SPARC_PLT64 665@deffnx {} BFD_RELOC_SPARC_HIX22 666@deffnx {} BFD_RELOC_SPARC_LOX10 667@deffnx {} BFD_RELOC_SPARC_H44 668@deffnx {} BFD_RELOC_SPARC_M44 669@deffnx {} BFD_RELOC_SPARC_L44 670@deffnx {} BFD_RELOC_SPARC_REGISTER 671@deffnx {} BFD_RELOC_SPARC_H34 672@deffnx {} BFD_RELOC_SPARC_SIZE32 673@deffnx {} BFD_RELOC_SPARC_SIZE64 674@deffnx {} BFD_RELOC_SPARC_WDISP10 675SPARC64 relocations 676@end deffn 677@deffn {} BFD_RELOC_SPARC_REV32 678SPARC little endian relocation 679@end deffn 680@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 681@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 682@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 683@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 684@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 685@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 686@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 687@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 688@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 689@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 690@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 691@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 692@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 693@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 694@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 695@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 696@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 697@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 698@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 699@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 700@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 701@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 702@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 703@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 704SPARC TLS relocations 705@end deffn 706@deffn {} BFD_RELOC_SPU_IMM7 707@deffnx {} BFD_RELOC_SPU_IMM8 708@deffnx {} BFD_RELOC_SPU_IMM10 709@deffnx {} BFD_RELOC_SPU_IMM10W 710@deffnx {} BFD_RELOC_SPU_IMM16 711@deffnx {} BFD_RELOC_SPU_IMM16W 712@deffnx {} BFD_RELOC_SPU_IMM18 713@deffnx {} BFD_RELOC_SPU_PCREL9a 714@deffnx {} BFD_RELOC_SPU_PCREL9b 715@deffnx {} BFD_RELOC_SPU_PCREL16 716@deffnx {} BFD_RELOC_SPU_LO16 717@deffnx {} BFD_RELOC_SPU_HI16 718@deffnx {} BFD_RELOC_SPU_PPU32 719@deffnx {} BFD_RELOC_SPU_PPU64 720@deffnx {} BFD_RELOC_SPU_ADD_PIC 721SPU Relocations. 722@end deffn 723@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 724Alpha ECOFF and ELF relocations. Some of these treat the symbol or 725"addend" in some special way. 726For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 727writing; when reading, it will be the absolute section symbol. The 728addend is the displacement in bytes of the "lda" instruction from 729the "ldah" instruction (which is at the address of this reloc). 730@end deffn 731@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 732For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 733with GPDISP_HI16 relocs. The addend is ignored when writing the 734relocations out, and is filled in with the file's GP value on 735reading, for convenience. 736@end deffn 737@deffn {} BFD_RELOC_ALPHA_GPDISP 738The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 739relocation except that there is no accompanying GPDISP_LO16 740relocation. 741@end deffn 742@deffn {} BFD_RELOC_ALPHA_LITERAL 743@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 744@deffnx {} BFD_RELOC_ALPHA_LITUSE 745The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 746the assembler turns it into a LDQ instruction to load the address of 747the symbol, and then fills in a register in the real instruction. 748 749The LITERAL reloc, at the LDQ instruction, refers to the .lita 750section symbol. The addend is ignored when writing, but is filled 751in with the file's GP value on reading, for convenience, as with the 752GPDISP_LO16 reloc. 753 754The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 755It should refer to the symbol to be referenced, as with 16_GOTOFF, 756but it generates output not based on the position within the .got 757section, but relative to the GP value chosen for the file during the 758final link stage. 759 760The LITUSE reloc, on the instruction using the loaded address, gives 761information to the linker that it might be able to use to optimize 762away some literal section references. The symbol is ignored (read 763as the absolute section symbol), and the "addend" indicates the type 764of instruction using the register: 7651 - "memory" fmt insn 7662 - byte-manipulation (byte offset reg) 7673 - jsr (target of branch) 768@end deffn 769@deffn {} BFD_RELOC_ALPHA_HINT 770The HINT relocation indicates a value that should be filled into the 771"hint" field of a jmp/jsr/ret instruction, for possible branch- 772prediction logic which may be provided on some processors. 773@end deffn 774@deffn {} BFD_RELOC_ALPHA_LINKAGE 775The LINKAGE relocation outputs a linkage pair in the object file, 776which is filled by the linker. 777@end deffn 778@deffn {} BFD_RELOC_ALPHA_CODEADDR 779The CODEADDR relocation outputs a STO_CA in the object file, 780which is filled by the linker. 781@end deffn 782@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 783@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 784The GPREL_HI/LO relocations together form a 32-bit offset from the 785GP register. 786@end deffn 787@deffn {} BFD_RELOC_ALPHA_BRSGP 788Like BFD_RELOC_23_PCREL_S2, except that the source and target must 789share a common GP, and the target address is adjusted for 790STO_ALPHA_STD_GPLOAD. 791@end deffn 792@deffn {} BFD_RELOC_ALPHA_NOP 793The NOP relocation outputs a NOP if the longword displacement 794between two procedure entry points is < 2^21. 795@end deffn 796@deffn {} BFD_RELOC_ALPHA_BSR 797The BSR relocation outputs a BSR if the longword displacement 798between two procedure entry points is < 2^21. 799@end deffn 800@deffn {} BFD_RELOC_ALPHA_LDA 801The LDA relocation outputs a LDA if the longword displacement 802between two procedure entry points is < 2^16. 803@end deffn 804@deffn {} BFD_RELOC_ALPHA_BOH 805The BOH relocation outputs a BSR if the longword displacement 806between two procedure entry points is < 2^21, or else a hint. 807@end deffn 808@deffn {} BFD_RELOC_ALPHA_TLSGD 809@deffnx {} BFD_RELOC_ALPHA_TLSLDM 810@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 811@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 812@deffnx {} BFD_RELOC_ALPHA_DTPREL64 813@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 814@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 815@deffnx {} BFD_RELOC_ALPHA_DTPREL16 816@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 817@deffnx {} BFD_RELOC_ALPHA_TPREL64 818@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 819@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 820@deffnx {} BFD_RELOC_ALPHA_TPREL16 821Alpha thread-local storage relocations. 822@end deffn 823@deffn {} BFD_RELOC_MIPS_JMP 824@deffnx {} BFD_RELOC_MICROMIPS_JMP 825The MIPS jump instruction. 826@end deffn 827@deffn {} BFD_RELOC_MIPS16_JMP 828The MIPS16 jump instruction. 829@end deffn 830@deffn {} BFD_RELOC_MIPS16_GPREL 831MIPS16 GP relative reloc. 832@end deffn 833@deffn {} BFD_RELOC_HI16 834High 16 bits of 32-bit value; simple reloc. 835@end deffn 836@deffn {} BFD_RELOC_HI16_S 837High 16 bits of 32-bit value but the low 16 bits will be sign 838extended and added to form the final result. If the low 16 839bits form a negative number, we need to add one to the high value 840to compensate for the borrow when the low bits are added. 841@end deffn 842@deffn {} BFD_RELOC_LO16 843Low 16 bits. 844@end deffn 845@deffn {} BFD_RELOC_HI16_PCREL 846High 16 bits of 32-bit pc-relative value 847@end deffn 848@deffn {} BFD_RELOC_HI16_S_PCREL 849High 16 bits of 32-bit pc-relative value, adjusted 850@end deffn 851@deffn {} BFD_RELOC_LO16_PCREL 852Low 16 bits of pc-relative value 853@end deffn 854@deffn {} BFD_RELOC_MIPS16_GOT16 855@deffnx {} BFD_RELOC_MIPS16_CALL16 856Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 85716-bit immediate fields 858@end deffn 859@deffn {} BFD_RELOC_MIPS16_HI16 860MIPS16 high 16 bits of 32-bit value. 861@end deffn 862@deffn {} BFD_RELOC_MIPS16_HI16_S 863MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 864extended and added to form the final result. If the low 16 865bits form a negative number, we need to add one to the high value 866to compensate for the borrow when the low bits are added. 867@end deffn 868@deffn {} BFD_RELOC_MIPS16_LO16 869MIPS16 low 16 bits. 870@end deffn 871@deffn {} BFD_RELOC_MIPS16_TLS_GD 872@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 873@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 874@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 875@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 876@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 877@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 878MIPS16 TLS relocations 879@end deffn 880@deffn {} BFD_RELOC_MIPS_LITERAL 881@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 882Relocation against a MIPS literal section. 883@end deffn 884@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 885@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 886@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 887microMIPS PC-relative relocations. 888@end deffn 889@deffn {} BFD_RELOC_MICROMIPS_GPREL16 890@deffnx {} BFD_RELOC_MICROMIPS_HI16 891@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 892@deffnx {} BFD_RELOC_MICROMIPS_LO16 893microMIPS versions of generic BFD relocs. 894@end deffn 895@deffn {} BFD_RELOC_MIPS_GOT16 896@deffnx {} BFD_RELOC_MICROMIPS_GOT16 897@deffnx {} BFD_RELOC_MIPS_CALL16 898@deffnx {} BFD_RELOC_MICROMIPS_CALL16 899@deffnx {} BFD_RELOC_MIPS_GOT_HI16 900@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 901@deffnx {} BFD_RELOC_MIPS_GOT_LO16 902@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 903@deffnx {} BFD_RELOC_MIPS_CALL_HI16 904@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 905@deffnx {} BFD_RELOC_MIPS_CALL_LO16 906@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 907@deffnx {} BFD_RELOC_MIPS_SUB 908@deffnx {} BFD_RELOC_MICROMIPS_SUB 909@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 910@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 911@deffnx {} BFD_RELOC_MIPS_GOT_OFST 912@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 913@deffnx {} BFD_RELOC_MIPS_GOT_DISP 914@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 915@deffnx {} BFD_RELOC_MIPS_SHIFT5 916@deffnx {} BFD_RELOC_MIPS_SHIFT6 917@deffnx {} BFD_RELOC_MIPS_INSERT_A 918@deffnx {} BFD_RELOC_MIPS_INSERT_B 919@deffnx {} BFD_RELOC_MIPS_DELETE 920@deffnx {} BFD_RELOC_MIPS_HIGHEST 921@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 922@deffnx {} BFD_RELOC_MIPS_HIGHER 923@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 924@deffnx {} BFD_RELOC_MIPS_SCN_DISP 925@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 926@deffnx {} BFD_RELOC_MIPS_REL16 927@deffnx {} BFD_RELOC_MIPS_RELGOT 928@deffnx {} BFD_RELOC_MIPS_JALR 929@deffnx {} BFD_RELOC_MICROMIPS_JALR 930@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 931@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 932@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 933@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 934@deffnx {} BFD_RELOC_MIPS_TLS_GD 935@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 936@deffnx {} BFD_RELOC_MIPS_TLS_LDM 937@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 938@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 939@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 940@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 941@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 942@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 943@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 944@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 945@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 946@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 947@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 948@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 949@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 950MIPS ELF relocations. 951@end deffn 952@deffn {} BFD_RELOC_MIPS_COPY 953@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 954MIPS ELF relocations (VxWorks and PLT extensions). 955@end deffn 956@deffn {} BFD_RELOC_MOXIE_10_PCREL 957Moxie ELF relocations. 958@end deffn 959@deffn {} BFD_RELOC_FRV_LABEL16 960@deffnx {} BFD_RELOC_FRV_LABEL24 961@deffnx {} BFD_RELOC_FRV_LO16 962@deffnx {} BFD_RELOC_FRV_HI16 963@deffnx {} BFD_RELOC_FRV_GPREL12 964@deffnx {} BFD_RELOC_FRV_GPRELU12 965@deffnx {} BFD_RELOC_FRV_GPREL32 966@deffnx {} BFD_RELOC_FRV_GPRELHI 967@deffnx {} BFD_RELOC_FRV_GPRELLO 968@deffnx {} BFD_RELOC_FRV_GOT12 969@deffnx {} BFD_RELOC_FRV_GOTHI 970@deffnx {} BFD_RELOC_FRV_GOTLO 971@deffnx {} BFD_RELOC_FRV_FUNCDESC 972@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 973@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 974@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 975@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 976@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 977@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 978@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 979@deffnx {} BFD_RELOC_FRV_GOTOFF12 980@deffnx {} BFD_RELOC_FRV_GOTOFFHI 981@deffnx {} BFD_RELOC_FRV_GOTOFFLO 982@deffnx {} BFD_RELOC_FRV_GETTLSOFF 983@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 984@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 985@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 986@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 987@deffnx {} BFD_RELOC_FRV_TLSMOFF12 988@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 989@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 990@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 991@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 992@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 993@deffnx {} BFD_RELOC_FRV_TLSOFF 994@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 995@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 996@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 997@deffnx {} BFD_RELOC_FRV_TLSMOFF 998Fujitsu Frv Relocations. 999@end deffn 1000@deffn {} BFD_RELOC_MN10300_GOTOFF24 1001This is a 24bit GOT-relative reloc for the mn10300. 1002@end deffn 1003@deffn {} BFD_RELOC_MN10300_GOT32 1004This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1005in the instruction. 1006@end deffn 1007@deffn {} BFD_RELOC_MN10300_GOT24 1008This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1009in the instruction. 1010@end deffn 1011@deffn {} BFD_RELOC_MN10300_GOT16 1012This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1013in the instruction. 1014@end deffn 1015@deffn {} BFD_RELOC_MN10300_COPY 1016Copy symbol at runtime. 1017@end deffn 1018@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1019Create GOT entry. 1020@end deffn 1021@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1022Create PLT entry. 1023@end deffn 1024@deffn {} BFD_RELOC_MN10300_RELATIVE 1025Adjust by program base. 1026@end deffn 1027@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1028Together with another reloc targeted at the same location, 1029allows for a value that is the difference of two symbols 1030in the same section. 1031@end deffn 1032@deffn {} BFD_RELOC_MN10300_ALIGN 1033The addend of this reloc is an alignment power that must 1034be honoured at the offset's location, regardless of linker 1035relaxation. 1036@end deffn 1037@deffn {} BFD_RELOC_MN10300_TLS_GD 1038@deffnx {} BFD_RELOC_MN10300_TLS_LD 1039@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1040@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1041@deffnx {} BFD_RELOC_MN10300_TLS_IE 1042@deffnx {} BFD_RELOC_MN10300_TLS_LE 1043@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1044@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1045@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1046Various TLS-related relocations. 1047@end deffn 1048@deffn {} BFD_RELOC_MN10300_32_PCREL 1049This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1050instruction. 1051@end deffn 1052@deffn {} BFD_RELOC_MN10300_16_PCREL 1053This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1054instruction. 1055@end deffn 1056@deffn {} BFD_RELOC_386_GOT32 1057@deffnx {} BFD_RELOC_386_PLT32 1058@deffnx {} BFD_RELOC_386_COPY 1059@deffnx {} BFD_RELOC_386_GLOB_DAT 1060@deffnx {} BFD_RELOC_386_JUMP_SLOT 1061@deffnx {} BFD_RELOC_386_RELATIVE 1062@deffnx {} BFD_RELOC_386_GOTOFF 1063@deffnx {} BFD_RELOC_386_GOTPC 1064@deffnx {} BFD_RELOC_386_TLS_TPOFF 1065@deffnx {} BFD_RELOC_386_TLS_IE 1066@deffnx {} BFD_RELOC_386_TLS_GOTIE 1067@deffnx {} BFD_RELOC_386_TLS_LE 1068@deffnx {} BFD_RELOC_386_TLS_GD 1069@deffnx {} BFD_RELOC_386_TLS_LDM 1070@deffnx {} BFD_RELOC_386_TLS_LDO_32 1071@deffnx {} BFD_RELOC_386_TLS_IE_32 1072@deffnx {} BFD_RELOC_386_TLS_LE_32 1073@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1074@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1075@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1076@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1077@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1078@deffnx {} BFD_RELOC_386_TLS_DESC 1079@deffnx {} BFD_RELOC_386_IRELATIVE 1080i386/elf relocations 1081@end deffn 1082@deffn {} BFD_RELOC_X86_64_GOT32 1083@deffnx {} BFD_RELOC_X86_64_PLT32 1084@deffnx {} BFD_RELOC_X86_64_COPY 1085@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1086@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1087@deffnx {} BFD_RELOC_X86_64_RELATIVE 1088@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1089@deffnx {} BFD_RELOC_X86_64_32S 1090@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1091@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1092@deffnx {} BFD_RELOC_X86_64_TPOFF64 1093@deffnx {} BFD_RELOC_X86_64_TLSGD 1094@deffnx {} BFD_RELOC_X86_64_TLSLD 1095@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1096@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1097@deffnx {} BFD_RELOC_X86_64_TPOFF32 1098@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1099@deffnx {} BFD_RELOC_X86_64_GOTPC32 1100@deffnx {} BFD_RELOC_X86_64_GOT64 1101@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1102@deffnx {} BFD_RELOC_X86_64_GOTPC64 1103@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1104@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1105@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1106@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1107@deffnx {} BFD_RELOC_X86_64_TLSDESC 1108@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1109x86-64/elf relocations 1110@end deffn 1111@deffn {} BFD_RELOC_NS32K_IMM_8 1112@deffnx {} BFD_RELOC_NS32K_IMM_16 1113@deffnx {} BFD_RELOC_NS32K_IMM_32 1114@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1115@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1116@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1117@deffnx {} BFD_RELOC_NS32K_DISP_8 1118@deffnx {} BFD_RELOC_NS32K_DISP_16 1119@deffnx {} BFD_RELOC_NS32K_DISP_32 1120@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1121@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1122@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1123ns32k relocations 1124@end deffn 1125@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1126@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1127PDP11 relocations 1128@end deffn 1129@deffn {} BFD_RELOC_PJ_CODE_HI16 1130@deffnx {} BFD_RELOC_PJ_CODE_LO16 1131@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1132@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1133@deffnx {} BFD_RELOC_PJ_CODE_REL16 1134@deffnx {} BFD_RELOC_PJ_CODE_REL32 1135Picojava relocs. Not all of these appear in object files. 1136@end deffn 1137@deffn {} BFD_RELOC_PPC_B26 1138@deffnx {} BFD_RELOC_PPC_BA26 1139@deffnx {} BFD_RELOC_PPC_TOC16 1140@deffnx {} BFD_RELOC_PPC_B16 1141@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1142@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1143@deffnx {} BFD_RELOC_PPC_BA16 1144@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1145@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1146@deffnx {} BFD_RELOC_PPC_COPY 1147@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1148@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1149@deffnx {} BFD_RELOC_PPC_RELATIVE 1150@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1151@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1152@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1153@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1154@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1155@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1156@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1157@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1158@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1159@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1160@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1161@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1162@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1163@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1164@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1165@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1166@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1167@deffnx {} BFD_RELOC_PPC_VLE_REL8 1168@deffnx {} BFD_RELOC_PPC_VLE_REL15 1169@deffnx {} BFD_RELOC_PPC_VLE_REL24 1170@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1171@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1172@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1173@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1174@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1175@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1176@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1177@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1178@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1179@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1180@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1181@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1182@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1183@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1184@deffnx {} BFD_RELOC_PPC64_HIGHER 1185@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1186@deffnx {} BFD_RELOC_PPC64_HIGHEST 1187@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1188@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1189@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1190@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1191@deffnx {} BFD_RELOC_PPC64_TOC 1192@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1193@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1194@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1195@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1196@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1197@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1198@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1199@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1200@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1201@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1202@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1203@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1204@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1205@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1206@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1207Power(rs6000) and PowerPC relocations. 1208@end deffn 1209@deffn {} BFD_RELOC_PPC_TLS 1210@deffnx {} BFD_RELOC_PPC_TLSGD 1211@deffnx {} BFD_RELOC_PPC_TLSLD 1212@deffnx {} BFD_RELOC_PPC_DTPMOD 1213@deffnx {} BFD_RELOC_PPC_TPREL16 1214@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1215@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1216@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1217@deffnx {} BFD_RELOC_PPC_TPREL 1218@deffnx {} BFD_RELOC_PPC_DTPREL16 1219@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1220@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1221@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1222@deffnx {} BFD_RELOC_PPC_DTPREL 1223@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1224@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1225@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1226@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1227@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1228@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1229@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1230@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1231@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1232@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1233@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1234@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1235@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1236@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1237@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1238@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1239@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1240@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1241@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1242@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1243@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1244@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1245@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1246@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1247@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1248@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1249@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1250@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1251PowerPC and PowerPC64 thread-local storage relocations. 1252@end deffn 1253@deffn {} BFD_RELOC_I370_D12 1254IBM 370/390 relocations 1255@end deffn 1256@deffn {} BFD_RELOC_CTOR 1257The type of reloc used to build a constructor table - at the moment 1258probably a 32 bit wide absolute relocation, but the target can choose. 1259It generally does map to one of the other relocation types. 1260@end deffn 1261@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1262ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1263not stored in the instruction. 1264@end deffn 1265@deffn {} BFD_RELOC_ARM_PCREL_BLX 1266ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1267not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1268field in the instruction. 1269@end deffn 1270@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1271Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1272not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1273field in the instruction. 1274@end deffn 1275@deffn {} BFD_RELOC_ARM_PCREL_CALL 1276ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1277@end deffn 1278@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1279ARM 26-bit pc-relative branch for B or conditional BL instruction. 1280@end deffn 1281@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1282@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1283@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1284@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1285@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1286@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1287Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1288The lowest bit must be zero and is not stored in the instruction. 1289Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1290"nn" one smaller in all cases. Note further that BRANCH23 1291corresponds to R_ARM_THM_CALL. 1292@end deffn 1293@deffn {} BFD_RELOC_ARM_OFFSET_IMM 129412-bit immediate offset, used in ARM-format ldr and str instructions. 1295@end deffn 1296@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 12975-bit immediate offset, used in Thumb-format ldr and str instructions. 1298@end deffn 1299@deffn {} BFD_RELOC_ARM_TARGET1 1300Pc-relative or absolute relocation depending on target. Used for 1301entries in .init_array sections. 1302@end deffn 1303@deffn {} BFD_RELOC_ARM_ROSEGREL32 1304Read-only segment base relative address. 1305@end deffn 1306@deffn {} BFD_RELOC_ARM_SBREL32 1307Data segment base relative address. 1308@end deffn 1309@deffn {} BFD_RELOC_ARM_TARGET2 1310This reloc is used for references to RTTI data from exception handling 1311tables. The actual definition depends on the target. It may be a 1312pc-relative or some form of GOT-indirect relocation. 1313@end deffn 1314@deffn {} BFD_RELOC_ARM_PREL31 131531-bit PC relative address. 1316@end deffn 1317@deffn {} BFD_RELOC_ARM_MOVW 1318@deffnx {} BFD_RELOC_ARM_MOVT 1319@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1320@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1321@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1322@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1323@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1324@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1325Low and High halfword relocations for MOVW and MOVT instructions. 1326@end deffn 1327@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1328@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1329@deffnx {} BFD_RELOC_ARM_GOT32 1330@deffnx {} BFD_RELOC_ARM_PLT32 1331@deffnx {} BFD_RELOC_ARM_RELATIVE 1332@deffnx {} BFD_RELOC_ARM_GOTOFF 1333@deffnx {} BFD_RELOC_ARM_GOTPC 1334@deffnx {} BFD_RELOC_ARM_GOT_PREL 1335Relocations for setting up GOTs and PLTs for shared libraries. 1336@end deffn 1337@deffn {} BFD_RELOC_ARM_TLS_GD32 1338@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1339@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1340@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1341@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1342@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1343@deffnx {} BFD_RELOC_ARM_TLS_IE32 1344@deffnx {} BFD_RELOC_ARM_TLS_LE32 1345@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1346@deffnx {} BFD_RELOC_ARM_TLS_CALL 1347@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1348@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1349@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1350@deffnx {} BFD_RELOC_ARM_TLS_DESC 1351ARM thread-local storage relocations. 1352@end deffn 1353@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1354@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1355@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1356@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1357@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1358@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1359@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1360@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1361@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1362@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1363@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1364@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1365@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1366@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1367@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1368@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1369@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1370@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1371@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1372@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1373@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1374@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1375@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1376@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1377@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1378@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1379@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1380@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1381ARM group relocations. 1382@end deffn 1383@deffn {} BFD_RELOC_ARM_V4BX 1384Annotation of BX instructions. 1385@end deffn 1386@deffn {} BFD_RELOC_ARM_IRELATIVE 1387ARM support for STT_GNU_IFUNC. 1388@end deffn 1389@deffn {} BFD_RELOC_ARM_IMMEDIATE 1390@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1391@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1392@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1393@deffnx {} BFD_RELOC_ARM_T32_IMM12 1394@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1395@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1396@deffnx {} BFD_RELOC_ARM_SMC 1397@deffnx {} BFD_RELOC_ARM_HVC 1398@deffnx {} BFD_RELOC_ARM_SWI 1399@deffnx {} BFD_RELOC_ARM_MULTI 1400@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1401@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1402@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1403@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1404@deffnx {} BFD_RELOC_ARM_ADR_IMM 1405@deffnx {} BFD_RELOC_ARM_LDR_IMM 1406@deffnx {} BFD_RELOC_ARM_LITERAL 1407@deffnx {} BFD_RELOC_ARM_IN_POOL 1408@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1409@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1410@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1411@deffnx {} BFD_RELOC_ARM_HWLITERAL 1412@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1413@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1414@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1415These relocs are only used within the ARM assembler. They are not 1416(at present) written to any object files. 1417@end deffn 1418@deffn {} BFD_RELOC_SH_PCDISP8BY2 1419@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1420@deffnx {} BFD_RELOC_SH_IMM3 1421@deffnx {} BFD_RELOC_SH_IMM3U 1422@deffnx {} BFD_RELOC_SH_DISP12 1423@deffnx {} BFD_RELOC_SH_DISP12BY2 1424@deffnx {} BFD_RELOC_SH_DISP12BY4 1425@deffnx {} BFD_RELOC_SH_DISP12BY8 1426@deffnx {} BFD_RELOC_SH_DISP20 1427@deffnx {} BFD_RELOC_SH_DISP20BY8 1428@deffnx {} BFD_RELOC_SH_IMM4 1429@deffnx {} BFD_RELOC_SH_IMM4BY2 1430@deffnx {} BFD_RELOC_SH_IMM4BY4 1431@deffnx {} BFD_RELOC_SH_IMM8 1432@deffnx {} BFD_RELOC_SH_IMM8BY2 1433@deffnx {} BFD_RELOC_SH_IMM8BY4 1434@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1435@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1436@deffnx {} BFD_RELOC_SH_SWITCH16 1437@deffnx {} BFD_RELOC_SH_SWITCH32 1438@deffnx {} BFD_RELOC_SH_USES 1439@deffnx {} BFD_RELOC_SH_COUNT 1440@deffnx {} BFD_RELOC_SH_ALIGN 1441@deffnx {} BFD_RELOC_SH_CODE 1442@deffnx {} BFD_RELOC_SH_DATA 1443@deffnx {} BFD_RELOC_SH_LABEL 1444@deffnx {} BFD_RELOC_SH_LOOP_START 1445@deffnx {} BFD_RELOC_SH_LOOP_END 1446@deffnx {} BFD_RELOC_SH_COPY 1447@deffnx {} BFD_RELOC_SH_GLOB_DAT 1448@deffnx {} BFD_RELOC_SH_JMP_SLOT 1449@deffnx {} BFD_RELOC_SH_RELATIVE 1450@deffnx {} BFD_RELOC_SH_GOTPC 1451@deffnx {} BFD_RELOC_SH_GOT_LOW16 1452@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1453@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1454@deffnx {} BFD_RELOC_SH_GOT_HI16 1455@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1456@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1457@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1458@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1459@deffnx {} BFD_RELOC_SH_PLT_LOW16 1460@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1461@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1462@deffnx {} BFD_RELOC_SH_PLT_HI16 1463@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1464@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1465@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1466@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1467@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1468@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1469@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1470@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1471@deffnx {} BFD_RELOC_SH_COPY64 1472@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1473@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1474@deffnx {} BFD_RELOC_SH_RELATIVE64 1475@deffnx {} BFD_RELOC_SH_GOT10BY4 1476@deffnx {} BFD_RELOC_SH_GOT10BY8 1477@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1478@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1479@deffnx {} BFD_RELOC_SH_GOTPLT32 1480@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1481@deffnx {} BFD_RELOC_SH_IMMU5 1482@deffnx {} BFD_RELOC_SH_IMMS6 1483@deffnx {} BFD_RELOC_SH_IMMS6BY32 1484@deffnx {} BFD_RELOC_SH_IMMU6 1485@deffnx {} BFD_RELOC_SH_IMMS10 1486@deffnx {} BFD_RELOC_SH_IMMS10BY2 1487@deffnx {} BFD_RELOC_SH_IMMS10BY4 1488@deffnx {} BFD_RELOC_SH_IMMS10BY8 1489@deffnx {} BFD_RELOC_SH_IMMS16 1490@deffnx {} BFD_RELOC_SH_IMMU16 1491@deffnx {} BFD_RELOC_SH_IMM_LOW16 1492@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1493@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1494@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1495@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1496@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1497@deffnx {} BFD_RELOC_SH_IMM_HI16 1498@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1499@deffnx {} BFD_RELOC_SH_PT_16 1500@deffnx {} BFD_RELOC_SH_TLS_GD_32 1501@deffnx {} BFD_RELOC_SH_TLS_LD_32 1502@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1503@deffnx {} BFD_RELOC_SH_TLS_IE_32 1504@deffnx {} BFD_RELOC_SH_TLS_LE_32 1505@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1506@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1507@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1508@deffnx {} BFD_RELOC_SH_GOT20 1509@deffnx {} BFD_RELOC_SH_GOTOFF20 1510@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1511@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1512@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1513@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1514@deffnx {} BFD_RELOC_SH_FUNCDESC 1515Renesas / SuperH SH relocs. Not all of these appear in object files. 1516@end deffn 1517@deffn {} BFD_RELOC_ARC_B22_PCREL 1518ARC Cores relocs. 1519ARC 22 bit pc-relative branch. The lowest two bits must be zero and are 1520not stored in the instruction. The high 20 bits are installed in bits 26 1521through 7 of the instruction. 1522@end deffn 1523@deffn {} BFD_RELOC_ARC_B26 1524ARC 26 bit absolute branch. The lowest two bits must be zero and are not 1525stored in the instruction. The high 24 bits are installed in bits 23 1526through 0. 1527@end deffn 1528@deffn {} BFD_RELOC_BFIN_16_IMM 1529ADI Blackfin 16 bit immediate absolute reloc. 1530@end deffn 1531@deffn {} BFD_RELOC_BFIN_16_HIGH 1532ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1533@end deffn 1534@deffn {} BFD_RELOC_BFIN_4_PCREL 1535ADI Blackfin 'a' part of LSETUP. 1536@end deffn 1537@deffn {} BFD_RELOC_BFIN_5_PCREL 1538ADI Blackfin. 1539@end deffn 1540@deffn {} BFD_RELOC_BFIN_16_LOW 1541ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1542@end deffn 1543@deffn {} BFD_RELOC_BFIN_10_PCREL 1544ADI Blackfin. 1545@end deffn 1546@deffn {} BFD_RELOC_BFIN_11_PCREL 1547ADI Blackfin 'b' part of LSETUP. 1548@end deffn 1549@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1550ADI Blackfin. 1551@end deffn 1552@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1553ADI Blackfin Short jump, pcrel. 1554@end deffn 1555@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1556ADI Blackfin Call.x not implemented. 1557@end deffn 1558@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1559ADI Blackfin Long Jump pcrel. 1560@end deffn 1561@deffn {} BFD_RELOC_BFIN_GOT17M4 1562@deffnx {} BFD_RELOC_BFIN_GOTHI 1563@deffnx {} BFD_RELOC_BFIN_GOTLO 1564@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1565@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1566@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1567@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1568@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1569@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1570@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1571@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1572@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1573@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1574@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1575ADI Blackfin FD-PIC relocations. 1576@end deffn 1577@deffn {} BFD_RELOC_BFIN_GOT 1578ADI Blackfin GOT relocation. 1579@end deffn 1580@deffn {} BFD_RELOC_BFIN_PLTPC 1581ADI Blackfin PLTPC relocation. 1582@end deffn 1583@deffn {} BFD_ARELOC_BFIN_PUSH 1584ADI Blackfin arithmetic relocation. 1585@end deffn 1586@deffn {} BFD_ARELOC_BFIN_CONST 1587ADI Blackfin arithmetic relocation. 1588@end deffn 1589@deffn {} BFD_ARELOC_BFIN_ADD 1590ADI Blackfin arithmetic relocation. 1591@end deffn 1592@deffn {} BFD_ARELOC_BFIN_SUB 1593ADI Blackfin arithmetic relocation. 1594@end deffn 1595@deffn {} BFD_ARELOC_BFIN_MULT 1596ADI Blackfin arithmetic relocation. 1597@end deffn 1598@deffn {} BFD_ARELOC_BFIN_DIV 1599ADI Blackfin arithmetic relocation. 1600@end deffn 1601@deffn {} BFD_ARELOC_BFIN_MOD 1602ADI Blackfin arithmetic relocation. 1603@end deffn 1604@deffn {} BFD_ARELOC_BFIN_LSHIFT 1605ADI Blackfin arithmetic relocation. 1606@end deffn 1607@deffn {} BFD_ARELOC_BFIN_RSHIFT 1608ADI Blackfin arithmetic relocation. 1609@end deffn 1610@deffn {} BFD_ARELOC_BFIN_AND 1611ADI Blackfin arithmetic relocation. 1612@end deffn 1613@deffn {} BFD_ARELOC_BFIN_OR 1614ADI Blackfin arithmetic relocation. 1615@end deffn 1616@deffn {} BFD_ARELOC_BFIN_XOR 1617ADI Blackfin arithmetic relocation. 1618@end deffn 1619@deffn {} BFD_ARELOC_BFIN_LAND 1620ADI Blackfin arithmetic relocation. 1621@end deffn 1622@deffn {} BFD_ARELOC_BFIN_LOR 1623ADI Blackfin arithmetic relocation. 1624@end deffn 1625@deffn {} BFD_ARELOC_BFIN_LEN 1626ADI Blackfin arithmetic relocation. 1627@end deffn 1628@deffn {} BFD_ARELOC_BFIN_NEG 1629ADI Blackfin arithmetic relocation. 1630@end deffn 1631@deffn {} BFD_ARELOC_BFIN_COMP 1632ADI Blackfin arithmetic relocation. 1633@end deffn 1634@deffn {} BFD_ARELOC_BFIN_PAGE 1635ADI Blackfin arithmetic relocation. 1636@end deffn 1637@deffn {} BFD_ARELOC_BFIN_HWPAGE 1638ADI Blackfin arithmetic relocation. 1639@end deffn 1640@deffn {} BFD_ARELOC_BFIN_ADDR 1641ADI Blackfin arithmetic relocation. 1642@end deffn 1643@deffn {} BFD_RELOC_D10V_10_PCREL_R 1644Mitsubishi D10V relocs. 1645This is a 10-bit reloc with the right 2 bits 1646assumed to be 0. 1647@end deffn 1648@deffn {} BFD_RELOC_D10V_10_PCREL_L 1649Mitsubishi D10V relocs. 1650This is a 10-bit reloc with the right 2 bits 1651assumed to be 0. This is the same as the previous reloc 1652except it is in the left container, i.e., 1653shifted left 15 bits. 1654@end deffn 1655@deffn {} BFD_RELOC_D10V_18 1656This is an 18-bit reloc with the right 2 bits 1657assumed to be 0. 1658@end deffn 1659@deffn {} BFD_RELOC_D10V_18_PCREL 1660This is an 18-bit reloc with the right 2 bits 1661assumed to be 0. 1662@end deffn 1663@deffn {} BFD_RELOC_D30V_6 1664Mitsubishi D30V relocs. 1665This is a 6-bit absolute reloc. 1666@end deffn 1667@deffn {} BFD_RELOC_D30V_9_PCREL 1668This is a 6-bit pc-relative reloc with 1669the right 3 bits assumed to be 0. 1670@end deffn 1671@deffn {} BFD_RELOC_D30V_9_PCREL_R 1672This is a 6-bit pc-relative reloc with 1673the right 3 bits assumed to be 0. Same 1674as the previous reloc but on the right side 1675of the container. 1676@end deffn 1677@deffn {} BFD_RELOC_D30V_15 1678This is a 12-bit absolute reloc with the 1679right 3 bitsassumed to be 0. 1680@end deffn 1681@deffn {} BFD_RELOC_D30V_15_PCREL 1682This is a 12-bit pc-relative reloc with 1683the right 3 bits assumed to be 0. 1684@end deffn 1685@deffn {} BFD_RELOC_D30V_15_PCREL_R 1686This is a 12-bit pc-relative reloc with 1687the right 3 bits assumed to be 0. Same 1688as the previous reloc but on the right side 1689of the container. 1690@end deffn 1691@deffn {} BFD_RELOC_D30V_21 1692This is an 18-bit absolute reloc with 1693the right 3 bits assumed to be 0. 1694@end deffn 1695@deffn {} BFD_RELOC_D30V_21_PCREL 1696This is an 18-bit pc-relative reloc with 1697the right 3 bits assumed to be 0. 1698@end deffn 1699@deffn {} BFD_RELOC_D30V_21_PCREL_R 1700This is an 18-bit pc-relative reloc with 1701the right 3 bits assumed to be 0. Same 1702as the previous reloc but on the right side 1703of the container. 1704@end deffn 1705@deffn {} BFD_RELOC_D30V_32 1706This is a 32-bit absolute reloc. 1707@end deffn 1708@deffn {} BFD_RELOC_D30V_32_PCREL 1709This is a 32-bit pc-relative reloc. 1710@end deffn 1711@deffn {} BFD_RELOC_DLX_HI16_S 1712DLX relocs 1713@end deffn 1714@deffn {} BFD_RELOC_DLX_LO16 1715DLX relocs 1716@end deffn 1717@deffn {} BFD_RELOC_DLX_JMP26 1718DLX relocs 1719@end deffn 1720@deffn {} BFD_RELOC_M32C_HI8 1721@deffnx {} BFD_RELOC_M32C_RL_JUMP 1722@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1723@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1724Renesas M16C/M32C Relocations. 1725@end deffn 1726@deffn {} BFD_RELOC_M32R_24 1727Renesas M32R (formerly Mitsubishi M32R) relocs. 1728This is a 24 bit absolute address. 1729@end deffn 1730@deffn {} BFD_RELOC_M32R_10_PCREL 1731This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1732@end deffn 1733@deffn {} BFD_RELOC_M32R_18_PCREL 1734This is an 18-bit reloc with the right 2 bits assumed to be 0. 1735@end deffn 1736@deffn {} BFD_RELOC_M32R_26_PCREL 1737This is a 26-bit reloc with the right 2 bits assumed to be 0. 1738@end deffn 1739@deffn {} BFD_RELOC_M32R_HI16_ULO 1740This is a 16-bit reloc containing the high 16 bits of an address 1741used when the lower 16 bits are treated as unsigned. 1742@end deffn 1743@deffn {} BFD_RELOC_M32R_HI16_SLO 1744This is a 16-bit reloc containing the high 16 bits of an address 1745used when the lower 16 bits are treated as signed. 1746@end deffn 1747@deffn {} BFD_RELOC_M32R_LO16 1748This is a 16-bit reloc containing the lower 16 bits of an address. 1749@end deffn 1750@deffn {} BFD_RELOC_M32R_SDA16 1751This is a 16-bit reloc containing the small data area offset for use in 1752add3, load, and store instructions. 1753@end deffn 1754@deffn {} BFD_RELOC_M32R_GOT24 1755@deffnx {} BFD_RELOC_M32R_26_PLTREL 1756@deffnx {} BFD_RELOC_M32R_COPY 1757@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1758@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1759@deffnx {} BFD_RELOC_M32R_RELATIVE 1760@deffnx {} BFD_RELOC_M32R_GOTOFF 1761@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1762@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1763@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1764@deffnx {} BFD_RELOC_M32R_GOTPC24 1765@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1766@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1767@deffnx {} BFD_RELOC_M32R_GOT16_LO 1768@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1769@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1770@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1771For PIC. 1772@end deffn 1773@deffn {} BFD_RELOC_V850_9_PCREL 1774This is a 9-bit reloc 1775@end deffn 1776@deffn {} BFD_RELOC_V850_22_PCREL 1777This is a 22-bit reloc 1778@end deffn 1779@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 1780This is a 16 bit offset from the short data area pointer. 1781@end deffn 1782@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 1783This is a 16 bit offset (of which only 15 bits are used) from the 1784short data area pointer. 1785@end deffn 1786@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 1787This is a 16 bit offset from the zero data area pointer. 1788@end deffn 1789@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 1790This is a 16 bit offset (of which only 15 bits are used) from the 1791zero data area pointer. 1792@end deffn 1793@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 1794This is an 8 bit offset (of which only 6 bits are used) from the 1795tiny data area pointer. 1796@end deffn 1797@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 1798This is an 8bit offset (of which only 7 bits are used) from the tiny 1799data area pointer. 1800@end deffn 1801@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 1802This is a 7 bit offset from the tiny data area pointer. 1803@end deffn 1804@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 1805This is a 16 bit offset from the tiny data area pointer. 1806@end deffn 1807@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 1808This is a 5 bit offset (of which only 4 bits are used) from the tiny 1809data area pointer. 1810@end deffn 1811@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 1812This is a 4 bit offset from the tiny data area pointer. 1813@end deffn 1814@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 1815This is a 16 bit offset from the short data area pointer, with the 1816bits placed non-contiguously in the instruction. 1817@end deffn 1818@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 1819This is a 16 bit offset from the zero data area pointer, with the 1820bits placed non-contiguously in the instruction. 1821@end deffn 1822@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 1823This is a 6 bit offset from the call table base pointer. 1824@end deffn 1825@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 1826This is a 16 bit offset from the call table base pointer. 1827@end deffn 1828@deffn {} BFD_RELOC_V850_LONGCALL 1829Used for relaxing indirect function calls. 1830@end deffn 1831@deffn {} BFD_RELOC_V850_LONGJUMP 1832Used for relaxing indirect jumps. 1833@end deffn 1834@deffn {} BFD_RELOC_V850_ALIGN 1835Used to maintain alignment whilst relaxing. 1836@end deffn 1837@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 1838This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 1839instructions. 1840@end deffn 1841@deffn {} BFD_RELOC_V850_16_PCREL 1842This is a 16-bit reloc. 1843@end deffn 1844@deffn {} BFD_RELOC_V850_17_PCREL 1845This is a 17-bit reloc. 1846@end deffn 1847@deffn {} BFD_RELOC_V850_23 1848This is a 23-bit reloc. 1849@end deffn 1850@deffn {} BFD_RELOC_V850_32_PCREL 1851This is a 32-bit reloc. 1852@end deffn 1853@deffn {} BFD_RELOC_V850_32_ABS 1854This is a 32-bit reloc. 1855@end deffn 1856@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 1857This is a 16-bit reloc. 1858@end deffn 1859@deffn {} BFD_RELOC_V850_16_S1 1860This is a 16-bit reloc. 1861@end deffn 1862@deffn {} BFD_RELOC_V850_LO16_S1 1863Low 16 bits. 16 bit shifted by 1. 1864@end deffn 1865@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 1866This is a 16 bit offset from the call table base pointer. 1867@end deffn 1868@deffn {} BFD_RELOC_V850_32_GOTPCREL 1869DSO relocations. 1870@end deffn 1871@deffn {} BFD_RELOC_V850_16_GOT 1872DSO relocations. 1873@end deffn 1874@deffn {} BFD_RELOC_V850_32_GOT 1875DSO relocations. 1876@end deffn 1877@deffn {} BFD_RELOC_V850_22_PLT_PCREL 1878DSO relocations. 1879@end deffn 1880@deffn {} BFD_RELOC_V850_32_PLT_PCREL 1881DSO relocations. 1882@end deffn 1883@deffn {} BFD_RELOC_V850_COPY 1884DSO relocations. 1885@end deffn 1886@deffn {} BFD_RELOC_V850_GLOB_DAT 1887DSO relocations. 1888@end deffn 1889@deffn {} BFD_RELOC_V850_JMP_SLOT 1890DSO relocations. 1891@end deffn 1892@deffn {} BFD_RELOC_V850_RELATIVE 1893DSO relocations. 1894@end deffn 1895@deffn {} BFD_RELOC_V850_16_GOTOFF 1896DSO relocations. 1897@end deffn 1898@deffn {} BFD_RELOC_V850_32_GOTOFF 1899DSO relocations. 1900@end deffn 1901@deffn {} BFD_RELOC_V850_CODE 1902start code. 1903@end deffn 1904@deffn {} BFD_RELOC_V850_DATA 1905start data in text. 1906@end deffn 1907@deffn {} BFD_RELOC_TIC30_LDP 1908This is a 8bit DP reloc for the tms320c30, where the most 1909significant 8 bits of a 24 bit word are placed into the least 1910significant 8 bits of the opcode. 1911@end deffn 1912@deffn {} BFD_RELOC_TIC54X_PARTLS7 1913This is a 7bit reloc for the tms320c54x, where the least 1914significant 7 bits of a 16 bit word are placed into the least 1915significant 7 bits of the opcode. 1916@end deffn 1917@deffn {} BFD_RELOC_TIC54X_PARTMS9 1918This is a 9bit DP reloc for the tms320c54x, where the most 1919significant 9 bits of a 16 bit word are placed into the least 1920significant 9 bits of the opcode. 1921@end deffn 1922@deffn {} BFD_RELOC_TIC54X_23 1923This is an extended address 23-bit reloc for the tms320c54x. 1924@end deffn 1925@deffn {} BFD_RELOC_TIC54X_16_OF_23 1926This is a 16-bit reloc for the tms320c54x, where the least 1927significant 16 bits of a 23-bit extended address are placed into 1928the opcode. 1929@end deffn 1930@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 1931This is a reloc for the tms320c54x, where the most 1932significant 7 bits of a 23-bit extended address are placed into 1933the opcode. 1934@end deffn 1935@deffn {} BFD_RELOC_C6000_PCR_S21 1936@deffnx {} BFD_RELOC_C6000_PCR_S12 1937@deffnx {} BFD_RELOC_C6000_PCR_S10 1938@deffnx {} BFD_RELOC_C6000_PCR_S7 1939@deffnx {} BFD_RELOC_C6000_ABS_S16 1940@deffnx {} BFD_RELOC_C6000_ABS_L16 1941@deffnx {} BFD_RELOC_C6000_ABS_H16 1942@deffnx {} BFD_RELOC_C6000_SBR_U15_B 1943@deffnx {} BFD_RELOC_C6000_SBR_U15_H 1944@deffnx {} BFD_RELOC_C6000_SBR_U15_W 1945@deffnx {} BFD_RELOC_C6000_SBR_S16 1946@deffnx {} BFD_RELOC_C6000_SBR_L16_B 1947@deffnx {} BFD_RELOC_C6000_SBR_L16_H 1948@deffnx {} BFD_RELOC_C6000_SBR_L16_W 1949@deffnx {} BFD_RELOC_C6000_SBR_H16_B 1950@deffnx {} BFD_RELOC_C6000_SBR_H16_H 1951@deffnx {} BFD_RELOC_C6000_SBR_H16_W 1952@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 1953@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 1954@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 1955@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 1956@deffnx {} BFD_RELOC_C6000_PREL31 1957@deffnx {} BFD_RELOC_C6000_COPY 1958@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 1959@deffnx {} BFD_RELOC_C6000_EHTYPE 1960@deffnx {} BFD_RELOC_C6000_PCR_H16 1961@deffnx {} BFD_RELOC_C6000_PCR_L16 1962@deffnx {} BFD_RELOC_C6000_ALIGN 1963@deffnx {} BFD_RELOC_C6000_FPHEAD 1964@deffnx {} BFD_RELOC_C6000_NOCMP 1965TMS320C6000 relocations. 1966@end deffn 1967@deffn {} BFD_RELOC_FR30_48 1968This is a 48 bit reloc for the FR30 that stores 32 bits. 1969@end deffn 1970@deffn {} BFD_RELOC_FR30_20 1971This is a 32 bit reloc for the FR30 that stores 20 bits split up into 1972two sections. 1973@end deffn 1974@deffn {} BFD_RELOC_FR30_6_IN_4 1975This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 19764 bits. 1977@end deffn 1978@deffn {} BFD_RELOC_FR30_8_IN_8 1979This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 1980into 8 bits. 1981@end deffn 1982@deffn {} BFD_RELOC_FR30_9_IN_8 1983This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 1984into 8 bits. 1985@end deffn 1986@deffn {} BFD_RELOC_FR30_10_IN_8 1987This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 1988into 8 bits. 1989@end deffn 1990@deffn {} BFD_RELOC_FR30_9_PCREL 1991This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 1992short offset into 8 bits. 1993@end deffn 1994@deffn {} BFD_RELOC_FR30_12_PCREL 1995This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 1996short offset into 11 bits. 1997@end deffn 1998@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 1999@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2000@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2001@deffnx {} BFD_RELOC_MCORE_PCREL_32 2002@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2003@deffnx {} BFD_RELOC_MCORE_RVA 2004Motorola Mcore relocations. 2005@end deffn 2006@deffn {} BFD_RELOC_MEP_8 2007@deffnx {} BFD_RELOC_MEP_16 2008@deffnx {} BFD_RELOC_MEP_32 2009@deffnx {} BFD_RELOC_MEP_PCREL8A2 2010@deffnx {} BFD_RELOC_MEP_PCREL12A2 2011@deffnx {} BFD_RELOC_MEP_PCREL17A2 2012@deffnx {} BFD_RELOC_MEP_PCREL24A2 2013@deffnx {} BFD_RELOC_MEP_PCABS24A2 2014@deffnx {} BFD_RELOC_MEP_LOW16 2015@deffnx {} BFD_RELOC_MEP_HI16U 2016@deffnx {} BFD_RELOC_MEP_HI16S 2017@deffnx {} BFD_RELOC_MEP_GPREL 2018@deffnx {} BFD_RELOC_MEP_TPREL 2019@deffnx {} BFD_RELOC_MEP_TPREL7 2020@deffnx {} BFD_RELOC_MEP_TPREL7A2 2021@deffnx {} BFD_RELOC_MEP_TPREL7A4 2022@deffnx {} BFD_RELOC_MEP_UIMM24 2023@deffnx {} BFD_RELOC_MEP_ADDR24A4 2024@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2025@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2026Toshiba Media Processor Relocations. 2027@end deffn 2028@deffn {} BFD_RELOC_MMIX_GETA 2029@deffnx {} BFD_RELOC_MMIX_GETA_1 2030@deffnx {} BFD_RELOC_MMIX_GETA_2 2031@deffnx {} BFD_RELOC_MMIX_GETA_3 2032These are relocations for the GETA instruction. 2033@end deffn 2034@deffn {} BFD_RELOC_MMIX_CBRANCH 2035@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2036@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2037@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2038@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2039These are relocations for a conditional branch instruction. 2040@end deffn 2041@deffn {} BFD_RELOC_MMIX_PUSHJ 2042@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2043@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2044@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2045@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2046These are relocations for the PUSHJ instruction. 2047@end deffn 2048@deffn {} BFD_RELOC_MMIX_JMP 2049@deffnx {} BFD_RELOC_MMIX_JMP_1 2050@deffnx {} BFD_RELOC_MMIX_JMP_2 2051@deffnx {} BFD_RELOC_MMIX_JMP_3 2052These are relocations for the JMP instruction. 2053@end deffn 2054@deffn {} BFD_RELOC_MMIX_ADDR19 2055This is a relocation for a relative address as in a GETA instruction or 2056a branch. 2057@end deffn 2058@deffn {} BFD_RELOC_MMIX_ADDR27 2059This is a relocation for a relative address as in a JMP instruction. 2060@end deffn 2061@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2062This is a relocation for an instruction field that may be a general 2063register or a value 0..255. 2064@end deffn 2065@deffn {} BFD_RELOC_MMIX_REG 2066This is a relocation for an instruction field that may be a general 2067register. 2068@end deffn 2069@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2070This is a relocation for two instruction fields holding a register and 2071an offset, the equivalent of the relocation. 2072@end deffn 2073@deffn {} BFD_RELOC_MMIX_LOCAL 2074This relocation is an assertion that the expression is not allocated as 2075a global register. It does not modify contents. 2076@end deffn 2077@deffn {} BFD_RELOC_AVR_7_PCREL 2078This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2079short offset into 7 bits. 2080@end deffn 2081@deffn {} BFD_RELOC_AVR_13_PCREL 2082This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2083short offset into 12 bits. 2084@end deffn 2085@deffn {} BFD_RELOC_AVR_16_PM 2086This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2087program memory address) into 16 bits. 2088@end deffn 2089@deffn {} BFD_RELOC_AVR_LO8_LDI 2090This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2091data memory address) into 8 bit immediate value of LDI insn. 2092@end deffn 2093@deffn {} BFD_RELOC_AVR_HI8_LDI 2094This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2095of data memory address) into 8 bit immediate value of LDI insn. 2096@end deffn 2097@deffn {} BFD_RELOC_AVR_HH8_LDI 2098This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2099of program memory address) into 8 bit immediate value of LDI insn. 2100@end deffn 2101@deffn {} BFD_RELOC_AVR_MS8_LDI 2102This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2103of 32 bit value) into 8 bit immediate value of LDI insn. 2104@end deffn 2105@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2106This is a 16 bit reloc for the AVR that stores negated 8 bit value 2107(usually data memory address) into 8 bit immediate value of SUBI insn. 2108@end deffn 2109@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2110This is a 16 bit reloc for the AVR that stores negated 8 bit value 2111(high 8 bit of data memory address) into 8 bit immediate value of 2112SUBI insn. 2113@end deffn 2114@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2115This is a 16 bit reloc for the AVR that stores negated 8 bit value 2116(most high 8 bit of program memory address) into 8 bit immediate value 2117of LDI or SUBI insn. 2118@end deffn 2119@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2120This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2121of 32 bit value) into 8 bit immediate value of LDI insn. 2122@end deffn 2123@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2124This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2125command address) into 8 bit immediate value of LDI insn. 2126@end deffn 2127@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2128This is a 16 bit reloc for the AVR that stores 8 bit value 2129(command address) into 8 bit immediate value of LDI insn. If the address 2130is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2131in the lower 128k. 2132@end deffn 2133@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2134This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2135of command address) into 8 bit immediate value of LDI insn. 2136@end deffn 2137@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2138This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2139of command address) into 8 bit immediate value of LDI insn. If the address 2140is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2141below 128k. 2142@end deffn 2143@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2144This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2145of command address) into 8 bit immediate value of LDI insn. 2146@end deffn 2147@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2148This is a 16 bit reloc for the AVR that stores negated 8 bit value 2149(usually command address) into 8 bit immediate value of SUBI insn. 2150@end deffn 2151@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2152This is a 16 bit reloc for the AVR that stores negated 8 bit value 2153(high 8 bit of 16 bit command address) into 8 bit immediate value 2154of SUBI insn. 2155@end deffn 2156@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2157This is a 16 bit reloc for the AVR that stores negated 8 bit value 2158(high 6 bit of 22 bit command address) into 8 bit immediate 2159value of SUBI insn. 2160@end deffn 2161@deffn {} BFD_RELOC_AVR_CALL 2162This is a 32 bit reloc for the AVR that stores 23 bit value 2163into 22 bits. 2164@end deffn 2165@deffn {} BFD_RELOC_AVR_LDI 2166This is a 16 bit reloc for the AVR that stores all needed bits 2167for absolute addressing with ldi with overflow check to linktime 2168@end deffn 2169@deffn {} BFD_RELOC_AVR_6 2170This is a 6 bit reloc for the AVR that stores offset for ldd/std 2171instructions 2172@end deffn 2173@deffn {} BFD_RELOC_AVR_6_ADIW 2174This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2175instructions 2176@end deffn 2177@deffn {} BFD_RELOC_AVR_8_LO 2178This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2179in .byte lo8(symbol) 2180@end deffn 2181@deffn {} BFD_RELOC_AVR_8_HI 2182This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2183in .byte hi8(symbol) 2184@end deffn 2185@deffn {} BFD_RELOC_AVR_8_HLO 2186This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2187in .byte hlo8(symbol) 2188@end deffn 2189@deffn {} BFD_RELOC_RL78_NEG8 2190@deffnx {} BFD_RELOC_RL78_NEG16 2191@deffnx {} BFD_RELOC_RL78_NEG24 2192@deffnx {} BFD_RELOC_RL78_NEG32 2193@deffnx {} BFD_RELOC_RL78_16_OP 2194@deffnx {} BFD_RELOC_RL78_24_OP 2195@deffnx {} BFD_RELOC_RL78_32_OP 2196@deffnx {} BFD_RELOC_RL78_8U 2197@deffnx {} BFD_RELOC_RL78_16U 2198@deffnx {} BFD_RELOC_RL78_24U 2199@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2200@deffnx {} BFD_RELOC_RL78_DIFF 2201@deffnx {} BFD_RELOC_RL78_GPRELB 2202@deffnx {} BFD_RELOC_RL78_GPRELW 2203@deffnx {} BFD_RELOC_RL78_GPRELL 2204@deffnx {} BFD_RELOC_RL78_SYM 2205@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2206@deffnx {} BFD_RELOC_RL78_OP_NEG 2207@deffnx {} BFD_RELOC_RL78_OP_AND 2208@deffnx {} BFD_RELOC_RL78_OP_SHRA 2209@deffnx {} BFD_RELOC_RL78_ABS8 2210@deffnx {} BFD_RELOC_RL78_ABS16 2211@deffnx {} BFD_RELOC_RL78_ABS16_REV 2212@deffnx {} BFD_RELOC_RL78_ABS32 2213@deffnx {} BFD_RELOC_RL78_ABS32_REV 2214@deffnx {} BFD_RELOC_RL78_ABS16U 2215@deffnx {} BFD_RELOC_RL78_ABS16UW 2216@deffnx {} BFD_RELOC_RL78_ABS16UL 2217@deffnx {} BFD_RELOC_RL78_RELAX 2218@deffnx {} BFD_RELOC_RL78_HI16 2219@deffnx {} BFD_RELOC_RL78_HI8 2220@deffnx {} BFD_RELOC_RL78_LO16 2221Renesas RL78 Relocations. 2222@end deffn 2223@deffn {} BFD_RELOC_RX_NEG8 2224@deffnx {} BFD_RELOC_RX_NEG16 2225@deffnx {} BFD_RELOC_RX_NEG24 2226@deffnx {} BFD_RELOC_RX_NEG32 2227@deffnx {} BFD_RELOC_RX_16_OP 2228@deffnx {} BFD_RELOC_RX_24_OP 2229@deffnx {} BFD_RELOC_RX_32_OP 2230@deffnx {} BFD_RELOC_RX_8U 2231@deffnx {} BFD_RELOC_RX_16U 2232@deffnx {} BFD_RELOC_RX_24U 2233@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2234@deffnx {} BFD_RELOC_RX_DIFF 2235@deffnx {} BFD_RELOC_RX_GPRELB 2236@deffnx {} BFD_RELOC_RX_GPRELW 2237@deffnx {} BFD_RELOC_RX_GPRELL 2238@deffnx {} BFD_RELOC_RX_SYM 2239@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2240@deffnx {} BFD_RELOC_RX_OP_NEG 2241@deffnx {} BFD_RELOC_RX_ABS8 2242@deffnx {} BFD_RELOC_RX_ABS16 2243@deffnx {} BFD_RELOC_RX_ABS16_REV 2244@deffnx {} BFD_RELOC_RX_ABS32 2245@deffnx {} BFD_RELOC_RX_ABS32_REV 2246@deffnx {} BFD_RELOC_RX_ABS16U 2247@deffnx {} BFD_RELOC_RX_ABS16UW 2248@deffnx {} BFD_RELOC_RX_ABS16UL 2249@deffnx {} BFD_RELOC_RX_RELAX 2250Renesas RX Relocations. 2251@end deffn 2252@deffn {} BFD_RELOC_390_12 2253Direct 12 bit. 2254@end deffn 2255@deffn {} BFD_RELOC_390_GOT12 225612 bit GOT offset. 2257@end deffn 2258@deffn {} BFD_RELOC_390_PLT32 225932 bit PC relative PLT address. 2260@end deffn 2261@deffn {} BFD_RELOC_390_COPY 2262Copy symbol at runtime. 2263@end deffn 2264@deffn {} BFD_RELOC_390_GLOB_DAT 2265Create GOT entry. 2266@end deffn 2267@deffn {} BFD_RELOC_390_JMP_SLOT 2268Create PLT entry. 2269@end deffn 2270@deffn {} BFD_RELOC_390_RELATIVE 2271Adjust by program base. 2272@end deffn 2273@deffn {} BFD_RELOC_390_GOTPC 227432 bit PC relative offset to GOT. 2275@end deffn 2276@deffn {} BFD_RELOC_390_GOT16 227716 bit GOT offset. 2278@end deffn 2279@deffn {} BFD_RELOC_390_PC16DBL 2280PC relative 16 bit shifted by 1. 2281@end deffn 2282@deffn {} BFD_RELOC_390_PLT16DBL 228316 bit PC rel. PLT shifted by 1. 2284@end deffn 2285@deffn {} BFD_RELOC_390_PC32DBL 2286PC relative 32 bit shifted by 1. 2287@end deffn 2288@deffn {} BFD_RELOC_390_PLT32DBL 228932 bit PC rel. PLT shifted by 1. 2290@end deffn 2291@deffn {} BFD_RELOC_390_GOTPCDBL 229232 bit PC rel. GOT shifted by 1. 2293@end deffn 2294@deffn {} BFD_RELOC_390_GOT64 229564 bit GOT offset. 2296@end deffn 2297@deffn {} BFD_RELOC_390_PLT64 229864 bit PC relative PLT address. 2299@end deffn 2300@deffn {} BFD_RELOC_390_GOTENT 230132 bit rel. offset to GOT entry. 2302@end deffn 2303@deffn {} BFD_RELOC_390_GOTOFF64 230464 bit offset to GOT. 2305@end deffn 2306@deffn {} BFD_RELOC_390_GOTPLT12 230712-bit offset to symbol-entry within GOT, with PLT handling. 2308@end deffn 2309@deffn {} BFD_RELOC_390_GOTPLT16 231016-bit offset to symbol-entry within GOT, with PLT handling. 2311@end deffn 2312@deffn {} BFD_RELOC_390_GOTPLT32 231332-bit offset to symbol-entry within GOT, with PLT handling. 2314@end deffn 2315@deffn {} BFD_RELOC_390_GOTPLT64 231664-bit offset to symbol-entry within GOT, with PLT handling. 2317@end deffn 2318@deffn {} BFD_RELOC_390_GOTPLTENT 231932-bit rel. offset to symbol-entry within GOT, with PLT handling. 2320@end deffn 2321@deffn {} BFD_RELOC_390_PLTOFF16 232216-bit rel. offset from the GOT to a PLT entry. 2323@end deffn 2324@deffn {} BFD_RELOC_390_PLTOFF32 232532-bit rel. offset from the GOT to a PLT entry. 2326@end deffn 2327@deffn {} BFD_RELOC_390_PLTOFF64 232864-bit rel. offset from the GOT to a PLT entry. 2329@end deffn 2330@deffn {} BFD_RELOC_390_TLS_LOAD 2331@deffnx {} BFD_RELOC_390_TLS_GDCALL 2332@deffnx {} BFD_RELOC_390_TLS_LDCALL 2333@deffnx {} BFD_RELOC_390_TLS_GD32 2334@deffnx {} BFD_RELOC_390_TLS_GD64 2335@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2336@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2337@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2338@deffnx {} BFD_RELOC_390_TLS_LDM32 2339@deffnx {} BFD_RELOC_390_TLS_LDM64 2340@deffnx {} BFD_RELOC_390_TLS_IE32 2341@deffnx {} BFD_RELOC_390_TLS_IE64 2342@deffnx {} BFD_RELOC_390_TLS_IEENT 2343@deffnx {} BFD_RELOC_390_TLS_LE32 2344@deffnx {} BFD_RELOC_390_TLS_LE64 2345@deffnx {} BFD_RELOC_390_TLS_LDO32 2346@deffnx {} BFD_RELOC_390_TLS_LDO64 2347@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2348@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2349@deffnx {} BFD_RELOC_390_TLS_TPOFF 2350s390 tls relocations. 2351@end deffn 2352@deffn {} BFD_RELOC_390_20 2353@deffnx {} BFD_RELOC_390_GOT20 2354@deffnx {} BFD_RELOC_390_GOTPLT20 2355@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2356Long displacement extension. 2357@end deffn 2358@deffn {} BFD_RELOC_390_IRELATIVE 2359STT_GNU_IFUNC relocation. 2360@end deffn 2361@deffn {} BFD_RELOC_SCORE_GPREL15 2362Score relocations 2363Low 16 bit for load/store 2364@end deffn 2365@deffn {} BFD_RELOC_SCORE_DUMMY2 2366@deffnx {} BFD_RELOC_SCORE_JMP 2367This is a 24-bit reloc with the right 1 bit assumed to be 0 2368@end deffn 2369@deffn {} BFD_RELOC_SCORE_BRANCH 2370This is a 19-bit reloc with the right 1 bit assumed to be 0 2371@end deffn 2372@deffn {} BFD_RELOC_SCORE_IMM30 2373This is a 32-bit reloc for 48-bit instructions. 2374@end deffn 2375@deffn {} BFD_RELOC_SCORE_IMM32 2376This is a 32-bit reloc for 48-bit instructions. 2377@end deffn 2378@deffn {} BFD_RELOC_SCORE16_JMP 2379This is a 11-bit reloc with the right 1 bit assumed to be 0 2380@end deffn 2381@deffn {} BFD_RELOC_SCORE16_BRANCH 2382This is a 8-bit reloc with the right 1 bit assumed to be 0 2383@end deffn 2384@deffn {} BFD_RELOC_SCORE_BCMP 2385This is a 9-bit reloc with the right 1 bit assumed to be 0 2386@end deffn 2387@deffn {} BFD_RELOC_SCORE_GOT15 2388@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2389@deffnx {} BFD_RELOC_SCORE_CALL15 2390@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2391Undocumented Score relocs 2392@end deffn 2393@deffn {} BFD_RELOC_IP2K_FR9 2394Scenix IP2K - 9-bit register number / data address 2395@end deffn 2396@deffn {} BFD_RELOC_IP2K_BANK 2397Scenix IP2K - 4-bit register/data bank number 2398@end deffn 2399@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2400Scenix IP2K - low 13 bits of instruction word address 2401@end deffn 2402@deffn {} BFD_RELOC_IP2K_PAGE3 2403Scenix IP2K - high 3 bits of instruction word address 2404@end deffn 2405@deffn {} BFD_RELOC_IP2K_LO8DATA 2406@deffnx {} BFD_RELOC_IP2K_HI8DATA 2407@deffnx {} BFD_RELOC_IP2K_EX8DATA 2408Scenix IP2K - ext/low/high 8 bits of data address 2409@end deffn 2410@deffn {} BFD_RELOC_IP2K_LO8INSN 2411@deffnx {} BFD_RELOC_IP2K_HI8INSN 2412Scenix IP2K - low/high 8 bits of instruction word address 2413@end deffn 2414@deffn {} BFD_RELOC_IP2K_PC_SKIP 2415Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2416@end deffn 2417@deffn {} BFD_RELOC_IP2K_TEXT 2418Scenix IP2K - 16 bit word address in text section. 2419@end deffn 2420@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2421Scenix IP2K - 7-bit sp or dp offset 2422@end deffn 2423@deffn {} BFD_RELOC_VPE4KMATH_DATA 2424@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2425Scenix VPE4K coprocessor - data/insn-space addressing 2426@end deffn 2427@deffn {} BFD_RELOC_VTABLE_INHERIT 2428@deffnx {} BFD_RELOC_VTABLE_ENTRY 2429These two relocations are used by the linker to determine which of 2430the entries in a C++ virtual function table are actually used. When 2431the --gc-sections option is given, the linker will zero out the entries 2432that are not used, so that the code for those functions need not be 2433included in the output. 2434 2435VTABLE_INHERIT is a zero-space relocation used to describe to the 2436linker the inheritance tree of a C++ virtual function table. The 2437relocation's symbol should be the parent class' vtable, and the 2438relocation should be located at the child vtable. 2439 2440VTABLE_ENTRY is a zero-space relocation that describes the use of a 2441virtual function table entry. The reloc's symbol should refer to the 2442table of the class mentioned in the code. Off of that base, an offset 2443describes the entry that is being used. For Rela hosts, this offset 2444is stored in the reloc's addend. For Rel hosts, we are forced to put 2445this offset in the reloc's section offset. 2446@end deffn 2447@deffn {} BFD_RELOC_IA64_IMM14 2448@deffnx {} BFD_RELOC_IA64_IMM22 2449@deffnx {} BFD_RELOC_IA64_IMM64 2450@deffnx {} BFD_RELOC_IA64_DIR32MSB 2451@deffnx {} BFD_RELOC_IA64_DIR32LSB 2452@deffnx {} BFD_RELOC_IA64_DIR64MSB 2453@deffnx {} BFD_RELOC_IA64_DIR64LSB 2454@deffnx {} BFD_RELOC_IA64_GPREL22 2455@deffnx {} BFD_RELOC_IA64_GPREL64I 2456@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2457@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2458@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2459@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2460@deffnx {} BFD_RELOC_IA64_LTOFF22 2461@deffnx {} BFD_RELOC_IA64_LTOFF64I 2462@deffnx {} BFD_RELOC_IA64_PLTOFF22 2463@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2464@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2465@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2466@deffnx {} BFD_RELOC_IA64_FPTR64I 2467@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2468@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2469@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2470@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2471@deffnx {} BFD_RELOC_IA64_PCREL21B 2472@deffnx {} BFD_RELOC_IA64_PCREL21BI 2473@deffnx {} BFD_RELOC_IA64_PCREL21M 2474@deffnx {} BFD_RELOC_IA64_PCREL21F 2475@deffnx {} BFD_RELOC_IA64_PCREL22 2476@deffnx {} BFD_RELOC_IA64_PCREL60B 2477@deffnx {} BFD_RELOC_IA64_PCREL64I 2478@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2479@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2480@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2481@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2482@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2483@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2484@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2485@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2486@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2487@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2488@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2489@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2490@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2491@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2492@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2493@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2494@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2495@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2496@deffnx {} BFD_RELOC_IA64_REL32MSB 2497@deffnx {} BFD_RELOC_IA64_REL32LSB 2498@deffnx {} BFD_RELOC_IA64_REL64MSB 2499@deffnx {} BFD_RELOC_IA64_REL64LSB 2500@deffnx {} BFD_RELOC_IA64_LTV32MSB 2501@deffnx {} BFD_RELOC_IA64_LTV32LSB 2502@deffnx {} BFD_RELOC_IA64_LTV64MSB 2503@deffnx {} BFD_RELOC_IA64_LTV64LSB 2504@deffnx {} BFD_RELOC_IA64_IPLTMSB 2505@deffnx {} BFD_RELOC_IA64_IPLTLSB 2506@deffnx {} BFD_RELOC_IA64_COPY 2507@deffnx {} BFD_RELOC_IA64_LTOFF22X 2508@deffnx {} BFD_RELOC_IA64_LDXMOV 2509@deffnx {} BFD_RELOC_IA64_TPREL14 2510@deffnx {} BFD_RELOC_IA64_TPREL22 2511@deffnx {} BFD_RELOC_IA64_TPREL64I 2512@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2513@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2514@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2515@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2516@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2517@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2518@deffnx {} BFD_RELOC_IA64_DTPREL14 2519@deffnx {} BFD_RELOC_IA64_DTPREL22 2520@deffnx {} BFD_RELOC_IA64_DTPREL64I 2521@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2522@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2523@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2524@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2525@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2526Intel IA64 Relocations. 2527@end deffn 2528@deffn {} BFD_RELOC_M68HC11_HI8 2529Motorola 68HC11 reloc. 2530This is the 8 bit high part of an absolute address. 2531@end deffn 2532@deffn {} BFD_RELOC_M68HC11_LO8 2533Motorola 68HC11 reloc. 2534This is the 8 bit low part of an absolute address. 2535@end deffn 2536@deffn {} BFD_RELOC_M68HC11_3B 2537Motorola 68HC11 reloc. 2538This is the 3 bit of a value. 2539@end deffn 2540@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2541Motorola 68HC11 reloc. 2542This reloc marks the beginning of a jump/call instruction. 2543It is used for linker relaxation to correctly identify beginning 2544of instruction and change some branches to use PC-relative 2545addressing mode. 2546@end deffn 2547@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2548Motorola 68HC11 reloc. 2549This reloc marks a group of several instructions that gcc generates 2550and for which the linker relaxation pass can modify and/or remove 2551some of them. 2552@end deffn 2553@deffn {} BFD_RELOC_M68HC11_LO16 2554Motorola 68HC11 reloc. 2555This is the 16-bit lower part of an address. It is used for 'call' 2556instruction to specify the symbol address without any special 2557transformation (due to memory bank window). 2558@end deffn 2559@deffn {} BFD_RELOC_M68HC11_PAGE 2560Motorola 68HC11 reloc. 2561This is a 8-bit reloc that specifies the page number of an address. 2562It is used by 'call' instruction to specify the page number of 2563the symbol. 2564@end deffn 2565@deffn {} BFD_RELOC_M68HC11_24 2566Motorola 68HC11 reloc. 2567This is a 24-bit reloc that represents the address with a 16-bit 2568value and a 8-bit page number. The symbol address is transformed 2569to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 2570@end deffn 2571@deffn {} BFD_RELOC_M68HC12_5B 2572Motorola 68HC12 reloc. 2573This is the 5 bits of a value. 2574@end deffn 2575@deffn {} BFD_RELOC_XGATE_RL_JUMP 2576Freescale XGATE reloc. 2577This reloc marks the beginning of a bra/jal instruction. 2578@end deffn 2579@deffn {} BFD_RELOC_XGATE_RL_GROUP 2580Freescale XGATE reloc. 2581This reloc marks a group of several instructions that gcc generates 2582and for which the linker relaxation pass can modify and/or remove 2583some of them. 2584@end deffn 2585@deffn {} BFD_RELOC_XGATE_LO16 2586Freescale XGATE reloc. 2587This is the 16-bit lower part of an address. It is used for the '16-bit' 2588instructions. 2589@end deffn 2590@deffn {} BFD_RELOC_XGATE_GPAGE 2591Freescale XGATE reloc. 2592@end deffn 2593@deffn {} BFD_RELOC_XGATE_24 2594Freescale XGATE reloc. 2595@end deffn 2596@deffn {} BFD_RELOC_XGATE_PCREL_9 2597Freescale XGATE reloc. 2598This is a 9-bit pc-relative reloc. 2599@end deffn 2600@deffn {} BFD_RELOC_XGATE_PCREL_10 2601Freescale XGATE reloc. 2602This is a 10-bit pc-relative reloc. 2603@end deffn 2604@deffn {} BFD_RELOC_XGATE_IMM8_LO 2605Freescale XGATE reloc. 2606This is the 16-bit lower part of an address. It is used for the '16-bit' 2607instructions. 2608@end deffn 2609@deffn {} BFD_RELOC_XGATE_IMM8_HI 2610Freescale XGATE reloc. 2611This is the 16-bit higher part of an address. It is used for the '16-bit' 2612instructions. 2613@end deffn 2614@deffn {} BFD_RELOC_XGATE_IMM3 2615Freescale XGATE reloc. 2616This is a 3-bit pc-relative reloc. 2617@end deffn 2618@deffn {} BFD_RELOC_XGATE_IMM4 2619Freescale XGATE reloc. 2620This is a 4-bit pc-relative reloc. 2621@end deffn 2622@deffn {} BFD_RELOC_XGATE_IMM5 2623Freescale XGATE reloc. 2624This is a 5-bit pc-relative reloc. 2625@end deffn 2626@deffn {} BFD_RELOC_M68HC12_9B 2627Motorola 68HC12 reloc. 2628This is the 9 bits of a value. 2629@end deffn 2630@deffn {} BFD_RELOC_M68HC12_16B 2631Motorola 68HC12 reloc. 2632This is the 16 bits of a value. 2633@end deffn 2634@deffn {} BFD_RELOC_M68HC12_9_PCREL 2635Motorola 68HC12/XGATE reloc. 2636This is a PCREL9 branch. 2637@end deffn 2638@deffn {} BFD_RELOC_M68HC12_10_PCREL 2639Motorola 68HC12/XGATE reloc. 2640This is a PCREL10 branch. 2641@end deffn 2642@deffn {} BFD_RELOC_M68HC12_LO8XG 2643Motorola 68HC12/XGATE reloc. 2644This is the 8 bit low part of an absolute address and immediately precedes 2645a matching HI8XG part. 2646@end deffn 2647@deffn {} BFD_RELOC_M68HC12_HI8XG 2648Motorola 68HC12/XGATE reloc. 2649This is the 8 bit high part of an absolute address and immediately follows 2650a matching LO8XG part. 2651@end deffn 2652@deffn {} BFD_RELOC_16C_NUM08 2653@deffnx {} BFD_RELOC_16C_NUM08_C 2654@deffnx {} BFD_RELOC_16C_NUM16 2655@deffnx {} BFD_RELOC_16C_NUM16_C 2656@deffnx {} BFD_RELOC_16C_NUM32 2657@deffnx {} BFD_RELOC_16C_NUM32_C 2658@deffnx {} BFD_RELOC_16C_DISP04 2659@deffnx {} BFD_RELOC_16C_DISP04_C 2660@deffnx {} BFD_RELOC_16C_DISP08 2661@deffnx {} BFD_RELOC_16C_DISP08_C 2662@deffnx {} BFD_RELOC_16C_DISP16 2663@deffnx {} BFD_RELOC_16C_DISP16_C 2664@deffnx {} BFD_RELOC_16C_DISP24 2665@deffnx {} BFD_RELOC_16C_DISP24_C 2666@deffnx {} BFD_RELOC_16C_DISP24a 2667@deffnx {} BFD_RELOC_16C_DISP24a_C 2668@deffnx {} BFD_RELOC_16C_REG04 2669@deffnx {} BFD_RELOC_16C_REG04_C 2670@deffnx {} BFD_RELOC_16C_REG04a 2671@deffnx {} BFD_RELOC_16C_REG04a_C 2672@deffnx {} BFD_RELOC_16C_REG14 2673@deffnx {} BFD_RELOC_16C_REG14_C 2674@deffnx {} BFD_RELOC_16C_REG16 2675@deffnx {} BFD_RELOC_16C_REG16_C 2676@deffnx {} BFD_RELOC_16C_REG20 2677@deffnx {} BFD_RELOC_16C_REG20_C 2678@deffnx {} BFD_RELOC_16C_ABS20 2679@deffnx {} BFD_RELOC_16C_ABS20_C 2680@deffnx {} BFD_RELOC_16C_ABS24 2681@deffnx {} BFD_RELOC_16C_ABS24_C 2682@deffnx {} BFD_RELOC_16C_IMM04 2683@deffnx {} BFD_RELOC_16C_IMM04_C 2684@deffnx {} BFD_RELOC_16C_IMM16 2685@deffnx {} BFD_RELOC_16C_IMM16_C 2686@deffnx {} BFD_RELOC_16C_IMM20 2687@deffnx {} BFD_RELOC_16C_IMM20_C 2688@deffnx {} BFD_RELOC_16C_IMM24 2689@deffnx {} BFD_RELOC_16C_IMM24_C 2690@deffnx {} BFD_RELOC_16C_IMM32 2691@deffnx {} BFD_RELOC_16C_IMM32_C 2692NS CR16C Relocations. 2693@end deffn 2694@deffn {} BFD_RELOC_CR16_NUM8 2695@deffnx {} BFD_RELOC_CR16_NUM16 2696@deffnx {} BFD_RELOC_CR16_NUM32 2697@deffnx {} BFD_RELOC_CR16_NUM32a 2698@deffnx {} BFD_RELOC_CR16_REGREL0 2699@deffnx {} BFD_RELOC_CR16_REGREL4 2700@deffnx {} BFD_RELOC_CR16_REGREL4a 2701@deffnx {} BFD_RELOC_CR16_REGREL14 2702@deffnx {} BFD_RELOC_CR16_REGREL14a 2703@deffnx {} BFD_RELOC_CR16_REGREL16 2704@deffnx {} BFD_RELOC_CR16_REGREL20 2705@deffnx {} BFD_RELOC_CR16_REGREL20a 2706@deffnx {} BFD_RELOC_CR16_ABS20 2707@deffnx {} BFD_RELOC_CR16_ABS24 2708@deffnx {} BFD_RELOC_CR16_IMM4 2709@deffnx {} BFD_RELOC_CR16_IMM8 2710@deffnx {} BFD_RELOC_CR16_IMM16 2711@deffnx {} BFD_RELOC_CR16_IMM20 2712@deffnx {} BFD_RELOC_CR16_IMM24 2713@deffnx {} BFD_RELOC_CR16_IMM32 2714@deffnx {} BFD_RELOC_CR16_IMM32a 2715@deffnx {} BFD_RELOC_CR16_DISP4 2716@deffnx {} BFD_RELOC_CR16_DISP8 2717@deffnx {} BFD_RELOC_CR16_DISP16 2718@deffnx {} BFD_RELOC_CR16_DISP20 2719@deffnx {} BFD_RELOC_CR16_DISP24 2720@deffnx {} BFD_RELOC_CR16_DISP24a 2721@deffnx {} BFD_RELOC_CR16_SWITCH8 2722@deffnx {} BFD_RELOC_CR16_SWITCH16 2723@deffnx {} BFD_RELOC_CR16_SWITCH32 2724@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 2725@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 2726@deffnx {} BFD_RELOC_CR16_GLOB_DAT 2727NS CR16 Relocations. 2728@end deffn 2729@deffn {} BFD_RELOC_CRX_REL4 2730@deffnx {} BFD_RELOC_CRX_REL8 2731@deffnx {} BFD_RELOC_CRX_REL8_CMP 2732@deffnx {} BFD_RELOC_CRX_REL16 2733@deffnx {} BFD_RELOC_CRX_REL24 2734@deffnx {} BFD_RELOC_CRX_REL32 2735@deffnx {} BFD_RELOC_CRX_REGREL12 2736@deffnx {} BFD_RELOC_CRX_REGREL22 2737@deffnx {} BFD_RELOC_CRX_REGREL28 2738@deffnx {} BFD_RELOC_CRX_REGREL32 2739@deffnx {} BFD_RELOC_CRX_ABS16 2740@deffnx {} BFD_RELOC_CRX_ABS32 2741@deffnx {} BFD_RELOC_CRX_NUM8 2742@deffnx {} BFD_RELOC_CRX_NUM16 2743@deffnx {} BFD_RELOC_CRX_NUM32 2744@deffnx {} BFD_RELOC_CRX_IMM16 2745@deffnx {} BFD_RELOC_CRX_IMM32 2746@deffnx {} BFD_RELOC_CRX_SWITCH8 2747@deffnx {} BFD_RELOC_CRX_SWITCH16 2748@deffnx {} BFD_RELOC_CRX_SWITCH32 2749NS CRX Relocations. 2750@end deffn 2751@deffn {} BFD_RELOC_CRIS_BDISP8 2752@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 2753@deffnx {} BFD_RELOC_CRIS_SIGNED_6 2754@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 2755@deffnx {} BFD_RELOC_CRIS_SIGNED_8 2756@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 2757@deffnx {} BFD_RELOC_CRIS_SIGNED_16 2758@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 2759@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 2760@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 2761These relocs are only used within the CRIS assembler. They are not 2762(at present) written to any object files. 2763@end deffn 2764@deffn {} BFD_RELOC_CRIS_COPY 2765@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 2766@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 2767@deffnx {} BFD_RELOC_CRIS_RELATIVE 2768Relocs used in ELF shared libraries for CRIS. 2769@end deffn 2770@deffn {} BFD_RELOC_CRIS_32_GOT 277132-bit offset to symbol-entry within GOT. 2772@end deffn 2773@deffn {} BFD_RELOC_CRIS_16_GOT 277416-bit offset to symbol-entry within GOT. 2775@end deffn 2776@deffn {} BFD_RELOC_CRIS_32_GOTPLT 277732-bit offset to symbol-entry within GOT, with PLT handling. 2778@end deffn 2779@deffn {} BFD_RELOC_CRIS_16_GOTPLT 278016-bit offset to symbol-entry within GOT, with PLT handling. 2781@end deffn 2782@deffn {} BFD_RELOC_CRIS_32_GOTREL 278332-bit offset to symbol, relative to GOT. 2784@end deffn 2785@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 278632-bit offset to symbol with PLT entry, relative to GOT. 2787@end deffn 2788@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 278932-bit offset to symbol with PLT entry, relative to this relocation. 2790@end deffn 2791@deffn {} BFD_RELOC_CRIS_32_GOT_GD 2792@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 2793@deffnx {} BFD_RELOC_CRIS_32_GD 2794@deffnx {} BFD_RELOC_CRIS_DTP 2795@deffnx {} BFD_RELOC_CRIS_32_DTPREL 2796@deffnx {} BFD_RELOC_CRIS_16_DTPREL 2797@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 2798@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 2799@deffnx {} BFD_RELOC_CRIS_32_TPREL 2800@deffnx {} BFD_RELOC_CRIS_16_TPREL 2801@deffnx {} BFD_RELOC_CRIS_DTPMOD 2802@deffnx {} BFD_RELOC_CRIS_32_IE 2803Relocs used in TLS code for CRIS. 2804@end deffn 2805@deffn {} BFD_RELOC_860_COPY 2806@deffnx {} BFD_RELOC_860_GLOB_DAT 2807@deffnx {} BFD_RELOC_860_JUMP_SLOT 2808@deffnx {} BFD_RELOC_860_RELATIVE 2809@deffnx {} BFD_RELOC_860_PC26 2810@deffnx {} BFD_RELOC_860_PLT26 2811@deffnx {} BFD_RELOC_860_PC16 2812@deffnx {} BFD_RELOC_860_LOW0 2813@deffnx {} BFD_RELOC_860_SPLIT0 2814@deffnx {} BFD_RELOC_860_LOW1 2815@deffnx {} BFD_RELOC_860_SPLIT1 2816@deffnx {} BFD_RELOC_860_LOW2 2817@deffnx {} BFD_RELOC_860_SPLIT2 2818@deffnx {} BFD_RELOC_860_LOW3 2819@deffnx {} BFD_RELOC_860_LOGOT0 2820@deffnx {} BFD_RELOC_860_SPGOT0 2821@deffnx {} BFD_RELOC_860_LOGOT1 2822@deffnx {} BFD_RELOC_860_SPGOT1 2823@deffnx {} BFD_RELOC_860_LOGOTOFF0 2824@deffnx {} BFD_RELOC_860_SPGOTOFF0 2825@deffnx {} BFD_RELOC_860_LOGOTOFF1 2826@deffnx {} BFD_RELOC_860_SPGOTOFF1 2827@deffnx {} BFD_RELOC_860_LOGOTOFF2 2828@deffnx {} BFD_RELOC_860_LOGOTOFF3 2829@deffnx {} BFD_RELOC_860_LOPC 2830@deffnx {} BFD_RELOC_860_HIGHADJ 2831@deffnx {} BFD_RELOC_860_HAGOT 2832@deffnx {} BFD_RELOC_860_HAGOTOFF 2833@deffnx {} BFD_RELOC_860_HAPC 2834@deffnx {} BFD_RELOC_860_HIGH 2835@deffnx {} BFD_RELOC_860_HIGOT 2836@deffnx {} BFD_RELOC_860_HIGOTOFF 2837Intel i860 Relocations. 2838@end deffn 2839@deffn {} BFD_RELOC_OPENRISC_ABS_26 2840@deffnx {} BFD_RELOC_OPENRISC_REL_26 2841OpenRISC Relocations. 2842@end deffn 2843@deffn {} BFD_RELOC_H8_DIR16A8 2844@deffnx {} BFD_RELOC_H8_DIR16R8 2845@deffnx {} BFD_RELOC_H8_DIR24A8 2846@deffnx {} BFD_RELOC_H8_DIR24R8 2847@deffnx {} BFD_RELOC_H8_DIR32A16 2848H8 elf Relocations. 2849@end deffn 2850@deffn {} BFD_RELOC_XSTORMY16_REL_12 2851@deffnx {} BFD_RELOC_XSTORMY16_12 2852@deffnx {} BFD_RELOC_XSTORMY16_24 2853@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 2854Sony Xstormy16 Relocations. 2855@end deffn 2856@deffn {} BFD_RELOC_RELC 2857Self-describing complex relocations. 2858@end deffn 2859@deffn {} BFD_RELOC_XC16X_PAG 2860@deffnx {} BFD_RELOC_XC16X_POF 2861@deffnx {} BFD_RELOC_XC16X_SEG 2862@deffnx {} BFD_RELOC_XC16X_SOF 2863Infineon Relocations. 2864@end deffn 2865@deffn {} BFD_RELOC_VAX_GLOB_DAT 2866@deffnx {} BFD_RELOC_VAX_JMP_SLOT 2867@deffnx {} BFD_RELOC_VAX_RELATIVE 2868Relocations used by VAX ELF. 2869@end deffn 2870@deffn {} BFD_RELOC_MT_PC16 2871Morpho MT - 16 bit immediate relocation. 2872@end deffn 2873@deffn {} BFD_RELOC_MT_HI16 2874Morpho MT - Hi 16 bits of an address. 2875@end deffn 2876@deffn {} BFD_RELOC_MT_LO16 2877Morpho MT - Low 16 bits of an address. 2878@end deffn 2879@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 2880Morpho MT - Used to tell the linker which vtable entries are used. 2881@end deffn 2882@deffn {} BFD_RELOC_MT_GNU_VTENTRY 2883Morpho MT - Used to tell the linker which vtable entries are used. 2884@end deffn 2885@deffn {} BFD_RELOC_MT_PCINSN8 2886Morpho MT - 8 bit immediate relocation. 2887@end deffn 2888@deffn {} BFD_RELOC_MSP430_10_PCREL 2889@deffnx {} BFD_RELOC_MSP430_16_PCREL 2890@deffnx {} BFD_RELOC_MSP430_16 2891@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 2892@deffnx {} BFD_RELOC_MSP430_16_BYTE 2893@deffnx {} BFD_RELOC_MSP430_2X_PCREL 2894@deffnx {} BFD_RELOC_MSP430_RL_PCREL 2895msp430 specific relocation codes 2896@end deffn 2897@deffn {} BFD_RELOC_IQ2000_OFFSET_16 2898@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 2899@deffnx {} BFD_RELOC_IQ2000_UHI16 2900IQ2000 Relocations. 2901@end deffn 2902@deffn {} BFD_RELOC_XTENSA_RTLD 2903Special Xtensa relocation used only by PLT entries in ELF shared 2904objects to indicate that the runtime linker should set the value 2905to one of its own internal functions or data structures. 2906@end deffn 2907@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 2908@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 2909@deffnx {} BFD_RELOC_XTENSA_RELATIVE 2910Xtensa relocations for ELF shared objects. 2911@end deffn 2912@deffn {} BFD_RELOC_XTENSA_PLT 2913Xtensa relocation used in ELF object files for symbols that may require 2914PLT entries. Otherwise, this is just a generic 32-bit relocation. 2915@end deffn 2916@deffn {} BFD_RELOC_XTENSA_DIFF8 2917@deffnx {} BFD_RELOC_XTENSA_DIFF16 2918@deffnx {} BFD_RELOC_XTENSA_DIFF32 2919Xtensa relocations to mark the difference of two local symbols. 2920These are only needed to support linker relaxation and can be ignored 2921when not relaxing. The field is set to the value of the difference 2922assuming no relaxation. The relocation encodes the position of the 2923first symbol so the linker can determine whether to adjust the field 2924value. 2925@end deffn 2926@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 2927@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 2928@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 2929@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 2930@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 2931@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 2932@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 2933@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 2934@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 2935@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 2936@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 2937@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 2938@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 2939@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 2940@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 2941Generic Xtensa relocations for instruction operands. Only the slot 2942number is encoded in the relocation. The relocation applies to the 2943last PC-relative immediate operand, or if there are no PC-relative 2944immediates, to the last immediate operand. 2945@end deffn 2946@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 2947@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 2948@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 2949@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 2950@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 2951@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 2952@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 2953@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 2954@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 2955@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 2956@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 2957@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 2958@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 2959@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 2960@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 2961Alternate Xtensa relocations. Only the slot is encoded in the 2962relocation. The meaning of these relocations is opcode-specific. 2963@end deffn 2964@deffn {} BFD_RELOC_XTENSA_OP0 2965@deffnx {} BFD_RELOC_XTENSA_OP1 2966@deffnx {} BFD_RELOC_XTENSA_OP2 2967Xtensa relocations for backward compatibility. These have all been 2968replaced by BFD_RELOC_XTENSA_SLOT0_OP. 2969@end deffn 2970@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 2971Xtensa relocation to mark that the assembler expanded the 2972instructions from an original target. The expansion size is 2973encoded in the reloc size. 2974@end deffn 2975@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 2976Xtensa relocation to mark that the linker should simplify 2977assembler-expanded instructions. This is commonly used 2978internally by the linker after analysis of a 2979BFD_RELOC_XTENSA_ASM_EXPAND. 2980@end deffn 2981@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 2982@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 2983@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 2984@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 2985@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 2986@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 2987@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 2988Xtensa TLS relocations. 2989@end deffn 2990@deffn {} BFD_RELOC_Z80_DISP8 29918 bit signed offset in (ix+d) or (iy+d). 2992@end deffn 2993@deffn {} BFD_RELOC_Z8K_DISP7 2994DJNZ offset. 2995@end deffn 2996@deffn {} BFD_RELOC_Z8K_CALLR 2997CALR offset. 2998@end deffn 2999@deffn {} BFD_RELOC_Z8K_IMM4L 30004 bit value. 3001@end deffn 3002@deffn {} BFD_RELOC_LM32_CALL 3003@deffnx {} BFD_RELOC_LM32_BRANCH 3004@deffnx {} BFD_RELOC_LM32_16_GOT 3005@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3006@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3007@deffnx {} BFD_RELOC_LM32_COPY 3008@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3009@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3010@deffnx {} BFD_RELOC_LM32_RELATIVE 3011Lattice Mico32 relocations. 3012@end deffn 3013@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3014Difference between two section addreses. Must be followed by a 3015BFD_RELOC_MACH_O_PAIR. 3016@end deffn 3017@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3018Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3019@end deffn 3020@deffn {} BFD_RELOC_MACH_O_PAIR 3021Pair of relocation. Contains the first symbol. 3022@end deffn 3023@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3024@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3025PCREL relocations. They are marked as branch to create PLT entry if 3026required. 3027@end deffn 3028@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3029Used when referencing a GOT entry. 3030@end deffn 3031@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3032Used when loading a GOT entry with movq. It is specially marked so that 3033the linker could optimize the movq to a leaq if possible. 3034@end deffn 3035@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32 3036Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3037@end deffn 3038@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64 3039Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3040@end deffn 3041@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3042Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3043@end deffn 3044@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3045Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3046@end deffn 3047@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3048Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3049@end deffn 3050@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3051This is a 32 bit reloc for the microblaze that stores the 3052low 16 bits of a value 3053@end deffn 3054@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3055This is a 32 bit pc-relative reloc for the microblaze that 3056stores the low 16 bits of a value 3057@end deffn 3058@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3059This is a 32 bit reloc for the microblaze that stores a 3060value relative to the read-only small data area anchor 3061@end deffn 3062@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3063This is a 32 bit reloc for the microblaze that stores a 3064value relative to the read-write small data area anchor 3065@end deffn 3066@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3067This is a 32 bit reloc for the microblaze to handle 3068expressions of the form "Symbol Op Symbol" 3069@end deffn 3070@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3071This is a 64 bit reloc that stores the 32 bit pc relative 3072value in two words (with an imm instruction). No relocation is 3073done here - only used for relaxing 3074@end deffn 3075@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3076This is a 64 bit reloc that stores the 32 bit pc relative 3077value in two words (with an imm instruction). The relocation is 3078PC-relative GOT offset 3079@end deffn 3080@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3081This is a 64 bit reloc that stores the 32 bit pc relative 3082value in two words (with an imm instruction). The relocation is 3083GOT offset 3084@end deffn 3085@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3086This is a 64 bit reloc that stores the 32 bit pc relative 3087value in two words (with an imm instruction). The relocation is 3088PC-relative offset into PLT 3089@end deffn 3090@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3091This is a 64 bit reloc that stores the 32 bit GOT relative 3092value in two words (with an imm instruction). The relocation is 3093relative offset from _GLOBAL_OFFSET_TABLE_ 3094@end deffn 3095@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3096This is a 32 bit reloc that stores the 32 bit GOT relative 3097value in a word. The relocation is relative offset from 3098@end deffn 3099@deffn {} BFD_RELOC_MICROBLAZE_COPY 3100This is used to tell the dynamic linker to copy the value out of 3101the dynamic object into the runtime process image. 3102@end deffn 3103@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3104AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3105Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3106@end deffn 3107@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3108Get to the page base of the global offset table entry for a symbol as 3109part of an ADRP instruction using a 21 bit PC relative value.Used in 3110conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3111@end deffn 3112@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3113AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3114offset, giving a 4KB aligned page base address. 3115@end deffn 3116@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3117AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3118offset, giving a 4KB aligned page base address, but with no overflow 3119checking. 3120@end deffn 3121@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3122AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3123@end deffn 3124@deffn {} BFD_RELOC_AARCH64_BRANCH19 3125AArch64 19 bit pc-relative conditional branch and compare & branch. 3126The lowest two bits must be zero and are not stored in the instruction, 3127giving a 21 bit signed byte offset. 3128@end deffn 3129@deffn {} BFD_RELOC_AARCH64_CALL26 3130AArch64 26 bit pc-relative unconditional branch and link. 3131The lowest two bits must be zero and are not stored in the instruction, 3132giving a 28 bit signed byte offset. 3133@end deffn 3134@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 3135AArch64 pseudo relocation code to be used internally by the AArch64 3136assembler and not (currently) written to any object files. 3137@end deffn 3138@deffn {} BFD_RELOC_AARCH64_JUMP26 3139AArch64 26 bit pc-relative unconditional branch. 3140The lowest two bits must be zero and are not stored in the instruction, 3141giving a 28 bit signed byte offset. 3142@end deffn 3143@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3144AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3145offset. The lowest two bits must be zero and are not stored in the 3146instruction, giving a 21 bit signed byte offset. 3147@end deffn 3148@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3149Unsigned 12 bit byte offset for 64 bit load/store from the page of 3150the GOT entry for this symbol. Used in conjunction with 3151BFD_RELOC_AARCH64_ADR_GOTPAGE. 3152@end deffn 3153@deffn {} BFD_RELOC_AARCH64_LDST_LO12 3154AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 3155address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3156@end deffn 3157@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3158AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3159address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3160@end deffn 3161@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3162AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3163address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3164@end deffn 3165@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3166AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3167address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3168@end deffn 3169@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3170AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3171address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3172@end deffn 3173@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3174AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3175address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3176@end deffn 3177@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3178AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3179of an unsigned address/value. 3180@end deffn 3181@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3182AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3183of a signed value. Changes instruction to MOVZ or MOVN depending on the 3184value's sign. 3185@end deffn 3186@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3187AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3188an address/value. No overflow checking. 3189@end deffn 3190@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3191AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3192of an unsigned address/value. 3193@end deffn 3194@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3195AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3196of an address/value. No overflow checking. 3197@end deffn 3198@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3199AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3200of a signed value. Changes instruction to MOVZ or MOVN depending on the 3201value's sign. 3202@end deffn 3203@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3204AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3205of an unsigned address/value. 3206@end deffn 3207@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3208AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3209of an address/value. No overflow checking. 3210@end deffn 3211@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3212AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3213of a signed value. Changes instruction to MOVZ or MOVN depending on the 3214value's sign. 3215@end deffn 3216@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3217AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3218of a signed or unsigned address/value. 3219@end deffn 3220@deffn {} BFD_RELOC_AARCH64_TLSDESC 3221AArch64 TLS relocation. 3222@end deffn 3223@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 3224AArch64 TLS DESC relocation. 3225@end deffn 3226@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC 3227AArch64 TLS DESC relocation. 3228@end deffn 3229@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE 3230AArch64 TLS DESC relocation. 3231@end deffn 3232@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 3233AArch64 TLS DESC relocation. 3234@end deffn 3235@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 3236AArch64 TLS DESC relocation. 3237@end deffn 3238@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC 3239AArch64 TLS DESC relocation. 3240@end deffn 3241@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19 3242AArch64 TLS DESC relocation. 3243@end deffn 3244@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 3245AArch64 TLS DESC relocation. 3246@end deffn 3247@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 3248AArch64 TLS DESC relocation. 3249@end deffn 3250@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 3251AArch64 TLS DESC relocation. 3252@end deffn 3253@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3254Unsigned 12 bit byte offset to global offset table entry for a symbols 3255tls_index structure. Used in conjunction with 3256BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3257@end deffn 3258@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3259Get to the page base of the global offset table entry for a symbols 3260tls_index structure as part of an adrp instruction using a 21 bit PC 3261relative value. Used in conjunction with 3262BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3263@end deffn 3264@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3265AArch64 TLS INITIAL EXEC relocation. 3266@end deffn 3267@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3268AArch64 TLS INITIAL EXEC relocation. 3269@end deffn 3270@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3271AArch64 TLS INITIAL EXEC relocation. 3272@end deffn 3273@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3274AArch64 TLS INITIAL EXEC relocation. 3275@end deffn 3276@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3277AArch64 TLS INITIAL EXEC relocation. 3278@end deffn 3279@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 3280AArch64 TLS LOCAL EXEC relocation. 3281@end deffn 3282@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 3283AArch64 TLS LOCAL EXEC relocation. 3284@end deffn 3285@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 3286AArch64 TLS LOCAL EXEC relocation. 3287@end deffn 3288@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 3289AArch64 TLS LOCAL EXEC relocation. 3290@end deffn 3291@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 3292AArch64 TLS LOCAL EXEC relocation. 3293@end deffn 3294@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 3295AArch64 TLS LOCAL EXEC relocation. 3296@end deffn 3297@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 3298AArch64 TLS LOCAL EXEC relocation. 3299@end deffn 3300@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 3301AArch64 TLS LOCAL EXEC relocation. 3302@end deffn 3303@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD64 3304AArch64 TLS relocation. 3305@end deffn 3306@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL64 3307AArch64 TLS relocation. 3308@end deffn 3309@deffn {} BFD_RELOC_AARCH64_TLS_TPREL64 3310AArch64 TLS relocation. 3311@end deffn 3312@deffn {} BFD_RELOC_AARCH64_TSTBR14 3313AArch64 14 bit pc-relative test bit and branch. 3314The lowest two bits must be zero and are not stored in the instruction, 3315giving a 16 bit signed byte offset. 3316@end deffn 3317@deffn {} BFD_RELOC_TILEPRO_COPY 3318@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 3319@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 3320@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 3321@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 3322@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 3323@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 3324@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 3325@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 3326@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 3327@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 3328@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 3329@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 3330@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 3331@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 3332@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 3333@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 3334@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 3335@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 3336@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 3337@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 3338@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 3339@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 3340@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 3341@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 3342@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 3343@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 3344@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 3345@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 3346@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 3347@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 3348@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 3349@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 3350@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 3351@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 3352@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 3353@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 3354@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 3355@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 3356@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 3357@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 3358@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 3359@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 3360@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 3361@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 3362@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 3363@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 3364@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 3365@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 3366@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 3367@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 3368@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 3369@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 3370@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 3371@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 3372@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 3373@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 3374@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 3375@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 3376@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 3377@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 3378@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 3379@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 3380@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 3381@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 3382@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 3383@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 3384@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 3385@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 3386@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 3387@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 3388@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 3389@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 3390@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 3391@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 3392@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 3393@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 3394@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 3395@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 3396Tilera TILEPro Relocations. 3397@end deffn 3398@deffn {} BFD_RELOC_TILEGX_HW0 3399@deffnx {} BFD_RELOC_TILEGX_HW1 3400@deffnx {} BFD_RELOC_TILEGX_HW2 3401@deffnx {} BFD_RELOC_TILEGX_HW3 3402@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 3403@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 3404@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 3405@deffnx {} BFD_RELOC_TILEGX_COPY 3406@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 3407@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 3408@deffnx {} BFD_RELOC_TILEGX_RELATIVE 3409@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 3410@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 3411@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 3412@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 3413@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 3414@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 3415@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 3416@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 3417@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 3418@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 3419@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 3420@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 3421@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 3422@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 3423@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 3424@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 3425@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 3426@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 3427@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 3428@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 3429@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 3430@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 3431@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 3432@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 3433@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 3434@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 3435@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 3436@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 3437@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 3438@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 3439@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 3440@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 3441@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 3442@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 3443@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 3444@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 3445@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 3446@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 3447@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 3448@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 3449@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 3450@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 3451@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 3452@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 3453@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 3454@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 3455@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 3456@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 3457@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 3458@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 3459@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 3460@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 3461@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 3462@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 3463@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 3464@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 3465@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 3466@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 3467@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 3468@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 3469@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 3470@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 3471@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 3472@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 3473@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 3474@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 3475@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 3476@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 3477@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 3478@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 3479@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 3480@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 3481@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 3482@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 3483@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 3484@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 3485@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 3486@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 3487@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 3488@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 3489@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 3490@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 3491@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 3492@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 3493Tilera TILE-Gx Relocations. 3494@end deffn 3495@deffn {} BFD_RELOC_EPIPHANY_SIMM8 3496Adapteva EPIPHANY - 8 bit signed pc-relative displacement 3497@end deffn 3498@deffn {} BFD_RELOC_EPIPHANY_SIMM24 3499Adapteva EPIPHANY - 24 bit signed pc-relative displacement 3500@end deffn 3501@deffn {} BFD_RELOC_EPIPHANY_HIGH 3502Adapteva EPIPHANY - 16 most-significant bits of absolute address 3503@end deffn 3504@deffn {} BFD_RELOC_EPIPHANY_LOW 3505Adapteva EPIPHANY - 16 least-significant bits of absolute address 3506@end deffn 3507@deffn {} BFD_RELOC_EPIPHANY_SIMM11 3508Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 3509@end deffn 3510@deffn {} BFD_RELOC_EPIPHANY_IMM11 3511Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 3512@end deffn 3513@deffn {} BFD_RELOC_EPIPHANY_IMM8 3514Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 3515@end deffn 3516 3517@example 3518 3519typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 3520@end example 3521@findex bfd_reloc_type_lookup 3522@subsubsection @code{bfd_reloc_type_lookup} 3523@strong{Synopsis} 3524@example 3525reloc_howto_type *bfd_reloc_type_lookup 3526 (bfd *abfd, bfd_reloc_code_real_type code); 3527reloc_howto_type *bfd_reloc_name_lookup 3528 (bfd *abfd, const char *reloc_name); 3529@end example 3530@strong{Description}@* 3531Return a pointer to a howto structure which, when 3532invoked, will perform the relocation @var{code} on data from the 3533architecture noted. 3534 3535@findex bfd_default_reloc_type_lookup 3536@subsubsection @code{bfd_default_reloc_type_lookup} 3537@strong{Synopsis} 3538@example 3539reloc_howto_type *bfd_default_reloc_type_lookup 3540 (bfd *abfd, bfd_reloc_code_real_type code); 3541@end example 3542@strong{Description}@* 3543Provides a default relocation lookup routine for any architecture. 3544 3545@findex bfd_get_reloc_code_name 3546@subsubsection @code{bfd_get_reloc_code_name} 3547@strong{Synopsis} 3548@example 3549const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 3550@end example 3551@strong{Description}@* 3552Provides a printable name for the supplied relocation code. 3553Useful mainly for printing error messages. 3554 3555@findex bfd_generic_relax_section 3556@subsubsection @code{bfd_generic_relax_section} 3557@strong{Synopsis} 3558@example 3559bfd_boolean bfd_generic_relax_section 3560 (bfd *abfd, 3561 asection *section, 3562 struct bfd_link_info *, 3563 bfd_boolean *); 3564@end example 3565@strong{Description}@* 3566Provides default handling for relaxing for back ends which 3567don't do relaxing. 3568 3569@findex bfd_generic_gc_sections 3570@subsubsection @code{bfd_generic_gc_sections} 3571@strong{Synopsis} 3572@example 3573bfd_boolean bfd_generic_gc_sections 3574 (bfd *, struct bfd_link_info *); 3575@end example 3576@strong{Description}@* 3577Provides default handling for relaxing for back ends which 3578don't do section gc -- i.e., does nothing. 3579 3580@findex bfd_generic_lookup_section_flags 3581@subsubsection @code{bfd_generic_lookup_section_flags} 3582@strong{Synopsis} 3583@example 3584bfd_boolean bfd_generic_lookup_section_flags 3585 (struct bfd_link_info *, struct flag_info *, asection *); 3586@end example 3587@strong{Description}@* 3588Provides default handling for section flags lookup 3589-- i.e., does nothing. 3590Returns FALSE if the section should be omitted, otherwise TRUE. 3591 3592@findex bfd_generic_merge_sections 3593@subsubsection @code{bfd_generic_merge_sections} 3594@strong{Synopsis} 3595@example 3596bfd_boolean bfd_generic_merge_sections 3597 (bfd *, struct bfd_link_info *); 3598@end example 3599@strong{Description}@* 3600Provides default handling for SEC_MERGE section merging for back ends 3601which don't have SEC_MERGE support -- i.e., does nothing. 3602 3603@findex bfd_generic_get_relocated_section_contents 3604@subsubsection @code{bfd_generic_get_relocated_section_contents} 3605@strong{Synopsis} 3606@example 3607bfd_byte *bfd_generic_get_relocated_section_contents 3608 (bfd *abfd, 3609 struct bfd_link_info *link_info, 3610 struct bfd_link_order *link_order, 3611 bfd_byte *data, 3612 bfd_boolean relocatable, 3613 asymbol **symbols); 3614@end example 3615@strong{Description}@* 3616Provides default handling of relocation effort for back ends 3617which can't be bothered to do it efficiently. 3618 3619