reloc.texi revision 1.2
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* The relocation is relative to the field being relocated. */ 285 bfd_boolean pc_relative; 286 287 /* The bit position of the reloc value in the destination. 288 The relocated value is left shifted by this amount. */ 289 unsigned int bitpos; 290 291 /* What type of overflow error should be checked for when 292 relocating. */ 293 enum complain_overflow complain_on_overflow; 294 295 /* If this field is non null, then the supplied function is 296 called rather than the normal function. This allows really 297 strange relocation methods to be accommodated (e.g., i960 callj 298 instructions). */ 299 bfd_reloc_status_type (*special_function) 300 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 301 bfd *, char **); 302 303 /* The textual name of the relocation type. */ 304 char *name; 305 306 /* Some formats record a relocation addend in the section contents 307 rather than with the relocation. For ELF formats this is the 308 distinction between USE_REL and USE_RELA (though the code checks 309 for USE_REL == 1/0). The value of this field is TRUE if the 310 addend is recorded with the section contents; when performing a 311 partial link (ld -r) the section contents (the data) will be 312 modified. The value of this field is FALSE if addends are 313 recorded with the relocation (in arelent.addend); when performing 314 a partial link the relocation will be modified. 315 All relocations for all ELF USE_RELA targets should set this field 316 to FALSE (values of TRUE should be looked on with suspicion). 317 However, the converse is not true: not all relocations of all ELF 318 USE_REL targets set this field to TRUE. Why this is so is peculiar 319 to each particular target. For relocs that aren't used in partial 320 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 321 bfd_boolean partial_inplace; 322 323 /* src_mask selects the part of the instruction (or data) to be used 324 in the relocation sum. If the target relocations don't have an 325 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 326 dst_mask to extract the addend from the section contents. If 327 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 328 field should be zero. Non-zero values for ELF USE_RELA targets are 329 bogus as in those cases the value in the dst_mask part of the 330 section contents should be treated as garbage. */ 331 bfd_vma src_mask; 332 333 /* dst_mask selects which parts of the instruction (or data) are 334 replaced with a relocated value. */ 335 bfd_vma dst_mask; 336 337 /* When some formats create PC relative instructions, they leave 338 the value of the pc of the place being relocated in the offset 339 slot of the instruction, so that a PC relative relocation can 340 be made just by adding in an ordinary offset (e.g., sun3 a.out). 341 Some formats leave the displacement part of an instruction 342 empty (e.g., m88k bcs); this flag signals the fact. */ 343 bfd_boolean pcrel_offset; 344@}; 345 346@end example 347@findex The HOWTO Macro 348@subsubsection @code{The HOWTO Macro} 349@strong{Description}@* 350The HOWTO define is horrible and will go away. 351@example 352#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 353 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 354@end example 355 356@strong{Description}@* 357And will be replaced with the totally magic way. But for the 358moment, we are compatible, so do it this way. 359@example 360#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 361 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 362 NAME, FALSE, 0, 0, IN) 363 364@end example 365 366@strong{Description}@* 367This is used to fill in an empty howto entry in an array. 368@example 369#define EMPTY_HOWTO(C) \ 370 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 371 NULL, FALSE, 0, 0, FALSE) 372 373@end example 374 375@strong{Description}@* 376Helper routine to turn a symbol into a relocation value. 377@example 378#define HOWTO_PREPARE(relocation, symbol) \ 379 @{ \ 380 if (symbol != NULL) \ 381 @{ \ 382 if (bfd_is_com_section (symbol->section)) \ 383 @{ \ 384 relocation = 0; \ 385 @} \ 386 else \ 387 @{ \ 388 relocation = symbol->value; \ 389 @} \ 390 @} \ 391 @} 392 393@end example 394 395@findex bfd_get_reloc_size 396@subsubsection @code{bfd_get_reloc_size} 397@strong{Synopsis} 398@example 399unsigned int bfd_get_reloc_size (reloc_howto_type *); 400@end example 401@strong{Description}@* 402For a reloc_howto_type that operates on a fixed number of bytes, 403this returns the number of bytes operated on. 404 405@findex arelent_chain 406@subsubsection @code{arelent_chain} 407@strong{Description}@* 408How relocs are tied together in an @code{asection}: 409@example 410typedef struct relent_chain 411@{ 412 arelent relent; 413 struct relent_chain *next; 414@} 415arelent_chain; 416 417@end example 418 419@findex bfd_check_overflow 420@subsubsection @code{bfd_check_overflow} 421@strong{Synopsis} 422@example 423bfd_reloc_status_type bfd_check_overflow 424 (enum complain_overflow how, 425 unsigned int bitsize, 426 unsigned int rightshift, 427 unsigned int addrsize, 428 bfd_vma relocation); 429@end example 430@strong{Description}@* 431Perform overflow checking on @var{relocation} which has 432@var{bitsize} significant bits and will be shifted right by 433@var{rightshift} bits, on a machine with addresses containing 434@var{addrsize} significant bits. The result is either of 435@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 436 437@findex bfd_perform_relocation 438@subsubsection @code{bfd_perform_relocation} 439@strong{Synopsis} 440@example 441bfd_reloc_status_type bfd_perform_relocation 442 (bfd *abfd, 443 arelent *reloc_entry, 444 void *data, 445 asection *input_section, 446 bfd *output_bfd, 447 char **error_message); 448@end example 449@strong{Description}@* 450If @var{output_bfd} is supplied to this function, the 451generated image will be relocatable; the relocations are 452copied to the output file after they have been changed to 453reflect the new state of the world. There are two ways of 454reflecting the results of partial linkage in an output file: 455by modifying the output data in place, and by modifying the 456relocation record. Some native formats (e.g., basic a.out and 457basic coff) have no way of specifying an addend in the 458relocation type, so the addend has to go in the output data. 459This is no big deal since in these formats the output data 460slot will always be big enough for the addend. Complex reloc 461types with addends were invented to solve just this problem. 462The @var{error_message} argument is set to an error message if 463this return @code{bfd_reloc_dangerous}. 464 465@findex bfd_install_relocation 466@subsubsection @code{bfd_install_relocation} 467@strong{Synopsis} 468@example 469bfd_reloc_status_type bfd_install_relocation 470 (bfd *abfd, 471 arelent *reloc_entry, 472 void *data, bfd_vma data_start, 473 asection *input_section, 474 char **error_message); 475@end example 476@strong{Description}@* 477This looks remarkably like @code{bfd_perform_relocation}, except it 478does not expect that the section contents have been filled in. 479I.e., it's suitable for use when creating, rather than applying 480a relocation. 481 482For now, this function should be considered reserved for the 483assembler. 484 485 486@node howto manager, , typedef arelent, Relocations 487@subsection The howto manager 488When an application wants to create a relocation, but doesn't 489know what the target machine might call it, it can find out by 490using this bit of code. 491 492@findex bfd_reloc_code_type 493@subsubsection @code{bfd_reloc_code_type} 494@strong{Description}@* 495The insides of a reloc code. The idea is that, eventually, there 496will be one enumerator for every type of relocation we ever do. 497Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 498return a howto pointer. 499 500This does mean that the application must determine the correct 501enumerator value; you can't get a howto pointer from a random set 502of attributes. 503 504Here are the possible values for @code{enum bfd_reloc_code_real}: 505 506@deffn {} BFD_RELOC_64 507@deffnx {} BFD_RELOC_32 508@deffnx {} BFD_RELOC_26 509@deffnx {} BFD_RELOC_24 510@deffnx {} BFD_RELOC_16 511@deffnx {} BFD_RELOC_14 512@deffnx {} BFD_RELOC_8 513Basic absolute relocations of N bits. 514@end deffn 515@deffn {} BFD_RELOC_64_PCREL 516@deffnx {} BFD_RELOC_32_PCREL 517@deffnx {} BFD_RELOC_24_PCREL 518@deffnx {} BFD_RELOC_16_PCREL 519@deffnx {} BFD_RELOC_12_PCREL 520@deffnx {} BFD_RELOC_8_PCREL 521PC-relative relocations. Sometimes these are relative to the address 522of the relocation itself; sometimes they are relative to the start of 523the section containing the relocation. It depends on the specific target. 524 525The 24-bit relocation is used in some Intel 960 configurations. 526@end deffn 527@deffn {} BFD_RELOC_32_SECREL 528Section relative relocations. Some targets need this for DWARF2. 529@end deffn 530@deffn {} BFD_RELOC_32_GOT_PCREL 531@deffnx {} BFD_RELOC_16_GOT_PCREL 532@deffnx {} BFD_RELOC_8_GOT_PCREL 533@deffnx {} BFD_RELOC_32_GOTOFF 534@deffnx {} BFD_RELOC_16_GOTOFF 535@deffnx {} BFD_RELOC_LO16_GOTOFF 536@deffnx {} BFD_RELOC_HI16_GOTOFF 537@deffnx {} BFD_RELOC_HI16_S_GOTOFF 538@deffnx {} BFD_RELOC_8_GOTOFF 539@deffnx {} BFD_RELOC_64_PLT_PCREL 540@deffnx {} BFD_RELOC_32_PLT_PCREL 541@deffnx {} BFD_RELOC_24_PLT_PCREL 542@deffnx {} BFD_RELOC_16_PLT_PCREL 543@deffnx {} BFD_RELOC_8_PLT_PCREL 544@deffnx {} BFD_RELOC_64_PLTOFF 545@deffnx {} BFD_RELOC_32_PLTOFF 546@deffnx {} BFD_RELOC_16_PLTOFF 547@deffnx {} BFD_RELOC_LO16_PLTOFF 548@deffnx {} BFD_RELOC_HI16_PLTOFF 549@deffnx {} BFD_RELOC_HI16_S_PLTOFF 550@deffnx {} BFD_RELOC_8_PLTOFF 551For ELF. 552@end deffn 553@deffn {} BFD_RELOC_68K_GLOB_DAT 554@deffnx {} BFD_RELOC_68K_JMP_SLOT 555@deffnx {} BFD_RELOC_68K_RELATIVE 556@deffnx {} BFD_RELOC_68K_TLS_GD32 557@deffnx {} BFD_RELOC_68K_TLS_GD16 558@deffnx {} BFD_RELOC_68K_TLS_GD8 559@deffnx {} BFD_RELOC_68K_TLS_LDM32 560@deffnx {} BFD_RELOC_68K_TLS_LDM16 561@deffnx {} BFD_RELOC_68K_TLS_LDM8 562@deffnx {} BFD_RELOC_68K_TLS_LDO32 563@deffnx {} BFD_RELOC_68K_TLS_LDO16 564@deffnx {} BFD_RELOC_68K_TLS_LDO8 565@deffnx {} BFD_RELOC_68K_TLS_IE32 566@deffnx {} BFD_RELOC_68K_TLS_IE16 567@deffnx {} BFD_RELOC_68K_TLS_IE8 568@deffnx {} BFD_RELOC_68K_TLS_LE32 569@deffnx {} BFD_RELOC_68K_TLS_LE16 570@deffnx {} BFD_RELOC_68K_TLS_LE8 571Relocations used by 68K ELF. 572@end deffn 573@deffn {} BFD_RELOC_VAX_GLOB_DAT 574@deffnx {} BFD_RELOC_VAX_GLOB_REF 575@deffnx {} BFD_RELOC_VAX_JMP_SLOT 576@deffnx {} BFD_RELOC_VAX_RELATIVE 577Relocations used by VAX ELF. 578@end deffn 579@deffn {} BFD_RELOC_32_BASEREL 580@deffnx {} BFD_RELOC_16_BASEREL 581@deffnx {} BFD_RELOC_LO16_BASEREL 582@deffnx {} BFD_RELOC_HI16_BASEREL 583@deffnx {} BFD_RELOC_HI16_S_BASEREL 584@deffnx {} BFD_RELOC_8_BASEREL 585@deffnx {} BFD_RELOC_RVA 586Linkage-table relative. 587@end deffn 588@deffn {} BFD_RELOC_8_FFnn 589Absolute 8-bit relocation, but used to form an address like 0xFFnn. 590@end deffn 591@deffn {} BFD_RELOC_32_PCREL_S2 592@deffnx {} BFD_RELOC_16_PCREL_S2 593@deffnx {} BFD_RELOC_23_PCREL_S2 594These PC-relative relocations are stored as word displacements -- 595i.e., byte displacements shifted right two bits. The 30-bit word 596displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 597SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 598signed 16-bit displacement is used on the MIPS, and the 23-bit 599displacement is used on the Alpha. 600@end deffn 601@deffn {} BFD_RELOC_HI22 602@deffnx {} BFD_RELOC_LO10 603High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 604the target word. These are used on the SPARC. 605@end deffn 606@deffn {} BFD_RELOC_GPREL16 607@deffnx {} BFD_RELOC_GPREL32 608For systems that allocate a Global Pointer register, these are 609displacements off that register. These relocation types are 610handled specially, because the value the register will have is 611decided relatively late. 612@end deffn 613@deffn {} BFD_RELOC_I960_CALLJ 614Reloc types used for i960/b.out. 615@end deffn 616@deffn {} BFD_RELOC_NONE 617@deffnx {} BFD_RELOC_SPARC_WDISP22 618@deffnx {} BFD_RELOC_SPARC22 619@deffnx {} BFD_RELOC_SPARC13 620@deffnx {} BFD_RELOC_SPARC_GOT10 621@deffnx {} BFD_RELOC_SPARC_GOT13 622@deffnx {} BFD_RELOC_SPARC_GOT22 623@deffnx {} BFD_RELOC_SPARC_PC10 624@deffnx {} BFD_RELOC_SPARC_PC22 625@deffnx {} BFD_RELOC_SPARC_WPLT30 626@deffnx {} BFD_RELOC_SPARC_COPY 627@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 628@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 629@deffnx {} BFD_RELOC_SPARC_RELATIVE 630@deffnx {} BFD_RELOC_SPARC_UA16 631@deffnx {} BFD_RELOC_SPARC_UA32 632@deffnx {} BFD_RELOC_SPARC_UA64 633@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 634@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 635@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 636@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 637@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 638@deffnx {} BFD_RELOC_SPARC_JMP_IREL 639@deffnx {} BFD_RELOC_SPARC_IRELATIVE 640SPARC ELF relocations. There is probably some overlap with other 641relocation types already defined. 642@end deffn 643@deffn {} BFD_RELOC_SPARC_BASE13 644@deffnx {} BFD_RELOC_SPARC_BASE22 645I think these are specific to SPARC a.out (e.g., Sun 4). 646@end deffn 647@deffn {} BFD_RELOC_SPARC_64 648@deffnx {} BFD_RELOC_SPARC_10 649@deffnx {} BFD_RELOC_SPARC_11 650@deffnx {} BFD_RELOC_SPARC_OLO10 651@deffnx {} BFD_RELOC_SPARC_HH22 652@deffnx {} BFD_RELOC_SPARC_HM10 653@deffnx {} BFD_RELOC_SPARC_LM22 654@deffnx {} BFD_RELOC_SPARC_PC_HH22 655@deffnx {} BFD_RELOC_SPARC_PC_HM10 656@deffnx {} BFD_RELOC_SPARC_PC_LM22 657@deffnx {} BFD_RELOC_SPARC_WDISP16 658@deffnx {} BFD_RELOC_SPARC_WDISP19 659@deffnx {} BFD_RELOC_SPARC_7 660@deffnx {} BFD_RELOC_SPARC_6 661@deffnx {} BFD_RELOC_SPARC_5 662@deffnx {} BFD_RELOC_SPARC_DISP64 663@deffnx {} BFD_RELOC_SPARC_PLT32 664@deffnx {} BFD_RELOC_SPARC_PLT64 665@deffnx {} BFD_RELOC_SPARC_HIX22 666@deffnx {} BFD_RELOC_SPARC_LOX10 667@deffnx {} BFD_RELOC_SPARC_H44 668@deffnx {} BFD_RELOC_SPARC_M44 669@deffnx {} BFD_RELOC_SPARC_L44 670@deffnx {} BFD_RELOC_SPARC_REGISTER 671SPARC64 relocations 672@end deffn 673@deffn {} BFD_RELOC_SPARC_REV32 674SPARC little endian relocation 675@end deffn 676@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 677@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 678@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 679@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 680@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 681@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 682@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 683@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 684@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 685@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 686@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 687@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 688@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 689@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 690@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 691@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 692@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 693@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 694@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 695@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 696@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 697@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 698@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 699@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 700SPARC TLS relocations 701@end deffn 702@deffn {} BFD_RELOC_SPU_IMM7 703@deffnx {} BFD_RELOC_SPU_IMM8 704@deffnx {} BFD_RELOC_SPU_IMM10 705@deffnx {} BFD_RELOC_SPU_IMM10W 706@deffnx {} BFD_RELOC_SPU_IMM16 707@deffnx {} BFD_RELOC_SPU_IMM16W 708@deffnx {} BFD_RELOC_SPU_IMM18 709@deffnx {} BFD_RELOC_SPU_PCREL9a 710@deffnx {} BFD_RELOC_SPU_PCREL9b 711@deffnx {} BFD_RELOC_SPU_PCREL16 712@deffnx {} BFD_RELOC_SPU_LO16 713@deffnx {} BFD_RELOC_SPU_HI16 714@deffnx {} BFD_RELOC_SPU_PPU32 715@deffnx {} BFD_RELOC_SPU_PPU64 716@deffnx {} BFD_RELOC_SPU_ADD_PIC 717SPU Relocations. 718@end deffn 719@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 720Alpha ECOFF and ELF relocations. Some of these treat the symbol or 721"addend" in some special way. 722For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 723writing; when reading, it will be the absolute section symbol. The 724addend is the displacement in bytes of the "lda" instruction from 725the "ldah" instruction (which is at the address of this reloc). 726@end deffn 727@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 728For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 729with GPDISP_HI16 relocs. The addend is ignored when writing the 730relocations out, and is filled in with the file's GP value on 731reading, for convenience. 732@end deffn 733@deffn {} BFD_RELOC_ALPHA_GPDISP 734The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 735relocation except that there is no accompanying GPDISP_LO16 736relocation. 737@end deffn 738@deffn {} BFD_RELOC_ALPHA_LITERAL 739@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 740@deffnx {} BFD_RELOC_ALPHA_LITUSE 741The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 742the assembler turns it into a LDQ instruction to load the address of 743the symbol, and then fills in a register in the real instruction. 744 745The LITERAL reloc, at the LDQ instruction, refers to the .lita 746section symbol. The addend is ignored when writing, but is filled 747in with the file's GP value on reading, for convenience, as with the 748GPDISP_LO16 reloc. 749 750The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 751It should refer to the symbol to be referenced, as with 16_GOTOFF, 752but it generates output not based on the position within the .got 753section, but relative to the GP value chosen for the file during the 754final link stage. 755 756The LITUSE reloc, on the instruction using the loaded address, gives 757information to the linker that it might be able to use to optimize 758away some literal section references. The symbol is ignored (read 759as the absolute section symbol), and the "addend" indicates the type 760of instruction using the register: 7611 - "memory" fmt insn 7622 - byte-manipulation (byte offset reg) 7633 - jsr (target of branch) 764@end deffn 765@deffn {} BFD_RELOC_ALPHA_HINT 766The HINT relocation indicates a value that should be filled into the 767"hint" field of a jmp/jsr/ret instruction, for possible branch- 768prediction logic which may be provided on some processors. 769@end deffn 770@deffn {} BFD_RELOC_ALPHA_LINKAGE 771The LINKAGE relocation outputs a linkage pair in the object file, 772which is filled by the linker. 773@end deffn 774@deffn {} BFD_RELOC_ALPHA_CODEADDR 775The CODEADDR relocation outputs a STO_CA in the object file, 776which is filled by the linker. 777@end deffn 778@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 779@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 780The GPREL_HI/LO relocations together form a 32-bit offset from the 781GP register. 782@end deffn 783@deffn {} BFD_RELOC_ALPHA_BRSGP 784Like BFD_RELOC_23_PCREL_S2, except that the source and target must 785share a common GP, and the target address is adjusted for 786STO_ALPHA_STD_GPLOAD. 787@end deffn 788@deffn {} BFD_RELOC_ALPHA_NOP 789The NOP relocation outputs a NOP if the longword displacement 790between two procedure entry points is < 2^21. 791@end deffn 792@deffn {} BFD_RELOC_ALPHA_BSR 793The BSR relocation outputs a BSR if the longword displacement 794between two procedure entry points is < 2^21. 795@end deffn 796@deffn {} BFD_RELOC_ALPHA_LDA 797The LDA relocation outputs a LDA if the longword displacement 798between two procedure entry points is < 2^16. 799@end deffn 800@deffn {} BFD_RELOC_ALPHA_BOH 801The BOH relocation outputs a BSR if the longword displacement 802between two procedure entry points is < 2^21, or else a hint. 803@end deffn 804@deffn {} BFD_RELOC_ALPHA_TLSGD 805@deffnx {} BFD_RELOC_ALPHA_TLSLDM 806@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 807@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 808@deffnx {} BFD_RELOC_ALPHA_DTPREL64 809@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 810@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 811@deffnx {} BFD_RELOC_ALPHA_DTPREL16 812@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 813@deffnx {} BFD_RELOC_ALPHA_TPREL64 814@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 815@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 816@deffnx {} BFD_RELOC_ALPHA_TPREL16 817Alpha thread-local storage relocations. 818@end deffn 819@deffn {} BFD_RELOC_MIPS_JMP 820Bits 27..2 of the relocation address shifted right 2 bits; 821simple reloc otherwise. 822@end deffn 823@deffn {} BFD_RELOC_MIPS16_JMP 824The MIPS16 jump instruction. 825@end deffn 826@deffn {} BFD_RELOC_MIPS16_GPREL 827MIPS16 GP relative reloc. 828@end deffn 829@deffn {} BFD_RELOC_HI16 830High 16 bits of 32-bit value; simple reloc. 831@end deffn 832@deffn {} BFD_RELOC_HI16_S 833High 16 bits of 32-bit value but the low 16 bits will be sign 834extended and added to form the final result. If the low 16 835bits form a negative number, we need to add one to the high value 836to compensate for the borrow when the low bits are added. 837@end deffn 838@deffn {} BFD_RELOC_LO16 839Low 16 bits. 840@end deffn 841@deffn {} BFD_RELOC_HI16_PCREL 842High 16 bits of 32-bit pc-relative value 843@end deffn 844@deffn {} BFD_RELOC_HI16_S_PCREL 845High 16 bits of 32-bit pc-relative value, adjusted 846@end deffn 847@deffn {} BFD_RELOC_LO16_PCREL 848Low 16 bits of pc-relative value 849@end deffn 850@deffn {} BFD_RELOC_MIPS16_GOT16 851@deffnx {} BFD_RELOC_MIPS16_CALL16 852Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 85316-bit immediate fields 854@end deffn 855@deffn {} BFD_RELOC_MIPS16_HI16 856MIPS16 high 16 bits of 32-bit value. 857@end deffn 858@deffn {} BFD_RELOC_MIPS16_HI16_S 859MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 860extended and added to form the final result. If the low 16 861bits form a negative number, we need to add one to the high value 862to compensate for the borrow when the low bits are added. 863@end deffn 864@deffn {} BFD_RELOC_MIPS16_LO16 865MIPS16 low 16 bits. 866@end deffn 867@deffn {} BFD_RELOC_MIPS_LITERAL 868Relocation against a MIPS literal section. 869@end deffn 870@deffn {} BFD_RELOC_MIPS_GOT16 871@deffnx {} BFD_RELOC_MIPS_CALL16 872@deffnx {} BFD_RELOC_MIPS_GOT_HI16 873@deffnx {} BFD_RELOC_MIPS_GOT_LO16 874@deffnx {} BFD_RELOC_MIPS_CALL_HI16 875@deffnx {} BFD_RELOC_MIPS_CALL_LO16 876@deffnx {} BFD_RELOC_MIPS_SUB 877@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 878@deffnx {} BFD_RELOC_MIPS_GOT_OFST 879@deffnx {} BFD_RELOC_MIPS_GOT_DISP 880@deffnx {} BFD_RELOC_MIPS_SHIFT5 881@deffnx {} BFD_RELOC_MIPS_SHIFT6 882@deffnx {} BFD_RELOC_MIPS_INSERT_A 883@deffnx {} BFD_RELOC_MIPS_INSERT_B 884@deffnx {} BFD_RELOC_MIPS_DELETE 885@deffnx {} BFD_RELOC_MIPS_HIGHEST 886@deffnx {} BFD_RELOC_MIPS_HIGHER 887@deffnx {} BFD_RELOC_MIPS_SCN_DISP 888@deffnx {} BFD_RELOC_MIPS_REL16 889@deffnx {} BFD_RELOC_MIPS_RELGOT 890@deffnx {} BFD_RELOC_MIPS_JALR 891@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 892@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 893@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 894@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 895@deffnx {} BFD_RELOC_MIPS_TLS_GD 896@deffnx {} BFD_RELOC_MIPS_TLS_LDM 897@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 898@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 899@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 900@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 901@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 902@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 903@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 904MIPS ELF relocations. 905@end deffn 906@deffn {} BFD_RELOC_MIPS_COPY 907@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 908MIPS ELF relocations (VxWorks and PLT extensions). 909@end deffn 910@deffn {} BFD_RELOC_MOXIE_10_PCREL 911Moxie ELF relocations. 912@end deffn 913@deffn {} BFD_RELOC_FRV_LABEL16 914@deffnx {} BFD_RELOC_FRV_LABEL24 915@deffnx {} BFD_RELOC_FRV_LO16 916@deffnx {} BFD_RELOC_FRV_HI16 917@deffnx {} BFD_RELOC_FRV_GPREL12 918@deffnx {} BFD_RELOC_FRV_GPRELU12 919@deffnx {} BFD_RELOC_FRV_GPREL32 920@deffnx {} BFD_RELOC_FRV_GPRELHI 921@deffnx {} BFD_RELOC_FRV_GPRELLO 922@deffnx {} BFD_RELOC_FRV_GOT12 923@deffnx {} BFD_RELOC_FRV_GOTHI 924@deffnx {} BFD_RELOC_FRV_GOTLO 925@deffnx {} BFD_RELOC_FRV_FUNCDESC 926@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 927@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 928@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 929@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 930@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 931@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 932@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 933@deffnx {} BFD_RELOC_FRV_GOTOFF12 934@deffnx {} BFD_RELOC_FRV_GOTOFFHI 935@deffnx {} BFD_RELOC_FRV_GOTOFFLO 936@deffnx {} BFD_RELOC_FRV_GETTLSOFF 937@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 938@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 939@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 940@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 941@deffnx {} BFD_RELOC_FRV_TLSMOFF12 942@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 943@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 944@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 945@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 946@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 947@deffnx {} BFD_RELOC_FRV_TLSOFF 948@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 949@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 950@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 951@deffnx {} BFD_RELOC_FRV_TLSMOFF 952Fujitsu Frv Relocations. 953@end deffn 954@deffn {} BFD_RELOC_MN10300_GOTOFF24 955This is a 24bit GOT-relative reloc for the mn10300. 956@end deffn 957@deffn {} BFD_RELOC_MN10300_GOT32 958This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 959in the instruction. 960@end deffn 961@deffn {} BFD_RELOC_MN10300_GOT24 962This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 963in the instruction. 964@end deffn 965@deffn {} BFD_RELOC_MN10300_GOT16 966This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 967in the instruction. 968@end deffn 969@deffn {} BFD_RELOC_MN10300_COPY 970Copy symbol at runtime. 971@end deffn 972@deffn {} BFD_RELOC_MN10300_GLOB_DAT 973Create GOT entry. 974@end deffn 975@deffn {} BFD_RELOC_MN10300_JMP_SLOT 976Create PLT entry. 977@end deffn 978@deffn {} BFD_RELOC_MN10300_RELATIVE 979Adjust by program base. 980@end deffn 981@deffn {} BFD_RELOC_MN10300_SYM_DIFF 982Together with another reloc targeted at the same location, 983allows for a value that is the difference of two symbols 984in the same section. 985@end deffn 986@deffn {} BFD_RELOC_MN10300_ALIGN 987The addend of this reloc is an alignment power that must 988be honoured at the offset's location, regardless of linker 989relaxation. 990@end deffn 991@deffn {} BFD_RELOC_386_GOT32 992@deffnx {} BFD_RELOC_386_PLT32 993@deffnx {} BFD_RELOC_386_COPY 994@deffnx {} BFD_RELOC_386_GLOB_DAT 995@deffnx {} BFD_RELOC_386_JUMP_SLOT 996@deffnx {} BFD_RELOC_386_RELATIVE 997@deffnx {} BFD_RELOC_386_GOTOFF 998@deffnx {} BFD_RELOC_386_GOTPC 999@deffnx {} BFD_RELOC_386_TLS_TPOFF 1000@deffnx {} BFD_RELOC_386_TLS_IE 1001@deffnx {} BFD_RELOC_386_TLS_GOTIE 1002@deffnx {} BFD_RELOC_386_TLS_LE 1003@deffnx {} BFD_RELOC_386_TLS_GD 1004@deffnx {} BFD_RELOC_386_TLS_LDM 1005@deffnx {} BFD_RELOC_386_TLS_LDO_32 1006@deffnx {} BFD_RELOC_386_TLS_IE_32 1007@deffnx {} BFD_RELOC_386_TLS_LE_32 1008@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1009@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1010@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1011@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1012@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1013@deffnx {} BFD_RELOC_386_TLS_DESC 1014@deffnx {} BFD_RELOC_386_IRELATIVE 1015i386/elf relocations 1016@end deffn 1017@deffn {} BFD_RELOC_X86_64_GOT32 1018@deffnx {} BFD_RELOC_X86_64_PLT32 1019@deffnx {} BFD_RELOC_X86_64_COPY 1020@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1021@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1022@deffnx {} BFD_RELOC_X86_64_RELATIVE 1023@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1024@deffnx {} BFD_RELOC_X86_64_32S 1025@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1026@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1027@deffnx {} BFD_RELOC_X86_64_TPOFF64 1028@deffnx {} BFD_RELOC_X86_64_TLSGD 1029@deffnx {} BFD_RELOC_X86_64_TLSLD 1030@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1031@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1032@deffnx {} BFD_RELOC_X86_64_TPOFF32 1033@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1034@deffnx {} BFD_RELOC_X86_64_GOTPC32 1035@deffnx {} BFD_RELOC_X86_64_GOT64 1036@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1037@deffnx {} BFD_RELOC_X86_64_GOTPC64 1038@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1039@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1040@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1041@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1042@deffnx {} BFD_RELOC_X86_64_TLSDESC 1043@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1044x86-64/elf relocations 1045@end deffn 1046@deffn {} BFD_RELOC_NS32K_IMM_8 1047@deffnx {} BFD_RELOC_NS32K_IMM_16 1048@deffnx {} BFD_RELOC_NS32K_IMM_32 1049@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1050@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1051@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1052@deffnx {} BFD_RELOC_NS32K_DISP_8 1053@deffnx {} BFD_RELOC_NS32K_DISP_16 1054@deffnx {} BFD_RELOC_NS32K_DISP_32 1055@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1056@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1057@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1058ns32k relocations 1059@end deffn 1060@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1061@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1062PDP11 relocations 1063@end deffn 1064@deffn {} BFD_RELOC_PJ_CODE_HI16 1065@deffnx {} BFD_RELOC_PJ_CODE_LO16 1066@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1067@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1068@deffnx {} BFD_RELOC_PJ_CODE_REL16 1069@deffnx {} BFD_RELOC_PJ_CODE_REL32 1070Picojava relocs. Not all of these appear in object files. 1071@end deffn 1072@deffn {} BFD_RELOC_PPC_B26 1073@deffnx {} BFD_RELOC_PPC_BA26 1074@deffnx {} BFD_RELOC_PPC_TOC16 1075@deffnx {} BFD_RELOC_PPC_B16 1076@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1077@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1078@deffnx {} BFD_RELOC_PPC_BA16 1079@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1080@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1081@deffnx {} BFD_RELOC_PPC_COPY 1082@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1083@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1084@deffnx {} BFD_RELOC_PPC_RELATIVE 1085@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1086@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1087@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1088@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1089@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1090@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1091@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1092@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1093@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1094@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1095@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1096@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1097@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1098@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1099@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1100@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1101@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1102@deffnx {} BFD_RELOC_PPC64_HIGHER 1103@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1104@deffnx {} BFD_RELOC_PPC64_HIGHEST 1105@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1106@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1107@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1108@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1109@deffnx {} BFD_RELOC_PPC64_TOC 1110@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1111@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1112@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1113@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1114@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1115@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1116@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1117@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1118@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1119@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1120@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1121@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1122@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1123@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1124@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1125Power(rs6000) and PowerPC relocations. 1126@end deffn 1127@deffn {} BFD_RELOC_PPC_TLS 1128@deffnx {} BFD_RELOC_PPC_TLSGD 1129@deffnx {} BFD_RELOC_PPC_TLSLD 1130@deffnx {} BFD_RELOC_PPC_DTPMOD 1131@deffnx {} BFD_RELOC_PPC_TPREL16 1132@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1133@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1134@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1135@deffnx {} BFD_RELOC_PPC_TPREL 1136@deffnx {} BFD_RELOC_PPC_DTPREL16 1137@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1138@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1139@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1140@deffnx {} BFD_RELOC_PPC_DTPREL 1141@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1142@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1143@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1144@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1145@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1146@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1147@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1148@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1149@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1150@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1151@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1152@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1153@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1154@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1155@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1156@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1157@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1158@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1159@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1160@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1161@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1162@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1163@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1164@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1165@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1166@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1167@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1168@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1169PowerPC and PowerPC64 thread-local storage relocations. 1170@end deffn 1171@deffn {} BFD_RELOC_I370_D12 1172IBM 370/390 relocations 1173@end deffn 1174@deffn {} BFD_RELOC_CTOR 1175The type of reloc used to build a constructor table - at the moment 1176probably a 32 bit wide absolute relocation, but the target can choose. 1177It generally does map to one of the other relocation types. 1178@end deffn 1179@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1180ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1181not stored in the instruction. 1182@end deffn 1183@deffn {} BFD_RELOC_ARM_PCREL_BLX 1184ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1185not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1186field in the instruction. 1187@end deffn 1188@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1189Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1190not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1191field in the instruction. 1192@end deffn 1193@deffn {} BFD_RELOC_ARM_PCREL_CALL 1194ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1195@end deffn 1196@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1197ARM 26-bit pc-relative branch for B or conditional BL instruction. 1198@end deffn 1199@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1200@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1201@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1202@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1203@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1204@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1205Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1206The lowest bit must be zero and is not stored in the instruction. 1207Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1208"nn" one smaller in all cases. Note further that BRANCH23 1209corresponds to R_ARM_THM_CALL. 1210@end deffn 1211@deffn {} BFD_RELOC_ARM_OFFSET_IMM 121212-bit immediate offset, used in ARM-format ldr and str instructions. 1213@end deffn 1214@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 12155-bit immediate offset, used in Thumb-format ldr and str instructions. 1216@end deffn 1217@deffn {} BFD_RELOC_ARM_TARGET1 1218Pc-relative or absolute relocation depending on target. Used for 1219entries in .init_array sections. 1220@end deffn 1221@deffn {} BFD_RELOC_ARM_ROSEGREL32 1222Read-only segment base relative address. 1223@end deffn 1224@deffn {} BFD_RELOC_ARM_SBREL32 1225Data segment base relative address. 1226@end deffn 1227@deffn {} BFD_RELOC_ARM_TARGET2 1228This reloc is used for references to RTTI data from exception handling 1229tables. The actual definition depends on the target. It may be a 1230pc-relative or some form of GOT-indirect relocation. 1231@end deffn 1232@deffn {} BFD_RELOC_ARM_PREL31 123331-bit PC relative address. 1234@end deffn 1235@deffn {} BFD_RELOC_ARM_MOVW 1236@deffnx {} BFD_RELOC_ARM_MOVT 1237@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1238@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1239@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1240@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1241@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1242@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1243Low and High halfword relocations for MOVW and MOVT instructions. 1244@end deffn 1245@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1246@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1247@deffnx {} BFD_RELOC_ARM_GOT32 1248@deffnx {} BFD_RELOC_ARM_PLT32 1249@deffnx {} BFD_RELOC_ARM_RELATIVE 1250@deffnx {} BFD_RELOC_ARM_GOTOFF 1251@deffnx {} BFD_RELOC_ARM_GOTPC 1252@deffnx {} BFD_RELOC_ARM_GOT_PREL 1253Relocations for setting up GOTs and PLTs for shared libraries. 1254@end deffn 1255@deffn {} BFD_RELOC_ARM_TLS_GD32 1256@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1257@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1258@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1259@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1260@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1261@deffnx {} BFD_RELOC_ARM_TLS_IE32 1262@deffnx {} BFD_RELOC_ARM_TLS_LE32 1263ARM thread-local storage relocations. 1264@end deffn 1265@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1266@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1267@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1268@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1269@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1270@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1271@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1272@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1273@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1274@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1275@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1276@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1277@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1278@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1279@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1280@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1281@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1282@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1283@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1284@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1285@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1286@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1287@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1288@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1289@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1290@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1291@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1292@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1293ARM group relocations. 1294@end deffn 1295@deffn {} BFD_RELOC_ARM_V4BX 1296Annotation of BX instructions. 1297@end deffn 1298@deffn {} BFD_RELOC_ARM_IMMEDIATE 1299@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1300@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1301@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1302@deffnx {} BFD_RELOC_ARM_T32_IMM12 1303@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1304@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1305@deffnx {} BFD_RELOC_ARM_SMC 1306@deffnx {} BFD_RELOC_ARM_HVC 1307@deffnx {} BFD_RELOC_ARM_SWI 1308@deffnx {} BFD_RELOC_ARM_MULTI 1309@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1310@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1311@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1312@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1313@deffnx {} BFD_RELOC_ARM_ADR_IMM 1314@deffnx {} BFD_RELOC_ARM_LDR_IMM 1315@deffnx {} BFD_RELOC_ARM_LITERAL 1316@deffnx {} BFD_RELOC_ARM_IN_POOL 1317@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1318@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1319@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1320@deffnx {} BFD_RELOC_ARM_HWLITERAL 1321@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1322@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1323@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1324These relocs are only used within the ARM assembler. They are not 1325(at present) written to any object files. 1326@end deffn 1327@deffn {} BFD_RELOC_SH_PCDISP8BY2 1328@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1329@deffnx {} BFD_RELOC_SH_IMM3 1330@deffnx {} BFD_RELOC_SH_IMM3U 1331@deffnx {} BFD_RELOC_SH_DISP12 1332@deffnx {} BFD_RELOC_SH_DISP12BY2 1333@deffnx {} BFD_RELOC_SH_DISP12BY4 1334@deffnx {} BFD_RELOC_SH_DISP12BY8 1335@deffnx {} BFD_RELOC_SH_DISP20 1336@deffnx {} BFD_RELOC_SH_DISP20BY8 1337@deffnx {} BFD_RELOC_SH_IMM4 1338@deffnx {} BFD_RELOC_SH_IMM4BY2 1339@deffnx {} BFD_RELOC_SH_IMM4BY4 1340@deffnx {} BFD_RELOC_SH_IMM8 1341@deffnx {} BFD_RELOC_SH_IMM8BY2 1342@deffnx {} BFD_RELOC_SH_IMM8BY4 1343@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1344@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1345@deffnx {} BFD_RELOC_SH_SWITCH16 1346@deffnx {} BFD_RELOC_SH_SWITCH32 1347@deffnx {} BFD_RELOC_SH_USES 1348@deffnx {} BFD_RELOC_SH_COUNT 1349@deffnx {} BFD_RELOC_SH_ALIGN 1350@deffnx {} BFD_RELOC_SH_CODE 1351@deffnx {} BFD_RELOC_SH_DATA 1352@deffnx {} BFD_RELOC_SH_LABEL 1353@deffnx {} BFD_RELOC_SH_LOOP_START 1354@deffnx {} BFD_RELOC_SH_LOOP_END 1355@deffnx {} BFD_RELOC_SH_COPY 1356@deffnx {} BFD_RELOC_SH_GLOB_DAT 1357@deffnx {} BFD_RELOC_SH_JMP_SLOT 1358@deffnx {} BFD_RELOC_SH_RELATIVE 1359@deffnx {} BFD_RELOC_SH_GOTPC 1360@deffnx {} BFD_RELOC_SH_GOT_LOW16 1361@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1362@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1363@deffnx {} BFD_RELOC_SH_GOT_HI16 1364@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1365@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1366@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1367@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1368@deffnx {} BFD_RELOC_SH_PLT_LOW16 1369@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1370@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1371@deffnx {} BFD_RELOC_SH_PLT_HI16 1372@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1373@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1374@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1375@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1376@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1377@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1378@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1379@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1380@deffnx {} BFD_RELOC_SH_COPY64 1381@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1382@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1383@deffnx {} BFD_RELOC_SH_RELATIVE64 1384@deffnx {} BFD_RELOC_SH_GOT10BY4 1385@deffnx {} BFD_RELOC_SH_GOT10BY8 1386@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1387@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1388@deffnx {} BFD_RELOC_SH_GOTPLT32 1389@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1390@deffnx {} BFD_RELOC_SH_IMMU5 1391@deffnx {} BFD_RELOC_SH_IMMS6 1392@deffnx {} BFD_RELOC_SH_IMMS6BY32 1393@deffnx {} BFD_RELOC_SH_IMMU6 1394@deffnx {} BFD_RELOC_SH_IMMS10 1395@deffnx {} BFD_RELOC_SH_IMMS10BY2 1396@deffnx {} BFD_RELOC_SH_IMMS10BY4 1397@deffnx {} BFD_RELOC_SH_IMMS10BY8 1398@deffnx {} BFD_RELOC_SH_IMMS16 1399@deffnx {} BFD_RELOC_SH_IMMU16 1400@deffnx {} BFD_RELOC_SH_IMM_LOW16 1401@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1402@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1403@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1404@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1405@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1406@deffnx {} BFD_RELOC_SH_IMM_HI16 1407@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1408@deffnx {} BFD_RELOC_SH_PT_16 1409@deffnx {} BFD_RELOC_SH_TLS_GD_32 1410@deffnx {} BFD_RELOC_SH_TLS_LD_32 1411@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1412@deffnx {} BFD_RELOC_SH_TLS_IE_32 1413@deffnx {} BFD_RELOC_SH_TLS_LE_32 1414@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1415@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1416@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1417@deffnx {} BFD_RELOC_SH_GOT20 1418@deffnx {} BFD_RELOC_SH_GOTOFF20 1419@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1420@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1421@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1422@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1423@deffnx {} BFD_RELOC_SH_FUNCDESC 1424Renesas / SuperH SH relocs. Not all of these appear in object files. 1425@end deffn 1426@deffn {} BFD_RELOC_ARC_B22_PCREL 1427ARC Cores relocs. 1428ARC 22 bit pc-relative branch. The lowest two bits must be zero and are 1429not stored in the instruction. The high 20 bits are installed in bits 26 1430through 7 of the instruction. 1431@end deffn 1432@deffn {} BFD_RELOC_ARC_B26 1433ARC 26 bit absolute branch. The lowest two bits must be zero and are not 1434stored in the instruction. The high 24 bits are installed in bits 23 1435through 0. 1436@end deffn 1437@deffn {} BFD_RELOC_BFIN_16_IMM 1438ADI Blackfin 16 bit immediate absolute reloc. 1439@end deffn 1440@deffn {} BFD_RELOC_BFIN_16_HIGH 1441ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1442@end deffn 1443@deffn {} BFD_RELOC_BFIN_4_PCREL 1444ADI Blackfin 'a' part of LSETUP. 1445@end deffn 1446@deffn {} BFD_RELOC_BFIN_5_PCREL 1447ADI Blackfin. 1448@end deffn 1449@deffn {} BFD_RELOC_BFIN_16_LOW 1450ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1451@end deffn 1452@deffn {} BFD_RELOC_BFIN_10_PCREL 1453ADI Blackfin. 1454@end deffn 1455@deffn {} BFD_RELOC_BFIN_11_PCREL 1456ADI Blackfin 'b' part of LSETUP. 1457@end deffn 1458@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1459ADI Blackfin. 1460@end deffn 1461@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1462ADI Blackfin Short jump, pcrel. 1463@end deffn 1464@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1465ADI Blackfin Call.x not implemented. 1466@end deffn 1467@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1468ADI Blackfin Long Jump pcrel. 1469@end deffn 1470@deffn {} BFD_RELOC_BFIN_GOT17M4 1471@deffnx {} BFD_RELOC_BFIN_GOTHI 1472@deffnx {} BFD_RELOC_BFIN_GOTLO 1473@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1474@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1475@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1476@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1477@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1478@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1479@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1480@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1481@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1482@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1483@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1484ADI Blackfin FD-PIC relocations. 1485@end deffn 1486@deffn {} BFD_RELOC_BFIN_GOT 1487ADI Blackfin GOT relocation. 1488@end deffn 1489@deffn {} BFD_RELOC_BFIN_PLTPC 1490ADI Blackfin PLTPC relocation. 1491@end deffn 1492@deffn {} BFD_ARELOC_BFIN_PUSH 1493ADI Blackfin arithmetic relocation. 1494@end deffn 1495@deffn {} BFD_ARELOC_BFIN_CONST 1496ADI Blackfin arithmetic relocation. 1497@end deffn 1498@deffn {} BFD_ARELOC_BFIN_ADD 1499ADI Blackfin arithmetic relocation. 1500@end deffn 1501@deffn {} BFD_ARELOC_BFIN_SUB 1502ADI Blackfin arithmetic relocation. 1503@end deffn 1504@deffn {} BFD_ARELOC_BFIN_MULT 1505ADI Blackfin arithmetic relocation. 1506@end deffn 1507@deffn {} BFD_ARELOC_BFIN_DIV 1508ADI Blackfin arithmetic relocation. 1509@end deffn 1510@deffn {} BFD_ARELOC_BFIN_MOD 1511ADI Blackfin arithmetic relocation. 1512@end deffn 1513@deffn {} BFD_ARELOC_BFIN_LSHIFT 1514ADI Blackfin arithmetic relocation. 1515@end deffn 1516@deffn {} BFD_ARELOC_BFIN_RSHIFT 1517ADI Blackfin arithmetic relocation. 1518@end deffn 1519@deffn {} BFD_ARELOC_BFIN_AND 1520ADI Blackfin arithmetic relocation. 1521@end deffn 1522@deffn {} BFD_ARELOC_BFIN_OR 1523ADI Blackfin arithmetic relocation. 1524@end deffn 1525@deffn {} BFD_ARELOC_BFIN_XOR 1526ADI Blackfin arithmetic relocation. 1527@end deffn 1528@deffn {} BFD_ARELOC_BFIN_LAND 1529ADI Blackfin arithmetic relocation. 1530@end deffn 1531@deffn {} BFD_ARELOC_BFIN_LOR 1532ADI Blackfin arithmetic relocation. 1533@end deffn 1534@deffn {} BFD_ARELOC_BFIN_LEN 1535ADI Blackfin arithmetic relocation. 1536@end deffn 1537@deffn {} BFD_ARELOC_BFIN_NEG 1538ADI Blackfin arithmetic relocation. 1539@end deffn 1540@deffn {} BFD_ARELOC_BFIN_COMP 1541ADI Blackfin arithmetic relocation. 1542@end deffn 1543@deffn {} BFD_ARELOC_BFIN_PAGE 1544ADI Blackfin arithmetic relocation. 1545@end deffn 1546@deffn {} BFD_ARELOC_BFIN_HWPAGE 1547ADI Blackfin arithmetic relocation. 1548@end deffn 1549@deffn {} BFD_ARELOC_BFIN_ADDR 1550ADI Blackfin arithmetic relocation. 1551@end deffn 1552@deffn {} BFD_RELOC_D10V_10_PCREL_R 1553Mitsubishi D10V relocs. 1554This is a 10-bit reloc with the right 2 bits 1555assumed to be 0. 1556@end deffn 1557@deffn {} BFD_RELOC_D10V_10_PCREL_L 1558Mitsubishi D10V relocs. 1559This is a 10-bit reloc with the right 2 bits 1560assumed to be 0. This is the same as the previous reloc 1561except it is in the left container, i.e., 1562shifted left 15 bits. 1563@end deffn 1564@deffn {} BFD_RELOC_D10V_18 1565This is an 18-bit reloc with the right 2 bits 1566assumed to be 0. 1567@end deffn 1568@deffn {} BFD_RELOC_D10V_18_PCREL 1569This is an 18-bit reloc with the right 2 bits 1570assumed to be 0. 1571@end deffn 1572@deffn {} BFD_RELOC_D30V_6 1573Mitsubishi D30V relocs. 1574This is a 6-bit absolute reloc. 1575@end deffn 1576@deffn {} BFD_RELOC_D30V_9_PCREL 1577This is a 6-bit pc-relative reloc with 1578the right 3 bits assumed to be 0. 1579@end deffn 1580@deffn {} BFD_RELOC_D30V_9_PCREL_R 1581This is a 6-bit pc-relative reloc with 1582the right 3 bits assumed to be 0. Same 1583as the previous reloc but on the right side 1584of the container. 1585@end deffn 1586@deffn {} BFD_RELOC_D30V_15 1587This is a 12-bit absolute reloc with the 1588right 3 bitsassumed to be 0. 1589@end deffn 1590@deffn {} BFD_RELOC_D30V_15_PCREL 1591This is a 12-bit pc-relative reloc with 1592the right 3 bits assumed to be 0. 1593@end deffn 1594@deffn {} BFD_RELOC_D30V_15_PCREL_R 1595This is a 12-bit pc-relative reloc with 1596the right 3 bits assumed to be 0. Same 1597as the previous reloc but on the right side 1598of the container. 1599@end deffn 1600@deffn {} BFD_RELOC_D30V_21 1601This is an 18-bit absolute reloc with 1602the right 3 bits assumed to be 0. 1603@end deffn 1604@deffn {} BFD_RELOC_D30V_21_PCREL 1605This is an 18-bit pc-relative reloc with 1606the right 3 bits assumed to be 0. 1607@end deffn 1608@deffn {} BFD_RELOC_D30V_21_PCREL_R 1609This is an 18-bit pc-relative reloc with 1610the right 3 bits assumed to be 0. Same 1611as the previous reloc but on the right side 1612of the container. 1613@end deffn 1614@deffn {} BFD_RELOC_D30V_32 1615This is a 32-bit absolute reloc. 1616@end deffn 1617@deffn {} BFD_RELOC_D30V_32_PCREL 1618This is a 32-bit pc-relative reloc. 1619@end deffn 1620@deffn {} BFD_RELOC_DLX_HI16_S 1621DLX relocs 1622@end deffn 1623@deffn {} BFD_RELOC_DLX_LO16 1624DLX relocs 1625@end deffn 1626@deffn {} BFD_RELOC_DLX_JMP26 1627DLX relocs 1628@end deffn 1629@deffn {} BFD_RELOC_M32C_HI8 1630@deffnx {} BFD_RELOC_M32C_RL_JUMP 1631@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1632@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1633Renesas M16C/M32C Relocations. 1634@end deffn 1635@deffn {} BFD_RELOC_M32R_24 1636Renesas M32R (formerly Mitsubishi M32R) relocs. 1637This is a 24 bit absolute address. 1638@end deffn 1639@deffn {} BFD_RELOC_M32R_10_PCREL 1640This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1641@end deffn 1642@deffn {} BFD_RELOC_M32R_18_PCREL 1643This is an 18-bit reloc with the right 2 bits assumed to be 0. 1644@end deffn 1645@deffn {} BFD_RELOC_M32R_26_PCREL 1646This is a 26-bit reloc with the right 2 bits assumed to be 0. 1647@end deffn 1648@deffn {} BFD_RELOC_M32R_HI16_ULO 1649This is a 16-bit reloc containing the high 16 bits of an address 1650used when the lower 16 bits are treated as unsigned. 1651@end deffn 1652@deffn {} BFD_RELOC_M32R_HI16_SLO 1653This is a 16-bit reloc containing the high 16 bits of an address 1654used when the lower 16 bits are treated as signed. 1655@end deffn 1656@deffn {} BFD_RELOC_M32R_LO16 1657This is a 16-bit reloc containing the lower 16 bits of an address. 1658@end deffn 1659@deffn {} BFD_RELOC_M32R_SDA16 1660This is a 16-bit reloc containing the small data area offset for use in 1661add3, load, and store instructions. 1662@end deffn 1663@deffn {} BFD_RELOC_M32R_GOT24 1664@deffnx {} BFD_RELOC_M32R_26_PLTREL 1665@deffnx {} BFD_RELOC_M32R_COPY 1666@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1667@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1668@deffnx {} BFD_RELOC_M32R_RELATIVE 1669@deffnx {} BFD_RELOC_M32R_GOTOFF 1670@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1671@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1672@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1673@deffnx {} BFD_RELOC_M32R_GOTPC24 1674@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1675@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1676@deffnx {} BFD_RELOC_M32R_GOT16_LO 1677@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1678@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1679@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1680For PIC. 1681@end deffn 1682@deffn {} BFD_RELOC_V850_9_PCREL 1683This is a 9-bit reloc 1684@end deffn 1685@deffn {} BFD_RELOC_V850_22_PCREL 1686This is a 22-bit reloc 1687@end deffn 1688@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 1689This is a 16 bit offset from the short data area pointer. 1690@end deffn 1691@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 1692This is a 16 bit offset (of which only 15 bits are used) from the 1693short data area pointer. 1694@end deffn 1695@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 1696This is a 16 bit offset from the zero data area pointer. 1697@end deffn 1698@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 1699This is a 16 bit offset (of which only 15 bits are used) from the 1700zero data area pointer. 1701@end deffn 1702@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 1703This is an 8 bit offset (of which only 6 bits are used) from the 1704tiny data area pointer. 1705@end deffn 1706@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 1707This is an 8bit offset (of which only 7 bits are used) from the tiny 1708data area pointer. 1709@end deffn 1710@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 1711This is a 7 bit offset from the tiny data area pointer. 1712@end deffn 1713@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 1714This is a 16 bit offset from the tiny data area pointer. 1715@end deffn 1716@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 1717This is a 5 bit offset (of which only 4 bits are used) from the tiny 1718data area pointer. 1719@end deffn 1720@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 1721This is a 4 bit offset from the tiny data area pointer. 1722@end deffn 1723@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 1724This is a 16 bit offset from the short data area pointer, with the 1725bits placed non-contiguously in the instruction. 1726@end deffn 1727@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 1728This is a 16 bit offset from the zero data area pointer, with the 1729bits placed non-contiguously in the instruction. 1730@end deffn 1731@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 1732This is a 6 bit offset from the call table base pointer. 1733@end deffn 1734@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 1735This is a 16 bit offset from the call table base pointer. 1736@end deffn 1737@deffn {} BFD_RELOC_V850_LONGCALL 1738Used for relaxing indirect function calls. 1739@end deffn 1740@deffn {} BFD_RELOC_V850_LONGJUMP 1741Used for relaxing indirect jumps. 1742@end deffn 1743@deffn {} BFD_RELOC_V850_ALIGN 1744Used to maintain alignment whilst relaxing. 1745@end deffn 1746@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 1747This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 1748instructions. 1749@end deffn 1750@deffn {} BFD_RELOC_V850_16_PCREL 1751This is a 16-bit reloc. 1752@end deffn 1753@deffn {} BFD_RELOC_V850_17_PCREL 1754This is a 17-bit reloc. 1755@end deffn 1756@deffn {} BFD_RELOC_V850_23 1757This is a 23-bit reloc. 1758@end deffn 1759@deffn {} BFD_RELOC_V850_32_PCREL 1760This is a 32-bit reloc. 1761@end deffn 1762@deffn {} BFD_RELOC_V850_32_ABS 1763This is a 32-bit reloc. 1764@end deffn 1765@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 1766This is a 16-bit reloc. 1767@end deffn 1768@deffn {} BFD_RELOC_V850_16_S1 1769This is a 16-bit reloc. 1770@end deffn 1771@deffn {} BFD_RELOC_V850_LO16_S1 1772Low 16 bits. 16 bit shifted by 1. 1773@end deffn 1774@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 1775This is a 16 bit offset from the call table base pointer. 1776@end deffn 1777@deffn {} BFD_RELOC_V850_32_GOTPCREL 1778DSO relocations. 1779@end deffn 1780@deffn {} BFD_RELOC_V850_16_GOT 1781DSO relocations. 1782@end deffn 1783@deffn {} BFD_RELOC_V850_32_GOT 1784DSO relocations. 1785@end deffn 1786@deffn {} BFD_RELOC_V850_22_PLT_PCREL 1787DSO relocations. 1788@end deffn 1789@deffn {} BFD_RELOC_V850_32_PLT_PCREL 1790DSO relocations. 1791@end deffn 1792@deffn {} BFD_RELOC_V850_COPY 1793DSO relocations. 1794@end deffn 1795@deffn {} BFD_RELOC_V850_GLOB_DAT 1796DSO relocations. 1797@end deffn 1798@deffn {} BFD_RELOC_V850_JMP_SLOT 1799DSO relocations. 1800@end deffn 1801@deffn {} BFD_RELOC_V850_RELATIVE 1802DSO relocations. 1803@end deffn 1804@deffn {} BFD_RELOC_V850_16_GOTOFF 1805DSO relocations. 1806@end deffn 1807@deffn {} BFD_RELOC_V850_32_GOTOFF 1808DSO relocations. 1809@end deffn 1810@deffn {} BFD_RELOC_V850_CODE 1811start code. 1812@end deffn 1813@deffn {} BFD_RELOC_V850_DATA 1814start data in text. 1815@end deffn 1816@deffn {} BFD_RELOC_MN10300_32_PCREL 1817This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1818instruction. 1819@end deffn 1820@deffn {} BFD_RELOC_MN10300_16_PCREL 1821This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1822instruction. 1823@end deffn 1824@deffn {} BFD_RELOC_TIC30_LDP 1825This is a 8bit DP reloc for the tms320c30, where the most 1826significant 8 bits of a 24 bit word are placed into the least 1827significant 8 bits of the opcode. 1828@end deffn 1829@deffn {} BFD_RELOC_TIC54X_PARTLS7 1830This is a 7bit reloc for the tms320c54x, where the least 1831significant 7 bits of a 16 bit word are placed into the least 1832significant 7 bits of the opcode. 1833@end deffn 1834@deffn {} BFD_RELOC_TIC54X_PARTMS9 1835This is a 9bit DP reloc for the tms320c54x, where the most 1836significant 9 bits of a 16 bit word are placed into the least 1837significant 9 bits of the opcode. 1838@end deffn 1839@deffn {} BFD_RELOC_TIC54X_23 1840This is an extended address 23-bit reloc for the tms320c54x. 1841@end deffn 1842@deffn {} BFD_RELOC_TIC54X_16_OF_23 1843This is a 16-bit reloc for the tms320c54x, where the least 1844significant 16 bits of a 23-bit extended address are placed into 1845the opcode. 1846@end deffn 1847@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 1848This is a reloc for the tms320c54x, where the most 1849significant 7 bits of a 23-bit extended address are placed into 1850the opcode. 1851@end deffn 1852@deffn {} BFD_RELOC_C6000_PCR_S21 1853@deffnx {} BFD_RELOC_C6000_PCR_S12 1854@deffnx {} BFD_RELOC_C6000_PCR_S10 1855@deffnx {} BFD_RELOC_C6000_PCR_S7 1856@deffnx {} BFD_RELOC_C6000_ABS_S16 1857@deffnx {} BFD_RELOC_C6000_ABS_L16 1858@deffnx {} BFD_RELOC_C6000_ABS_H16 1859@deffnx {} BFD_RELOC_C6000_SBR_U15_B 1860@deffnx {} BFD_RELOC_C6000_SBR_U15_H 1861@deffnx {} BFD_RELOC_C6000_SBR_U15_W 1862@deffnx {} BFD_RELOC_C6000_SBR_S16 1863@deffnx {} BFD_RELOC_C6000_SBR_L16_B 1864@deffnx {} BFD_RELOC_C6000_SBR_L16_H 1865@deffnx {} BFD_RELOC_C6000_SBR_L16_W 1866@deffnx {} BFD_RELOC_C6000_SBR_H16_B 1867@deffnx {} BFD_RELOC_C6000_SBR_H16_H 1868@deffnx {} BFD_RELOC_C6000_SBR_H16_W 1869@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 1870@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 1871@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 1872@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 1873@deffnx {} BFD_RELOC_C6000_PREL31 1874@deffnx {} BFD_RELOC_C6000_COPY 1875@deffnx {} BFD_RELOC_C6000_ALIGN 1876@deffnx {} BFD_RELOC_C6000_FPHEAD 1877@deffnx {} BFD_RELOC_C6000_NOCMP 1878TMS320C6000 relocations. 1879@end deffn 1880@deffn {} BFD_RELOC_FR30_48 1881This is a 48 bit reloc for the FR30 that stores 32 bits. 1882@end deffn 1883@deffn {} BFD_RELOC_FR30_20 1884This is a 32 bit reloc for the FR30 that stores 20 bits split up into 1885two sections. 1886@end deffn 1887@deffn {} BFD_RELOC_FR30_6_IN_4 1888This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 18894 bits. 1890@end deffn 1891@deffn {} BFD_RELOC_FR30_8_IN_8 1892This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 1893into 8 bits. 1894@end deffn 1895@deffn {} BFD_RELOC_FR30_9_IN_8 1896This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 1897into 8 bits. 1898@end deffn 1899@deffn {} BFD_RELOC_FR30_10_IN_8 1900This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 1901into 8 bits. 1902@end deffn 1903@deffn {} BFD_RELOC_FR30_9_PCREL 1904This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 1905short offset into 8 bits. 1906@end deffn 1907@deffn {} BFD_RELOC_FR30_12_PCREL 1908This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 1909short offset into 11 bits. 1910@end deffn 1911@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 1912@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 1913@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 1914@deffnx {} BFD_RELOC_MCORE_PCREL_32 1915@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 1916@deffnx {} BFD_RELOC_MCORE_RVA 1917Motorola Mcore relocations. 1918@end deffn 1919@deffn {} BFD_RELOC_MEP_8 1920@deffnx {} BFD_RELOC_MEP_16 1921@deffnx {} BFD_RELOC_MEP_32 1922@deffnx {} BFD_RELOC_MEP_PCREL8A2 1923@deffnx {} BFD_RELOC_MEP_PCREL12A2 1924@deffnx {} BFD_RELOC_MEP_PCREL17A2 1925@deffnx {} BFD_RELOC_MEP_PCREL24A2 1926@deffnx {} BFD_RELOC_MEP_PCABS24A2 1927@deffnx {} BFD_RELOC_MEP_LOW16 1928@deffnx {} BFD_RELOC_MEP_HI16U 1929@deffnx {} BFD_RELOC_MEP_HI16S 1930@deffnx {} BFD_RELOC_MEP_GPREL 1931@deffnx {} BFD_RELOC_MEP_TPREL 1932@deffnx {} BFD_RELOC_MEP_TPREL7 1933@deffnx {} BFD_RELOC_MEP_TPREL7A2 1934@deffnx {} BFD_RELOC_MEP_TPREL7A4 1935@deffnx {} BFD_RELOC_MEP_UIMM24 1936@deffnx {} BFD_RELOC_MEP_ADDR24A4 1937@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 1938@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 1939Toshiba Media Processor Relocations. 1940@end deffn 1941@deffn {} BFD_RELOC_MMIX_GETA 1942@deffnx {} BFD_RELOC_MMIX_GETA_1 1943@deffnx {} BFD_RELOC_MMIX_GETA_2 1944@deffnx {} BFD_RELOC_MMIX_GETA_3 1945These are relocations for the GETA instruction. 1946@end deffn 1947@deffn {} BFD_RELOC_MMIX_CBRANCH 1948@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 1949@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 1950@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 1951@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 1952These are relocations for a conditional branch instruction. 1953@end deffn 1954@deffn {} BFD_RELOC_MMIX_PUSHJ 1955@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 1956@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 1957@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 1958@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 1959These are relocations for the PUSHJ instruction. 1960@end deffn 1961@deffn {} BFD_RELOC_MMIX_JMP 1962@deffnx {} BFD_RELOC_MMIX_JMP_1 1963@deffnx {} BFD_RELOC_MMIX_JMP_2 1964@deffnx {} BFD_RELOC_MMIX_JMP_3 1965These are relocations for the JMP instruction. 1966@end deffn 1967@deffn {} BFD_RELOC_MMIX_ADDR19 1968This is a relocation for a relative address as in a GETA instruction or 1969a branch. 1970@end deffn 1971@deffn {} BFD_RELOC_MMIX_ADDR27 1972This is a relocation for a relative address as in a JMP instruction. 1973@end deffn 1974@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 1975This is a relocation for an instruction field that may be a general 1976register or a value 0..255. 1977@end deffn 1978@deffn {} BFD_RELOC_MMIX_REG 1979This is a relocation for an instruction field that may be a general 1980register. 1981@end deffn 1982@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 1983This is a relocation for two instruction fields holding a register and 1984an offset, the equivalent of the relocation. 1985@end deffn 1986@deffn {} BFD_RELOC_MMIX_LOCAL 1987This relocation is an assertion that the expression is not allocated as 1988a global register. It does not modify contents. 1989@end deffn 1990@deffn {} BFD_RELOC_AVR_7_PCREL 1991This is a 16 bit reloc for the AVR that stores 8 bit pc relative 1992short offset into 7 bits. 1993@end deffn 1994@deffn {} BFD_RELOC_AVR_13_PCREL 1995This is a 16 bit reloc for the AVR that stores 13 bit pc relative 1996short offset into 12 bits. 1997@end deffn 1998@deffn {} BFD_RELOC_AVR_16_PM 1999This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2000program memory address) into 16 bits. 2001@end deffn 2002@deffn {} BFD_RELOC_AVR_LO8_LDI 2003This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2004data memory address) into 8 bit immediate value of LDI insn. 2005@end deffn 2006@deffn {} BFD_RELOC_AVR_HI8_LDI 2007This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2008of data memory address) into 8 bit immediate value of LDI insn. 2009@end deffn 2010@deffn {} BFD_RELOC_AVR_HH8_LDI 2011This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2012of program memory address) into 8 bit immediate value of LDI insn. 2013@end deffn 2014@deffn {} BFD_RELOC_AVR_MS8_LDI 2015This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2016of 32 bit value) into 8 bit immediate value of LDI insn. 2017@end deffn 2018@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2019This is a 16 bit reloc for the AVR that stores negated 8 bit value 2020(usually data memory address) into 8 bit immediate value of SUBI insn. 2021@end deffn 2022@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2023This is a 16 bit reloc for the AVR that stores negated 8 bit value 2024(high 8 bit of data memory address) into 8 bit immediate value of 2025SUBI insn. 2026@end deffn 2027@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2028This is a 16 bit reloc for the AVR that stores negated 8 bit value 2029(most high 8 bit of program memory address) into 8 bit immediate value 2030of LDI or SUBI insn. 2031@end deffn 2032@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2033This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2034of 32 bit value) into 8 bit immediate value of LDI insn. 2035@end deffn 2036@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2037This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2038command address) into 8 bit immediate value of LDI insn. 2039@end deffn 2040@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2041This is a 16 bit reloc for the AVR that stores 8 bit value 2042(command address) into 8 bit immediate value of LDI insn. If the address 2043is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2044in the lower 128k. 2045@end deffn 2046@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2047This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2048of command address) into 8 bit immediate value of LDI insn. 2049@end deffn 2050@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2051This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2052of command address) into 8 bit immediate value of LDI insn. If the address 2053is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2054below 128k. 2055@end deffn 2056@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2057This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2058of command address) into 8 bit immediate value of LDI insn. 2059@end deffn 2060@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2061This is a 16 bit reloc for the AVR that stores negated 8 bit value 2062(usually command address) into 8 bit immediate value of SUBI insn. 2063@end deffn 2064@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2065This is a 16 bit reloc for the AVR that stores negated 8 bit value 2066(high 8 bit of 16 bit command address) into 8 bit immediate value 2067of SUBI insn. 2068@end deffn 2069@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2070This is a 16 bit reloc for the AVR that stores negated 8 bit value 2071(high 6 bit of 22 bit command address) into 8 bit immediate 2072value of SUBI insn. 2073@end deffn 2074@deffn {} BFD_RELOC_AVR_CALL 2075This is a 32 bit reloc for the AVR that stores 23 bit value 2076into 22 bits. 2077@end deffn 2078@deffn {} BFD_RELOC_AVR_LDI 2079This is a 16 bit reloc for the AVR that stores all needed bits 2080for absolute addressing with ldi with overflow check to linktime 2081@end deffn 2082@deffn {} BFD_RELOC_AVR_6 2083This is a 6 bit reloc for the AVR that stores offset for ldd/std 2084instructions 2085@end deffn 2086@deffn {} BFD_RELOC_AVR_6_ADIW 2087This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2088instructions 2089@end deffn 2090@deffn {} BFD_RELOC_RX_NEG8 2091@deffnx {} BFD_RELOC_RX_NEG16 2092@deffnx {} BFD_RELOC_RX_NEG24 2093@deffnx {} BFD_RELOC_RX_NEG32 2094@deffnx {} BFD_RELOC_RX_16_OP 2095@deffnx {} BFD_RELOC_RX_24_OP 2096@deffnx {} BFD_RELOC_RX_32_OP 2097@deffnx {} BFD_RELOC_RX_8U 2098@deffnx {} BFD_RELOC_RX_16U 2099@deffnx {} BFD_RELOC_RX_24U 2100@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2101@deffnx {} BFD_RELOC_RX_DIFF 2102@deffnx {} BFD_RELOC_RX_GPRELB 2103@deffnx {} BFD_RELOC_RX_GPRELW 2104@deffnx {} BFD_RELOC_RX_GPRELL 2105@deffnx {} BFD_RELOC_RX_SYM 2106@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2107@deffnx {} BFD_RELOC_RX_ABS8 2108@deffnx {} BFD_RELOC_RX_ABS16 2109@deffnx {} BFD_RELOC_RX_ABS32 2110@deffnx {} BFD_RELOC_RX_ABS16U 2111@deffnx {} BFD_RELOC_RX_ABS16UW 2112@deffnx {} BFD_RELOC_RX_ABS16UL 2113@deffnx {} BFD_RELOC_RX_RELAX 2114Renesas RX Relocations. 2115@end deffn 2116@deffn {} BFD_RELOC_390_12 2117Direct 12 bit. 2118@end deffn 2119@deffn {} BFD_RELOC_390_GOT12 212012 bit GOT offset. 2121@end deffn 2122@deffn {} BFD_RELOC_390_PLT32 212332 bit PC relative PLT address. 2124@end deffn 2125@deffn {} BFD_RELOC_390_COPY 2126Copy symbol at runtime. 2127@end deffn 2128@deffn {} BFD_RELOC_390_GLOB_DAT 2129Create GOT entry. 2130@end deffn 2131@deffn {} BFD_RELOC_390_JMP_SLOT 2132Create PLT entry. 2133@end deffn 2134@deffn {} BFD_RELOC_390_RELATIVE 2135Adjust by program base. 2136@end deffn 2137@deffn {} BFD_RELOC_390_GOTPC 213832 bit PC relative offset to GOT. 2139@end deffn 2140@deffn {} BFD_RELOC_390_GOT16 214116 bit GOT offset. 2142@end deffn 2143@deffn {} BFD_RELOC_390_PC16DBL 2144PC relative 16 bit shifted by 1. 2145@end deffn 2146@deffn {} BFD_RELOC_390_PLT16DBL 214716 bit PC rel. PLT shifted by 1. 2148@end deffn 2149@deffn {} BFD_RELOC_390_PC32DBL 2150PC relative 32 bit shifted by 1. 2151@end deffn 2152@deffn {} BFD_RELOC_390_PLT32DBL 215332 bit PC rel. PLT shifted by 1. 2154@end deffn 2155@deffn {} BFD_RELOC_390_GOTPCDBL 215632 bit PC rel. GOT shifted by 1. 2157@end deffn 2158@deffn {} BFD_RELOC_390_GOT64 215964 bit GOT offset. 2160@end deffn 2161@deffn {} BFD_RELOC_390_PLT64 216264 bit PC relative PLT address. 2163@end deffn 2164@deffn {} BFD_RELOC_390_GOTENT 216532 bit rel. offset to GOT entry. 2166@end deffn 2167@deffn {} BFD_RELOC_390_GOTOFF64 216864 bit offset to GOT. 2169@end deffn 2170@deffn {} BFD_RELOC_390_GOTPLT12 217112-bit offset to symbol-entry within GOT, with PLT handling. 2172@end deffn 2173@deffn {} BFD_RELOC_390_GOTPLT16 217416-bit offset to symbol-entry within GOT, with PLT handling. 2175@end deffn 2176@deffn {} BFD_RELOC_390_GOTPLT32 217732-bit offset to symbol-entry within GOT, with PLT handling. 2178@end deffn 2179@deffn {} BFD_RELOC_390_GOTPLT64 218064-bit offset to symbol-entry within GOT, with PLT handling. 2181@end deffn 2182@deffn {} BFD_RELOC_390_GOTPLTENT 218332-bit rel. offset to symbol-entry within GOT, with PLT handling. 2184@end deffn 2185@deffn {} BFD_RELOC_390_PLTOFF16 218616-bit rel. offset from the GOT to a PLT entry. 2187@end deffn 2188@deffn {} BFD_RELOC_390_PLTOFF32 218932-bit rel. offset from the GOT to a PLT entry. 2190@end deffn 2191@deffn {} BFD_RELOC_390_PLTOFF64 219264-bit rel. offset from the GOT to a PLT entry. 2193@end deffn 2194@deffn {} BFD_RELOC_390_TLS_LOAD 2195@deffnx {} BFD_RELOC_390_TLS_GDCALL 2196@deffnx {} BFD_RELOC_390_TLS_LDCALL 2197@deffnx {} BFD_RELOC_390_TLS_GD32 2198@deffnx {} BFD_RELOC_390_TLS_GD64 2199@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2200@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2201@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2202@deffnx {} BFD_RELOC_390_TLS_LDM32 2203@deffnx {} BFD_RELOC_390_TLS_LDM64 2204@deffnx {} BFD_RELOC_390_TLS_IE32 2205@deffnx {} BFD_RELOC_390_TLS_IE64 2206@deffnx {} BFD_RELOC_390_TLS_IEENT 2207@deffnx {} BFD_RELOC_390_TLS_LE32 2208@deffnx {} BFD_RELOC_390_TLS_LE64 2209@deffnx {} BFD_RELOC_390_TLS_LDO32 2210@deffnx {} BFD_RELOC_390_TLS_LDO64 2211@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2212@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2213@deffnx {} BFD_RELOC_390_TLS_TPOFF 2214s390 tls relocations. 2215@end deffn 2216@deffn {} BFD_RELOC_390_20 2217@deffnx {} BFD_RELOC_390_GOT20 2218@deffnx {} BFD_RELOC_390_GOTPLT20 2219@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2220Long displacement extension. 2221@end deffn 2222@deffn {} BFD_RELOC_SCORE_GPREL15 2223Score relocations 2224Low 16 bit for load/store 2225@end deffn 2226@deffn {} BFD_RELOC_SCORE_DUMMY2 2227@deffnx {} BFD_RELOC_SCORE_JMP 2228This is a 24-bit reloc with the right 1 bit assumed to be 0 2229@end deffn 2230@deffn {} BFD_RELOC_SCORE_BRANCH 2231This is a 19-bit reloc with the right 1 bit assumed to be 0 2232@end deffn 2233@deffn {} BFD_RELOC_SCORE_IMM30 2234This is a 32-bit reloc for 48-bit instructions. 2235@end deffn 2236@deffn {} BFD_RELOC_SCORE_IMM32 2237This is a 32-bit reloc for 48-bit instructions. 2238@end deffn 2239@deffn {} BFD_RELOC_SCORE16_JMP 2240This is a 11-bit reloc with the right 1 bit assumed to be 0 2241@end deffn 2242@deffn {} BFD_RELOC_SCORE16_BRANCH 2243This is a 8-bit reloc with the right 1 bit assumed to be 0 2244@end deffn 2245@deffn {} BFD_RELOC_SCORE_BCMP 2246This is a 9-bit reloc with the right 1 bit assumed to be 0 2247@end deffn 2248@deffn {} BFD_RELOC_SCORE_GOT15 2249@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2250@deffnx {} BFD_RELOC_SCORE_CALL15 2251@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2252Undocumented Score relocs 2253@end deffn 2254@deffn {} BFD_RELOC_IP2K_FR9 2255Scenix IP2K - 9-bit register number / data address 2256@end deffn 2257@deffn {} BFD_RELOC_IP2K_BANK 2258Scenix IP2K - 4-bit register/data bank number 2259@end deffn 2260@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2261Scenix IP2K - low 13 bits of instruction word address 2262@end deffn 2263@deffn {} BFD_RELOC_IP2K_PAGE3 2264Scenix IP2K - high 3 bits of instruction word address 2265@end deffn 2266@deffn {} BFD_RELOC_IP2K_LO8DATA 2267@deffnx {} BFD_RELOC_IP2K_HI8DATA 2268@deffnx {} BFD_RELOC_IP2K_EX8DATA 2269Scenix IP2K - ext/low/high 8 bits of data address 2270@end deffn 2271@deffn {} BFD_RELOC_IP2K_LO8INSN 2272@deffnx {} BFD_RELOC_IP2K_HI8INSN 2273Scenix IP2K - low/high 8 bits of instruction word address 2274@end deffn 2275@deffn {} BFD_RELOC_IP2K_PC_SKIP 2276Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2277@end deffn 2278@deffn {} BFD_RELOC_IP2K_TEXT 2279Scenix IP2K - 16 bit word address in text section. 2280@end deffn 2281@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2282Scenix IP2K - 7-bit sp or dp offset 2283@end deffn 2284@deffn {} BFD_RELOC_VPE4KMATH_DATA 2285@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2286Scenix VPE4K coprocessor - data/insn-space addressing 2287@end deffn 2288@deffn {} BFD_RELOC_VTABLE_INHERIT 2289@deffnx {} BFD_RELOC_VTABLE_ENTRY 2290These two relocations are used by the linker to determine which of 2291the entries in a C++ virtual function table are actually used. When 2292the --gc-sections option is given, the linker will zero out the entries 2293that are not used, so that the code for those functions need not be 2294included in the output. 2295 2296VTABLE_INHERIT is a zero-space relocation used to describe to the 2297linker the inheritance tree of a C++ virtual function table. The 2298relocation's symbol should be the parent class' vtable, and the 2299relocation should be located at the child vtable. 2300 2301VTABLE_ENTRY is a zero-space relocation that describes the use of a 2302virtual function table entry. The reloc's symbol should refer to the 2303table of the class mentioned in the code. Off of that base, an offset 2304describes the entry that is being used. For Rela hosts, this offset 2305is stored in the reloc's addend. For Rel hosts, we are forced to put 2306this offset in the reloc's section offset. 2307@end deffn 2308@deffn {} BFD_RELOC_IA64_IMM14 2309@deffnx {} BFD_RELOC_IA64_IMM22 2310@deffnx {} BFD_RELOC_IA64_IMM64 2311@deffnx {} BFD_RELOC_IA64_DIR32MSB 2312@deffnx {} BFD_RELOC_IA64_DIR32LSB 2313@deffnx {} BFD_RELOC_IA64_DIR64MSB 2314@deffnx {} BFD_RELOC_IA64_DIR64LSB 2315@deffnx {} BFD_RELOC_IA64_GPREL22 2316@deffnx {} BFD_RELOC_IA64_GPREL64I 2317@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2318@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2319@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2320@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2321@deffnx {} BFD_RELOC_IA64_LTOFF22 2322@deffnx {} BFD_RELOC_IA64_LTOFF64I 2323@deffnx {} BFD_RELOC_IA64_PLTOFF22 2324@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2325@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2326@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2327@deffnx {} BFD_RELOC_IA64_FPTR64I 2328@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2329@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2330@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2331@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2332@deffnx {} BFD_RELOC_IA64_PCREL21B 2333@deffnx {} BFD_RELOC_IA64_PCREL21BI 2334@deffnx {} BFD_RELOC_IA64_PCREL21M 2335@deffnx {} BFD_RELOC_IA64_PCREL21F 2336@deffnx {} BFD_RELOC_IA64_PCREL22 2337@deffnx {} BFD_RELOC_IA64_PCREL60B 2338@deffnx {} BFD_RELOC_IA64_PCREL64I 2339@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2340@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2341@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2342@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2343@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2344@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2345@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2346@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2347@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2348@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2349@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2350@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2351@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2352@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2353@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2354@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2355@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2356@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2357@deffnx {} BFD_RELOC_IA64_REL32MSB 2358@deffnx {} BFD_RELOC_IA64_REL32LSB 2359@deffnx {} BFD_RELOC_IA64_REL64MSB 2360@deffnx {} BFD_RELOC_IA64_REL64LSB 2361@deffnx {} BFD_RELOC_IA64_LTV32MSB 2362@deffnx {} BFD_RELOC_IA64_LTV32LSB 2363@deffnx {} BFD_RELOC_IA64_LTV64MSB 2364@deffnx {} BFD_RELOC_IA64_LTV64LSB 2365@deffnx {} BFD_RELOC_IA64_IPLTMSB 2366@deffnx {} BFD_RELOC_IA64_IPLTLSB 2367@deffnx {} BFD_RELOC_IA64_COPY 2368@deffnx {} BFD_RELOC_IA64_LTOFF22X 2369@deffnx {} BFD_RELOC_IA64_LDXMOV 2370@deffnx {} BFD_RELOC_IA64_TPREL14 2371@deffnx {} BFD_RELOC_IA64_TPREL22 2372@deffnx {} BFD_RELOC_IA64_TPREL64I 2373@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2374@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2375@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2376@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2377@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2378@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2379@deffnx {} BFD_RELOC_IA64_DTPREL14 2380@deffnx {} BFD_RELOC_IA64_DTPREL22 2381@deffnx {} BFD_RELOC_IA64_DTPREL64I 2382@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2383@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2384@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2385@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2386@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2387Intel IA64 Relocations. 2388@end deffn 2389@deffn {} BFD_RELOC_M68HC11_HI8 2390Motorola 68HC11 reloc. 2391This is the 8 bit high part of an absolute address. 2392@end deffn 2393@deffn {} BFD_RELOC_M68HC11_LO8 2394Motorola 68HC11 reloc. 2395This is the 8 bit low part of an absolute address. 2396@end deffn 2397@deffn {} BFD_RELOC_M68HC11_3B 2398Motorola 68HC11 reloc. 2399This is the 3 bit of a value. 2400@end deffn 2401@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2402Motorola 68HC11 reloc. 2403This reloc marks the beginning of a jump/call instruction. 2404It is used for linker relaxation to correctly identify beginning 2405of instruction and change some branches to use PC-relative 2406addressing mode. 2407@end deffn 2408@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2409Motorola 68HC11 reloc. 2410This reloc marks a group of several instructions that gcc generates 2411and for which the linker relaxation pass can modify and/or remove 2412some of them. 2413@end deffn 2414@deffn {} BFD_RELOC_M68HC11_LO16 2415Motorola 68HC11 reloc. 2416This is the 16-bit lower part of an address. It is used for 'call' 2417instruction to specify the symbol address without any special 2418transformation (due to memory bank window). 2419@end deffn 2420@deffn {} BFD_RELOC_M68HC11_PAGE 2421Motorola 68HC11 reloc. 2422This is a 8-bit reloc that specifies the page number of an address. 2423It is used by 'call' instruction to specify the page number of 2424the symbol. 2425@end deffn 2426@deffn {} BFD_RELOC_M68HC11_24 2427Motorola 68HC11 reloc. 2428This is a 24-bit reloc that represents the address with a 16-bit 2429value and a 8-bit page number. The symbol address is transformed 2430to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 2431@end deffn 2432@deffn {} BFD_RELOC_M68HC12_5B 2433Motorola 68HC12 reloc. 2434This is the 5 bits of a value. 2435@end deffn 2436@deffn {} BFD_RELOC_16C_NUM08 2437@deffnx {} BFD_RELOC_16C_NUM08_C 2438@deffnx {} BFD_RELOC_16C_NUM16 2439@deffnx {} BFD_RELOC_16C_NUM16_C 2440@deffnx {} BFD_RELOC_16C_NUM32 2441@deffnx {} BFD_RELOC_16C_NUM32_C 2442@deffnx {} BFD_RELOC_16C_DISP04 2443@deffnx {} BFD_RELOC_16C_DISP04_C 2444@deffnx {} BFD_RELOC_16C_DISP08 2445@deffnx {} BFD_RELOC_16C_DISP08_C 2446@deffnx {} BFD_RELOC_16C_DISP16 2447@deffnx {} BFD_RELOC_16C_DISP16_C 2448@deffnx {} BFD_RELOC_16C_DISP24 2449@deffnx {} BFD_RELOC_16C_DISP24_C 2450@deffnx {} BFD_RELOC_16C_DISP24a 2451@deffnx {} BFD_RELOC_16C_DISP24a_C 2452@deffnx {} BFD_RELOC_16C_REG04 2453@deffnx {} BFD_RELOC_16C_REG04_C 2454@deffnx {} BFD_RELOC_16C_REG04a 2455@deffnx {} BFD_RELOC_16C_REG04a_C 2456@deffnx {} BFD_RELOC_16C_REG14 2457@deffnx {} BFD_RELOC_16C_REG14_C 2458@deffnx {} BFD_RELOC_16C_REG16 2459@deffnx {} BFD_RELOC_16C_REG16_C 2460@deffnx {} BFD_RELOC_16C_REG20 2461@deffnx {} BFD_RELOC_16C_REG20_C 2462@deffnx {} BFD_RELOC_16C_ABS20 2463@deffnx {} BFD_RELOC_16C_ABS20_C 2464@deffnx {} BFD_RELOC_16C_ABS24 2465@deffnx {} BFD_RELOC_16C_ABS24_C 2466@deffnx {} BFD_RELOC_16C_IMM04 2467@deffnx {} BFD_RELOC_16C_IMM04_C 2468@deffnx {} BFD_RELOC_16C_IMM16 2469@deffnx {} BFD_RELOC_16C_IMM16_C 2470@deffnx {} BFD_RELOC_16C_IMM20 2471@deffnx {} BFD_RELOC_16C_IMM20_C 2472@deffnx {} BFD_RELOC_16C_IMM24 2473@deffnx {} BFD_RELOC_16C_IMM24_C 2474@deffnx {} BFD_RELOC_16C_IMM32 2475@deffnx {} BFD_RELOC_16C_IMM32_C 2476NS CR16C Relocations. 2477@end deffn 2478@deffn {} BFD_RELOC_CR16_NUM8 2479@deffnx {} BFD_RELOC_CR16_NUM16 2480@deffnx {} BFD_RELOC_CR16_NUM32 2481@deffnx {} BFD_RELOC_CR16_NUM32a 2482@deffnx {} BFD_RELOC_CR16_REGREL0 2483@deffnx {} BFD_RELOC_CR16_REGREL4 2484@deffnx {} BFD_RELOC_CR16_REGREL4a 2485@deffnx {} BFD_RELOC_CR16_REGREL14 2486@deffnx {} BFD_RELOC_CR16_REGREL14a 2487@deffnx {} BFD_RELOC_CR16_REGREL16 2488@deffnx {} BFD_RELOC_CR16_REGREL20 2489@deffnx {} BFD_RELOC_CR16_REGREL20a 2490@deffnx {} BFD_RELOC_CR16_ABS20 2491@deffnx {} BFD_RELOC_CR16_ABS24 2492@deffnx {} BFD_RELOC_CR16_IMM4 2493@deffnx {} BFD_RELOC_CR16_IMM8 2494@deffnx {} BFD_RELOC_CR16_IMM16 2495@deffnx {} BFD_RELOC_CR16_IMM20 2496@deffnx {} BFD_RELOC_CR16_IMM24 2497@deffnx {} BFD_RELOC_CR16_IMM32 2498@deffnx {} BFD_RELOC_CR16_IMM32a 2499@deffnx {} BFD_RELOC_CR16_DISP4 2500@deffnx {} BFD_RELOC_CR16_DISP8 2501@deffnx {} BFD_RELOC_CR16_DISP16 2502@deffnx {} BFD_RELOC_CR16_DISP20 2503@deffnx {} BFD_RELOC_CR16_DISP24 2504@deffnx {} BFD_RELOC_CR16_DISP24a 2505@deffnx {} BFD_RELOC_CR16_SWITCH8 2506@deffnx {} BFD_RELOC_CR16_SWITCH16 2507@deffnx {} BFD_RELOC_CR16_SWITCH32 2508@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 2509@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 2510@deffnx {} BFD_RELOC_CR16_GLOB_DAT 2511NS CR16 Relocations. 2512@end deffn 2513@deffn {} BFD_RELOC_CRX_REL4 2514@deffnx {} BFD_RELOC_CRX_REL8 2515@deffnx {} BFD_RELOC_CRX_REL8_CMP 2516@deffnx {} BFD_RELOC_CRX_REL16 2517@deffnx {} BFD_RELOC_CRX_REL24 2518@deffnx {} BFD_RELOC_CRX_REL32 2519@deffnx {} BFD_RELOC_CRX_REGREL12 2520@deffnx {} BFD_RELOC_CRX_REGREL22 2521@deffnx {} BFD_RELOC_CRX_REGREL28 2522@deffnx {} BFD_RELOC_CRX_REGREL32 2523@deffnx {} BFD_RELOC_CRX_ABS16 2524@deffnx {} BFD_RELOC_CRX_ABS32 2525@deffnx {} BFD_RELOC_CRX_NUM8 2526@deffnx {} BFD_RELOC_CRX_NUM16 2527@deffnx {} BFD_RELOC_CRX_NUM32 2528@deffnx {} BFD_RELOC_CRX_IMM16 2529@deffnx {} BFD_RELOC_CRX_IMM32 2530@deffnx {} BFD_RELOC_CRX_SWITCH8 2531@deffnx {} BFD_RELOC_CRX_SWITCH16 2532@deffnx {} BFD_RELOC_CRX_SWITCH32 2533NS CRX Relocations. 2534@end deffn 2535@deffn {} BFD_RELOC_CRIS_BDISP8 2536@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 2537@deffnx {} BFD_RELOC_CRIS_SIGNED_6 2538@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 2539@deffnx {} BFD_RELOC_CRIS_SIGNED_8 2540@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 2541@deffnx {} BFD_RELOC_CRIS_SIGNED_16 2542@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 2543@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 2544@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 2545These relocs are only used within the CRIS assembler. They are not 2546(at present) written to any object files. 2547@end deffn 2548@deffn {} BFD_RELOC_CRIS_COPY 2549@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 2550@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 2551@deffnx {} BFD_RELOC_CRIS_RELATIVE 2552Relocs used in ELF shared libraries for CRIS. 2553@end deffn 2554@deffn {} BFD_RELOC_CRIS_32_GOT 255532-bit offset to symbol-entry within GOT. 2556@end deffn 2557@deffn {} BFD_RELOC_CRIS_16_GOT 255816-bit offset to symbol-entry within GOT. 2559@end deffn 2560@deffn {} BFD_RELOC_CRIS_32_GOTPLT 256132-bit offset to symbol-entry within GOT, with PLT handling. 2562@end deffn 2563@deffn {} BFD_RELOC_CRIS_16_GOTPLT 256416-bit offset to symbol-entry within GOT, with PLT handling. 2565@end deffn 2566@deffn {} BFD_RELOC_CRIS_32_GOTREL 256732-bit offset to symbol, relative to GOT. 2568@end deffn 2569@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 257032-bit offset to symbol with PLT entry, relative to GOT. 2571@end deffn 2572@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 257332-bit offset to symbol with PLT entry, relative to this relocation. 2574@end deffn 2575@deffn {} BFD_RELOC_CRIS_32_GOT_GD 2576@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 2577@deffnx {} BFD_RELOC_CRIS_32_GD 2578@deffnx {} BFD_RELOC_CRIS_DTP 2579@deffnx {} BFD_RELOC_CRIS_32_DTPREL 2580@deffnx {} BFD_RELOC_CRIS_16_DTPREL 2581@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 2582@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 2583@deffnx {} BFD_RELOC_CRIS_32_TPREL 2584@deffnx {} BFD_RELOC_CRIS_16_TPREL 2585@deffnx {} BFD_RELOC_CRIS_DTPMOD 2586@deffnx {} BFD_RELOC_CRIS_32_IE 2587Relocs used in TLS code for CRIS. 2588@end deffn 2589@deffn {} BFD_RELOC_860_COPY 2590@deffnx {} BFD_RELOC_860_GLOB_DAT 2591@deffnx {} BFD_RELOC_860_JUMP_SLOT 2592@deffnx {} BFD_RELOC_860_RELATIVE 2593@deffnx {} BFD_RELOC_860_PC26 2594@deffnx {} BFD_RELOC_860_PLT26 2595@deffnx {} BFD_RELOC_860_PC16 2596@deffnx {} BFD_RELOC_860_LOW0 2597@deffnx {} BFD_RELOC_860_SPLIT0 2598@deffnx {} BFD_RELOC_860_LOW1 2599@deffnx {} BFD_RELOC_860_SPLIT1 2600@deffnx {} BFD_RELOC_860_LOW2 2601@deffnx {} BFD_RELOC_860_SPLIT2 2602@deffnx {} BFD_RELOC_860_LOW3 2603@deffnx {} BFD_RELOC_860_LOGOT0 2604@deffnx {} BFD_RELOC_860_SPGOT0 2605@deffnx {} BFD_RELOC_860_LOGOT1 2606@deffnx {} BFD_RELOC_860_SPGOT1 2607@deffnx {} BFD_RELOC_860_LOGOTOFF0 2608@deffnx {} BFD_RELOC_860_SPGOTOFF0 2609@deffnx {} BFD_RELOC_860_LOGOTOFF1 2610@deffnx {} BFD_RELOC_860_SPGOTOFF1 2611@deffnx {} BFD_RELOC_860_LOGOTOFF2 2612@deffnx {} BFD_RELOC_860_LOGOTOFF3 2613@deffnx {} BFD_RELOC_860_LOPC 2614@deffnx {} BFD_RELOC_860_HIGHADJ 2615@deffnx {} BFD_RELOC_860_HAGOT 2616@deffnx {} BFD_RELOC_860_HAGOTOFF 2617@deffnx {} BFD_RELOC_860_HAPC 2618@deffnx {} BFD_RELOC_860_HIGH 2619@deffnx {} BFD_RELOC_860_HIGOT 2620@deffnx {} BFD_RELOC_860_HIGOTOFF 2621Intel i860 Relocations. 2622@end deffn 2623@deffn {} BFD_RELOC_OPENRISC_ABS_26 2624@deffnx {} BFD_RELOC_OPENRISC_REL_26 2625OpenRISC Relocations. 2626@end deffn 2627@deffn {} BFD_RELOC_H8_DIR16A8 2628@deffnx {} BFD_RELOC_H8_DIR16R8 2629@deffnx {} BFD_RELOC_H8_DIR24A8 2630@deffnx {} BFD_RELOC_H8_DIR24R8 2631@deffnx {} BFD_RELOC_H8_DIR32A16 2632H8 elf Relocations. 2633@end deffn 2634@deffn {} BFD_RELOC_XSTORMY16_REL_12 2635@deffnx {} BFD_RELOC_XSTORMY16_12 2636@deffnx {} BFD_RELOC_XSTORMY16_24 2637@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 2638Sony Xstormy16 Relocations. 2639@end deffn 2640@deffn {} BFD_RELOC_RELC 2641Self-describing complex relocations. 2642@end deffn 2643@deffn {} BFD_RELOC_XC16X_PAG 2644@deffnx {} BFD_RELOC_XC16X_POF 2645@deffnx {} BFD_RELOC_XC16X_SEG 2646@deffnx {} BFD_RELOC_XC16X_SOF 2647Infineon Relocations. 2648@end deffn 2649@deffn {} BFD_RELOC_VAX_GLOB_DAT 2650@deffnx {} BFD_RELOC_VAX_JMP_SLOT 2651@deffnx {} BFD_RELOC_VAX_RELATIVE 2652Relocations used by VAX ELF. 2653@end deffn 2654@deffn {} BFD_RELOC_MT_PC16 2655Morpho MT - 16 bit immediate relocation. 2656@end deffn 2657@deffn {} BFD_RELOC_MT_HI16 2658Morpho MT - Hi 16 bits of an address. 2659@end deffn 2660@deffn {} BFD_RELOC_MT_LO16 2661Morpho MT - Low 16 bits of an address. 2662@end deffn 2663@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 2664Morpho MT - Used to tell the linker which vtable entries are used. 2665@end deffn 2666@deffn {} BFD_RELOC_MT_GNU_VTENTRY 2667Morpho MT - Used to tell the linker which vtable entries are used. 2668@end deffn 2669@deffn {} BFD_RELOC_MT_PCINSN8 2670Morpho MT - 8 bit immediate relocation. 2671@end deffn 2672@deffn {} BFD_RELOC_MSP430_10_PCREL 2673@deffnx {} BFD_RELOC_MSP430_16_PCREL 2674@deffnx {} BFD_RELOC_MSP430_16 2675@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 2676@deffnx {} BFD_RELOC_MSP430_16_BYTE 2677@deffnx {} BFD_RELOC_MSP430_2X_PCREL 2678@deffnx {} BFD_RELOC_MSP430_RL_PCREL 2679msp430 specific relocation codes 2680@end deffn 2681@deffn {} BFD_RELOC_IQ2000_OFFSET_16 2682@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 2683@deffnx {} BFD_RELOC_IQ2000_UHI16 2684IQ2000 Relocations. 2685@end deffn 2686@deffn {} BFD_RELOC_XTENSA_RTLD 2687Special Xtensa relocation used only by PLT entries in ELF shared 2688objects to indicate that the runtime linker should set the value 2689to one of its own internal functions or data structures. 2690@end deffn 2691@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 2692@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 2693@deffnx {} BFD_RELOC_XTENSA_RELATIVE 2694Xtensa relocations for ELF shared objects. 2695@end deffn 2696@deffn {} BFD_RELOC_XTENSA_PLT 2697Xtensa relocation used in ELF object files for symbols that may require 2698PLT entries. Otherwise, this is just a generic 32-bit relocation. 2699@end deffn 2700@deffn {} BFD_RELOC_XTENSA_DIFF8 2701@deffnx {} BFD_RELOC_XTENSA_DIFF16 2702@deffnx {} BFD_RELOC_XTENSA_DIFF32 2703Xtensa relocations to mark the difference of two local symbols. 2704These are only needed to support linker relaxation and can be ignored 2705when not relaxing. The field is set to the value of the difference 2706assuming no relaxation. The relocation encodes the position of the 2707first symbol so the linker can determine whether to adjust the field 2708value. 2709@end deffn 2710@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 2711@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 2712@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 2713@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 2714@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 2715@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 2716@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 2717@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 2718@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 2719@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 2720@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 2721@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 2722@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 2723@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 2724@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 2725Generic Xtensa relocations for instruction operands. Only the slot 2726number is encoded in the relocation. The relocation applies to the 2727last PC-relative immediate operand, or if there are no PC-relative 2728immediates, to the last immediate operand. 2729@end deffn 2730@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 2731@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 2732@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 2733@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 2734@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 2735@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 2736@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 2737@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 2738@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 2739@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 2740@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 2741@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 2742@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 2743@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 2744@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 2745Alternate Xtensa relocations. Only the slot is encoded in the 2746relocation. The meaning of these relocations is opcode-specific. 2747@end deffn 2748@deffn {} BFD_RELOC_XTENSA_OP0 2749@deffnx {} BFD_RELOC_XTENSA_OP1 2750@deffnx {} BFD_RELOC_XTENSA_OP2 2751Xtensa relocations for backward compatibility. These have all been 2752replaced by BFD_RELOC_XTENSA_SLOT0_OP. 2753@end deffn 2754@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 2755Xtensa relocation to mark that the assembler expanded the 2756instructions from an original target. The expansion size is 2757encoded in the reloc size. 2758@end deffn 2759@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 2760Xtensa relocation to mark that the linker should simplify 2761assembler-expanded instructions. This is commonly used 2762internally by the linker after analysis of a 2763BFD_RELOC_XTENSA_ASM_EXPAND. 2764@end deffn 2765@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 2766@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 2767@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 2768@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 2769@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 2770@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 2771@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 2772Xtensa TLS relocations. 2773@end deffn 2774@deffn {} BFD_RELOC_Z80_DISP8 27758 bit signed offset in (ix+d) or (iy+d). 2776@end deffn 2777@deffn {} BFD_RELOC_Z8K_DISP7 2778DJNZ offset. 2779@end deffn 2780@deffn {} BFD_RELOC_Z8K_CALLR 2781CALR offset. 2782@end deffn 2783@deffn {} BFD_RELOC_Z8K_IMM4L 27844 bit value. 2785@end deffn 2786@deffn {} BFD_RELOC_LM32_CALL 2787@deffnx {} BFD_RELOC_LM32_BRANCH 2788@deffnx {} BFD_RELOC_LM32_16_GOT 2789@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 2790@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 2791@deffnx {} BFD_RELOC_LM32_COPY 2792@deffnx {} BFD_RELOC_LM32_GLOB_DAT 2793@deffnx {} BFD_RELOC_LM32_JMP_SLOT 2794@deffnx {} BFD_RELOC_LM32_RELATIVE 2795Lattice Mico32 relocations. 2796@end deffn 2797@deffn {} BFD_RELOC_MACH_O_SECTDIFF 2798Difference between two section addreses. Must be followed by a 2799BFD_RELOC_MACH_O_PAIR. 2800@end deffn 2801@deffn {} BFD_RELOC_MACH_O_PAIR 2802Pair of relocation. Contains the first symbol. 2803@end deffn 2804@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 2805@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 2806PCREL relocations. They are marked as branch to create PLT entry if 2807required. 2808@end deffn 2809@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 2810Used when referencing a GOT entry. 2811@end deffn 2812@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 2813Used when loading a GOT entry with movq. It is specially marked so that 2814the linker could optimize the movq to a leaq if possible. 2815@end deffn 2816@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32 2817Symbol will be substracted. Must be followed by a BFD_RELOC_64. 2818@end deffn 2819@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64 2820Symbol will be substracted. Must be followed by a BFD_RELOC_64. 2821@end deffn 2822@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 2823Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 2824@end deffn 2825@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 2826Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 2827@end deffn 2828@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 2829Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 2830@end deffn 2831@deffn {} BFD_RELOC_MICROBLAZE_32_LO 2832This is a 32 bit reloc for the microblaze that stores the 2833low 16 bits of a value 2834@end deffn 2835@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 2836This is a 32 bit pc-relative reloc for the microblaze that 2837stores the low 16 bits of a value 2838@end deffn 2839@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 2840This is a 32 bit reloc for the microblaze that stores a 2841value relative to the read-only small data area anchor 2842@end deffn 2843@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 2844This is a 32 bit reloc for the microblaze that stores a 2845value relative to the read-write small data area anchor 2846@end deffn 2847@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 2848This is a 32 bit reloc for the microblaze to handle 2849expressions of the form "Symbol Op Symbol" 2850@end deffn 2851@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 2852This is a 64 bit reloc that stores the 32 bit pc relative 2853value in two words (with an imm instruction). No relocation is 2854done here - only used for relaxing 2855@end deffn 2856@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 2857This is a 64 bit reloc that stores the 32 bit pc relative 2858value in two words (with an imm instruction). The relocation is 2859PC-relative GOT offset 2860@end deffn 2861@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 2862This is a 64 bit reloc that stores the 32 bit pc relative 2863value in two words (with an imm instruction). The relocation is 2864GOT offset 2865@end deffn 2866@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 2867This is a 64 bit reloc that stores the 32 bit pc relative 2868value in two words (with an imm instruction). The relocation is 2869PC-relative offset into PLT 2870@end deffn 2871@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 2872This is a 64 bit reloc that stores the 32 bit GOT relative 2873value in two words (with an imm instruction). The relocation is 2874relative offset from _GLOBAL_OFFSET_TABLE_ 2875@end deffn 2876@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 2877This is a 32 bit reloc that stores the 32 bit GOT relative 2878value in a word. The relocation is relative offset from 2879@end deffn 2880@deffn {} BFD_RELOC_MICROBLAZE_COPY 2881This is used to tell the dynamic linker to copy the value out of 2882the dynamic object into the runtime process image. 2883@end deffn 2884 2885@example 2886 2887typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 2888@end example 2889@findex bfd_reloc_type_lookup 2890@subsubsection @code{bfd_reloc_type_lookup} 2891@strong{Synopsis} 2892@example 2893reloc_howto_type *bfd_reloc_type_lookup 2894 (bfd *abfd, bfd_reloc_code_real_type code); 2895reloc_howto_type *bfd_reloc_name_lookup 2896 (bfd *abfd, const char *reloc_name); 2897@end example 2898@strong{Description}@* 2899Return a pointer to a howto structure which, when 2900invoked, will perform the relocation @var{code} on data from the 2901architecture noted. 2902 2903@findex bfd_default_reloc_type_lookup 2904@subsubsection @code{bfd_default_reloc_type_lookup} 2905@strong{Synopsis} 2906@example 2907reloc_howto_type *bfd_default_reloc_type_lookup 2908 (bfd *abfd, bfd_reloc_code_real_type code); 2909@end example 2910@strong{Description}@* 2911Provides a default relocation lookup routine for any architecture. 2912 2913@findex bfd_get_reloc_code_name 2914@subsubsection @code{bfd_get_reloc_code_name} 2915@strong{Synopsis} 2916@example 2917const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 2918@end example 2919@strong{Description}@* 2920Provides a printable name for the supplied relocation code. 2921Useful mainly for printing error messages. 2922 2923@findex bfd_generic_relax_section 2924@subsubsection @code{bfd_generic_relax_section} 2925@strong{Synopsis} 2926@example 2927bfd_boolean bfd_generic_relax_section 2928 (bfd *abfd, 2929 asection *section, 2930 struct bfd_link_info *, 2931 bfd_boolean *); 2932@end example 2933@strong{Description}@* 2934Provides default handling for relaxing for back ends which 2935don't do relaxing. 2936 2937@findex bfd_generic_gc_sections 2938@subsubsection @code{bfd_generic_gc_sections} 2939@strong{Synopsis} 2940@example 2941bfd_boolean bfd_generic_gc_sections 2942 (bfd *, struct bfd_link_info *); 2943@end example 2944@strong{Description}@* 2945Provides default handling for relaxing for back ends which 2946don't do section gc -- i.e., does nothing. 2947 2948@findex bfd_generic_merge_sections 2949@subsubsection @code{bfd_generic_merge_sections} 2950@strong{Synopsis} 2951@example 2952bfd_boolean bfd_generic_merge_sections 2953 (bfd *, struct bfd_link_info *); 2954@end example 2955@strong{Description}@* 2956Provides default handling for SEC_MERGE section merging for back ends 2957which don't have SEC_MERGE support -- i.e., does nothing. 2958 2959@findex bfd_generic_get_relocated_section_contents 2960@subsubsection @code{bfd_generic_get_relocated_section_contents} 2961@strong{Synopsis} 2962@example 2963bfd_byte *bfd_generic_get_relocated_section_contents 2964 (bfd *abfd, 2965 struct bfd_link_info *link_info, 2966 struct bfd_link_order *link_order, 2967 bfd_byte *data, 2968 bfd_boolean relocatable, 2969 asymbol **symbols); 2970@end example 2971@strong{Description}@* 2972Provides default handling of relocation effort for back ends 2973which can't be bothered to do it efficiently. 2974 2975