1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* CPU data header for bpf. 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6Copyright (C) 1996-2020 Free Software Foundation, Inc. 7 8This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24*/ 25 26#ifndef BPF_CPU_H 27#define BPF_CPU_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33#define CGEN_ARCH bpf 34 35/* Given symbol S, return bpf_cgen_<S>. */ 36#define CGEN_SYM(s) bpf##_cgen_##s 37 38 39/* Selected cpu families. */ 40#define HAVE_CPU_BPFBF 41 42#define CGEN_INSN_LSB0_P 1 43 44/* Minimum size of any insn (in bytes). */ 45#define CGEN_MIN_INSN_SIZE 8 46 47/* Maximum size of any insn (in bytes). */ 48#define CGEN_MAX_INSN_SIZE 16 49 50#define CGEN_INT_INSN_P 0 51 52/* Maximum number of syntax elements in an instruction. */ 53#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 16 54 55/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 56 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 57 we can't hash on everything up to the space. */ 58#define CGEN_MNEMONIC_OPERANDS 59 60/* Maximum number of fields in an instruction. */ 61#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 62 63/* Enums. */ 64 65/* Enum declaration for eBPF instruction codes. */ 66typedef enum insn_op_code_alu { 67 OP_CODE_ADD = 0, OP_CODE_SUB = 1, OP_CODE_MUL = 2, OP_CODE_DIV = 3 68 , OP_CODE_OR = 4, OP_CODE_AND = 5, OP_CODE_LSH = 6, OP_CODE_RSH = 7 69 , OP_CODE_NEG = 8, OP_CODE_MOD = 9, OP_CODE_XOR = 10, OP_CODE_MOV = 11 70 , OP_CODE_ARSH = 12, OP_CODE_END = 13, OP_CODE_JA = 0, OP_CODE_JEQ = 1 71 , OP_CODE_JGT = 2, OP_CODE_JGE = 3, OP_CODE_JSET = 4, OP_CODE_JNE = 5 72 , OP_CODE_JSGT = 6, OP_CODE_JSGE = 7, OP_CODE_CALL = 8, OP_CODE_EXIT = 9 73 , OP_CODE_JLT = 10, OP_CODE_JLE = 11, OP_CODE_JSLT = 12, OP_CODE_JSLE = 13 74} INSN_OP_CODE_ALU; 75 76/* Enum declaration for eBPF instruction source. */ 77typedef enum insn_op_src { 78 OP_SRC_K, OP_SRC_X 79} INSN_OP_SRC; 80 81/* Enum declaration for eBPF instruction class. */ 82typedef enum insn_op_class { 83 OP_CLASS_LD = 0, OP_CLASS_LDX = 1, OP_CLASS_ST = 2, OP_CLASS_STX = 3 84 , OP_CLASS_ALU = 4, OP_CLASS_JMP = 5, OP_CLASS_ALU64 = 7 85} INSN_OP_CLASS; 86 87/* Enum declaration for eBPF load/store instruction modes. */ 88typedef enum insn_op_mode { 89 OP_MODE_IMM = 0, OP_MODE_ABS = 1, OP_MODE_IND = 2, OP_MODE_MEM = 3 90 , OP_MODE_XADD = 6 91} INSN_OP_MODE; 92 93/* Enum declaration for eBPF load/store instruction sizes. */ 94typedef enum insn_op_size { 95 OP_SIZE_W, OP_SIZE_H, OP_SIZE_B, OP_SIZE_DW 96} INSN_OP_SIZE; 97 98/* Attributes. */ 99 100/* Enum declaration for machine type selection. */ 101typedef enum mach_attr { 102 MACH_BASE, MACH_BPF, MACH_MAX 103} MACH_ATTR; 104 105/* Enum declaration for instruction set selection. */ 106typedef enum isa_attr { 107 ISA_EBPFLE, ISA_EBPFBE, ISA_MAX 108} ISA_ATTR; 109 110/* Number of architecture variants. */ 111#define MAX_ISAS ((int) ISA_MAX) 112#define MAX_MACHS ((int) MACH_MAX) 113 114/* Ifield support. */ 115 116/* Ifield attribute indices. */ 117 118/* Enum declaration for cgen_ifld attrs. */ 119typedef enum cgen_ifld_attr { 120 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 121 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 122 , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS 123} CGEN_IFLD_ATTR; 124 125/* Number of non-boolean elements in cgen_ifld_attr. */ 126#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 127 128/* cgen_ifld attribute accessor macros. */ 129#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 130#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) 131#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) 132#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 133#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 134#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) 135#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 136#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) 137 138/* Enum declaration for bpf ifield types. */ 139typedef enum ifield_type { 140 BPF_F_NIL, BPF_F_ANYOF, BPF_F_OP_CODE, BPF_F_OP_SRC 141 , BPF_F_OP_CLASS, BPF_F_OP_MODE, BPF_F_OP_SIZE, BPF_F_DSTLE 142 , BPF_F_SRCLE, BPF_F_DSTBE, BPF_F_SRCBE, BPF_F_REGS 143 , BPF_F_OFFSET16, BPF_F_IMM32, BPF_F_IMM64_A, BPF_F_IMM64_B 144 , BPF_F_IMM64_C, BPF_F_IMM64, BPF_F_MAX 145} IFIELD_TYPE; 146 147#define MAX_IFLD ((int) BPF_F_MAX) 148 149/* Hardware attribute indices. */ 150 151/* Enum declaration for cgen_hw attrs. */ 152typedef enum cgen_hw_attr { 153 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 154 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA 155 , CGEN_HW_END_NBOOLS 156} CGEN_HW_ATTR; 157 158/* Number of non-boolean elements in cgen_hw_attr. */ 159#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 160 161/* cgen_hw attribute accessor macros. */ 162#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 163#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) 164#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) 165#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) 166#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) 167#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) 168 169/* Enum declaration for bpf hardware types. */ 170typedef enum cgen_hw_type { 171 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 172 , HW_H_IADDR, HW_H_GPR, HW_H_PC, HW_H_SINT64 173 , HW_MAX 174} CGEN_HW_TYPE; 175 176#define MAX_HW ((int) HW_MAX) 177 178/* Operand attribute indices. */ 179 180/* Enum declaration for cgen_operand attrs. */ 181typedef enum cgen_operand_attr { 182 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 183 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 184 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA 185 , CGEN_OPERAND_END_NBOOLS 186} CGEN_OPERAND_ATTR; 187 188/* Number of non-boolean elements in cgen_operand_attr. */ 189#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 190 191/* cgen_operand attribute accessor macros. */ 192#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 193#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) 194#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 195#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 196#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 197#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 198#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) 199#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 200#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) 201#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 202 203/* Enum declaration for bpf operand types. */ 204typedef enum cgen_operand_type { 205 BPF_OPERAND_PC, BPF_OPERAND_DSTLE, BPF_OPERAND_SRCLE, BPF_OPERAND_DSTBE 206 , BPF_OPERAND_SRCBE, BPF_OPERAND_DISP16, BPF_OPERAND_DISP32, BPF_OPERAND_IMM32 207 , BPF_OPERAND_OFFSET16, BPF_OPERAND_IMM64, BPF_OPERAND_ENDSIZE, BPF_OPERAND_MAX 208} CGEN_OPERAND_TYPE; 209 210/* Number of operands types. */ 211#define MAX_OPERANDS 11 212 213/* Maximum number of operands referenced by any insn. */ 214#define MAX_OPERAND_INSTANCES 8 215 216/* Insn attribute indices. */ 217 218/* Enum declaration for cgen_insn attrs. */ 219typedef enum cgen_insn_attr { 220 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 221 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 222 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 223 , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS 224} CGEN_INSN_ATTR; 225 226/* Number of non-boolean elements in cgen_insn_attr. */ 227#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 228 229/* cgen_insn attribute accessor macros. */ 230#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 231#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) 232#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) 233#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) 234#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 235#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) 236#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) 237#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 238#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) 239#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) 240#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) 241#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) 242 243/* cgen.h uses things we just defined. */ 244#include "opcode/cgen.h" 245 246extern const struct cgen_ifld bpf_cgen_ifld_table[]; 247 248/* Attributes. */ 249extern const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[]; 250extern const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[]; 251extern const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[]; 252extern const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[]; 253 254/* Hardware decls. */ 255 256extern CGEN_KEYWORD bpf_cgen_opval_h_gpr; 257 258extern const CGEN_HW_ENTRY bpf_cgen_hw_table[]; 259 260 261 262 #ifdef __cplusplus 263 } 264 #endif 265 266#endif /* BPF_CPU_H */ 267