1/* Instruction printing code for the ARM 2 Copyright (C) 1994-2022 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith@cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#include "sysdep.h" 24#include <assert.h> 25 26#include "disassemble.h" 27#include "opcode/arm.h" 28#include "opintl.h" 29#include "safe-ctype.h" 30#include "libiberty.h" 31#include "floatformat.h" 32 33/* FIXME: This shouldn't be done here. */ 34#include "coff/internal.h" 35#include "libcoff.h" 36#include "bfd.h" 37#include "elf-bfd.h" 38#include "elf/internal.h" 39#include "elf/arm.h" 40#include "mach-o.h" 41 42/* Cached mapping symbol state. */ 43enum map_type 44{ 45 MAP_ARM, 46 MAP_THUMB, 47 MAP_DATA 48}; 49 50struct arm_private_data 51{ 52 /* The features to use when disassembling optional instructions. */ 53 arm_feature_set features; 54 55 /* Track the last type (although this doesn't seem to be useful) */ 56 enum map_type last_type; 57 58 /* Tracking symbol table information */ 59 int last_mapping_sym; 60 61 /* The end range of the current range being disassembled. */ 62 bfd_vma last_stop_offset; 63 bfd_vma last_mapping_addr; 64}; 65 66enum mve_instructions 67{ 68 MVE_VPST, 69 MVE_VPT_FP_T1, 70 MVE_VPT_FP_T2, 71 MVE_VPT_VEC_T1, 72 MVE_VPT_VEC_T2, 73 MVE_VPT_VEC_T3, 74 MVE_VPT_VEC_T4, 75 MVE_VPT_VEC_T5, 76 MVE_VPT_VEC_T6, 77 MVE_VCMP_FP_T1, 78 MVE_VCMP_FP_T2, 79 MVE_VCMP_VEC_T1, 80 MVE_VCMP_VEC_T2, 81 MVE_VCMP_VEC_T3, 82 MVE_VCMP_VEC_T4, 83 MVE_VCMP_VEC_T5, 84 MVE_VCMP_VEC_T6, 85 MVE_VDUP, 86 MVE_VEOR, 87 MVE_VFMAS_FP_SCALAR, 88 MVE_VFMA_FP_SCALAR, 89 MVE_VFMA_FP, 90 MVE_VFMS_FP, 91 MVE_VHADD_T1, 92 MVE_VHADD_T2, 93 MVE_VHSUB_T1, 94 MVE_VHSUB_T2, 95 MVE_VRHADD, 96 MVE_VLD2, 97 MVE_VLD4, 98 MVE_VST2, 99 MVE_VST4, 100 MVE_VLDRB_T1, 101 MVE_VLDRH_T2, 102 MVE_VLDRB_T5, 103 MVE_VLDRH_T6, 104 MVE_VLDRW_T7, 105 MVE_VSTRB_T1, 106 MVE_VSTRH_T2, 107 MVE_VSTRB_T5, 108 MVE_VSTRH_T6, 109 MVE_VSTRW_T7, 110 MVE_VLDRB_GATHER_T1, 111 MVE_VLDRH_GATHER_T2, 112 MVE_VLDRW_GATHER_T3, 113 MVE_VLDRD_GATHER_T4, 114 MVE_VLDRW_GATHER_T5, 115 MVE_VLDRD_GATHER_T6, 116 MVE_VSTRB_SCATTER_T1, 117 MVE_VSTRH_SCATTER_T2, 118 MVE_VSTRW_SCATTER_T3, 119 MVE_VSTRD_SCATTER_T4, 120 MVE_VSTRW_SCATTER_T5, 121 MVE_VSTRD_SCATTER_T6, 122 MVE_VCVT_FP_FIX_VEC, 123 MVE_VCVT_BETWEEN_FP_INT, 124 MVE_VCVT_FP_HALF_FP, 125 MVE_VCVT_FROM_FP_TO_INT, 126 MVE_VRINT_FP, 127 MVE_VMOV_HFP_TO_GP, 128 MVE_VMOV_GP_TO_VEC_LANE, 129 MVE_VMOV_IMM_TO_VEC, 130 MVE_VMOV_VEC_TO_VEC, 131 MVE_VMOV2_VEC_LANE_TO_GP, 132 MVE_VMOV2_GP_TO_VEC_LANE, 133 MVE_VMOV_VEC_LANE_TO_GP, 134 MVE_VMVN_IMM, 135 MVE_VMVN_REG, 136 MVE_VORR_IMM, 137 MVE_VORR_REG, 138 MVE_VORN, 139 MVE_VBIC_IMM, 140 MVE_VBIC_REG, 141 MVE_VMOVX, 142 MVE_VMOVL, 143 MVE_VMOVN, 144 MVE_VMULL_INT, 145 MVE_VMULL_POLY, 146 MVE_VQDMULL_T1, 147 MVE_VQDMULL_T2, 148 MVE_VQMOVN, 149 MVE_VQMOVUN, 150 MVE_VADDV, 151 MVE_VMLADAV_T1, 152 MVE_VMLADAV_T2, 153 MVE_VMLALDAV, 154 MVE_VMLAS, 155 MVE_VADDLV, 156 MVE_VMLSDAV_T1, 157 MVE_VMLSDAV_T2, 158 MVE_VMLSLDAV, 159 MVE_VRMLALDAVH, 160 MVE_VRMLSLDAVH, 161 MVE_VQDMLADH, 162 MVE_VQRDMLADH, 163 MVE_VQDMLAH, 164 MVE_VQRDMLAH, 165 MVE_VQDMLASH, 166 MVE_VQRDMLASH, 167 MVE_VQDMLSDH, 168 MVE_VQRDMLSDH, 169 MVE_VQDMULH_T1, 170 MVE_VQRDMULH_T2, 171 MVE_VQDMULH_T3, 172 MVE_VQRDMULH_T4, 173 MVE_VDDUP, 174 MVE_VDWDUP, 175 MVE_VIWDUP, 176 MVE_VIDUP, 177 MVE_VCADD_FP, 178 MVE_VCADD_VEC, 179 MVE_VHCADD, 180 MVE_VCMLA_FP, 181 MVE_VCMUL_FP, 182 MVE_VQRSHL_T1, 183 MVE_VQRSHL_T2, 184 MVE_VQRSHRN, 185 MVE_VQRSHRUN, 186 MVE_VQSHL_T1, 187 MVE_VQSHL_T2, 188 MVE_VQSHLU_T3, 189 MVE_VQSHL_T4, 190 MVE_VQSHRN, 191 MVE_VQSHRUN, 192 MVE_VRSHL_T1, 193 MVE_VRSHL_T2, 194 MVE_VRSHR, 195 MVE_VRSHRN, 196 MVE_VSHL_T1, 197 MVE_VSHL_T2, 198 MVE_VSHL_T3, 199 MVE_VSHLC, 200 MVE_VSHLL_T1, 201 MVE_VSHLL_T2, 202 MVE_VSHR, 203 MVE_VSHRN, 204 MVE_VSLI, 205 MVE_VSRI, 206 MVE_VADC, 207 MVE_VABAV, 208 MVE_VABD_FP, 209 MVE_VABD_VEC, 210 MVE_VABS_FP, 211 MVE_VABS_VEC, 212 MVE_VADD_FP_T1, 213 MVE_VADD_FP_T2, 214 MVE_VADD_VEC_T1, 215 MVE_VADD_VEC_T2, 216 MVE_VSBC, 217 MVE_VSUB_FP_T1, 218 MVE_VSUB_FP_T2, 219 MVE_VSUB_VEC_T1, 220 MVE_VSUB_VEC_T2, 221 MVE_VAND, 222 MVE_VBRSR, 223 MVE_VCLS, 224 MVE_VCLZ, 225 MVE_VCTP, 226 MVE_VMAX, 227 MVE_VMAXA, 228 MVE_VMAXNM_FP, 229 MVE_VMAXNMA_FP, 230 MVE_VMAXNMV_FP, 231 MVE_VMAXNMAV_FP, 232 MVE_VMAXV, 233 MVE_VMAXAV, 234 MVE_VMIN, 235 MVE_VMINA, 236 MVE_VMINNM_FP, 237 MVE_VMINNMA_FP, 238 MVE_VMINNMV_FP, 239 MVE_VMINNMAV_FP, 240 MVE_VMINV, 241 MVE_VMINAV, 242 MVE_VMLA, 243 MVE_VMUL_FP_T1, 244 MVE_VMUL_FP_T2, 245 MVE_VMUL_VEC_T1, 246 MVE_VMUL_VEC_T2, 247 MVE_VMULH, 248 MVE_VRMULH, 249 MVE_VNEG_FP, 250 MVE_VNEG_VEC, 251 MVE_VPNOT, 252 MVE_VPSEL, 253 MVE_VQABS, 254 MVE_VQADD_T1, 255 MVE_VQADD_T2, 256 MVE_VQSUB_T1, 257 MVE_VQSUB_T2, 258 MVE_VQNEG, 259 MVE_VREV16, 260 MVE_VREV32, 261 MVE_VREV64, 262 MVE_LSLL, 263 MVE_LSLLI, 264 MVE_LSRL, 265 MVE_ASRL, 266 MVE_ASRLI, 267 MVE_SQRSHRL, 268 MVE_SQRSHR, 269 MVE_UQRSHL, 270 MVE_UQRSHLL, 271 MVE_UQSHL, 272 MVE_UQSHLL, 273 MVE_URSHRL, 274 MVE_URSHR, 275 MVE_SRSHRL, 276 MVE_SRSHR, 277 MVE_SQSHLL, 278 MVE_SQSHL, 279 MVE_CINC, 280 MVE_CINV, 281 MVE_CNEG, 282 MVE_CSINC, 283 MVE_CSINV, 284 MVE_CSET, 285 MVE_CSETM, 286 MVE_CSNEG, 287 MVE_CSEL, 288 MVE_NONE 289}; 290 291enum mve_unpredictable 292{ 293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. 294 */ 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and 296 fcB = 1 (vpt). */ 297 UNPRED_R13, /* Unpredictable because r13 (sp) or 298 r15 (sp) used. */ 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ 300 UNPRED_Q_GT_4, /* Unpredictable because 301 vec reg start > 4 (vld4/st4). */ 302 UNPRED_Q_GT_6, /* Unpredictable because 303 vec reg start > 6 (vld2/st2). */ 304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 305 and WB bit = 1. */ 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are 307 equal. */ 308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */ 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the 310 same. */ 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and 312 size = 1. */ 313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and 314 size = 2. */ 315 UNPRED_NONE /* No unpredictable behavior. */ 316}; 317 318enum mve_undefined 319{ 320 UNDEF_SIZE, /* undefined size. */ 321 UNDEF_SIZE_0, /* undefined because size == 0. */ 322 UNDEF_SIZE_2, /* undefined because size == 2. */ 323 UNDEF_SIZE_3, /* undefined because size == 3. */ 324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ 327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ 328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and 329 size == 0. */ 330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and 331 size == 1. */ 332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */ 334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and 336 op1 == (0 or 1). */ 337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and 338 op2 == 0 and op1 == (0 or 1). */ 339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode 340 in {0xx1, x0x1}. */ 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ 342 UNDEF_NONE /* no undefined behavior. */ 343}; 344 345struct opcode32 346{ 347 arm_feature_set arch; /* Architecture defining this insn. */ 348 unsigned long value; /* If arch is 0 then value is a sentinel. */ 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 350 const char * assembler; /* How to disassemble this insn. */ 351}; 352 353struct cdeopcode32 354{ 355 arm_feature_set arch; /* Architecture defining this insn. */ 356 uint8_t coproc_shift; /* coproc is this far into op. */ 357 uint16_t coproc_mask; /* Length of coproc field in op. */ 358 unsigned long value; /* If arch is 0 then value is a sentinel. */ 359 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 360 const char * assembler; /* How to disassemble this insn. */ 361}; 362 363/* MVE opcodes. */ 364 365struct mopcode32 366{ 367 arm_feature_set arch; /* Architecture defining this insn. */ 368 enum mve_instructions mve_op; /* Specific mve instruction for faster 369 decoding. */ 370 unsigned long value; /* If arch is 0 then value is a sentinel. */ 371 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 372 const char * assembler; /* How to disassemble this insn. */ 373}; 374 375enum isa { 376 ANY, 377 T32, 378 ARM 379}; 380 381 382/* Shared (between Arm and Thumb mode) opcode. */ 383struct sopcode32 384{ 385 enum isa isa; /* Execution mode instruction availability. */ 386 arm_feature_set arch; /* Architecture defining this insn. */ 387 unsigned long value; /* If arch is 0 then value is a sentinel. */ 388 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 389 const char * assembler; /* How to disassemble this insn. */ 390}; 391 392struct opcode16 393{ 394 arm_feature_set arch; /* Architecture defining this insn. */ 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 396 const char *assembler; /* How to disassemble this insn. */ 397}; 398 399/* print_insn_coprocessor recognizes the following format control codes: 400 401 %% % 402 403 %c print condition code (always bits 28-31 in ARM mode) 404 %b print condition code allowing cp_num == 9 405 %q print shifter argument 406 %u print condition code (unconditional in ARM mode, 407 UNPREDICTABLE if not AL in Thumb) 408 %A print address for ldc/stc/ldf/stf instruction 409 %B print vstm/vldm register list 410 %C print vscclrm register list 411 %I print cirrus signed shift immediate: bits 0..3|4..6 412 %J print register for VLDR instruction 413 %K print address for VLDR instruction 414 %F print the COUNT field of a LFM/SFM instruction. 415 %P print floating point precision in arithmetic insn 416 %Q print floating point precision in ldf/stf insn 417 %R print floating point rounding mode 418 419 %<bitfield>c print as a condition code (for vsel) 420 %<bitfield>r print as an ARM register 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 422 %<bitfield>ru as %<>r but each u register must be unique. 423 %<bitfield>d print the bitfield in decimal 424 %<bitfield>k print immediate for VFPv3 conversion instruction 425 %<bitfield>x print the bitfield in hex 426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 427 %<bitfield>f print a floating point constant if >7 else a 428 floating point register 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 430 %<bitfield>g print as an iWMMXt 64-bit register 431 %<bitfield>G print as an iWMMXt general purpose or control register 432 %<bitfield>D print as a NEON D register 433 %<bitfield>Q print as a NEON Q register 434 %<bitfield>V print as a NEON D or Q register 435 %<bitfield>E print a quarter-float immediate value 436 437 %y<code> print a single precision VFP reg. 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 439 %z<code> print a double precision VFP reg 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 441 442 %<bitfield>'c print specified char iff bitfield is all ones 443 %<bitfield>`c print specified char iff bitfield is all zeroes 444 %<bitfield>?ab... select from array of values in big endian order 445 446 %L print as an iWMMXt N/M width field. 447 %Z print the Immediate of a WSHUFH instruction. 448 %l like 'A' except use byte offsets for 'B' & 'H' 449 versions. 450 %i print 5-bit immediate in bits 8,3..0 451 (print "32" when 0) 452 %r print register offset address for wldt/wstr instruction. */ 453 454enum opcode_sentinel_enum 455{ 456 SENTINEL_IWMMXT_START = 1, 457 SENTINEL_IWMMXT_END, 458 SENTINEL_GENERIC_START 459} opcode_sentinels; 460 461#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 462#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x" 463#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x" 464#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 465 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */ 467 468/* print_insn_cde recognizes the following format control codes: 469 470 %% % 471 472 %a print 'a' iff bit 28 is 1 473 %p print bits 8-10 as coprocessor 474 %<bitfield>d print as decimal 475 %<bitfield>r print as an ARM register 476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv 477 %<bitfield>T print as an ARM register + 1 478 %<bitfield>R as %r but r13 is UNPREDICTABLE 479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE 480 %j print immediate taken from bits (16..21,7,0..5) 481 %k print immediate taken from bits (20..21,7,0..5). 482 %l print immediate taken from bits (20..22,7,4..5). */ 483 484/* At the moment there is only one valid position for the coprocessor number, 485 and hence that's encoded in the macro below. */ 486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ 487 { ARCH, 8, 7, VALUE, MASK, ASM } 488static const struct cdeopcode32 cde_opcodes[] = 489{ 490 /* Custom Datapath Extension instructions. */ 491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 492 0xee000000, 0xefc00840, 493 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"), 494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 495 0xee000040, 0xefc00840, 496 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"), 497 498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 499 0xee400000, 0xefc00840, 500 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"), 501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 502 0xee400040, 0xefc00840, 503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"), 504 505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 506 0xee800000, 0xef800840, 507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"), 508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 509 0xee800040, 0xef800840, 510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"), 511 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 513 0xec200000, 0xeeb00840, 514 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"), 515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 516 0xec200040, 0xeeb00840, 517 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"), 518 519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 520 0xec300000, 0xeeb00840, 521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"), 522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 523 0xec300040, 0xeeb00840, 524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"), 525 526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 527 0xec800000, 0xee800840, 528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"), 529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), 530 0xec800040, 0xee800840, 531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"), 532 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) 534 535}; 536 537static const struct sopcode32 coprocessor_opcodes[] = 538{ 539 /* XScale instructions. */ 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 541 0x0e200010, 0x0fff0ff0, 542 "mia%c\tacc0, %0-3r, %12-15r"}, 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 544 0x0e280010, 0x0fff0ff0, 545 "miaph%c\tacc0, %0-3r, %12-15r"}, 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 549 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 552 553 /* Intel Wireless MMX technology instructions. */ 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 628 0x0e800120, 0x0f800ff0, 629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 643 0x0e8000a0, 0x0f800ff0, 644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 707 {ANY, ARM_FEATURE_CORE_LOW (0), 708 SENTINEL_IWMMXT_END, 0, "" }, 709 710 /* Floating point coprocessor (FPA) instructions. */ 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 797 798 /* Armv8.1-M Mainline instructions. */ 799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, 801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, 803 804 /* ARMv8-M Mainline Security Extensions instructions. */ 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 809 810 /* Register load/store. */ 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, 845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), 846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, 847 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 856 857 /* Data transfer between ARM and NEON registers. */ 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 874 /* Half-precision conversion instructions. */ 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 883 884 /* Floating point coprocessor (VFP) instructions. */ 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 890 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"}, 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"}, 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"}, 907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 908 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"}, 909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 910 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"}, 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"}, 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"}, 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"}, 935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"}, 937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"}, 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 1043 1044 /* Cirrus coprocessor instructions. */ 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1046 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1048 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1050 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1052 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1054 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1056 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1058 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1060 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1062 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1064 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1066 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1068 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1070 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1072 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1074 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1076 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1098 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1122 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1150 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1152 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1162 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1164 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1166 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1168 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1170 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1182 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1184 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1186 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1188 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 1201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1206 0x0e000600, 0x0ff00f10, 1207 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1209 0x0e100600, 0x0ff00f10, 1210 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1212 0x0e200600, 0x0ff00f10, 1213 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 1215 0x0e300600, 0x0ff00f10, 1216 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 1217 1218 /* VFP Fused multiply add instructions. */ 1219 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 1235 1236 /* FP v5. */ 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 1245 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 1247 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 1249 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 1251 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 1253 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 1255 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 1257 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 1259 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 1261 1262 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, 1284 1285 /* BFloat16 instructions. */ 1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, 1288 1289 /* Dot Product instructions in the space of coprocessor 13. */ 1290 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 1292 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, 1294 1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 1312 1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 1314 cp_num: bit <11:8> == 0b1001. 1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1370 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1374 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1376 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1378 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1380 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1382 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1384 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1386 1387 /* ARMv8.3 javascript conversion instruction. */ 1388 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1390 1391 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1392}; 1393 1394/* Generic coprocessor instructions. These are only matched if a more specific 1395 SIMD or co-processor instruction does not match first. */ 1396 1397static const struct sopcode32 generic_coprocessor_opcodes[] = 1398{ 1399 /* Generic coprocessor instructions. */ 1400 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1401 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 1402 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 1403 0x0c500000, 0x0ff00000, 1404 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1406 0x0e000000, 0x0f000010, 1407 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 1408 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1409 0x0e10f010, 0x0f10f010, 1410 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 1411 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1412 0x0e100010, 0x0f100010, 1413 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 1414 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1415 0x0e000010, 0x0f100010, 1416 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 1421 1422 /* V6 coprocessor instructions. */ 1423 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1424 0xfc500000, 0xfff00000, 1425 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 1426 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1427 0xfc400000, 0xfff00000, 1428 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 1429 1430 /* V5 coprocessor instructions. */ 1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 1433 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 1435 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1436 0xfe000000, 0xff000010, 1437 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1439 0xfe000010, 0xff100010, 1440 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 1441 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 1442 0xfe100010, 0xff100010, 1443 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 1444 1445 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1446}; 1447 1448/* Neon opcode table: This does not encode the top byte -- that is 1449 checked by the print_insn_neon routine, as it depends on whether we are 1450 doing thumb32 or arm32 disassembly. */ 1451 1452/* print_insn_neon recognizes the following format control codes: 1453 1454 %% % 1455 1456 %c print condition code 1457 %u print condition code (unconditional in ARM mode, 1458 UNPREDICTABLE if not AL in Thumb) 1459 %A print v{st,ld}[1234] operands 1460 %B print v{st,ld}[1234] any one operands 1461 %C print v{st,ld}[1234] single->all operands 1462 %D print scalar 1463 %E print vmov, vmvn, vorr, vbic encoded constant 1464 %F print vtbl,vtbx register list 1465 1466 %<bitfield>r print as an ARM register 1467 %<bitfield>d print the bitfield in decimal 1468 %<bitfield>e print the 2^N - bitfield in decimal 1469 %<bitfield>D print as a NEON D register 1470 %<bitfield>Q print as a NEON Q register 1471 %<bitfield>R print as a NEON D or Q register 1472 %<bitfield>Sn print byte scaled width limited by n 1473 %<bitfield>Tn print short scaled width limited by n 1474 %<bitfield>Un print long scaled width limited by n 1475 1476 %<bitfield>'c print specified char iff bitfield is all ones 1477 %<bitfield>`c print specified char iff bitfield is all zeroes 1478 %<bitfield>?ab... select from array of values in big endian order. */ 1479 1480static const struct opcode32 neon_opcodes[] = 1481{ 1482 /* Extract. */ 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1484 0xf2b00840, 0xffb00850, 1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1487 0xf2b00000, 0xffb00810, 1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1489 1490 /* Data transfer between ARM and NEON registers. */ 1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 1503 1504 /* Move data element to all lanes. */ 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1511 1512 /* Table lookup. */ 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1517 1518 /* Half-precision conversions. */ 1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1523 1524 /* NEON fused multiply add instructions. */ 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1533 1534 /* BFloat16 instructions. */ 1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, 1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), 1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"}, 1547 1548 /* Matrix Multiply instructions. */ 1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), 1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, 1561 1562 /* Two registers, miscellaneous. */ 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1606 0xf3b20300, 0xffb30fd0, 1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf3bb0600, 0xffbf0e10, 1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1658 0xf3b70600, 0xffbf0e10, 1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1660 1661 /* Three registers of the same length. */ 1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1779 0xf2000b00, 0xff800f10, 1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1782 0xf2000b10, 0xff800f10, 1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1791 0xf3000b00, 0xff800f10, 1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1794 0xf2000000, 0xfe800f10, 1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1797 0xf2000010, 0xfe800f10, 1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1800 0xf2000100, 0xfe800f10, 1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1803 0xf2000200, 0xfe800f10, 1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1806 0xf2000210, 0xfe800f10, 1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1809 0xf2000300, 0xfe800f10, 1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1812 0xf2000310, 0xfe800f10, 1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1815 0xf2000400, 0xfe800f10, 1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1818 0xf2000410, 0xfe800f10, 1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1821 0xf2000500, 0xfe800f10, 1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1824 0xf2000510, 0xfe800f10, 1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1827 0xf2000600, 0xfe800f10, 1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1830 0xf2000610, 0xfe800f10, 1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1833 0xf2000700, 0xfe800f10, 1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1836 0xf2000710, 0xfe800f10, 1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1839 0xf2000910, 0xfe800f10, 1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1842 0xf2000a00, 0xfe800f10, 1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1845 0xf2000a10, 0xfe800f10, 1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1848 0xf3000b10, 0xff800f10, 1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1851 0xf3000c10, 0xff800f10, 1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1853 1854 /* One register and an immediate value. */ 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1881 1882 /* Two registers and a shift amount. */ 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1894 0xf2880950, 0xfeb80fd0, 1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1917 0xf2900950, 0xfeb00fd0, 1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1962 0xf2a00950, 0xfea00fd0, 1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2001 0xf2a00e10, 0xfea00e90, 2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 2004 0xf2a00c10, 0xfea00e90, 2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 2006 2007 /* Three registers of different lengths. */ 2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2013 0xf2800400, 0xff800f50, 2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2016 0xf2800600, 0xff800f50, 2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2019 0xf2800900, 0xff800f50, 2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2022 0xf2800b00, 0xff800f50, 2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2025 0xf2800d00, 0xff800f50, 2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2028 0xf3800400, 0xff800f50, 2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2031 0xf3800600, 0xff800f50, 2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2034 0xf2800000, 0xfe800f50, 2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2037 0xf2800100, 0xfe800f50, 2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2040 0xf2800200, 0xfe800f50, 2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2043 0xf2800300, 0xfe800f50, 2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2046 0xf2800500, 0xfe800f50, 2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2049 0xf2800700, 0xfe800f50, 2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2052 0xf2800800, 0xfe800f50, 2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2055 0xf2800a00, 0xfe800f50, 2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2058 0xf2800c00, 0xfe800f50, 2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 2060 2061 /* Two registers and a scalar. */ 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2113 0xf2800240, 0xfe800f50, 2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2116 0xf2800640, 0xfe800f50, 2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2119 0xf2800a40, 0xfe800f50, 2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2122 0xf2800e40, 0xff800f50, 2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2125 0xf2800f40, 0xff800f50, 2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2128 0xf3800e40, 0xff800f50, 2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 2131 0xf3800f40, 0xff800f50, 2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 2133 }, 2134 2135 /* Element and structure load/store. */ 2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 2174 2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 2176}; 2177 2178/* mve opcode table. */ 2179 2180/* print_insn_mve recognizes the following format control codes: 2181 2182 %% % 2183 2184 %a print '+' or '-' or imm offset in vldr[bhwd] and 2185 vstr[bhwd] 2186 %c print condition code 2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw] 2188 %u print 'U' (unsigned) or 'S' for various mve instructions 2189 %i print MVE predicate(s) for vpt and vpst 2190 %j print a 5-bit immediate from hw2[14:12,7:6] 2191 %k print 48 if the 7th position bit is set else print 64. 2192 %m print rounding mode for vcvt and vrint 2193 %n print vector comparison code for predicated instruction 2194 %s print size for various vcvt instructions 2195 %v print vector predicate for instruction in predicated 2196 block 2197 %o print offset scaled for vldr[hwd] and vstr[hwd] 2198 %w print writeback mode for MVE v{st,ld}[24] 2199 %B print v{st,ld}[24] any one operands 2200 %E print vmov, vmvn, vorr, vbic encoded constant 2201 %N print generic index for vmov 2202 %T print bottom ('b') or top ('t') of source register 2203 %X print exchange field in vmla* instructions 2204 2205 %<bitfield>r print as an ARM register 2206 %<bitfield>d print the bitfield in decimal 2207 %<bitfield>A print accumulate or not 2208 %<bitfield>c print bitfield as a condition code 2209 %<bitfield>C print bitfield as an inverted condition code 2210 %<bitfield>Q print as a MVE Q register 2211 %<bitfield>F print as a MVE S register 2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is 2213 UNPREDICTABLE 2214 2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE 2216 %<bitfield>s print size for vector predicate & non VMOV instructions 2217 %<bitfield>I print carry flag or not 2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm 2219 %<bitfield>h print high half of 64-bit destination reg 2220 %<bitfield>k print immediate for vector conversion instruction 2221 %<bitfield>l print low half of 64-bit destination reg 2222 %<bitfield>o print rotate value for vcmul 2223 %<bitfield>u print immediate value for vddup/vdwdup 2224 %<bitfield>x print the bitfield in hex. 2225 */ 2226 2227static const struct mopcode32 mve_opcodes[] = 2228{ 2229 /* MVE. */ 2230 2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2232 MVE_VPST, 2233 0xfe310f4d, 0xffbf1fff, 2234 "vpst%i" 2235 }, 2236 2237 /* Floating point VPT T1. */ 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2239 MVE_VPT_FP_T1, 2240 0xee310f00, 0xefb10f50, 2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2242 /* Floating point VPT T2. */ 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2244 MVE_VPT_FP_T2, 2245 0xee310f40, 0xefb10f50, 2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, 2247 2248 /* Vector VPT T1. */ 2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2250 MVE_VPT_VEC_T1, 2251 0xfe010f00, 0xff811f51, 2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2253 /* Vector VPT T2. */ 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2255 MVE_VPT_VEC_T2, 2256 0xfe010f01, 0xff811f51, 2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2258 /* Vector VPT T3. */ 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2260 MVE_VPT_VEC_T3, 2261 0xfe011f00, 0xff811f50, 2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2263 /* Vector VPT T4. */ 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2265 MVE_VPT_VEC_T4, 2266 0xfe010f40, 0xff811f70, 2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2268 /* Vector VPT T5. */ 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2270 MVE_VPT_VEC_T5, 2271 0xfe010f60, 0xff811f70, 2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2273 /* Vector VPT T6. */ 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2275 MVE_VPT_VEC_T6, 2276 0xfe011f40, 0xff811f50, 2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2278 2279 /* Vector VBIC immediate. */ 2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2281 MVE_VBIC_IMM, 2282 0xef800070, 0xefb81070, 2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"}, 2284 2285 /* Vector VBIC register. */ 2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2287 MVE_VBIC_REG, 2288 0xef100150, 0xffb11f51, 2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2290 2291 /* Vector VABAV. */ 2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2293 MVE_VABAV, 2294 0xee800f01, 0xefc10f51, 2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, 2296 2297 /* Vector VABD floating point. */ 2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2299 MVE_VABD_FP, 2300 0xff200d40, 0xffa11f51, 2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2302 2303 /* Vector VABD. */ 2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2305 MVE_VABD_VEC, 2306 0xef000740, 0xef811f51, 2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2308 2309 /* Vector VABS floating point. */ 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2311 MVE_VABS_FP, 2312 0xFFB10740, 0xFFB31FD1, 2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 2314 /* Vector VABS. */ 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2316 MVE_VABS_VEC, 2317 0xffb10340, 0xffb31fd1, 2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2319 2320 /* Vector VADD floating point T1. */ 2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2322 MVE_VADD_FP_T1, 2323 0xef000d40, 0xffa11f51, 2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2325 /* Vector VADD floating point T2. */ 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2327 MVE_VADD_FP_T2, 2328 0xee300f40, 0xefb11f70, 2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2330 /* Vector VADD T1. */ 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2332 MVE_VADD_VEC_T1, 2333 0xef000840, 0xff811f51, 2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2335 /* Vector VADD T2. */ 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2337 MVE_VADD_VEC_T2, 2338 0xee010f40, 0xff811f70, 2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2340 2341 /* Vector VADDLV. */ 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2343 MVE_VADDLV, 2344 0xee890f00, 0xef8f1fd1, 2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, 2346 2347 /* Vector VADDV. */ 2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2349 MVE_VADDV, 2350 0xeef10f00, 0xeff31fd1, 2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, 2352 2353 /* Vector VADC. */ 2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2355 MVE_VADC, 2356 0xee300f00, 0xffb10f51, 2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2358 2359 /* Vector VAND. */ 2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2361 MVE_VAND, 2362 0xef000150, 0xffb11f51, 2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2364 2365 /* Vector VBRSR register. */ 2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2367 MVE_VBRSR, 2368 0xfe011e60, 0xff811f70, 2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2370 2371 /* Vector VCADD floating point. */ 2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2373 MVE_VCADD_FP, 2374 0xfc800840, 0xfea11f51, 2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"}, 2376 2377 /* Vector VCADD. */ 2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2379 MVE_VCADD_VEC, 2380 0xfe000f00, 0xff810f51, 2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, 2382 2383 /* Vector VCLS. */ 2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2385 MVE_VCLS, 2386 0xffb00440, 0xffb31fd1, 2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2388 2389 /* Vector VCLZ. */ 2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2391 MVE_VCLZ, 2392 0xffb004c0, 0xffb31fd1, 2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2394 2395 /* Vector VCMLA. */ 2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2397 MVE_VCMLA_FP, 2398 0xfc200840, 0xfe211f51, 2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"}, 2400 2401 /* Vector VCMP floating point T1. */ 2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2403 MVE_VCMP_FP_T1, 2404 0xee310f00, 0xeff1ef50, 2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, 2406 2407 /* Vector VCMP floating point T2. */ 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2409 MVE_VCMP_FP_T2, 2410 0xee310f40, 0xeff1ef50, 2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, 2412 2413 /* Vector VCMP T1. */ 2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2415 MVE_VCMP_VEC_T1, 2416 0xfe010f00, 0xffc1ff51, 2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2418 /* Vector VCMP T2. */ 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2420 MVE_VCMP_VEC_T2, 2421 0xfe010f01, 0xffc1ff51, 2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2423 /* Vector VCMP T3. */ 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2425 MVE_VCMP_VEC_T3, 2426 0xfe011f00, 0xffc1ff50, 2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, 2428 /* Vector VCMP T4. */ 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2430 MVE_VCMP_VEC_T4, 2431 0xfe010f40, 0xffc1ff70, 2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, 2433 /* Vector VCMP T5. */ 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2435 MVE_VCMP_VEC_T5, 2436 0xfe010f60, 0xffc1ff70, 2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, 2438 /* Vector VCMP T6. */ 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2440 MVE_VCMP_VEC_T6, 2441 0xfe011f40, 0xffc1ff50, 2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, 2443 2444 /* Vector VDUP. */ 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2446 MVE_VDUP, 2447 0xeea00b10, 0xffb10f5f, 2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2449 2450 /* Vector VEOR. */ 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2452 MVE_VEOR, 2453 0xff000150, 0xffd11f51, 2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2455 2456 /* Vector VFMA, vector * scalar. */ 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2458 MVE_VFMA_FP_SCALAR, 2459 0xee310e40, 0xefb11f70, 2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2461 2462 /* Vector VFMA floating point. */ 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2464 MVE_VFMA_FP, 2465 0xef000c50, 0xffa11f51, 2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2467 2468 /* Vector VFMS floating point. */ 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2470 MVE_VFMS_FP, 2471 0xef200c50, 0xffa11f51, 2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2473 2474 /* Vector VFMAS, vector * scalar. */ 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2476 MVE_VFMAS_FP_SCALAR, 2477 0xee311e40, 0xefb11f70, 2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2479 2480 /* Vector VHADD T1. */ 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2482 MVE_VHADD_T1, 2483 0xef000040, 0xef811f51, 2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2485 2486 /* Vector VHADD T2. */ 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2488 MVE_VHADD_T2, 2489 0xee000f40, 0xef811f70, 2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2491 2492 /* Vector VHSUB T1. */ 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2494 MVE_VHSUB_T1, 2495 0xef000240, 0xef811f51, 2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2497 2498 /* Vector VHSUB T2. */ 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2500 MVE_VHSUB_T2, 2501 0xee001f40, 0xef811f70, 2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2503 2504 /* Vector VCMUL. */ 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2506 MVE_VCMUL_FP, 2507 0xee300e00, 0xefb10f50, 2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"}, 2509 2510 /* Vector VCTP. */ 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2512 MVE_VCTP, 2513 0xf000e801, 0xffc0ffff, 2514 "vctp%v.%20-21s\t%16-19r"}, 2515 2516 /* Vector VDUP. */ 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2518 MVE_VDUP, 2519 0xeea00b10, 0xffb10f5f, 2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, 2521 2522 /* Vector VRHADD. */ 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2524 MVE_VRHADD, 2525 0xef000140, 0xef811f51, 2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2527 2528 /* Vector VCVT. */ 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2530 MVE_VCVT_FP_FIX_VEC, 2531 0xef800c50, 0xef801cd1, 2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"}, 2533 2534 /* Vector VCVT. */ 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2536 MVE_VCVT_BETWEEN_FP_INT, 2537 0xffb30640, 0xffb31e51, 2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2539 2540 /* Vector VCVT between single and half-precision float, bottom half. */ 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2542 MVE_VCVT_FP_HALF_FP, 2543 0xee3f0e01, 0xefbf1fd1, 2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, 2545 2546 /* Vector VCVT between single and half-precision float, top half. */ 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2548 MVE_VCVT_FP_HALF_FP, 2549 0xee3f1e01, 0xefbf1fd1, 2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, 2551 2552 /* Vector VCVT. */ 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2554 MVE_VCVT_FROM_FP_TO_INT, 2555 0xffb30040, 0xffb31c51, 2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, 2557 2558 /* Vector VDDUP. */ 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2560 MVE_VDDUP, 2561 0xee011f6e, 0xff811f7e, 2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, 2563 2564 /* Vector VDWDUP. */ 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2566 MVE_VDWDUP, 2567 0xee011f60, 0xff811f70, 2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, 2569 2570 /* Vector VHCADD. */ 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2572 MVE_VHCADD, 2573 0xee000f00, 0xff810f51, 2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, 2575 2576 /* Vector VIWDUP. */ 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2578 MVE_VIWDUP, 2579 0xee010f60, 0xff811f70, 2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, 2581 2582 /* Vector VIDUP. */ 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2584 MVE_VIDUP, 2585 0xee010f6e, 0xff811f7e, 2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, 2587 2588 /* Vector VLD2. */ 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2590 MVE_VLD2, 2591 0xfc901e00, 0xff901e5f, 2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, 2593 2594 /* Vector VLD4. */ 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2596 MVE_VLD4, 2597 0xfc901e01, 0xff901e1f, 2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, 2599 2600 /* Vector VLDRB gather load. */ 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2602 MVE_VLDRB_GATHER_T1, 2603 0xec900e00, 0xefb01e50, 2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 2605 2606 /* Vector VLDRH gather load. */ 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2608 MVE_VLDRH_GATHER_T2, 2609 0xec900e10, 0xefb01e50, 2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2611 2612 /* Vector VLDRW gather load. */ 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2614 MVE_VLDRW_GATHER_T3, 2615 0xfc900f40, 0xffb01fd0, 2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2617 2618 /* Vector VLDRD gather load. */ 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2620 MVE_VLDRD_GATHER_T4, 2621 0xec900fd0, 0xefb01fd0, 2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 2623 2624 /* Vector VLDRW gather load. */ 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2626 MVE_VLDRW_GATHER_T5, 2627 0xfd101e00, 0xff111f00, 2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 2629 2630 /* Vector VLDRD gather load, variant T6. */ 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2632 MVE_VLDRD_GATHER_T6, 2633 0xfd101f00, 0xff111f00, 2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 2635 2636 /* Vector VLDRB. */ 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2638 MVE_VLDRB_T1, 2639 0xec100e00, 0xee581e00, 2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"}, 2641 2642 /* Vector VLDRH. */ 2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2644 MVE_VLDRH_T2, 2645 0xec180e00, 0xee581e00, 2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"}, 2647 2648 /* Vector VLDRB unsigned, variant T5. */ 2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2650 MVE_VLDRB_T5, 2651 0xec101e00, 0xfe101f80, 2652 "vldrb%v.u8\t%13-15,22Q, %d"}, 2653 2654 /* Vector VLDRH unsigned, variant T6. */ 2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2656 MVE_VLDRH_T6, 2657 0xec101e80, 0xfe101f80, 2658 "vldrh%v.u16\t%13-15,22Q, %d"}, 2659 2660 /* Vector VLDRW unsigned, variant T7. */ 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2662 MVE_VLDRW_T7, 2663 0xec101f00, 0xfe101f80, 2664 "vldrw%v.u32\t%13-15,22Q, %d"}, 2665 2666 /* Vector VMAX. */ 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2668 MVE_VMAX, 2669 0xef000640, 0xef811f51, 2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2671 2672 /* Vector VMAXA. */ 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2674 MVE_VMAXA, 2675 0xee330e81, 0xffb31fd1, 2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2677 2678 /* Vector VMAXNM floating point. */ 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2680 MVE_VMAXNM_FP, 2681 0xff000f50, 0xffa11f51, 2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2683 2684 /* Vector VMAXNMA floating point. */ 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2686 MVE_VMAXNMA_FP, 2687 0xee3f0e81, 0xefbf1fd1, 2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2689 2690 /* Vector VMAXNMV floating point. */ 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2692 MVE_VMAXNMV_FP, 2693 0xeeee0f00, 0xefff0fd1, 2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2695 2696 /* Vector VMAXNMAV floating point. */ 2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2698 MVE_VMAXNMAV_FP, 2699 0xeeec0f00, 0xefff0fd1, 2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2701 2702 /* Vector VMAXV. */ 2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2704 MVE_VMAXV, 2705 0xeee20f00, 0xeff30fd1, 2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2707 2708 /* Vector VMAXAV. */ 2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2710 MVE_VMAXAV, 2711 0xeee00f00, 0xfff30fd1, 2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2713 2714 /* Vector VMIN. */ 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2716 MVE_VMIN, 2717 0xef000650, 0xef811f51, 2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2719 2720 /* Vector VMINA. */ 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2722 MVE_VMINA, 2723 0xee331e81, 0xffb31fd1, 2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 2725 2726 /* Vector VMINNM floating point. */ 2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2728 MVE_VMINNM_FP, 2729 0xff200f50, 0xffa11f51, 2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2731 2732 /* Vector VMINNMA floating point. */ 2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2734 MVE_VMINNMA_FP, 2735 0xee3f1e81, 0xefbf1fd1, 2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, 2737 2738 /* Vector VMINNMV floating point. */ 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2740 MVE_VMINNMV_FP, 2741 0xeeee0f80, 0xefff0fd1, 2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, 2743 2744 /* Vector VMINNMAV floating point. */ 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2746 MVE_VMINNMAV_FP, 2747 0xeeec0f80, 0xefff0fd1, 2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, 2749 2750 /* Vector VMINV. */ 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2752 MVE_VMINV, 2753 0xeee20f80, 0xeff30fd1, 2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, 2755 2756 /* Vector VMINAV. */ 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2758 MVE_VMINAV, 2759 0xeee00f80, 0xfff30fd1, 2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, 2761 2762 /* Vector VMLA. */ 2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2764 MVE_VMLA, 2765 0xee010e40, 0xef811f70, 2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2767 2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction 2769 opcode aliasing. */ 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2771 MVE_VMLALDAV, 2772 0xee801e00, 0xef801f51, 2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2774 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2776 MVE_VMLALDAV, 2777 0xee800e00, 0xef801f51, 2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2779 2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2782 MVE_VMLADAV_T1, 2783 0xeef00e00, 0xeff01f51, 2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2785 2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2788 MVE_VMLADAV_T2, 2789 0xeef00f00, 0xeff11f51, 2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2791 2792 /* Vector VMLADAV T1 variant. */ 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2794 MVE_VMLADAV_T1, 2795 0xeef01e00, 0xeff01f51, 2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2797 2798 /* Vector VMLADAV T2 variant. */ 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2800 MVE_VMLADAV_T2, 2801 0xeef01f00, 0xeff11f51, 2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, 2803 2804 /* Vector VMLAS. */ 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2806 MVE_VMLAS, 2807 0xee011e40, 0xef811f70, 2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 2809 2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction 2811 opcode aliasing. */ 2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2813 MVE_VRMLSLDAVH, 2814 0xfe800e01, 0xff810f51, 2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2816 2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction 2818 opcdoe aliasing. */ 2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2820 MVE_VMLSLDAV, 2821 0xee800e01, 0xff800f51, 2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 2823 2824 /* Vector VMLSDAV T1 Variant. */ 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2826 MVE_VMLSDAV_T1, 2827 0xeef00e01, 0xfff00f51, 2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, 2829 2830 /* Vector VMLSDAV T2 Variant. */ 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2832 MVE_VMLSDAV_T2, 2833 0xfef00e01, 0xfff10f51, 2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, 2835 2836 /* Vector VMOV between gpr and half precision register, op == 0. */ 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2838 MVE_VMOV_HFP_TO_GP, 2839 0xee000910, 0xfff00f7f, 2840 "vmov.f16\t%7,16-19F, %12-15r"}, 2841 2842 /* Vector VMOV between gpr and half precision register, op == 1. */ 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2844 MVE_VMOV_HFP_TO_GP, 2845 0xee100910, 0xfff00f7f, 2846 "vmov.f16\t%12-15r, %7,16-19F"}, 2847 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2849 MVE_VMOV_GP_TO_VEC_LANE, 2850 0xee000b10, 0xff900f1f, 2851 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"}, 2852 2853 /* Vector VORR immediate to vector. 2854 NOTE: MVE_VORR_IMM must appear in the table 2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2857 MVE_VORR_IMM, 2858 0xef800050, 0xefb810f0, 2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"}, 2860 2861 /* Vector VQSHL T2 Variant. 2862 NOTE: MVE_VQSHL_T2 must appear in the table before 2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2865 MVE_VQSHL_T2, 2866 0xef800750, 0xef801fd1, 2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2868 2869 /* Vector VQSHLU T3 Variant 2870 NOTE: MVE_VQSHL_T2 must appear in the table before 2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2872 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2874 MVE_VQSHLU_T3, 2875 0xff800650, 0xff801fd1, 2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2877 2878 /* Vector VRSHR 2879 NOTE: MVE_VRSHR must appear in the table before 2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2882 MVE_VRSHR, 2883 0xef800250, 0xef801fd1, 2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2885 2886 /* Vector VSHL. 2887 NOTE: MVE_VSHL must appear in the table before 2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2890 MVE_VSHL_T1, 2891 0xef800550, 0xff801fd1, 2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2893 2894 /* Vector VSHR 2895 NOTE: MVE_VSHR must appear in the table before 2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2898 MVE_VSHR, 2899 0xef800050, 0xef801fd1, 2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2901 2902 /* Vector VSLI 2903 NOTE: MVE_VSLI must appear in the table before 2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2906 MVE_VSLI, 2907 0xff800550, 0xff801fd1, 2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2909 2910 /* Vector VSRI 2911 NOTE: MVE_VSRI must appear in the table before 2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ 2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2914 MVE_VSRI, 2915 0xff800450, 0xff801fd1, 2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2917 2918 /* Vector VMOV immediate to vector, 2919 undefinded for cmode == 1111 */ 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2921 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, 2922 2923 /* Vector VMOV immediate to vector, 2924 cmode == 1101 */ 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2926 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, 2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2928 2929 /* Vector VMOV immediate to vector. */ 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2931 MVE_VMOV_IMM_TO_VEC, 2932 0xef800050, 0xefb810d0, 2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, 2934 2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2937 MVE_VMOV2_VEC_LANE_TO_GP, 2938 0xec000f00, 0xffb01ff0, 2939 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"}, 2940 2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2943 MVE_VMOV2_VEC_LANE_TO_GP, 2944 0xec000f10, 0xffb01ff0, 2945 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"}, 2946 2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2949 MVE_VMOV2_GP_TO_VEC_LANE, 2950 0xec100f00, 0xffb01ff0, 2951 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, 2952 2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2955 MVE_VMOV2_GP_TO_VEC_LANE, 2956 0xec100f10, 0xffb01ff0, 2957 "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"}, 2958 2959 /* Vector VMOV Vector lane to gpr. */ 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2961 MVE_VMOV_VEC_LANE_TO_GP, 2962 0xee100b10, 0xff100f1f, 2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"}, 2964 2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due 2966 to instruction opcode aliasing. */ 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2968 MVE_VSHLL_T1, 2969 0xeea00f40, 0xefa00fd1, 2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 2971 2972 /* Vector VMOVL long. */ 2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2974 MVE_VMOVL, 2975 0xeea00f40, 0xefa70fd1, 2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, 2977 2978 /* Vector VMOV and narrow. */ 2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 2980 MVE_VMOVN, 2981 0xfe310e81, 0xffb30fd1, 2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, 2983 2984 /* Floating point move extract. */ 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2986 MVE_VMOVX, 2987 0xfeb00a40, 0xffbf0fd0, 2988 "vmovx.f16\t%22,12-15F, %5,0-3F"}, 2989 2990 /* Vector VMUL floating-point T1 variant. */ 2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2992 MVE_VMUL_FP_T1, 2993 0xff000d50, 0xffa11f51, 2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 2995 2996 /* Vector VMUL floating-point T2 variant. */ 2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 2998 MVE_VMUL_FP_T2, 2999 0xee310e60, 0xefb11f70, 3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3001 3002 /* Vector VMUL T1 variant. */ 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3004 MVE_VMUL_VEC_T1, 3005 0xef000950, 0xff811f51, 3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3007 3008 /* Vector VMUL T2 variant. */ 3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3010 MVE_VMUL_VEC_T2, 3011 0xee011e60, 0xff811f70, 3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3013 3014 /* Vector VMULH. */ 3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3016 MVE_VMULH, 3017 0xee010e01, 0xef811f51, 3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3019 3020 /* Vector VRMULH. */ 3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3022 MVE_VRMULH, 3023 0xee011e01, 0xef811f51, 3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3025 3026 /* Vector VMULL integer. */ 3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3028 MVE_VMULL_INT, 3029 0xee010e00, 0xef810f51, 3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3031 3032 /* Vector VMULL polynomial. */ 3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3034 MVE_VMULL_POLY, 3035 0xee310e00, 0xefb10f51, 3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3037 3038 /* Vector VMVN immediate to vector. */ 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3040 MVE_VMVN_IMM, 3041 0xef800070, 0xefb810f0, 3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, 3043 3044 /* Vector VMVN register. */ 3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3046 MVE_VMVN_REG, 3047 0xffb005c0, 0xffbf1fd1, 3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"}, 3049 3050 /* Vector VNEG floating point. */ 3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3052 MVE_VNEG_FP, 3053 0xffb107c0, 0xffb31fd1, 3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3055 3056 /* Vector VNEG. */ 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3058 MVE_VNEG_VEC, 3059 0xffb103c0, 0xffb31fd1, 3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3061 3062 /* Vector VORN, vector bitwise or not. */ 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3064 MVE_VORN, 3065 0xef300150, 0xffb11f51, 3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3067 3068 /* Vector VORR register. */ 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3070 MVE_VORR_REG, 3071 0xef200150, 0xffb11f51, 3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3073 3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if 3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen 3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes 3077 array. */ 3078 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3080 MVE_VMOV_VEC_TO_VEC, 3081 0xef200150, 0xffb11f51, 3082 "vmov%v\t%13-15,22Q, %17-19,7Q"}, 3083 3084 /* Vector VQDMULL T1 variant. */ 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3086 MVE_VQDMULL_T1, 3087 0xee300f01, 0xefb10f51, 3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3089 3090 /* Vector VPNOT. */ 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3092 MVE_VPNOT, 3093 0xfe310f4d, 0xffffffff, 3094 "vpnot%v"}, 3095 3096 /* Vector VPSEL. */ 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3098 MVE_VPSEL, 3099 0xfe310f01, 0xffb11f51, 3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3101 3102 /* Vector VQABS. */ 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3104 MVE_VQABS, 3105 0xffb00740, 0xffb31fd1, 3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3107 3108 /* Vector VQADD T1 variant. */ 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3110 MVE_VQADD_T1, 3111 0xef000050, 0xef811f51, 3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3113 3114 /* Vector VQADD T2 variant. */ 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3116 MVE_VQADD_T2, 3117 0xee000f60, 0xef811f70, 3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3119 3120 /* Vector VQDMULL T2 variant. */ 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3122 MVE_VQDMULL_T2, 3123 0xee300f60, 0xefb10f70, 3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3125 3126 /* Vector VQMOVN. */ 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3128 MVE_VQMOVN, 3129 0xee330e01, 0xefb30fd1, 3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, 3131 3132 /* Vector VQMOVUN. */ 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3134 MVE_VQMOVUN, 3135 0xee310e81, 0xffb30fd1, 3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3137 3138 /* Vector VQDMLADH. */ 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3140 MVE_VQDMLADH, 3141 0xee000e00, 0xff810f51, 3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3143 3144 /* Vector VQRDMLADH. */ 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3146 MVE_VQRDMLADH, 3147 0xee000e01, 0xff810f51, 3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3149 3150 /* Vector VQDMLAH. */ 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3152 MVE_VQDMLAH, 3153 0xee000e60, 0xff811f70, 3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3155 3156 /* Vector VQRDMLAH. */ 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3158 MVE_VQRDMLAH, 3159 0xee000e40, 0xff811f70, 3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3161 3162 /* Vector VQDMLASH. */ 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3164 MVE_VQDMLASH, 3165 0xee001e60, 0xff811f70, 3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3167 3168 /* Vector VQRDMLASH. */ 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3170 MVE_VQRDMLASH, 3171 0xee001e40, 0xff811f70, 3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3173 3174 /* Vector VQDMLSDH. */ 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3176 MVE_VQDMLSDH, 3177 0xfe000e00, 0xff810f51, 3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3179 3180 /* Vector VQRDMLSDH. */ 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3182 MVE_VQRDMLSDH, 3183 0xfe000e01, 0xff810f51, 3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3185 3186 /* Vector VQDMULH T1 variant. */ 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3188 MVE_VQDMULH_T1, 3189 0xef000b40, 0xff811f51, 3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3191 3192 /* Vector VQRDMULH T2 variant. */ 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3194 MVE_VQRDMULH_T2, 3195 0xff000b40, 0xff811f51, 3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3197 3198 /* Vector VQDMULH T3 variant. */ 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3200 MVE_VQDMULH_T3, 3201 0xee010e60, 0xff811f70, 3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3203 3204 /* Vector VQRDMULH T4 variant. */ 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3206 MVE_VQRDMULH_T4, 3207 0xfe010e60, 0xff811f70, 3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3209 3210 /* Vector VQNEG. */ 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3212 MVE_VQNEG, 3213 0xffb007c0, 0xffb31fd1, 3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, 3215 3216 /* Vector VQRSHL T1 variant. */ 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3218 MVE_VQRSHL_T1, 3219 0xef000550, 0xef811f51, 3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3221 3222 /* Vector VQRSHL T2 variant. */ 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3224 MVE_VQRSHL_T2, 3225 0xee331ee0, 0xefb31ff0, 3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3227 3228 /* Vector VQRSHRN. */ 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3230 MVE_VQRSHRN, 3231 0xee800f41, 0xefa00fd1, 3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3233 3234 /* Vector VQRSHRUN. */ 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3236 MVE_VQRSHRUN, 3237 0xfe800fc0, 0xffa00fd1, 3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3239 3240 /* Vector VQSHL T1 Variant. */ 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3242 MVE_VQSHL_T1, 3243 0xee311ee0, 0xefb31ff0, 3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3245 3246 /* Vector VQSHL T4 Variant. */ 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3248 MVE_VQSHL_T4, 3249 0xef000450, 0xef811f51, 3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3251 3252 /* Vector VQSHRN. */ 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3254 MVE_VQSHRN, 3255 0xee800f40, 0xefa00fd1, 3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3257 3258 /* Vector VQSHRUN. */ 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3260 MVE_VQSHRUN, 3261 0xee800fc0, 0xffa00fd1, 3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3263 3264 /* Vector VQSUB T1 Variant. */ 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3266 MVE_VQSUB_T1, 3267 0xef000250, 0xef811f51, 3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3269 3270 /* Vector VQSUB T2 Variant. */ 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3272 MVE_VQSUB_T2, 3273 0xee001f60, 0xef811f70, 3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3275 3276 /* Vector VREV16. */ 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3278 MVE_VREV16, 3279 0xffb00140, 0xffb31fd1, 3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"}, 3281 3282 /* Vector VREV32. */ 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3284 MVE_VREV32, 3285 0xffb000c0, 0xffb31fd1, 3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3287 3288 /* Vector VREV64. */ 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3290 MVE_VREV64, 3291 0xffb00040, 0xffb31fd1, 3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, 3293 3294 /* Vector VRINT floating point. */ 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3296 MVE_VRINT_FP, 3297 0xffb20440, 0xffb31c51, 3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, 3299 3300 /* Vector VRMLALDAVH. */ 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3302 MVE_VRMLALDAVH, 3303 0xee800f00, 0xef811f51, 3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3305 3306 /* Vector VRMLALDAVH. */ 3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3308 MVE_VRMLALDAVH, 3309 0xee801f00, 0xef811f51, 3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, 3311 3312 /* Vector VRSHL T1 Variant. */ 3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3314 MVE_VRSHL_T1, 3315 0xef000540, 0xef811f51, 3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3317 3318 /* Vector VRSHL T2 Variant. */ 3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3320 MVE_VRSHL_T2, 3321 0xee331e60, 0xefb31ff0, 3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3323 3324 /* Vector VRSHRN. */ 3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3326 MVE_VRSHRN, 3327 0xfe800fc1, 0xffa00fd1, 3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3329 3330 /* Vector VSBC. */ 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3332 MVE_VSBC, 3333 0xfe300f00, 0xffb10f51, 3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3335 3336 /* Vector VSHL T2 Variant. */ 3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3338 MVE_VSHL_T2, 3339 0xee311e60, 0xefb31ff0, 3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, 3341 3342 /* Vector VSHL T3 Variant. */ 3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3344 MVE_VSHL_T3, 3345 0xef000440, 0xef811f51, 3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, 3347 3348 /* Vector VSHLC. */ 3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3350 MVE_VSHLC, 3351 0xeea00fc0, 0xffa01ff0, 3352 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"}, 3353 3354 /* Vector VSHLL T2 Variant. */ 3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3356 MVE_VSHLL_T2, 3357 0xee310e01, 0xefb30fd1, 3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"}, 3359 3360 /* Vector VSHRN. */ 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3362 MVE_VSHRN, 3363 0xee800fc1, 0xffa00fd1, 3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, 3365 3366 /* Vector VST2 no writeback. */ 3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3368 MVE_VST2, 3369 0xfc801e00, 0xffb01e5f, 3370 "vst2%5d.%7-8s\t%B, [%16-19r]"}, 3371 3372 /* Vector VST2 writeback. */ 3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3374 MVE_VST2, 3375 0xfca01e00, 0xffb01e5f, 3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"}, 3377 3378 /* Vector VST4 no writeback. */ 3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3380 MVE_VST4, 3381 0xfc801e01, 0xffb01e1f, 3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"}, 3383 3384 /* Vector VST4 writeback. */ 3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3386 MVE_VST4, 3387 0xfca01e01, 0xffb01e1f, 3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"}, 3389 3390 /* Vector VSTRB scatter store, T1 variant. */ 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3392 MVE_VSTRB_SCATTER_T1, 3393 0xec800e00, 0xffb01e50, 3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, 3395 3396 /* Vector VSTRH scatter store, T2 variant. */ 3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3398 MVE_VSTRH_SCATTER_T2, 3399 0xec800e10, 0xffb01e50, 3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3401 3402 /* Vector VSTRW scatter store, T3 variant. */ 3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3404 MVE_VSTRW_SCATTER_T3, 3405 0xec800e40, 0xffb01e50, 3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3407 3408 /* Vector VSTRD scatter store, T4 variant. */ 3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3410 MVE_VSTRD_SCATTER_T4, 3411 0xec800fd0, 0xffb01fd0, 3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, 3413 3414 /* Vector VSTRW scatter store, T5 variant. */ 3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3416 MVE_VSTRW_SCATTER_T5, 3417 0xfd001e00, 0xff111f00, 3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 3419 3420 /* Vector VSTRD scatter store, T6 variant. */ 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3422 MVE_VSTRD_SCATTER_T6, 3423 0xfd001f00, 0xff111f00, 3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, 3425 3426 /* Vector VSTRB. */ 3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3428 MVE_VSTRB_T1, 3429 0xec000e00, 0xfe581e00, 3430 "vstrb%v.%7-8s\t%13-15Q, %d"}, 3431 3432 /* Vector VSTRH. */ 3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3434 MVE_VSTRH_T2, 3435 0xec080e00, 0xfe581e00, 3436 "vstrh%v.%7-8s\t%13-15Q, %d"}, 3437 3438 /* Vector VSTRB variant T5. */ 3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3440 MVE_VSTRB_T5, 3441 0xec001e00, 0xfe101f80, 3442 "vstrb%v.8\t%13-15,22Q, %d"}, 3443 3444 /* Vector VSTRH variant T6. */ 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3446 MVE_VSTRH_T6, 3447 0xec001e80, 0xfe101f80, 3448 "vstrh%v.16\t%13-15,22Q, %d"}, 3449 3450 /* Vector VSTRW variant T7. */ 3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3452 MVE_VSTRW_T7, 3453 0xec001f00, 0xfe101f80, 3454 "vstrw%v.32\t%13-15,22Q, %d"}, 3455 3456 /* Vector VSUB floating point T1 variant. */ 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3458 MVE_VSUB_FP_T1, 3459 0xef200d40, 0xffa11f51, 3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3461 3462 /* Vector VSUB floating point T2 variant. */ 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), 3464 MVE_VSUB_FP_T2, 3465 0xee301f40, 0xefb11f70, 3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3467 3468 /* Vector VSUB T1 variant. */ 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3470 MVE_VSUB_VEC_T1, 3471 0xff000840, 0xff811f51, 3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, 3473 3474 /* Vector VSUB T2 variant. */ 3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3476 MVE_VSUB_VEC_T2, 3477 0xee011f40, 0xff811f70, 3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, 3479 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3481 MVE_ASRLI, 3482 0xea50012f, 0xfff1813f, 3483 "asrl%c\t%17-19l, %9-11h, %j"}, 3484 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3486 MVE_ASRL, 3487 0xea50012d, 0xfff101ff, 3488 "asrl%c\t%17-19l, %9-11h, %12-15S"}, 3489 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3491 MVE_LSLLI, 3492 0xea50010f, 0xfff1813f, 3493 "lsll%c\t%17-19l, %9-11h, %j"}, 3494 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3496 MVE_LSLL, 3497 0xea50010d, 0xfff101ff, 3498 "lsll%c\t%17-19l, %9-11h, %12-15S"}, 3499 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3501 MVE_LSRL, 3502 0xea50011f, 0xfff1813f, 3503 "lsrl%c\t%17-19l, %9-11h, %j"}, 3504 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3506 MVE_SQRSHRL, 3507 0xea51012d, 0xfff1017f, 3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, 3509 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3511 MVE_SQRSHR, 3512 0xea500f2d, 0xfff00fff, 3513 "sqrshr%c\t%16-19S, %12-15S"}, 3514 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3516 MVE_SQSHLL, 3517 0xea51013f, 0xfff1813f, 3518 "sqshll%c\t%17-19l, %9-11h, %j"}, 3519 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3521 MVE_SQSHL, 3522 0xea500f3f, 0xfff08f3f, 3523 "sqshl%c\t%16-19S, %j"}, 3524 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3526 MVE_SRSHRL, 3527 0xea51012f, 0xfff1813f, 3528 "srshrl%c\t%17-19l, %9-11h, %j"}, 3529 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3531 MVE_SRSHR, 3532 0xea500f2f, 0xfff08f3f, 3533 "srshr%c\t%16-19S, %j"}, 3534 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3536 MVE_UQRSHLL, 3537 0xea51010d, 0xfff1017f, 3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, 3539 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3541 MVE_UQRSHL, 3542 0xea500f0d, 0xfff00fff, 3543 "uqrshl%c\t%16-19S, %12-15S"}, 3544 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3546 MVE_UQSHLL, 3547 0xea51010f, 0xfff1813f, 3548 "uqshll%c\t%17-19l, %9-11h, %j"}, 3549 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3551 MVE_UQSHL, 3552 0xea500f0f, 0xfff08f3f, 3553 "uqshl%c\t%16-19S, %j"}, 3554 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3556 MVE_URSHRL, 3557 0xea51011f, 0xfff1813f, 3558 "urshrl%c\t%17-19l, %9-11h, %j"}, 3559 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 3561 MVE_URSHR, 3562 0xea500f1f, 0xfff08f3f, 3563 "urshr%c\t%16-19S, %j"}, 3564 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3566 MVE_CSINC, 3567 0xea509000, 0xfff0f000, 3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3569 3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3571 MVE_CSINV, 3572 0xea50a000, 0xfff0f000, 3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3574 3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3576 MVE_CSET, 3577 0xea5f900f, 0xfffff00f, 3578 "cset\t%8-11S, %4-7C"}, 3579 3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3581 MVE_CSETM, 3582 0xea5fa00f, 0xfffff00f, 3583 "csetm\t%8-11S, %4-7C"}, 3584 3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3586 MVE_CSEL, 3587 0xea508000, 0xfff0f000, 3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3589 3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3591 MVE_CSNEG, 3592 0xea50b000, 0xfff0f000, 3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, 3594 3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3596 MVE_CINC, 3597 0xea509000, 0xfff0f000, 3598 "cinc\t%8-11S, %16-19Z, %4-7C"}, 3599 3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3601 MVE_CINV, 3602 0xea50a000, 0xfff0f000, 3603 "cinv\t%8-11S, %16-19Z, %4-7C"}, 3604 3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 3606 MVE_CNEG, 3607 0xea50b000, 0xfff0f000, 3608 "cneg\t%8-11S, %16-19Z, %4-7C"}, 3609 3610 {ARM_FEATURE_CORE_LOW (0), 3611 MVE_NONE, 3612 0x00000000, 0x00000000, 0} 3613}; 3614 3615/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 3616 ordered: they must be searched linearly from the top to obtain a correct 3617 match. */ 3618 3619/* print_insn_arm recognizes the following format control codes: 3620 3621 %% % 3622 3623 %a print address for ldr/str instruction 3624 %s print address for ldr/str halfword/signextend instruction 3625 %S like %s but allow UNPREDICTABLE addressing 3626 %b print branch destination 3627 %c print condition code (always bits 28-31) 3628 %m print register mask for ldm/stm instruction 3629 %o print operand2 (immediate or register + shift) 3630 %p print 'p' iff bits 12-15 are 15 3631 %t print 't' iff bit 21 set and bit 24 clear 3632 %B print arm BLX(1) destination 3633 %C print the PSR sub type. 3634 %U print barrier type. 3635 %P print address for pli instruction. 3636 3637 %<bitfield>r print as an ARM register 3638 %<bitfield>T print as an ARM register + 1 3639 %<bitfield>R as %r but r15 is UNPREDICTABLE 3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 3642 %<bitfield>d print the bitfield in decimal 3643 %<bitfield>W print the bitfield plus one in decimal 3644 %<bitfield>x print the bitfield in hex 3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 3646 3647 %<bitfield>'c print specified char iff bitfield is all ones 3648 %<bitfield>`c print specified char iff bitfield is all zeroes 3649 %<bitfield>?ab... select from array of values in big endian order 3650 3651 %e print arm SMI operand (bits 0..7,8..19). 3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 3654 %R print the SPSR/CPSR or banked register of an MRS. */ 3655 3656static const struct opcode32 arm_opcodes[] = 3657{ 3658 /* ARM instructions. */ 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3660 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3662 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 3663 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3673 0x00800090, 0x0fa000f0, 3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 3676 0x00a00090, 0x0fa000f0, 3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 3678 3679 /* V8.2 RAS extension instructions. */ 3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 3681 0xe320f010, 0xffffffff, "esb"}, 3682 3683 /* V8-R instructions. */ 3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 3685 0xf57ff04c, 0xffffffff, "dfb"}, 3686 3687 /* V8 instructions. */ 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3689 0x0320f005, 0x0fffffff, "sevl"}, 3690 /* Defined in V8 but is in NOP space so available to all arch. */ 3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3692 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 3721 /* CRC32 instructions. */ 3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 3734 3735 /* Privileged Access Never extension instructions. */ 3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 3737 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 3738 3739 /* Virtualization Extension instructions. */ 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 3742 3743 /* Integer Divide Extension instructions. */ 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 3748 3749 /* MP Extension instructions. */ 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 3751 3752 /* Speculation Barriers. */ 3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 3756 3757 /* V7 instructions. */ 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 3766 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 3767 3768 /* ARM V6T2 instructions. */ 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 3777 3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 3782 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 3791 3792 /* ARM Security extension instructions. */ 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 3794 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 3795 3796 /* ARM V6K instructions. */ 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3798 0xf57ff01f, 0xffffffff, "clrex"}, 3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 3811 3812 /* ARMv8.5-A instructions. */ 3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, 3814 3815 /* ARM V6K NOP hints. */ 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3817 0x0320f001, 0x0fffffff, "yield%c"}, 3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3819 0x0320f002, 0x0fffffff, "wfe%c"}, 3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3821 0x0320f003, 0x0fffffff, "wfi%c"}, 3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3823 0x0320f004, 0x0fffffff, "sev%c"}, 3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 3825 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 3826 3827 /* ARM V6 instructions. */ 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3829 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3831 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3833 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3835 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3837 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3847 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4027 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 4072 4073 /* V5J instruction. */ 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 4076 4077 /* V5 Instructions. */ 4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4079 0xe1200070, 0xfff000f0, 4080 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4082 0xfa000000, 0xfe000000, "blx\t%B"}, 4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 4087 4088 /* V5E "El Segundo" Instructions. */ 4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 4094 0xf450f000, 0xfc70f000, "pld\t%a"}, 4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 4103 4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 4108 4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 4117 4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 4126 4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 4131 4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 4140 4141 /* ARM Instructions. */ 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 4144 4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 4157 4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 4166 4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 4175 4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 4182 4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 4189 4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 4196 4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 4203 4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 4210 4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 4217 4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 4224 4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 4231 4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 4238 4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 4245 4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 4252 4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 4259 4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 4266 4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 4273 4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 4288 4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 4295 4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 4302 4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 4307 4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 4310 4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 4315 4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4349 0x092d0000, 0x0fff0000, "push%c\t%m"}, 4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4354 4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 4393 4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 4398 4399 /* The rest. */ 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 4401 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 4404 {ARM_FEATURE_CORE_LOW (0), 4405 0x00000000, 0x00000000, 0} 4406}; 4407 4408/* print_insn_thumb16 recognizes the following format control codes: 4409 4410 %S print Thumb register (bits 3..5 as high number if bit 6 set) 4411 %D print Thumb register (bits 0..2 as high number if bit 7 set) 4412 %<bitfield>I print bitfield as a signed decimal 4413 (top bit of range being the sign bit) 4414 %N print Thumb register mask (with LR) 4415 %O print Thumb register mask (with PC) 4416 %M print Thumb register mask 4417 %b print CZB's 6-bit unsigned branch destination 4418 %s print Thumb right-shift immediate (6..10; 0 == 32). 4419 %c print the condition code 4420 %C print the condition code, or "s" if not conditional 4421 %x print warning if conditional an not at end of IT block" 4422 %X print "\t; unpredictable <IT:code>" if conditional 4423 %I print IT instruction suffix and operands 4424 %W print Thumb Writeback indicator for LDMIA 4425 %<bitfield>r print bitfield as an ARM register 4426 %<bitfield>d print bitfield as a decimal 4427 %<bitfield>H print (bitfield * 2) as a decimal 4428 %<bitfield>W print (bitfield * 4) as a decimal 4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 4430 %<bitfield>B print Thumb branch destination (signed displacement) 4431 %<bitfield>c print bitfield as a condition code 4432 %<bitnum>'c print specified char iff bit is one 4433 %<bitnum>?ab print a if bit is one else print b. */ 4434 4435static const struct opcode16 thumb_opcodes[] = 4436{ 4437 /* Thumb instructions. */ 4438 4439 /* ARMv8-M Security Extensions instructions. */ 4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 4442 4443 /* ARM V8 instructions. */ 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 4447 4448 /* ARM V6K no-argument instructions. */ 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 4455 4456 /* ARM V6T2 instructions. */ 4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 4462 4463 /* ARM V6. */ 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 4475 4476 /* ARM V5 ISA extends Thumb. */ 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 4482 /* ARM V4T ISA (Thumb v1). */ 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4484 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 4485 /* Format 4. */ 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 4502 /* format 13 */ 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 4505 /* format 5 */ 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 4510 /* format 14 */ 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 4513 /* format 2 */ 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 4522 /* format 8 */ 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 4529 /* format 7 */ 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 4534 /* format 1 */ 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 4540 /* format 3 */ 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 4545 /* format 6 */ 4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4548 0x4800, 0xF800, 4549 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 4550 /* format 9 */ 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 4559 /* format 10 */ 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 4564 /* format 11 */ 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4566 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4568 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 4569 /* format 12 */ 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4571 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 4573 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 4574 /* format 15 */ 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 4577 /* format 17 */ 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 4579 /* format 16 */ 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 4583 /* format 18 */ 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 4585 4586 /* The E800 .. FFFF range is unconditionally redirected to the 4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 4588 are processed via that table. Thus, we can never encounter a 4589 bare "second half of BL/BLX(1)" instruction here. */ 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 4592}; 4593 4594/* Thumb32 opcodes use the same table structure as the ARM opcodes. 4595 We adopt the convention that hw1 is the high 16 bits of .value and 4596 .mask, hw2 the low 16 bits. 4597 4598 print_insn_thumb32 recognizes the following format control codes: 4599 4600 %% % 4601 4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 4603 %M print a modified 12-bit immediate (same location) 4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 4607 %S print a possibly-shifted Rm 4608 4609 %L print address for a ldrd/strd instruction 4610 %a print the address of a plain load/store 4611 %w print the width and signedness of a core load/store 4612 %m print register mask for ldm/stm 4613 %n print register mask for clrm 4614 4615 %E print the lsb and width fields of a bfc/bfi instruction 4616 %F print the lsb and width fields of a sbfx/ubfx instruction 4617 %G print a fallback offset for Branch Future instructions 4618 %W print an offset for BF instruction 4619 %Y print an offset for BFL instruction 4620 %Z print an offset for BFCSEL instruction 4621 %Q print an offset for Low Overhead Loop instructions 4622 %P print an offset for Low Overhead Loop end instructions 4623 %b print a conditional branch offset 4624 %B print an unconditional branch offset 4625 %s print the shift field of an SSAT instruction 4626 %R print the rotation field of an SXT instruction 4627 %U print barrier type. 4628 %P print address for pli instruction. 4629 %c print the condition code 4630 %x print warning if conditional an not at end of IT block" 4631 %X print "\t; unpredictable <IT:code>" if conditional 4632 4633 %<bitfield>d print bitfield in decimal 4634 %<bitfield>D print bitfield plus one in decimal 4635 %<bitfield>W print bitfield*4 in decimal 4636 %<bitfield>r print bitfield as an ARM register 4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE 4639 %<bitfield>c print bitfield as a condition code 4640 4641 %<bitfield>'c print specified char iff bitfield is all ones 4642 %<bitfield>`c print specified char iff bitfield is all zeroes 4643 %<bitfield>?ab... select from array of values in big endian order 4644 4645 With one exception at the bottom (done because BL and BLX(1) need 4646 to come dead last), this table was machine-sorted first in 4647 decreasing order of number of bits set in the mask, then in 4648 increasing numeric order of mask, then in increasing numeric order 4649 of opcode. This order is not the clearest for a human reader, but 4650 is guaranteed never to catch a special-case bit pattern with a more 4651 general mask, which is important, because this instruction encoding 4652 makes heavy use of special-case bit patterns. */ 4653static const struct opcode32 thumb32_opcodes[] = 4654{ 4655 /* Arm v8.1-M Mainline Pointer Authentication and Branch Target 4656 Identification Extension. */ 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4658 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"}, 4659 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4660 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"}, 4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4662 0xf3af800f, 0xffffffff, "bti"}, 4663 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4664 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"}, 4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4666 0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"}, 4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4668 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"}, 4669 {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI), 4670 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"}, 4671 4672 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions 4673 instructions. */ 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4675 0xf00fe001, 0xffffffff, "lctp%c"}, 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4677 0xf02fc001, 0xfffff001, "le\t%P"}, 4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4679 0xf00fc001, 0xfffff001, "le\tlr, %P"}, 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4681 0xf01fc001, 0xfffff001, "letp\tlr, %P"}, 4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4683 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, 4684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4685 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"}, 4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4687 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, 4688 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4689 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"}, 4690 4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4692 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, 4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4694 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4696 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"}, 4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4698 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, 4699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4700 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"}, 4701 4702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 4703 0xe89f0000, 0xffff2000, "clrm%c\t%n"}, 4704 4705 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 4706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 4707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4708 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 4709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4710 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 4711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4712 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 4713 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 4714 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 4715 4716 /* ARM V8.2 RAS extension instructions. */ 4717 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 4718 0xf3af8010, 0xffffffff, "esb"}, 4719 4720 /* V8 instructions. */ 4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4722 0xf3af8005, 0xffffffff, "sevl%c.w"}, 4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4724 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4726 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4728 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4730 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4732 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4734 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4736 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 4737 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4738 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 4739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4740 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 4741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4742 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 4743 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4744 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 4745 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4746 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 4747 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4748 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 4749 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4750 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 4751 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 4752 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 4753 4754 /* V8-R instructions. */ 4755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R), 4756 0xf3bf8f4c, 0xffffffff, "dfb%c"}, 4757 4758 /* CRC32 instructions. */ 4759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4760 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 4761 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4762 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 4763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4764 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 4765 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4766 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 4767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4768 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 4769 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), 4770 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 4771 4772 /* Speculation Barriers. */ 4773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 4776 4777 /* V7 instructions. */ 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 4779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 4783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4786 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 4788 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 4789 4790 /* Virtualization Extension instructions. */ 4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 4792 /* We skip ERET as that is SUBS pc, lr, #0. */ 4793 4794 /* MP Extension instructions. */ 4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 4796 4797 /* Security extension instructions. */ 4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 4799 4800 /* ARMv8.5-A instructions. */ 4801 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, 4802 4803 /* Instructions defined in the basic V6T2 set. */ 4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4810 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 4812 4813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4814 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4816 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4818 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4820 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 4821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4822 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 4823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4824 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4826 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4828 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4830 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4832 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4834 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4836 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4838 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4840 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4842 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 4843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4844 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4846 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4848 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4850 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4852 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4854 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4856 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4858 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4860 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 4861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4862 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4864 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4866 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4868 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4870 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4872 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4874 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4876 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4878 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4880 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4882 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4884 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4886 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4888 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4890 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4892 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4894 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4896 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4898 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4900 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4902 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4904 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4906 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4908 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4910 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4912 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4914 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4916 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4918 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4920 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4922 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4924 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4926 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4928 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4930 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4932 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4934 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4936 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4938 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4940 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4942 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4944 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4946 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4948 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 4949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4950 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4952 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4954 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4956 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4958 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4960 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4962 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4964 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4966 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4968 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 4969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 4970 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4972 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4974 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4976 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4978 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4980 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4982 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4984 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4986 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4988 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4990 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4992 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4994 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4996 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 4998 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5000 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5002 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5004 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5006 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5008 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5010 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5012 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5014 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5016 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 5017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5018 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5020 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5022 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5024 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5026 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5028 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5030 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5032 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5034 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5036 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5037 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5038 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5040 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5042 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5044 0xf810f000, 0xff70f000, "pld%c\t%a"}, 5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5046 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5048 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5050 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5052 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5054 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5056 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5058 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5060 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5062 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5064 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 5065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5066 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5068 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 5069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5070 0xfb100000, 0xfff000c0, 5071 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 5072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5073 0xfbc00080, 0xfff000c0, 5074 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5076 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5078 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5080 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5082 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5084 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 5085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5086 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5088 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 5089 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5090 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 5091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5092 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5094 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5096 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5098 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5100 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5102 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5104 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5106 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5108 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5110 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 5111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 5112 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5114 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5116 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5118 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5120 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5122 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5124 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5126 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 5127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5128 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 5129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5130 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5132 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 5133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5134 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 5135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5136 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5138 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5140 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 5141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5142 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5144 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5146 0xe9400000, 0xff500000, 5147 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5149 0xe9500000, 0xff500000, 5150 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 5151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5152 0xe8600000, 0xff700000, 5153 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 5154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5155 0xe8700000, 0xff700000, 5156 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 5157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5158 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5160 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 5161 5162 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 5163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5164 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 5165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5166 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 5167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5168 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 5169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 5170 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 5171 5172 /* These have been 32-bit since the invention of Thumb. */ 5173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5174 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 5175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 5176 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 5177 5178 /* Fallback. */ 5179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 5180 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 5181 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 5182}; 5183 5184static const char *const arm_conditional[] = 5185{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 5186 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 5187 5188static const char *const arm_fp_const[] = 5189{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 5190 5191static const char *const arm_shift[] = 5192{"lsl", "lsr", "asr", "ror"}; 5193 5194typedef struct 5195{ 5196 const char *name; 5197 const char *description; 5198 const char *reg_names[16]; 5199} 5200arm_regname; 5201 5202static const arm_regname regnames[] = 5203{ 5204 { "reg-names-raw", N_("Select raw register names"), 5205 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 5206 { "reg-names-gcc", N_("Select register names used by GCC"), 5207 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5208 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 5209 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 5210 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 5211 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 5212 { "reg-names-apcs", N_("Select register names used in the APCS"), 5213 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 5214 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 5215 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 5216 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 5217 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 5218 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } } 5219}; 5220 5221static const char *const iwmmxt_wwnames[] = 5222{"b", "h", "w", "d"}; 5223 5224static const char *const iwmmxt_wwssnames[] = 5225{"b", "bus", "bc", "bss", 5226 "h", "hus", "hc", "hss", 5227 "w", "wus", "wc", "wss", 5228 "d", "dus", "dc", "dss" 5229}; 5230 5231static const char *const iwmmxt_regnames[] = 5232{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 5233 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 5234}; 5235 5236static const char *const iwmmxt_cregnames[] = 5237{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 5238 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 5239}; 5240 5241static const char *const vec_condnames[] = 5242{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le" 5243}; 5244 5245static const char *const mve_predicatenames[] = 5246{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "", 5247 "eee", "ee", "eet", "e", "ett", "et", "ete" 5248}; 5249 5250/* Names for 2-bit size field for mve vector isntructions. */ 5251static const char *const mve_vec_sizename[] = 5252 { "8", "16", "32", "64"}; 5253 5254/* Indicates whether we are processing a then predicate, 5255 else predicate or none at all. */ 5256enum vpt_pred_state 5257{ 5258 PRED_NONE, 5259 PRED_THEN, 5260 PRED_ELSE 5261}; 5262 5263/* Information used to process a vpt block and subsequent instructions. */ 5264struct vpt_block 5265{ 5266 /* Are we in a vpt block. */ 5267 bool in_vpt_block; 5268 5269 /* Next predicate state if in vpt block. */ 5270 enum vpt_pred_state next_pred_state; 5271 5272 /* Mask from vpt/vpst instruction. */ 5273 long predicate_mask; 5274 5275 /* Instruction number in vpt block. */ 5276 long current_insn_num; 5277 5278 /* Number of instructions in vpt block.. */ 5279 long num_pred_insn; 5280}; 5281 5282static struct vpt_block vpt_block_state = 5283{ 5284 false, 5285 PRED_NONE, 5286 0, 5287 0, 5288 0 5289}; 5290 5291/* Default to GCC register name set. */ 5292static unsigned int regname_selected = 1; 5293 5294#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 5295#define arm_regnames regnames[regname_selected].reg_names 5296 5297static bool force_thumb = false; 5298static uint16_t cde_coprocs = 0; 5299 5300/* Current IT instruction state. This contains the same state as the IT 5301 bits in the CPSR. */ 5302static unsigned int ifthen_state; 5303/* IT state for the next instruction. */ 5304static unsigned int ifthen_next_state; 5305/* The address of the insn for which the IT state is valid. */ 5306static bfd_vma ifthen_address; 5307#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 5308/* Indicates that the current Conditional state is unconditional or outside 5309 an IT block. */ 5310#define COND_UNCOND 16 5311 5312 5313/* Functions. */ 5314/* Extract the predicate mask for a VPT or VPST instruction. 5315 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */ 5316 5317static long 5318mve_extract_pred_mask (long given) 5319{ 5320 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13); 5321} 5322 5323/* Return the number of instructions in a MVE predicate block. */ 5324static long 5325num_instructions_vpt_block (long given) 5326{ 5327 long mask = mve_extract_pred_mask (given); 5328 if (mask == 0) 5329 return 0; 5330 5331 if (mask == 8) 5332 return 1; 5333 5334 if ((mask & 7) == 4) 5335 return 2; 5336 5337 if ((mask & 3) == 2) 5338 return 3; 5339 5340 if ((mask & 1) == 1) 5341 return 4; 5342 5343 return 0; 5344} 5345 5346static void 5347mark_outside_vpt_block (void) 5348{ 5349 vpt_block_state.in_vpt_block = false; 5350 vpt_block_state.next_pred_state = PRED_NONE; 5351 vpt_block_state.predicate_mask = 0; 5352 vpt_block_state.current_insn_num = 0; 5353 vpt_block_state.num_pred_insn = 0; 5354} 5355 5356static void 5357mark_inside_vpt_block (long given) 5358{ 5359 vpt_block_state.in_vpt_block = true; 5360 vpt_block_state.next_pred_state = PRED_THEN; 5361 vpt_block_state.predicate_mask = mve_extract_pred_mask (given); 5362 vpt_block_state.current_insn_num = 0; 5363 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given); 5364 assert (vpt_block_state.num_pred_insn >= 1); 5365} 5366 5367static enum vpt_pred_state 5368invert_next_predicate_state (enum vpt_pred_state astate) 5369{ 5370 if (astate == PRED_THEN) 5371 return PRED_ELSE; 5372 else if (astate == PRED_ELSE) 5373 return PRED_THEN; 5374 else 5375 return PRED_NONE; 5376} 5377 5378static enum vpt_pred_state 5379update_next_predicate_state (void) 5380{ 5381 long pred_mask = vpt_block_state.predicate_mask; 5382 long mask_for_insn = 0; 5383 5384 switch (vpt_block_state.current_insn_num) 5385 { 5386 case 1: 5387 mask_for_insn = 8; 5388 break; 5389 5390 case 2: 5391 mask_for_insn = 4; 5392 break; 5393 5394 case 3: 5395 mask_for_insn = 2; 5396 break; 5397 5398 case 4: 5399 return PRED_NONE; 5400 } 5401 5402 if (pred_mask & mask_for_insn) 5403 return invert_next_predicate_state (vpt_block_state.next_pred_state); 5404 else 5405 return vpt_block_state.next_pred_state; 5406} 5407 5408static void 5409update_vpt_block_state (void) 5410{ 5411 vpt_block_state.current_insn_num++; 5412 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn) 5413 { 5414 /* No more instructions to process in vpt block. */ 5415 mark_outside_vpt_block (); 5416 return; 5417 } 5418 5419 vpt_block_state.next_pred_state = update_next_predicate_state (); 5420} 5421 5422/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 5423 Returns pointer to following character of the format string and 5424 fills in *VALUEP and *WIDTHP with the extracted value and number of 5425 bits extracted. WIDTHP can be NULL. */ 5426 5427static const char * 5428arm_decode_bitfield (const char *ptr, 5429 unsigned long insn, 5430 unsigned long *valuep, 5431 int *widthp) 5432{ 5433 unsigned long value = 0; 5434 int width = 0; 5435 5436 do 5437 { 5438 int start, end; 5439 int bits; 5440 5441 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 5442 start = start * 10 + *ptr - '0'; 5443 if (*ptr == '-') 5444 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 5445 end = end * 10 + *ptr - '0'; 5446 else 5447 end = start; 5448 bits = end - start; 5449 if (bits < 0) 5450 abort (); 5451 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 5452 width += bits + 1; 5453 } 5454 while (*ptr++ == ','); 5455 *valuep = value; 5456 if (widthp) 5457 *widthp = width; 5458 return ptr - 1; 5459} 5460 5461static void 5462arm_decode_shift (long given, fprintf_ftype func, void *stream, 5463 bool print_shift) 5464{ 5465 func (stream, "%s", arm_regnames[given & 0xf]); 5466 5467 if ((given & 0xff0) != 0) 5468 { 5469 if ((given & 0x10) == 0) 5470 { 5471 int amount = (given & 0xf80) >> 7; 5472 int shift = (given & 0x60) >> 5; 5473 5474 if (amount == 0) 5475 { 5476 if (shift == 3) 5477 { 5478 func (stream, ", rrx"); 5479 return; 5480 } 5481 5482 amount = 32; 5483 } 5484 5485 if (print_shift) 5486 func (stream, ", %s #%d", arm_shift[shift], amount); 5487 else 5488 func (stream, ", #%d", amount); 5489 } 5490 else if ((given & 0x80) == 0x80) 5491 func (stream, "\t; <illegal shifter operand>"); 5492 else if (print_shift) 5493 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 5494 arm_regnames[(given & 0xf00) >> 8]); 5495 else 5496 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 5497 } 5498} 5499 5500/* Return TRUE if the MATCHED_INSN can be inside an IT block. */ 5501 5502static bool 5503is_mve_okay_in_it (enum mve_instructions matched_insn) 5504{ 5505 switch (matched_insn) 5506 { 5507 case MVE_VMOV_GP_TO_VEC_LANE: 5508 case MVE_VMOV2_VEC_LANE_TO_GP: 5509 case MVE_VMOV2_GP_TO_VEC_LANE: 5510 case MVE_VMOV_VEC_LANE_TO_GP: 5511 case MVE_LSLL: 5512 case MVE_LSLLI: 5513 case MVE_LSRL: 5514 case MVE_ASRL: 5515 case MVE_ASRLI: 5516 case MVE_SQRSHRL: 5517 case MVE_SQRSHR: 5518 case MVE_UQRSHL: 5519 case MVE_UQRSHLL: 5520 case MVE_UQSHL: 5521 case MVE_UQSHLL: 5522 case MVE_URSHRL: 5523 case MVE_URSHR: 5524 case MVE_SRSHRL: 5525 case MVE_SRSHR: 5526 case MVE_SQSHLL: 5527 case MVE_SQSHL: 5528 return true; 5529 default: 5530 return false; 5531 } 5532} 5533 5534static bool 5535is_mve_architecture (struct disassemble_info *info) 5536{ 5537 struct arm_private_data *private_data = info->private_data; 5538 arm_feature_set allowed_arches = private_data->features; 5539 5540 arm_feature_set arm_ext_v8_1m_main 5541 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 5542 5543 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 5544 && !ARM_CPU_IS_ANY (allowed_arches)) 5545 return true; 5546 else 5547 return false; 5548} 5549 5550static bool 5551is_vpt_instruction (long given) 5552{ 5553 5554 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */ 5555 if ((given & 0x0040e000) == 0) 5556 return false; 5557 5558 /* VPT floating point T1 variant. */ 5559 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1)) 5560 /* VPT floating point T2 variant. */ 5561 || ((given & 0xefb10f50) == 0xee310f40) 5562 /* VPT vector T1 variant. */ 5563 || ((given & 0xff811f51) == 0xfe010f00) 5564 /* VPT vector T2 variant. */ 5565 || ((given & 0xff811f51) == 0xfe010f01 5566 && ((given & 0x300000) != 0x300000)) 5567 /* VPT vector T3 variant. */ 5568 || ((given & 0xff811f50) == 0xfe011f00) 5569 /* VPT vector T4 variant. */ 5570 || ((given & 0xff811f70) == 0xfe010f40) 5571 /* VPT vector T5 variant. */ 5572 || ((given & 0xff811f70) == 0xfe010f60) 5573 /* VPT vector T6 variant. */ 5574 || ((given & 0xff811f50) == 0xfe011f40) 5575 /* VPST vector T variant. */ 5576 || ((given & 0xffbf1fff) == 0xfe310f4d)) 5577 return true; 5578 else 5579 return false; 5580} 5581 5582/* Decode a bitfield from opcode GIVEN, with starting bitfield = START 5583 and ending bitfield = END. END must be greater than START. */ 5584 5585static unsigned long 5586arm_decode_field (unsigned long given, unsigned int start, unsigned int end) 5587{ 5588 int bits = end - start; 5589 5590 if (bits < 0) 5591 abort (); 5592 5593 return ((given >> start) & ((2ul << bits) - 1)); 5594} 5595 5596/* Decode a bitfield from opcode GIVEN, with multiple bitfields: 5597 START:END and START2:END2. END/END2 must be greater than 5598 START/START2. */ 5599 5600static unsigned long 5601arm_decode_field_multiple (unsigned long given, unsigned int start, 5602 unsigned int end, unsigned int start2, 5603 unsigned int end2) 5604{ 5605 int bits = end - start; 5606 int bits2 = end2 - start2; 5607 unsigned long value = 0; 5608 int width = 0; 5609 5610 if (bits2 < 0) 5611 abort (); 5612 5613 value = arm_decode_field (given, start, end); 5614 width += bits + 1; 5615 5616 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width; 5617 return value; 5618} 5619 5620/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN. 5621 This helps us decode instructions that change mnemonic depending on specific 5622 operand values/encodings. */ 5623 5624static bool 5625is_mve_encoding_conflict (unsigned long given, 5626 enum mve_instructions matched_insn) 5627{ 5628 switch (matched_insn) 5629 { 5630 case MVE_VPST: 5631 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5632 return true; 5633 else 5634 return false; 5635 5636 case MVE_VPT_FP_T1: 5637 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5638 return true; 5639 if ((arm_decode_field (given, 12, 12) == 0) 5640 && (arm_decode_field (given, 0, 0) == 1)) 5641 return true; 5642 return false; 5643 5644 case MVE_VPT_FP_T2: 5645 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5646 return true; 5647 if (arm_decode_field (given, 0, 3) == 0xd) 5648 return true; 5649 return false; 5650 5651 case MVE_VPT_VEC_T1: 5652 case MVE_VPT_VEC_T2: 5653 case MVE_VPT_VEC_T3: 5654 case MVE_VPT_VEC_T4: 5655 case MVE_VPT_VEC_T5: 5656 case MVE_VPT_VEC_T6: 5657 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) 5658 return true; 5659 if (arm_decode_field (given, 20, 21) == 3) 5660 return true; 5661 return false; 5662 5663 case MVE_VCMP_FP_T1: 5664 if ((arm_decode_field (given, 12, 12) == 0) 5665 && (arm_decode_field (given, 0, 0) == 1)) 5666 return true; 5667 else 5668 return false; 5669 5670 case MVE_VCMP_FP_T2: 5671 if (arm_decode_field (given, 0, 3) == 0xd) 5672 return true; 5673 else 5674 return false; 5675 5676 case MVE_VQADD_T2: 5677 case MVE_VQSUB_T2: 5678 case MVE_VMUL_VEC_T2: 5679 case MVE_VMULH: 5680 case MVE_VRMULH: 5681 case MVE_VMLA: 5682 case MVE_VMAX: 5683 case MVE_VMIN: 5684 case MVE_VBRSR: 5685 case MVE_VADD_VEC_T2: 5686 case MVE_VSUB_VEC_T2: 5687 case MVE_VABAV: 5688 case MVE_VQRSHL_T1: 5689 case MVE_VQSHL_T4: 5690 case MVE_VRSHL_T1: 5691 case MVE_VSHL_T3: 5692 case MVE_VCADD_VEC: 5693 case MVE_VHCADD: 5694 case MVE_VDDUP: 5695 case MVE_VIDUP: 5696 case MVE_VQRDMLADH: 5697 case MVE_VQDMLAH: 5698 case MVE_VQRDMLAH: 5699 case MVE_VQDMLASH: 5700 case MVE_VQRDMLASH: 5701 case MVE_VQDMLSDH: 5702 case MVE_VQRDMLSDH: 5703 case MVE_VQDMULH_T3: 5704 case MVE_VQRDMULH_T4: 5705 case MVE_VQDMLADH: 5706 case MVE_VMLAS: 5707 case MVE_VMULL_INT: 5708 case MVE_VHADD_T2: 5709 case MVE_VHSUB_T2: 5710 case MVE_VCMP_VEC_T1: 5711 case MVE_VCMP_VEC_T2: 5712 case MVE_VCMP_VEC_T3: 5713 case MVE_VCMP_VEC_T4: 5714 case MVE_VCMP_VEC_T5: 5715 case MVE_VCMP_VEC_T6: 5716 if (arm_decode_field (given, 20, 21) == 3) 5717 return true; 5718 else 5719 return false; 5720 5721 case MVE_VLD2: 5722 case MVE_VLD4: 5723 case MVE_VST2: 5724 case MVE_VST4: 5725 if (arm_decode_field (given, 7, 8) == 3) 5726 return true; 5727 else 5728 return false; 5729 5730 case MVE_VSTRB_T1: 5731 case MVE_VSTRH_T2: 5732 if ((arm_decode_field (given, 24, 24) == 0) 5733 && (arm_decode_field (given, 21, 21) == 0)) 5734 { 5735 return true; 5736 } 5737 else if ((arm_decode_field (given, 7, 8) == 3)) 5738 return true; 5739 else 5740 return false; 5741 5742 case MVE_VLDRB_T1: 5743 case MVE_VLDRH_T2: 5744 case MVE_VLDRW_T7: 5745 case MVE_VSTRB_T5: 5746 case MVE_VSTRH_T6: 5747 case MVE_VSTRW_T7: 5748 if ((arm_decode_field (given, 24, 24) == 0) 5749 && (arm_decode_field (given, 21, 21) == 0)) 5750 { 5751 return true; 5752 } 5753 else 5754 return false; 5755 5756 case MVE_VCVT_FP_FIX_VEC: 5757 return (arm_decode_field (given, 16, 21) & 0x38) == 0; 5758 5759 case MVE_VBIC_IMM: 5760 case MVE_VORR_IMM: 5761 { 5762 unsigned long cmode = arm_decode_field (given, 8, 11); 5763 5764 if ((cmode & 1) == 0) 5765 return true; 5766 else if ((cmode & 0xc) == 0xc) 5767 return true; 5768 else 5769 return false; 5770 } 5771 5772 case MVE_VMVN_IMM: 5773 { 5774 unsigned long cmode = arm_decode_field (given, 8, 11); 5775 5776 if (cmode == 0xe) 5777 return true; 5778 else if ((cmode & 0x9) == 1) 5779 return true; 5780 else if ((cmode & 0xd) == 9) 5781 return true; 5782 else 5783 return false; 5784 } 5785 5786 case MVE_VMOV_IMM_TO_VEC: 5787 if ((arm_decode_field (given, 5, 5) == 1) 5788 && (arm_decode_field (given, 8, 11) != 0xe)) 5789 return true; 5790 else 5791 return false; 5792 5793 case MVE_VMOVL: 5794 { 5795 unsigned long size = arm_decode_field (given, 19, 20); 5796 if ((size == 0) || (size == 3)) 5797 return true; 5798 else 5799 return false; 5800 } 5801 5802 case MVE_VMAXA: 5803 case MVE_VMINA: 5804 case MVE_VMAXV: 5805 case MVE_VMAXAV: 5806 case MVE_VMINV: 5807 case MVE_VMINAV: 5808 case MVE_VQRSHL_T2: 5809 case MVE_VQSHL_T1: 5810 case MVE_VRSHL_T2: 5811 case MVE_VSHL_T2: 5812 case MVE_VSHLL_T2: 5813 case MVE_VADDV: 5814 case MVE_VMOVN: 5815 case MVE_VQMOVUN: 5816 case MVE_VQMOVN: 5817 if (arm_decode_field (given, 18, 19) == 3) 5818 return true; 5819 else 5820 return false; 5821 5822 case MVE_VMLSLDAV: 5823 case MVE_VRMLSLDAVH: 5824 case MVE_VMLALDAV: 5825 case MVE_VADDLV: 5826 if (arm_decode_field (given, 20, 22) == 7) 5827 return true; 5828 else 5829 return false; 5830 5831 case MVE_VRMLALDAVH: 5832 if ((arm_decode_field (given, 20, 22) & 6) == 6) 5833 return true; 5834 else 5835 return false; 5836 5837 case MVE_VDWDUP: 5838 case MVE_VIWDUP: 5839 if ((arm_decode_field (given, 20, 21) == 3) 5840 || (arm_decode_field (given, 1, 3) == 7)) 5841 return true; 5842 else 5843 return false; 5844 5845 5846 case MVE_VSHLL_T1: 5847 if (arm_decode_field (given, 16, 18) == 0) 5848 { 5849 unsigned long sz = arm_decode_field (given, 19, 20); 5850 5851 if ((sz == 1) || (sz == 2)) 5852 return true; 5853 else 5854 return false; 5855 } 5856 else 5857 return false; 5858 5859 case MVE_VQSHL_T2: 5860 case MVE_VQSHLU_T3: 5861 case MVE_VRSHR: 5862 case MVE_VSHL_T1: 5863 case MVE_VSHR: 5864 case MVE_VSLI: 5865 case MVE_VSRI: 5866 if (arm_decode_field (given, 19, 21) == 0) 5867 return true; 5868 else 5869 return false; 5870 5871 case MVE_VCTP: 5872 if (arm_decode_field (given, 16, 19) == 0xf) 5873 return true; 5874 else 5875 return false; 5876 5877 case MVE_ASRLI: 5878 case MVE_ASRL: 5879 case MVE_LSLLI: 5880 case MVE_LSLL: 5881 case MVE_LSRL: 5882 case MVE_SQRSHRL: 5883 case MVE_SQSHLL: 5884 case MVE_SRSHRL: 5885 case MVE_UQRSHLL: 5886 case MVE_UQSHLL: 5887 case MVE_URSHRL: 5888 if (arm_decode_field (given, 9, 11) == 0x7) 5889 return true; 5890 else 5891 return false; 5892 5893 case MVE_CSINC: 5894 case MVE_CSINV: 5895 { 5896 unsigned long rm, rn; 5897 rm = arm_decode_field (given, 0, 3); 5898 rn = arm_decode_field (given, 16, 19); 5899 /* CSET/CSETM. */ 5900 if (rm == 0xf && rn == 0xf) 5901 return true; 5902 /* CINC/CINV. */ 5903 else if (rn == rm && rn != 0xf) 5904 return true; 5905 } 5906 /* Fall through. */ 5907 case MVE_CSEL: 5908 case MVE_CSNEG: 5909 if (arm_decode_field (given, 0, 3) == 0xd) 5910 return true; 5911 /* CNEG. */ 5912 else if (matched_insn == MVE_CSNEG) 5913 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19)) 5914 return true; 5915 return false; 5916 5917 default: 5918 case MVE_VADD_FP_T1: 5919 case MVE_VADD_FP_T2: 5920 case MVE_VADD_VEC_T1: 5921 return false; 5922 5923 } 5924} 5925 5926static void 5927print_mve_vld_str_addr (struct disassemble_info *info, 5928 unsigned long given, 5929 enum mve_instructions matched_insn) 5930{ 5931 void *stream = info->stream; 5932 fprintf_ftype func = info->fprintf_func; 5933 5934 unsigned long p, w, gpr, imm, add, mod_imm; 5935 5936 imm = arm_decode_field (given, 0, 6); 5937 mod_imm = imm; 5938 5939 switch (matched_insn) 5940 { 5941 case MVE_VLDRB_T1: 5942 case MVE_VSTRB_T1: 5943 gpr = arm_decode_field (given, 16, 18); 5944 break; 5945 5946 case MVE_VLDRH_T2: 5947 case MVE_VSTRH_T2: 5948 gpr = arm_decode_field (given, 16, 18); 5949 mod_imm = imm << 1; 5950 break; 5951 5952 case MVE_VLDRH_T6: 5953 case MVE_VSTRH_T6: 5954 gpr = arm_decode_field (given, 16, 19); 5955 mod_imm = imm << 1; 5956 break; 5957 5958 case MVE_VLDRW_T7: 5959 case MVE_VSTRW_T7: 5960 gpr = arm_decode_field (given, 16, 19); 5961 mod_imm = imm << 2; 5962 break; 5963 5964 case MVE_VLDRB_T5: 5965 case MVE_VSTRB_T5: 5966 gpr = arm_decode_field (given, 16, 19); 5967 break; 5968 5969 default: 5970 return; 5971 } 5972 5973 p = arm_decode_field (given, 24, 24); 5974 w = arm_decode_field (given, 21, 21); 5975 5976 add = arm_decode_field (given, 23, 23); 5977 5978 char * add_sub; 5979 5980 /* Don't print anything for '+' as it is implied. */ 5981 if (add == 1) 5982 add_sub = ""; 5983 else 5984 add_sub = "-"; 5985 5986 if (p == 1) 5987 { 5988 /* Offset mode. */ 5989 if (w == 0) 5990 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm); 5991 /* Pre-indexed mode. */ 5992 else 5993 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm); 5994 } 5995 else if ((p == 0) && (w == 1)) 5996 /* Post-index mode. */ 5997 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm); 5998} 5999 6000/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN. 6001 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why 6002 this encoding is undefined. */ 6003 6004static bool 6005is_mve_undefined (unsigned long given, enum mve_instructions matched_insn, 6006 enum mve_undefined *undefined_code) 6007{ 6008 *undefined_code = UNDEF_NONE; 6009 6010 switch (matched_insn) 6011 { 6012 case MVE_VDUP: 6013 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3) 6014 { 6015 *undefined_code = UNDEF_SIZE_3; 6016 return true; 6017 } 6018 else 6019 return false; 6020 6021 case MVE_VQADD_T1: 6022 case MVE_VQSUB_T1: 6023 case MVE_VMUL_VEC_T1: 6024 case MVE_VABD_VEC: 6025 case MVE_VADD_VEC_T1: 6026 case MVE_VSUB_VEC_T1: 6027 case MVE_VQDMULH_T1: 6028 case MVE_VQRDMULH_T2: 6029 case MVE_VRHADD: 6030 case MVE_VHADD_T1: 6031 case MVE_VHSUB_T1: 6032 if (arm_decode_field (given, 20, 21) == 3) 6033 { 6034 *undefined_code = UNDEF_SIZE_3; 6035 return true; 6036 } 6037 else 6038 return false; 6039 6040 case MVE_VLDRB_T1: 6041 if (arm_decode_field (given, 7, 8) == 3) 6042 { 6043 *undefined_code = UNDEF_SIZE_3; 6044 return true; 6045 } 6046 else 6047 return false; 6048 6049 case MVE_VLDRH_T2: 6050 if (arm_decode_field (given, 7, 8) <= 1) 6051 { 6052 *undefined_code = UNDEF_SIZE_LE_1; 6053 return true; 6054 } 6055 else 6056 return false; 6057 6058 case MVE_VSTRB_T1: 6059 if ((arm_decode_field (given, 7, 8) == 0)) 6060 { 6061 *undefined_code = UNDEF_SIZE_0; 6062 return true; 6063 } 6064 else 6065 return false; 6066 6067 case MVE_VSTRH_T2: 6068 if ((arm_decode_field (given, 7, 8) <= 1)) 6069 { 6070 *undefined_code = UNDEF_SIZE_LE_1; 6071 return true; 6072 } 6073 else 6074 return false; 6075 6076 case MVE_VLDRB_GATHER_T1: 6077 if (arm_decode_field (given, 7, 8) == 3) 6078 { 6079 *undefined_code = UNDEF_SIZE_3; 6080 return true; 6081 } 6082 else if ((arm_decode_field (given, 28, 28) == 0) 6083 && (arm_decode_field (given, 7, 8) == 0)) 6084 { 6085 *undefined_code = UNDEF_NOT_UNS_SIZE_0; 6086 return true; 6087 } 6088 else 6089 return false; 6090 6091 case MVE_VLDRH_GATHER_T2: 6092 if (arm_decode_field (given, 7, 8) == 3) 6093 { 6094 *undefined_code = UNDEF_SIZE_3; 6095 return true; 6096 } 6097 else if ((arm_decode_field (given, 28, 28) == 0) 6098 && (arm_decode_field (given, 7, 8) == 1)) 6099 { 6100 *undefined_code = UNDEF_NOT_UNS_SIZE_1; 6101 return true; 6102 } 6103 else if (arm_decode_field (given, 7, 8) == 0) 6104 { 6105 *undefined_code = UNDEF_SIZE_0; 6106 return true; 6107 } 6108 else 6109 return false; 6110 6111 case MVE_VLDRW_GATHER_T3: 6112 if (arm_decode_field (given, 7, 8) != 2) 6113 { 6114 *undefined_code = UNDEF_SIZE_NOT_2; 6115 return true; 6116 } 6117 else if (arm_decode_field (given, 28, 28) == 0) 6118 { 6119 *undefined_code = UNDEF_NOT_UNSIGNED; 6120 return true; 6121 } 6122 else 6123 return false; 6124 6125 case MVE_VLDRD_GATHER_T4: 6126 if (arm_decode_field (given, 7, 8) != 3) 6127 { 6128 *undefined_code = UNDEF_SIZE_NOT_3; 6129 return true; 6130 } 6131 else if (arm_decode_field (given, 28, 28) == 0) 6132 { 6133 *undefined_code = UNDEF_NOT_UNSIGNED; 6134 return true; 6135 } 6136 else 6137 return false; 6138 6139 case MVE_VSTRB_SCATTER_T1: 6140 if (arm_decode_field (given, 7, 8) == 3) 6141 { 6142 *undefined_code = UNDEF_SIZE_3; 6143 return true; 6144 } 6145 else 6146 return false; 6147 6148 case MVE_VSTRH_SCATTER_T2: 6149 { 6150 unsigned long size = arm_decode_field (given, 7, 8); 6151 if (size == 3) 6152 { 6153 *undefined_code = UNDEF_SIZE_3; 6154 return true; 6155 } 6156 else if (size == 0) 6157 { 6158 *undefined_code = UNDEF_SIZE_0; 6159 return true; 6160 } 6161 else 6162 return false; 6163 } 6164 6165 case MVE_VSTRW_SCATTER_T3: 6166 if (arm_decode_field (given, 7, 8) != 2) 6167 { 6168 *undefined_code = UNDEF_SIZE_NOT_2; 6169 return true; 6170 } 6171 else 6172 return false; 6173 6174 case MVE_VSTRD_SCATTER_T4: 6175 if (arm_decode_field (given, 7, 8) != 3) 6176 { 6177 *undefined_code = UNDEF_SIZE_NOT_3; 6178 return true; 6179 } 6180 else 6181 return false; 6182 6183 case MVE_VCVT_FP_FIX_VEC: 6184 { 6185 unsigned long imm6 = arm_decode_field (given, 16, 21); 6186 if ((imm6 & 0x20) == 0) 6187 { 6188 *undefined_code = UNDEF_VCVT_IMM6; 6189 return true; 6190 } 6191 6192 if ((arm_decode_field (given, 9, 9) == 0) 6193 && ((imm6 & 0x30) == 0x20)) 6194 { 6195 *undefined_code = UNDEF_VCVT_FSI_IMM6; 6196 return true; 6197 } 6198 6199 return false; 6200 } 6201 6202 case MVE_VNEG_FP: 6203 case MVE_VABS_FP: 6204 case MVE_VCVT_BETWEEN_FP_INT: 6205 case MVE_VCVT_FROM_FP_TO_INT: 6206 { 6207 unsigned long size = arm_decode_field (given, 18, 19); 6208 if (size == 0) 6209 { 6210 *undefined_code = UNDEF_SIZE_0; 6211 return true; 6212 } 6213 else if (size == 3) 6214 { 6215 *undefined_code = UNDEF_SIZE_3; 6216 return true; 6217 } 6218 else 6219 return false; 6220 } 6221 6222 case MVE_VMOV_VEC_LANE_TO_GP: 6223 { 6224 unsigned long op1 = arm_decode_field (given, 21, 22); 6225 unsigned long op2 = arm_decode_field (given, 5, 6); 6226 unsigned long u = arm_decode_field (given, 23, 23); 6227 6228 if ((op2 == 0) && (u == 1)) 6229 { 6230 if ((op1 == 0) || (op1 == 1)) 6231 { 6232 *undefined_code = UNDEF_BAD_U_OP1_OP2; 6233 return true; 6234 } 6235 else 6236 return false; 6237 } 6238 else if (op2 == 2) 6239 { 6240 if ((op1 == 0) || (op1 == 1)) 6241 { 6242 *undefined_code = UNDEF_BAD_OP1_OP2; 6243 return true; 6244 } 6245 else 6246 return false; 6247 } 6248 6249 return false; 6250 } 6251 6252 case MVE_VMOV_GP_TO_VEC_LANE: 6253 if (arm_decode_field (given, 5, 6) == 2) 6254 { 6255 unsigned long op1 = arm_decode_field (given, 21, 22); 6256 if ((op1 == 0) || (op1 == 1)) 6257 { 6258 *undefined_code = UNDEF_BAD_OP1_OP2; 6259 return true; 6260 } 6261 else 6262 return false; 6263 } 6264 else 6265 return false; 6266 6267 case MVE_VMOV_VEC_TO_VEC: 6268 if ((arm_decode_field (given, 5, 5) == 1) 6269 || (arm_decode_field (given, 22, 22) == 1)) 6270 return true; 6271 return false; 6272 6273 case MVE_VMOV_IMM_TO_VEC: 6274 if (arm_decode_field (given, 5, 5) == 0) 6275 { 6276 unsigned long cmode = arm_decode_field (given, 8, 11); 6277 6278 if (((cmode & 9) == 1) || ((cmode & 5) == 1)) 6279 { 6280 *undefined_code = UNDEF_OP_0_BAD_CMODE; 6281 return true; 6282 } 6283 else 6284 return false; 6285 } 6286 else 6287 return false; 6288 6289 case MVE_VSHLL_T2: 6290 case MVE_VMOVN: 6291 if (arm_decode_field (given, 18, 19) == 2) 6292 { 6293 *undefined_code = UNDEF_SIZE_2; 6294 return true; 6295 } 6296 else 6297 return false; 6298 6299 case MVE_VRMLALDAVH: 6300 case MVE_VMLADAV_T1: 6301 case MVE_VMLADAV_T2: 6302 case MVE_VMLALDAV: 6303 if ((arm_decode_field (given, 28, 28) == 1) 6304 && (arm_decode_field (given, 12, 12) == 1)) 6305 { 6306 *undefined_code = UNDEF_XCHG_UNS; 6307 return true; 6308 } 6309 else 6310 return false; 6311 6312 case MVE_VQSHRN: 6313 case MVE_VQSHRUN: 6314 case MVE_VSHLL_T1: 6315 case MVE_VSHRN: 6316 { 6317 unsigned long sz = arm_decode_field (given, 19, 20); 6318 if (sz == 1) 6319 return false; 6320 else if ((sz & 2) == 2) 6321 return false; 6322 else 6323 { 6324 *undefined_code = UNDEF_SIZE; 6325 return true; 6326 } 6327 } 6328 break; 6329 6330 case MVE_VQSHL_T2: 6331 case MVE_VQSHLU_T3: 6332 case MVE_VRSHR: 6333 case MVE_VSHL_T1: 6334 case MVE_VSHR: 6335 case MVE_VSLI: 6336 case MVE_VSRI: 6337 { 6338 unsigned long sz = arm_decode_field (given, 19, 21); 6339 if ((sz & 7) == 1) 6340 return false; 6341 else if ((sz & 6) == 2) 6342 return false; 6343 else if ((sz & 4) == 4) 6344 return false; 6345 else 6346 { 6347 *undefined_code = UNDEF_SIZE; 6348 return true; 6349 } 6350 } 6351 6352 case MVE_VQRSHRN: 6353 case MVE_VQRSHRUN: 6354 if (arm_decode_field (given, 19, 20) == 0) 6355 { 6356 *undefined_code = UNDEF_SIZE_0; 6357 return true; 6358 } 6359 else 6360 return false; 6361 6362 case MVE_VABS_VEC: 6363 if (arm_decode_field (given, 18, 19) == 3) 6364 { 6365 *undefined_code = UNDEF_SIZE_3; 6366 return true; 6367 } 6368 else 6369 return false; 6370 6371 case MVE_VQNEG: 6372 case MVE_VQABS: 6373 case MVE_VNEG_VEC: 6374 case MVE_VCLS: 6375 case MVE_VCLZ: 6376 if (arm_decode_field (given, 18, 19) == 3) 6377 { 6378 *undefined_code = UNDEF_SIZE_3; 6379 return true; 6380 } 6381 else 6382 return false; 6383 6384 case MVE_VREV16: 6385 if (arm_decode_field (given, 18, 19) == 0) 6386 return false; 6387 else 6388 { 6389 *undefined_code = UNDEF_SIZE_NOT_0; 6390 return true; 6391 } 6392 6393 case MVE_VREV32: 6394 { 6395 unsigned long size = arm_decode_field (given, 18, 19); 6396 if ((size & 2) == 2) 6397 { 6398 *undefined_code = UNDEF_SIZE_2; 6399 return true; 6400 } 6401 else 6402 return false; 6403 } 6404 6405 case MVE_VREV64: 6406 if (arm_decode_field (given, 18, 19) != 3) 6407 return false; 6408 else 6409 { 6410 *undefined_code = UNDEF_SIZE_3; 6411 return true; 6412 } 6413 6414 default: 6415 return false; 6416 } 6417} 6418 6419/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN. 6420 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to 6421 why this encoding is unpredictable. */ 6422 6423static bool 6424is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, 6425 enum mve_unpredictable *unpredictable_code) 6426{ 6427 *unpredictable_code = UNPRED_NONE; 6428 6429 switch (matched_insn) 6430 { 6431 case MVE_VCMP_FP_T2: 6432 case MVE_VPT_FP_T2: 6433 if ((arm_decode_field (given, 12, 12) == 0) 6434 && (arm_decode_field (given, 5, 5) == 1)) 6435 { 6436 *unpredictable_code = UNPRED_FCA_0_FCB_1; 6437 return true; 6438 } 6439 else 6440 return false; 6441 6442 case MVE_VPT_VEC_T4: 6443 case MVE_VPT_VEC_T5: 6444 case MVE_VPT_VEC_T6: 6445 case MVE_VCMP_VEC_T4: 6446 case MVE_VCMP_VEC_T5: 6447 case MVE_VCMP_VEC_T6: 6448 if (arm_decode_field (given, 0, 3) == 0xd) 6449 { 6450 *unpredictable_code = UNPRED_R13; 6451 return true; 6452 } 6453 else 6454 return false; 6455 6456 case MVE_VDUP: 6457 { 6458 unsigned long gpr = arm_decode_field (given, 12, 15); 6459 if (gpr == 0xd) 6460 { 6461 *unpredictable_code = UNPRED_R13; 6462 return true; 6463 } 6464 else if (gpr == 0xf) 6465 { 6466 *unpredictable_code = UNPRED_R15; 6467 return true; 6468 } 6469 6470 return false; 6471 } 6472 6473 case MVE_VQADD_T2: 6474 case MVE_VQSUB_T2: 6475 case MVE_VMUL_FP_T2: 6476 case MVE_VMUL_VEC_T2: 6477 case MVE_VMLA: 6478 case MVE_VBRSR: 6479 case MVE_VADD_FP_T2: 6480 case MVE_VSUB_FP_T2: 6481 case MVE_VADD_VEC_T2: 6482 case MVE_VSUB_VEC_T2: 6483 case MVE_VQRSHL_T2: 6484 case MVE_VQSHL_T1: 6485 case MVE_VRSHL_T2: 6486 case MVE_VSHL_T2: 6487 case MVE_VSHLC: 6488 case MVE_VQDMLAH: 6489 case MVE_VQRDMLAH: 6490 case MVE_VQDMLASH: 6491 case MVE_VQRDMLASH: 6492 case MVE_VQDMULH_T3: 6493 case MVE_VQRDMULH_T4: 6494 case MVE_VMLAS: 6495 case MVE_VFMA_FP_SCALAR: 6496 case MVE_VFMAS_FP_SCALAR: 6497 case MVE_VHADD_T2: 6498 case MVE_VHSUB_T2: 6499 { 6500 unsigned long gpr = arm_decode_field (given, 0, 3); 6501 if (gpr == 0xd) 6502 { 6503 *unpredictable_code = UNPRED_R13; 6504 return true; 6505 } 6506 else if (gpr == 0xf) 6507 { 6508 *unpredictable_code = UNPRED_R15; 6509 return true; 6510 } 6511 6512 return false; 6513 } 6514 6515 case MVE_VLD2: 6516 case MVE_VST2: 6517 { 6518 unsigned long rn = arm_decode_field (given, 16, 19); 6519 6520 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6521 { 6522 *unpredictable_code = UNPRED_R13_AND_WB; 6523 return true; 6524 } 6525 6526 if (rn == 0xf) 6527 { 6528 *unpredictable_code = UNPRED_R15; 6529 return true; 6530 } 6531 6532 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6) 6533 { 6534 *unpredictable_code = UNPRED_Q_GT_6; 6535 return true; 6536 } 6537 else 6538 return false; 6539 } 6540 6541 case MVE_VLD4: 6542 case MVE_VST4: 6543 { 6544 unsigned long rn = arm_decode_field (given, 16, 19); 6545 6546 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6547 { 6548 *unpredictable_code = UNPRED_R13_AND_WB; 6549 return true; 6550 } 6551 6552 if (rn == 0xf) 6553 { 6554 *unpredictable_code = UNPRED_R15; 6555 return true; 6556 } 6557 6558 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4) 6559 { 6560 *unpredictable_code = UNPRED_Q_GT_4; 6561 return true; 6562 } 6563 else 6564 return false; 6565 } 6566 6567 case MVE_VLDRB_T5: 6568 case MVE_VLDRH_T6: 6569 case MVE_VLDRW_T7: 6570 case MVE_VSTRB_T5: 6571 case MVE_VSTRH_T6: 6572 case MVE_VSTRW_T7: 6573 { 6574 unsigned long rn = arm_decode_field (given, 16, 19); 6575 6576 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) 6577 { 6578 *unpredictable_code = UNPRED_R13_AND_WB; 6579 return true; 6580 } 6581 else if (rn == 0xf) 6582 { 6583 *unpredictable_code = UNPRED_R15; 6584 return true; 6585 } 6586 else 6587 return false; 6588 } 6589 6590 case MVE_VLDRB_GATHER_T1: 6591 if (arm_decode_field (given, 0, 0) == 1) 6592 { 6593 *unpredictable_code = UNPRED_OS; 6594 return true; 6595 } 6596 6597 /* fall through. */ 6598 /* To handle common code with T2-T4 variants. */ 6599 case MVE_VLDRH_GATHER_T2: 6600 case MVE_VLDRW_GATHER_T3: 6601 case MVE_VLDRD_GATHER_T4: 6602 { 6603 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6604 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6605 6606 if (qd == qm) 6607 { 6608 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6609 return true; 6610 } 6611 6612 if (arm_decode_field (given, 16, 19) == 0xf) 6613 { 6614 *unpredictable_code = UNPRED_R15; 6615 return true; 6616 } 6617 6618 return false; 6619 } 6620 6621 case MVE_VLDRW_GATHER_T5: 6622 case MVE_VLDRD_GATHER_T6: 6623 { 6624 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6625 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7); 6626 6627 if (qd == qm) 6628 { 6629 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6630 return true; 6631 } 6632 else 6633 return false; 6634 } 6635 6636 case MVE_VSTRB_SCATTER_T1: 6637 if (arm_decode_field (given, 16, 19) == 0xf) 6638 { 6639 *unpredictable_code = UNPRED_R15; 6640 return true; 6641 } 6642 else if (arm_decode_field (given, 0, 0) == 1) 6643 { 6644 *unpredictable_code = UNPRED_OS; 6645 return true; 6646 } 6647 else 6648 return false; 6649 6650 case MVE_VSTRH_SCATTER_T2: 6651 case MVE_VSTRW_SCATTER_T3: 6652 case MVE_VSTRD_SCATTER_T4: 6653 if (arm_decode_field (given, 16, 19) == 0xf) 6654 { 6655 *unpredictable_code = UNPRED_R15; 6656 return true; 6657 } 6658 else 6659 return false; 6660 6661 case MVE_VMOV2_VEC_LANE_TO_GP: 6662 case MVE_VMOV2_GP_TO_VEC_LANE: 6663 case MVE_VCVT_BETWEEN_FP_INT: 6664 case MVE_VCVT_FROM_FP_TO_INT: 6665 { 6666 unsigned long rt = arm_decode_field (given, 0, 3); 6667 unsigned long rt2 = arm_decode_field (given, 16, 19); 6668 6669 if ((rt == 0xd) || (rt2 == 0xd)) 6670 { 6671 *unpredictable_code = UNPRED_R13; 6672 return true; 6673 } 6674 else if ((rt == 0xf) || (rt2 == 0xf)) 6675 { 6676 *unpredictable_code = UNPRED_R15; 6677 return true; 6678 } 6679 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE) 6680 { 6681 *unpredictable_code = UNPRED_GP_REGS_EQUAL; 6682 return true; 6683 } 6684 6685 return false; 6686 } 6687 6688 case MVE_VMAXV: 6689 case MVE_VMAXAV: 6690 case MVE_VMAXNMV_FP: 6691 case MVE_VMAXNMAV_FP: 6692 case MVE_VMINNMV_FP: 6693 case MVE_VMINNMAV_FP: 6694 case MVE_VMINV: 6695 case MVE_VMINAV: 6696 case MVE_VABAV: 6697 case MVE_VMOV_HFP_TO_GP: 6698 case MVE_VMOV_GP_TO_VEC_LANE: 6699 case MVE_VMOV_VEC_LANE_TO_GP: 6700 { 6701 unsigned long rda = arm_decode_field (given, 12, 15); 6702 if (rda == 0xd) 6703 { 6704 *unpredictable_code = UNPRED_R13; 6705 return true; 6706 } 6707 else if (rda == 0xf) 6708 { 6709 *unpredictable_code = UNPRED_R15; 6710 return true; 6711 } 6712 6713 return false; 6714 } 6715 6716 case MVE_VMULL_INT: 6717 { 6718 unsigned long Qd; 6719 unsigned long Qm; 6720 unsigned long Qn; 6721 6722 if (arm_decode_field (given, 20, 21) == 2) 6723 { 6724 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6725 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6726 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6727 6728 if ((Qd == Qn) || (Qd == Qm)) 6729 { 6730 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6731 return true; 6732 } 6733 else 6734 return false; 6735 } 6736 else 6737 return false; 6738 } 6739 6740 case MVE_VCMUL_FP: 6741 case MVE_VQDMULL_T1: 6742 { 6743 unsigned long Qd; 6744 unsigned long Qm; 6745 unsigned long Qn; 6746 6747 if (arm_decode_field (given, 28, 28) == 1) 6748 { 6749 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6750 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6751 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6752 6753 if ((Qd == Qn) || (Qd == Qm)) 6754 { 6755 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6756 return true; 6757 } 6758 else 6759 return false; 6760 } 6761 else 6762 return false; 6763 } 6764 6765 case MVE_VQDMULL_T2: 6766 { 6767 unsigned long gpr = arm_decode_field (given, 0, 3); 6768 if (gpr == 0xd) 6769 { 6770 *unpredictable_code = UNPRED_R13; 6771 return true; 6772 } 6773 else if (gpr == 0xf) 6774 { 6775 *unpredictable_code = UNPRED_R15; 6776 return true; 6777 } 6778 6779 if (arm_decode_field (given, 28, 28) == 1) 6780 { 6781 unsigned long Qd 6782 = arm_decode_field_multiple (given, 13, 15, 22, 22); 6783 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6784 6785 if (Qd == Qn) 6786 { 6787 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6788 return true; 6789 } 6790 else 6791 return false; 6792 } 6793 6794 return false; 6795 } 6796 6797 case MVE_VMLSLDAV: 6798 case MVE_VRMLSLDAVH: 6799 case MVE_VMLALDAV: 6800 case MVE_VADDLV: 6801 if (arm_decode_field (given, 20, 22) == 6) 6802 { 6803 *unpredictable_code = UNPRED_R13; 6804 return true; 6805 } 6806 else 6807 return false; 6808 6809 case MVE_VDWDUP: 6810 case MVE_VIWDUP: 6811 if (arm_decode_field (given, 1, 3) == 6) 6812 { 6813 *unpredictable_code = UNPRED_R13; 6814 return true; 6815 } 6816 else 6817 return false; 6818 6819 case MVE_VCADD_VEC: 6820 case MVE_VHCADD: 6821 { 6822 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6823 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6824 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2) 6825 { 6826 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; 6827 return true; 6828 } 6829 else 6830 return false; 6831 } 6832 6833 case MVE_VCADD_FP: 6834 { 6835 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6836 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6837 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1) 6838 { 6839 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6840 return true; 6841 } 6842 else 6843 return false; 6844 } 6845 6846 case MVE_VCMLA_FP: 6847 { 6848 unsigned long Qda; 6849 unsigned long Qm; 6850 unsigned long Qn; 6851 6852 if (arm_decode_field (given, 20, 20) == 1) 6853 { 6854 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22); 6855 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); 6856 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); 6857 6858 if ((Qda == Qn) || (Qda == Qm)) 6859 { 6860 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; 6861 return true; 6862 } 6863 else 6864 return false; 6865 } 6866 else 6867 return false; 6868 6869 } 6870 6871 case MVE_VCTP: 6872 if (arm_decode_field (given, 16, 19) == 0xd) 6873 { 6874 *unpredictable_code = UNPRED_R13; 6875 return true; 6876 } 6877 else 6878 return false; 6879 6880 case MVE_VREV64: 6881 { 6882 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); 6883 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6); 6884 6885 if (qd == qm) 6886 { 6887 *unpredictable_code = UNPRED_Q_REGS_EQUAL; 6888 return true; 6889 } 6890 else 6891 return false; 6892 } 6893 6894 case MVE_LSLL: 6895 case MVE_LSLLI: 6896 case MVE_LSRL: 6897 case MVE_ASRL: 6898 case MVE_ASRLI: 6899 case MVE_UQSHLL: 6900 case MVE_UQRSHLL: 6901 case MVE_URSHRL: 6902 case MVE_SRSHRL: 6903 case MVE_SQSHLL: 6904 case MVE_SQRSHRL: 6905 { 6906 unsigned long gpr = arm_decode_field (given, 9, 11); 6907 gpr = ((gpr << 1) | 1); 6908 if (gpr == 0xd) 6909 { 6910 *unpredictable_code = UNPRED_R13; 6911 return true; 6912 } 6913 else if (gpr == 0xf) 6914 { 6915 *unpredictable_code = UNPRED_R15; 6916 return true; 6917 } 6918 6919 return false; 6920 } 6921 6922 default: 6923 return false; 6924 } 6925} 6926 6927static void 6928print_mve_vmov_index (struct disassemble_info *info, unsigned long given) 6929{ 6930 unsigned long op1 = arm_decode_field (given, 21, 22); 6931 unsigned long op2 = arm_decode_field (given, 5, 6); 6932 unsigned long h = arm_decode_field (given, 16, 16); 6933 unsigned long index_operand, esize, targetBeat, idx; 6934 void *stream = info->stream; 6935 fprintf_ftype func = info->fprintf_func; 6936 6937 if ((op1 & 0x2) == 0x2) 6938 { 6939 index_operand = op2; 6940 esize = 8; 6941 } 6942 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) 6943 { 6944 index_operand = op2 >> 1; 6945 esize = 16; 6946 } 6947 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) 6948 { 6949 index_operand = 0; 6950 esize = 32; 6951 } 6952 else 6953 { 6954 func (stream, "<undefined index>"); 6955 return; 6956 } 6957 6958 targetBeat = (op1 & 0x1) | (h << 1); 6959 idx = index_operand + targetBeat * (32/esize); 6960 6961 func (stream, "%lu", idx); 6962} 6963 6964/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits 6965 in length and integer of floating-point type. */ 6966static void 6967print_simd_imm8 (struct disassemble_info *info, unsigned long given, 6968 unsigned int ibit_loc, const struct mopcode32 *insn) 6969{ 6970 int bits = 0; 6971 int cmode = (given >> 8) & 0xf; 6972 int op = (given >> 5) & 0x1; 6973 unsigned long value = 0, hival = 0; 6974 unsigned shift; 6975 int size = 0; 6976 int isfloat = 0; 6977 void *stream = info->stream; 6978 fprintf_ftype func = info->fprintf_func; 6979 6980 /* On Neon the 'i' bit is at bit 24, on mve it is 6981 at bit 28. */ 6982 bits |= ((given >> ibit_loc) & 1) << 7; 6983 bits |= ((given >> 16) & 7) << 4; 6984 bits |= ((given >> 0) & 15) << 0; 6985 6986 if (cmode < 8) 6987 { 6988 shift = (cmode >> 1) & 3; 6989 value = (unsigned long) bits << (8 * shift); 6990 size = 32; 6991 } 6992 else if (cmode < 12) 6993 { 6994 shift = (cmode >> 1) & 1; 6995 value = (unsigned long) bits << (8 * shift); 6996 size = 16; 6997 } 6998 else if (cmode < 14) 6999 { 7000 shift = (cmode & 1) + 1; 7001 value = (unsigned long) bits << (8 * shift); 7002 value |= (1ul << (8 * shift)) - 1; 7003 size = 32; 7004 } 7005 else if (cmode == 14) 7006 { 7007 if (op) 7008 { 7009 /* Bit replication into bytes. */ 7010 int ix; 7011 unsigned long mask; 7012 7013 value = 0; 7014 hival = 0; 7015 for (ix = 7; ix >= 0; ix--) 7016 { 7017 mask = ((bits >> ix) & 1) ? 0xff : 0; 7018 if (ix <= 3) 7019 value = (value << 8) | mask; 7020 else 7021 hival = (hival << 8) | mask; 7022 } 7023 size = 64; 7024 } 7025 else 7026 { 7027 /* Byte replication. */ 7028 value = (unsigned long) bits; 7029 size = 8; 7030 } 7031 } 7032 else if (!op) 7033 { 7034 /* Floating point encoding. */ 7035 int tmp; 7036 7037 value = (unsigned long) (bits & 0x7f) << 19; 7038 value |= (unsigned long) (bits & 0x80) << 24; 7039 tmp = bits & 0x40 ? 0x3c : 0x40; 7040 value |= (unsigned long) tmp << 24; 7041 size = 32; 7042 isfloat = 1; 7043 } 7044 else 7045 { 7046 func (stream, "<illegal constant %.8x:%x:%x>", 7047 bits, cmode, op); 7048 size = 32; 7049 return; 7050 } 7051 7052 /* printU determines whether the immediate value should be printed as 7053 unsigned. */ 7054 unsigned printU = 0; 7055 switch (insn->mve_op) 7056 { 7057 default: 7058 break; 7059 /* We want this for instructions that don't have a 'signed' type. */ 7060 case MVE_VBIC_IMM: 7061 case MVE_VORR_IMM: 7062 case MVE_VMVN_IMM: 7063 case MVE_VMOV_IMM_TO_VEC: 7064 printU = 1; 7065 break; 7066 } 7067 switch (size) 7068 { 7069 case 8: 7070 func (stream, "#%ld\t; 0x%.2lx", value, value); 7071 break; 7072 7073 case 16: 7074 func (stream, 7075 printU 7076 ? "#%lu\t; 0x%.4lx" 7077 : "#%ld\t; 0x%.4lx", value, value); 7078 break; 7079 7080 case 32: 7081 if (isfloat) 7082 { 7083 unsigned char valbytes[4]; 7084 double fvalue; 7085 7086 /* Do this a byte at a time so we don't have to 7087 worry about the host's endianness. */ 7088 valbytes[0] = value & 0xff; 7089 valbytes[1] = (value >> 8) & 0xff; 7090 valbytes[2] = (value >> 16) & 0xff; 7091 valbytes[3] = (value >> 24) & 0xff; 7092 7093 floatformat_to_double 7094 (& floatformat_ieee_single_little, valbytes, 7095 & fvalue); 7096 7097 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 7098 value); 7099 } 7100 else 7101 func (stream, 7102 printU 7103 ? "#%lu\t; 0x%.8lx" 7104 : "#%ld\t; 0x%.8lx", 7105 (long) (((value & 0x80000000L) != 0) 7106 && !printU 7107 ? value | ~0xffffffffL : value), 7108 value); 7109 break; 7110 7111 case 64: 7112 func (stream, "#0x%.8lx%.8lx", hival, value); 7113 break; 7114 7115 default: 7116 abort (); 7117 } 7118 7119} 7120 7121static void 7122print_mve_undefined (struct disassemble_info *info, 7123 enum mve_undefined undefined_code) 7124{ 7125 void *stream = info->stream; 7126 fprintf_ftype func = info->fprintf_func; 7127 7128 func (stream, "\t\tundefined instruction: "); 7129 7130 switch (undefined_code) 7131 { 7132 case UNDEF_SIZE: 7133 func (stream, "illegal size"); 7134 break; 7135 7136 case UNDEF_SIZE_0: 7137 func (stream, "size equals zero"); 7138 break; 7139 7140 case UNDEF_SIZE_2: 7141 func (stream, "size equals two"); 7142 break; 7143 7144 case UNDEF_SIZE_3: 7145 func (stream, "size equals three"); 7146 break; 7147 7148 case UNDEF_SIZE_LE_1: 7149 func (stream, "size <= 1"); 7150 break; 7151 7152 case UNDEF_SIZE_NOT_0: 7153 func (stream, "size not equal to 0"); 7154 break; 7155 7156 case UNDEF_SIZE_NOT_2: 7157 func (stream, "size not equal to 2"); 7158 break; 7159 7160 case UNDEF_SIZE_NOT_3: 7161 func (stream, "size not equal to 3"); 7162 break; 7163 7164 case UNDEF_NOT_UNS_SIZE_0: 7165 func (stream, "not unsigned and size = zero"); 7166 break; 7167 7168 case UNDEF_NOT_UNS_SIZE_1: 7169 func (stream, "not unsigned and size = one"); 7170 break; 7171 7172 case UNDEF_NOT_UNSIGNED: 7173 func (stream, "not unsigned"); 7174 break; 7175 7176 case UNDEF_VCVT_IMM6: 7177 func (stream, "invalid imm6"); 7178 break; 7179 7180 case UNDEF_VCVT_FSI_IMM6: 7181 func (stream, "fsi = 0 and invalid imm6"); 7182 break; 7183 7184 case UNDEF_BAD_OP1_OP2: 7185 func (stream, "bad size with op2 = 2 and op1 = 0 or 1"); 7186 break; 7187 7188 case UNDEF_BAD_U_OP1_OP2: 7189 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1"); 7190 break; 7191 7192 case UNDEF_OP_0_BAD_CMODE: 7193 func (stream, "op field equal 0 and bad cmode"); 7194 break; 7195 7196 case UNDEF_XCHG_UNS: 7197 func (stream, "exchange and unsigned together"); 7198 break; 7199 7200 case UNDEF_NONE: 7201 break; 7202 } 7203 7204} 7205 7206static void 7207print_mve_unpredictable (struct disassemble_info *info, 7208 enum mve_unpredictable unpredict_code) 7209{ 7210 void *stream = info->stream; 7211 fprintf_ftype func = info->fprintf_func; 7212 7213 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION); 7214 7215 switch (unpredict_code) 7216 { 7217 case UNPRED_IT_BLOCK: 7218 func (stream, "mve instruction in it block"); 7219 break; 7220 7221 case UNPRED_FCA_0_FCB_1: 7222 func (stream, "condition bits, fca = 0 and fcb = 1"); 7223 break; 7224 7225 case UNPRED_R13: 7226 func (stream, "use of r13 (sp)"); 7227 break; 7228 7229 case UNPRED_R15: 7230 func (stream, "use of r15 (pc)"); 7231 break; 7232 7233 case UNPRED_Q_GT_4: 7234 func (stream, "start register block > r4"); 7235 break; 7236 7237 case UNPRED_Q_GT_6: 7238 func (stream, "start register block > r6"); 7239 break; 7240 7241 case UNPRED_R13_AND_WB: 7242 func (stream, "use of r13 and write back"); 7243 break; 7244 7245 case UNPRED_Q_REGS_EQUAL: 7246 func (stream, 7247 "same vector register used for destination and other operand"); 7248 break; 7249 7250 case UNPRED_OS: 7251 func (stream, "use of offset scaled"); 7252 break; 7253 7254 case UNPRED_GP_REGS_EQUAL: 7255 func (stream, "same general-purpose register used for both operands"); 7256 break; 7257 7258 case UNPRED_Q_REGS_EQ_AND_SIZE_1: 7259 func (stream, "use of identical q registers and size = 1"); 7260 break; 7261 7262 case UNPRED_Q_REGS_EQ_AND_SIZE_2: 7263 func (stream, "use of identical q registers and size = 1"); 7264 break; 7265 7266 case UNPRED_NONE: 7267 break; 7268 } 7269} 7270 7271/* Print register block operand for mve vld2/vld4/vst2/vld4. */ 7272 7273static void 7274print_mve_register_blocks (struct disassemble_info *info, 7275 unsigned long given, 7276 enum mve_instructions matched_insn) 7277{ 7278 void *stream = info->stream; 7279 fprintf_ftype func = info->fprintf_func; 7280 7281 unsigned long q_reg_start = arm_decode_field_multiple (given, 7282 13, 15, 7283 22, 22); 7284 switch (matched_insn) 7285 { 7286 case MVE_VLD2: 7287 case MVE_VST2: 7288 if (q_reg_start <= 6) 7289 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1); 7290 else 7291 func (stream, "<illegal reg q%ld>", q_reg_start); 7292 break; 7293 7294 case MVE_VLD4: 7295 case MVE_VST4: 7296 if (q_reg_start <= 4) 7297 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start, 7298 q_reg_start + 1, q_reg_start + 2, 7299 q_reg_start + 3); 7300 else 7301 func (stream, "<illegal reg q%ld>", q_reg_start); 7302 break; 7303 7304 default: 7305 break; 7306 } 7307} 7308 7309static void 7310print_mve_rounding_mode (struct disassemble_info *info, 7311 unsigned long given, 7312 enum mve_instructions matched_insn) 7313{ 7314 void *stream = info->stream; 7315 fprintf_ftype func = info->fprintf_func; 7316 7317 switch (matched_insn) 7318 { 7319 case MVE_VCVT_FROM_FP_TO_INT: 7320 { 7321 switch (arm_decode_field (given, 8, 9)) 7322 { 7323 case 0: 7324 func (stream, "a"); 7325 break; 7326 7327 case 1: 7328 func (stream, "n"); 7329 break; 7330 7331 case 2: 7332 func (stream, "p"); 7333 break; 7334 7335 case 3: 7336 func (stream, "m"); 7337 break; 7338 7339 default: 7340 break; 7341 } 7342 } 7343 break; 7344 7345 case MVE_VRINT_FP: 7346 { 7347 switch (arm_decode_field (given, 7, 9)) 7348 { 7349 case 0: 7350 func (stream, "n"); 7351 break; 7352 7353 case 1: 7354 func (stream, "x"); 7355 break; 7356 7357 case 2: 7358 func (stream, "a"); 7359 break; 7360 7361 case 3: 7362 func (stream, "z"); 7363 break; 7364 7365 case 5: 7366 func (stream, "m"); 7367 break; 7368 7369 case 7: 7370 func (stream, "p"); 7371 7372 case 4: 7373 case 6: 7374 default: 7375 break; 7376 } 7377 } 7378 break; 7379 7380 default: 7381 break; 7382 } 7383} 7384 7385static void 7386print_mve_vcvt_size (struct disassemble_info *info, 7387 unsigned long given, 7388 enum mve_instructions matched_insn) 7389{ 7390 unsigned long mode = 0; 7391 void *stream = info->stream; 7392 fprintf_ftype func = info->fprintf_func; 7393 7394 switch (matched_insn) 7395 { 7396 case MVE_VCVT_FP_FIX_VEC: 7397 { 7398 mode = (((given & 0x200) >> 7) 7399 | ((given & 0x10000000) >> 27) 7400 | ((given & 0x100) >> 8)); 7401 7402 switch (mode) 7403 { 7404 case 0: 7405 func (stream, "f16.s16"); 7406 break; 7407 7408 case 1: 7409 func (stream, "s16.f16"); 7410 break; 7411 7412 case 2: 7413 func (stream, "f16.u16"); 7414 break; 7415 7416 case 3: 7417 func (stream, "u16.f16"); 7418 break; 7419 7420 case 4: 7421 func (stream, "f32.s32"); 7422 break; 7423 7424 case 5: 7425 func (stream, "s32.f32"); 7426 break; 7427 7428 case 6: 7429 func (stream, "f32.u32"); 7430 break; 7431 7432 case 7: 7433 func (stream, "u32.f32"); 7434 break; 7435 7436 default: 7437 break; 7438 } 7439 break; 7440 } 7441 case MVE_VCVT_BETWEEN_FP_INT: 7442 { 7443 unsigned long size = arm_decode_field (given, 18, 19); 7444 unsigned long op = arm_decode_field (given, 7, 8); 7445 7446 if (size == 1) 7447 { 7448 switch (op) 7449 { 7450 case 0: 7451 func (stream, "f16.s16"); 7452 break; 7453 7454 case 1: 7455 func (stream, "f16.u16"); 7456 break; 7457 7458 case 2: 7459 func (stream, "s16.f16"); 7460 break; 7461 7462 case 3: 7463 func (stream, "u16.f16"); 7464 break; 7465 7466 default: 7467 break; 7468 } 7469 } 7470 else if (size == 2) 7471 { 7472 switch (op) 7473 { 7474 case 0: 7475 func (stream, "f32.s32"); 7476 break; 7477 7478 case 1: 7479 func (stream, "f32.u32"); 7480 break; 7481 7482 case 2: 7483 func (stream, "s32.f32"); 7484 break; 7485 7486 case 3: 7487 func (stream, "u32.f32"); 7488 break; 7489 } 7490 } 7491 } 7492 break; 7493 7494 case MVE_VCVT_FP_HALF_FP: 7495 { 7496 unsigned long op = arm_decode_field (given, 28, 28); 7497 if (op == 0) 7498 func (stream, "f16.f32"); 7499 else if (op == 1) 7500 func (stream, "f32.f16"); 7501 } 7502 break; 7503 7504 case MVE_VCVT_FROM_FP_TO_INT: 7505 { 7506 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19); 7507 7508 switch (size) 7509 { 7510 case 2: 7511 func (stream, "s16.f16"); 7512 break; 7513 7514 case 3: 7515 func (stream, "u16.f16"); 7516 break; 7517 7518 case 4: 7519 func (stream, "s32.f32"); 7520 break; 7521 7522 case 5: 7523 func (stream, "u32.f32"); 7524 break; 7525 7526 default: 7527 break; 7528 } 7529 } 7530 break; 7531 7532 default: 7533 break; 7534 } 7535} 7536 7537static void 7538print_mve_rotate (struct disassemble_info *info, unsigned long rot, 7539 unsigned long rot_width) 7540{ 7541 void *stream = info->stream; 7542 fprintf_ftype func = info->fprintf_func; 7543 7544 if (rot_width == 1) 7545 { 7546 switch (rot) 7547 { 7548 case 0: 7549 func (stream, "90"); 7550 break; 7551 case 1: 7552 func (stream, "270"); 7553 break; 7554 default: 7555 break; 7556 } 7557 } 7558 else if (rot_width == 2) 7559 { 7560 switch (rot) 7561 { 7562 case 0: 7563 func (stream, "0"); 7564 break; 7565 case 1: 7566 func (stream, "90"); 7567 break; 7568 case 2: 7569 func (stream, "180"); 7570 break; 7571 case 3: 7572 func (stream, "270"); 7573 break; 7574 default: 7575 break; 7576 } 7577 } 7578} 7579 7580static void 7581print_instruction_predicate (struct disassemble_info *info) 7582{ 7583 void *stream = info->stream; 7584 fprintf_ftype func = info->fprintf_func; 7585 7586 if (vpt_block_state.next_pred_state == PRED_THEN) 7587 func (stream, "t"); 7588 else if (vpt_block_state.next_pred_state == PRED_ELSE) 7589 func (stream, "e"); 7590} 7591 7592static void 7593print_mve_size (struct disassemble_info *info, 7594 unsigned long size, 7595 enum mve_instructions matched_insn) 7596{ 7597 void *stream = info->stream; 7598 fprintf_ftype func = info->fprintf_func; 7599 7600 switch (matched_insn) 7601 { 7602 case MVE_VABAV: 7603 case MVE_VABD_VEC: 7604 case MVE_VABS_FP: 7605 case MVE_VABS_VEC: 7606 case MVE_VADD_VEC_T1: 7607 case MVE_VADD_VEC_T2: 7608 case MVE_VADDV: 7609 case MVE_VBRSR: 7610 case MVE_VCADD_VEC: 7611 case MVE_VCLS: 7612 case MVE_VCLZ: 7613 case MVE_VCMP_VEC_T1: 7614 case MVE_VCMP_VEC_T2: 7615 case MVE_VCMP_VEC_T3: 7616 case MVE_VCMP_VEC_T4: 7617 case MVE_VCMP_VEC_T5: 7618 case MVE_VCMP_VEC_T6: 7619 case MVE_VCTP: 7620 case MVE_VDDUP: 7621 case MVE_VDWDUP: 7622 case MVE_VHADD_T1: 7623 case MVE_VHADD_T2: 7624 case MVE_VHCADD: 7625 case MVE_VHSUB_T1: 7626 case MVE_VHSUB_T2: 7627 case MVE_VIDUP: 7628 case MVE_VIWDUP: 7629 case MVE_VLD2: 7630 case MVE_VLD4: 7631 case MVE_VLDRB_GATHER_T1: 7632 case MVE_VLDRH_GATHER_T2: 7633 case MVE_VLDRW_GATHER_T3: 7634 case MVE_VLDRD_GATHER_T4: 7635 case MVE_VLDRB_T1: 7636 case MVE_VLDRH_T2: 7637 case MVE_VMAX: 7638 case MVE_VMAXA: 7639 case MVE_VMAXV: 7640 case MVE_VMAXAV: 7641 case MVE_VMIN: 7642 case MVE_VMINA: 7643 case MVE_VMINV: 7644 case MVE_VMINAV: 7645 case MVE_VMLA: 7646 case MVE_VMLAS: 7647 case MVE_VMUL_VEC_T1: 7648 case MVE_VMUL_VEC_T2: 7649 case MVE_VMULH: 7650 case MVE_VRMULH: 7651 case MVE_VMULL_INT: 7652 case MVE_VNEG_FP: 7653 case MVE_VNEG_VEC: 7654 case MVE_VPT_VEC_T1: 7655 case MVE_VPT_VEC_T2: 7656 case MVE_VPT_VEC_T3: 7657 case MVE_VPT_VEC_T4: 7658 case MVE_VPT_VEC_T5: 7659 case MVE_VPT_VEC_T6: 7660 case MVE_VQABS: 7661 case MVE_VQADD_T1: 7662 case MVE_VQADD_T2: 7663 case MVE_VQDMLADH: 7664 case MVE_VQRDMLADH: 7665 case MVE_VQDMLAH: 7666 case MVE_VQRDMLAH: 7667 case MVE_VQDMLASH: 7668 case MVE_VQRDMLASH: 7669 case MVE_VQDMLSDH: 7670 case MVE_VQRDMLSDH: 7671 case MVE_VQDMULH_T1: 7672 case MVE_VQRDMULH_T2: 7673 case MVE_VQDMULH_T3: 7674 case MVE_VQRDMULH_T4: 7675 case MVE_VQNEG: 7676 case MVE_VQRSHL_T1: 7677 case MVE_VQRSHL_T2: 7678 case MVE_VQSHL_T1: 7679 case MVE_VQSHL_T4: 7680 case MVE_VQSUB_T1: 7681 case MVE_VQSUB_T2: 7682 case MVE_VREV32: 7683 case MVE_VREV64: 7684 case MVE_VRHADD: 7685 case MVE_VRINT_FP: 7686 case MVE_VRSHL_T1: 7687 case MVE_VRSHL_T2: 7688 case MVE_VSHL_T2: 7689 case MVE_VSHL_T3: 7690 case MVE_VSHLL_T2: 7691 case MVE_VST2: 7692 case MVE_VST4: 7693 case MVE_VSTRB_SCATTER_T1: 7694 case MVE_VSTRH_SCATTER_T2: 7695 case MVE_VSTRW_SCATTER_T3: 7696 case MVE_VSTRB_T1: 7697 case MVE_VSTRH_T2: 7698 case MVE_VSUB_VEC_T1: 7699 case MVE_VSUB_VEC_T2: 7700 if (size <= 3) 7701 func (stream, "%s", mve_vec_sizename[size]); 7702 else 7703 func (stream, "<undef size>"); 7704 break; 7705 7706 case MVE_VABD_FP: 7707 case MVE_VADD_FP_T1: 7708 case MVE_VADD_FP_T2: 7709 case MVE_VSUB_FP_T1: 7710 case MVE_VSUB_FP_T2: 7711 case MVE_VCMP_FP_T1: 7712 case MVE_VCMP_FP_T2: 7713 case MVE_VFMA_FP_SCALAR: 7714 case MVE_VFMA_FP: 7715 case MVE_VFMS_FP: 7716 case MVE_VFMAS_FP_SCALAR: 7717 case MVE_VMAXNM_FP: 7718 case MVE_VMAXNMA_FP: 7719 case MVE_VMAXNMV_FP: 7720 case MVE_VMAXNMAV_FP: 7721 case MVE_VMINNM_FP: 7722 case MVE_VMINNMA_FP: 7723 case MVE_VMINNMV_FP: 7724 case MVE_VMINNMAV_FP: 7725 case MVE_VMUL_FP_T1: 7726 case MVE_VMUL_FP_T2: 7727 case MVE_VPT_FP_T1: 7728 case MVE_VPT_FP_T2: 7729 if (size == 0) 7730 func (stream, "32"); 7731 else if (size == 1) 7732 func (stream, "16"); 7733 break; 7734 7735 case MVE_VCADD_FP: 7736 case MVE_VCMLA_FP: 7737 case MVE_VCMUL_FP: 7738 case MVE_VMLADAV_T1: 7739 case MVE_VMLALDAV: 7740 case MVE_VMLSDAV_T1: 7741 case MVE_VMLSLDAV: 7742 case MVE_VMOVN: 7743 case MVE_VQDMULL_T1: 7744 case MVE_VQDMULL_T2: 7745 case MVE_VQMOVN: 7746 case MVE_VQMOVUN: 7747 if (size == 0) 7748 func (stream, "16"); 7749 else if (size == 1) 7750 func (stream, "32"); 7751 break; 7752 7753 case MVE_VMOVL: 7754 if (size == 1) 7755 func (stream, "8"); 7756 else if (size == 2) 7757 func (stream, "16"); 7758 break; 7759 7760 case MVE_VDUP: 7761 switch (size) 7762 { 7763 case 0: 7764 func (stream, "32"); 7765 break; 7766 case 1: 7767 func (stream, "16"); 7768 break; 7769 case 2: 7770 func (stream, "8"); 7771 break; 7772 default: 7773 break; 7774 } 7775 break; 7776 7777 case MVE_VMOV_GP_TO_VEC_LANE: 7778 case MVE_VMOV_VEC_LANE_TO_GP: 7779 switch (size) 7780 { 7781 case 0: case 4: 7782 func (stream, "32"); 7783 break; 7784 7785 case 1: case 3: 7786 case 5: case 7: 7787 func (stream, "16"); 7788 break; 7789 7790 case 8: case 9: case 10: case 11: 7791 case 12: case 13: case 14: case 15: 7792 func (stream, "8"); 7793 break; 7794 7795 default: 7796 break; 7797 } 7798 break; 7799 7800 case MVE_VMOV_IMM_TO_VEC: 7801 switch (size) 7802 { 7803 case 0: case 4: case 8: 7804 case 12: case 24: case 26: 7805 func (stream, "i32"); 7806 break; 7807 case 16: case 20: 7808 func (stream, "i16"); 7809 break; 7810 case 28: 7811 func (stream, "i8"); 7812 break; 7813 case 29: 7814 func (stream, "i64"); 7815 break; 7816 case 30: 7817 func (stream, "f32"); 7818 break; 7819 default: 7820 break; 7821 } 7822 break; 7823 7824 case MVE_VMULL_POLY: 7825 if (size == 0) 7826 func (stream, "p8"); 7827 else if (size == 1) 7828 func (stream, "p16"); 7829 break; 7830 7831 case MVE_VMVN_IMM: 7832 switch (size) 7833 { 7834 case 0: case 2: case 4: 7835 case 6: case 12: case 13: 7836 func (stream, "32"); 7837 break; 7838 7839 case 8: case 10: 7840 func (stream, "16"); 7841 break; 7842 7843 default: 7844 break; 7845 } 7846 break; 7847 7848 case MVE_VBIC_IMM: 7849 case MVE_VORR_IMM: 7850 switch (size) 7851 { 7852 case 1: case 3: 7853 case 5: case 7: 7854 func (stream, "32"); 7855 break; 7856 7857 case 9: case 11: 7858 func (stream, "16"); 7859 break; 7860 7861 default: 7862 break; 7863 } 7864 break; 7865 7866 case MVE_VQSHRN: 7867 case MVE_VQSHRUN: 7868 case MVE_VQRSHRN: 7869 case MVE_VQRSHRUN: 7870 case MVE_VRSHRN: 7871 case MVE_VSHRN: 7872 { 7873 switch (size) 7874 { 7875 case 1: 7876 func (stream, "16"); 7877 break; 7878 7879 case 2: case 3: 7880 func (stream, "32"); 7881 break; 7882 7883 default: 7884 break; 7885 } 7886 } 7887 break; 7888 7889 case MVE_VQSHL_T2: 7890 case MVE_VQSHLU_T3: 7891 case MVE_VRSHR: 7892 case MVE_VSHL_T1: 7893 case MVE_VSHLL_T1: 7894 case MVE_VSHR: 7895 case MVE_VSLI: 7896 case MVE_VSRI: 7897 { 7898 switch (size) 7899 { 7900 case 1: 7901 func (stream, "8"); 7902 break; 7903 7904 case 2: case 3: 7905 func (stream, "16"); 7906 break; 7907 7908 case 4: case 5: case 6: case 7: 7909 func (stream, "32"); 7910 break; 7911 7912 default: 7913 break; 7914 } 7915 } 7916 break; 7917 7918 default: 7919 break; 7920 } 7921} 7922 7923static void 7924print_mve_shift_n (struct disassemble_info *info, long given, 7925 enum mve_instructions matched_insn) 7926{ 7927 void *stream = info->stream; 7928 fprintf_ftype func = info->fprintf_func; 7929 7930 int startAt0 7931 = matched_insn == MVE_VQSHL_T2 7932 || matched_insn == MVE_VQSHLU_T3 7933 || matched_insn == MVE_VSHL_T1 7934 || matched_insn == MVE_VSHLL_T1 7935 || matched_insn == MVE_VSLI; 7936 7937 unsigned imm6 = (given & 0x3f0000) >> 16; 7938 7939 if (matched_insn == MVE_VSHLL_T1) 7940 imm6 &= 0x1f; 7941 7942 unsigned shiftAmount = 0; 7943 if ((imm6 & 0x20) != 0) 7944 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6; 7945 else if ((imm6 & 0x10) != 0) 7946 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6; 7947 else if ((imm6 & 0x08) != 0) 7948 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6; 7949 else 7950 print_mve_undefined (info, UNDEF_SIZE_0); 7951 7952 func (stream, "%u", shiftAmount); 7953} 7954 7955static void 7956print_vec_condition (struct disassemble_info *info, long given, 7957 enum mve_instructions matched_insn) 7958{ 7959 void *stream = info->stream; 7960 fprintf_ftype func = info->fprintf_func; 7961 long vec_cond = 0; 7962 7963 switch (matched_insn) 7964 { 7965 case MVE_VPT_FP_T1: 7966 case MVE_VCMP_FP_T1: 7967 vec_cond = (((given & 0x1000) >> 10) 7968 | ((given & 1) << 1) 7969 | ((given & 0x0080) >> 7)); 7970 func (stream, "%s",vec_condnames[vec_cond]); 7971 break; 7972 7973 case MVE_VPT_FP_T2: 7974 case MVE_VCMP_FP_T2: 7975 vec_cond = (((given & 0x1000) >> 10) 7976 | ((given & 0x0020) >> 4) 7977 | ((given & 0x0080) >> 7)); 7978 func (stream, "%s",vec_condnames[vec_cond]); 7979 break; 7980 7981 case MVE_VPT_VEC_T1: 7982 case MVE_VCMP_VEC_T1: 7983 vec_cond = (given & 0x0080) >> 7; 7984 func (stream, "%s",vec_condnames[vec_cond]); 7985 break; 7986 7987 case MVE_VPT_VEC_T2: 7988 case MVE_VCMP_VEC_T2: 7989 vec_cond = 2 | ((given & 0x0080) >> 7); 7990 func (stream, "%s",vec_condnames[vec_cond]); 7991 break; 7992 7993 case MVE_VPT_VEC_T3: 7994 case MVE_VCMP_VEC_T3: 7995 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7); 7996 func (stream, "%s",vec_condnames[vec_cond]); 7997 break; 7998 7999 case MVE_VPT_VEC_T4: 8000 case MVE_VCMP_VEC_T4: 8001 vec_cond = (given & 0x0080) >> 7; 8002 func (stream, "%s",vec_condnames[vec_cond]); 8003 break; 8004 8005 case MVE_VPT_VEC_T5: 8006 case MVE_VCMP_VEC_T5: 8007 vec_cond = 2 | ((given & 0x0080) >> 7); 8008 func (stream, "%s",vec_condnames[vec_cond]); 8009 break; 8010 8011 case MVE_VPT_VEC_T6: 8012 case MVE_VCMP_VEC_T6: 8013 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7); 8014 func (stream, "%s",vec_condnames[vec_cond]); 8015 break; 8016 8017 case MVE_NONE: 8018 case MVE_VPST: 8019 default: 8020 break; 8021 } 8022} 8023 8024#define W_BIT 21 8025#define I_BIT 22 8026#define U_BIT 23 8027#define P_BIT 24 8028 8029#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 8030#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 8031#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 8032#define PRE_BIT_SET (given & (1 << P_BIT)) 8033 8034 8035/* Print one coprocessor instruction on INFO->STREAM. 8036 Return TRUE if the instuction matched, FALSE if this is not a 8037 recognised coprocessor instruction. */ 8038 8039static bool 8040print_insn_coprocessor_1 (const struct sopcode32 *opcodes, 8041 bfd_vma pc, 8042 struct disassemble_info *info, 8043 long given, 8044 bool thumb) 8045{ 8046 const struct sopcode32 *insn; 8047 void *stream = info->stream; 8048 fprintf_ftype func = info->fprintf_func; 8049 unsigned long mask; 8050 unsigned long value = 0; 8051 int cond; 8052 int cp_num; 8053 struct arm_private_data *private_data = info->private_data; 8054 arm_feature_set allowed_arches = ARM_ARCH_NONE; 8055 arm_feature_set arm_ext_v8_1m_main = 8056 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); 8057 8058 allowed_arches = private_data->features; 8059 8060 for (insn = opcodes; insn->assembler; insn++) 8061 { 8062 unsigned long u_reg = 16; 8063 bool is_unpredictable = false; 8064 signed long value_in_comment = 0; 8065 const char *c; 8066 8067 if (ARM_FEATURE_ZERO (insn->arch)) 8068 switch (insn->value) 8069 { 8070 case SENTINEL_IWMMXT_START: 8071 if (info->mach != bfd_mach_arm_XScale 8072 && info->mach != bfd_mach_arm_iWMMXt 8073 && info->mach != bfd_mach_arm_iWMMXt2) 8074 do 8075 insn++; 8076 while ((! ARM_FEATURE_ZERO (insn->arch)) 8077 && insn->value != SENTINEL_IWMMXT_END); 8078 continue; 8079 8080 case SENTINEL_IWMMXT_END: 8081 continue; 8082 8083 case SENTINEL_GENERIC_START: 8084 allowed_arches = private_data->features; 8085 continue; 8086 8087 default: 8088 abort (); 8089 } 8090 8091 mask = insn->mask; 8092 value = insn->value; 8093 cp_num = (given >> 8) & 0xf; 8094 8095 if (thumb) 8096 { 8097 /* The high 4 bits are 0xe for Arm conditional instructions, and 8098 0xe for arm unconditional instructions. The rest of the 8099 encoding is the same. */ 8100 mask |= 0xf0000000; 8101 value |= 0xe0000000; 8102 if (ifthen_state) 8103 cond = IFTHEN_COND; 8104 else 8105 cond = COND_UNCOND; 8106 } 8107 else 8108 { 8109 /* Only match unconditional instuctions against unconditional 8110 patterns. */ 8111 if ((given & 0xf0000000) == 0xf0000000) 8112 { 8113 mask |= 0xf0000000; 8114 cond = COND_UNCOND; 8115 } 8116 else 8117 { 8118 cond = (given >> 28) & 0xf; 8119 if (cond == 0xe) 8120 cond = COND_UNCOND; 8121 } 8122 } 8123 8124 if ((insn->isa == T32 && !thumb) 8125 || (insn->isa == ARM && thumb)) 8126 continue; 8127 8128 if ((given & mask) != value) 8129 continue; 8130 8131 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 8132 continue; 8133 8134 if (insn->value == 0xfe000010 /* mcr2 */ 8135 || insn->value == 0xfe100010 /* mrc2 */ 8136 || insn->value == 0xfc100000 /* ldc2 */ 8137 || insn->value == 0xfc000000) /* stc2 */ 8138 { 8139 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8140 is_unpredictable = true; 8141 8142 /* Armv8.1-M Mainline FP & MVE instructions. */ 8143 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8144 && !ARM_CPU_IS_ANY (allowed_arches) 8145 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8146 continue; 8147 8148 } 8149 else if (insn->value == 0x0e000000 /* cdp */ 8150 || insn->value == 0xfe000000 /* cdp2 */ 8151 || insn->value == 0x0e000010 /* mcr */ 8152 || insn->value == 0x0e100010 /* mrc */ 8153 || insn->value == 0x0c100000 /* ldc */ 8154 || insn->value == 0x0c000000) /* stc */ 8155 { 8156 /* Floating-point instructions. */ 8157 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 8158 continue; 8159 8160 /* Armv8.1-M Mainline FP & MVE instructions. */ 8161 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) 8162 && !ARM_CPU_IS_ANY (allowed_arches) 8163 && (cp_num == 8 || cp_num == 14 || cp_num == 15)) 8164 continue; 8165 } 8166 else if ((insn->value == 0xec100f80 /* vldr (system register) */ 8167 || insn->value == 0xec000f80) /* vstr (system register) */ 8168 && arm_decode_field (given, 24, 24) == 0 8169 && arm_decode_field (given, 21, 21) == 0) 8170 /* If the P and W bits are both 0 then these encodings match the MVE 8171 VLDR and VSTR instructions, these are in a different table, so we 8172 don't let it match here. */ 8173 continue; 8174 8175 for (c = insn->assembler; *c; c++) 8176 { 8177 if (*c == '%') 8178 { 8179 const char mod = *++c; 8180 switch (mod) 8181 { 8182 case '%': 8183 func (stream, "%%"); 8184 break; 8185 8186 case 'A': 8187 case 'K': 8188 { 8189 int rn = (given >> 16) & 0xf; 8190 bfd_vma offset = given & 0xff; 8191 8192 if (mod == 'K') 8193 offset = given & 0x7f; 8194 8195 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 8196 8197 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 8198 { 8199 /* Not unindexed. The offset is scaled. */ 8200 if (cp_num == 9) 8201 /* vldr.16/vstr.16 will shift the address 8202 left by 1 bit only. */ 8203 offset = offset * 2; 8204 else 8205 offset = offset * 4; 8206 8207 if (NEGATIVE_BIT_SET) 8208 offset = - offset; 8209 if (rn != 15) 8210 value_in_comment = offset; 8211 } 8212 8213 if (PRE_BIT_SET) 8214 { 8215 if (offset) 8216 func (stream, ", #%d]%s", 8217 (int) offset, 8218 WRITEBACK_BIT_SET ? "!" : ""); 8219 else if (NEGATIVE_BIT_SET) 8220 func (stream, ", #-0]"); 8221 else 8222 func (stream, "]"); 8223 } 8224 else 8225 { 8226 func (stream, "]"); 8227 8228 if (WRITEBACK_BIT_SET) 8229 { 8230 if (offset) 8231 func (stream, ", #%d", (int) offset); 8232 else if (NEGATIVE_BIT_SET) 8233 func (stream, ", #-0"); 8234 } 8235 else 8236 { 8237 func (stream, ", {%s%d}", 8238 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 8239 (int) offset); 8240 value_in_comment = offset; 8241 } 8242 } 8243 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 8244 { 8245 func (stream, "\t; "); 8246 /* For unaligned PCs, apply off-by-alignment 8247 correction. */ 8248 info->print_address_func (offset + pc 8249 + info->bytes_per_chunk * 2 8250 - (pc & 3), 8251 info); 8252 } 8253 } 8254 break; 8255 8256 case 'B': 8257 { 8258 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 8259 int offset = (given >> 1) & 0x3f; 8260 8261 if (offset == 1) 8262 func (stream, "{d%d}", regno); 8263 else if (regno + offset > 32) 8264 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 8265 else 8266 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 8267 } 8268 break; 8269 8270 case 'C': 8271 { 8272 bool single = ((given >> 8) & 1) == 0; 8273 char reg_prefix = single ? 's' : 'd'; 8274 int Dreg = (given >> 22) & 0x1; 8275 int Vdreg = (given >> 12) & 0xf; 8276 int reg = single ? ((Vdreg << 1) | Dreg) 8277 : ((Dreg << 4) | Vdreg); 8278 int num = (given >> (single ? 0 : 1)) & 0x7f; 8279 int maxreg = single ? 31 : 15; 8280 int topreg = reg + num - 1; 8281 8282 if (!num) 8283 func (stream, "{VPR}"); 8284 else if (num == 1) 8285 func (stream, "{%c%d, VPR}", reg_prefix, reg); 8286 else if (topreg > maxreg) 8287 func (stream, "{%c%d-<overflow reg d%d, VPR}", 8288 reg_prefix, reg, single ? topreg >> 1 : topreg); 8289 else 8290 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg, 8291 reg_prefix, topreg); 8292 } 8293 break; 8294 8295 case 'u': 8296 if (cond != COND_UNCOND) 8297 is_unpredictable = true; 8298 8299 /* Fall through. */ 8300 case 'c': 8301 if (cond != COND_UNCOND && cp_num == 9) 8302 is_unpredictable = true; 8303 8304 /* Fall through. */ 8305 case 'b': 8306 func (stream, "%s", arm_conditional[cond]); 8307 break; 8308 8309 case 'I': 8310 /* Print a Cirrus/DSP shift immediate. */ 8311 /* Immediates are 7bit signed ints with bits 0..3 in 8312 bits 0..3 of opcode and bits 4..6 in bits 5..7 8313 of opcode. */ 8314 { 8315 int imm; 8316 8317 imm = (given & 0xf) | ((given & 0xe0) >> 1); 8318 8319 /* Is ``imm'' a negative number? */ 8320 if (imm & 0x40) 8321 imm -= 0x80; 8322 8323 func (stream, "%d", imm); 8324 } 8325 8326 break; 8327 8328 case 'J': 8329 { 8330 unsigned long regno 8331 = arm_decode_field_multiple (given, 13, 15, 22, 22); 8332 8333 switch (regno) 8334 { 8335 case 0x1: 8336 func (stream, "FPSCR"); 8337 break; 8338 case 0x2: 8339 func (stream, "FPSCR_nzcvqc"); 8340 break; 8341 case 0xc: 8342 func (stream, "VPR"); 8343 break; 8344 case 0xd: 8345 func (stream, "P0"); 8346 break; 8347 case 0xe: 8348 func (stream, "FPCXTNS"); 8349 break; 8350 case 0xf: 8351 func (stream, "FPCXTS"); 8352 break; 8353 default: 8354 func (stream, "<invalid reg %lu>", regno); 8355 break; 8356 } 8357 } 8358 break; 8359 8360 case 'F': 8361 switch (given & 0x00408000) 8362 { 8363 case 0: 8364 func (stream, "4"); 8365 break; 8366 case 0x8000: 8367 func (stream, "1"); 8368 break; 8369 case 0x00400000: 8370 func (stream, "2"); 8371 break; 8372 default: 8373 func (stream, "3"); 8374 } 8375 break; 8376 8377 case 'P': 8378 switch (given & 0x00080080) 8379 { 8380 case 0: 8381 func (stream, "s"); 8382 break; 8383 case 0x80: 8384 func (stream, "d"); 8385 break; 8386 case 0x00080000: 8387 func (stream, "e"); 8388 break; 8389 default: 8390 func (stream, _("<illegal precision>")); 8391 break; 8392 } 8393 break; 8394 8395 case 'Q': 8396 switch (given & 0x00408000) 8397 { 8398 case 0: 8399 func (stream, "s"); 8400 break; 8401 case 0x8000: 8402 func (stream, "d"); 8403 break; 8404 case 0x00400000: 8405 func (stream, "e"); 8406 break; 8407 default: 8408 func (stream, "p"); 8409 break; 8410 } 8411 break; 8412 8413 case 'R': 8414 switch (given & 0x60) 8415 { 8416 case 0: 8417 break; 8418 case 0x20: 8419 func (stream, "p"); 8420 break; 8421 case 0x40: 8422 func (stream, "m"); 8423 break; 8424 default: 8425 func (stream, "z"); 8426 break; 8427 } 8428 break; 8429 8430 case '0': case '1': case '2': case '3': case '4': 8431 case '5': case '6': case '7': case '8': case '9': 8432 { 8433 int width; 8434 8435 c = arm_decode_bitfield (c, given, &value, &width); 8436 8437 switch (*c) 8438 { 8439 case 'R': 8440 if (value == 15) 8441 is_unpredictable = true; 8442 /* Fall through. */ 8443 case 'r': 8444 if (c[1] == 'u') 8445 { 8446 /* Eat the 'u' character. */ 8447 ++ c; 8448 8449 if (u_reg == value) 8450 is_unpredictable = true; 8451 u_reg = value; 8452 } 8453 func (stream, "%s", arm_regnames[value]); 8454 break; 8455 case 'V': 8456 if (given & (1 << 6)) 8457 goto Q; 8458 /* FALLTHROUGH */ 8459 case 'D': 8460 func (stream, "d%ld", value); 8461 break; 8462 case 'Q': 8463 Q: 8464 if (value & 1) 8465 func (stream, "<illegal reg q%ld.5>", value >> 1); 8466 else 8467 func (stream, "q%ld", value >> 1); 8468 break; 8469 case 'd': 8470 func (stream, "%ld", value); 8471 value_in_comment = value; 8472 break; 8473 case 'E': 8474 { 8475 /* Converts immediate 8 bit back to float value. */ 8476 unsigned floatVal = (value & 0x80) << 24 8477 | (value & 0x3F) << 19 8478 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 8479 8480 /* Quarter float have a maximum value of 31.0. 8481 Get floating point value multiplied by 1e7. 8482 The maximum value stays in limit of a 32-bit int. */ 8483 unsigned decVal = 8484 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 8485 (16 + (value & 0xF)); 8486 8487 if (!(decVal % 1000000)) 8488 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 8489 floatVal, value & 0x80 ? '-' : ' ', 8490 decVal / 10000000, 8491 decVal % 10000000 / 1000000); 8492 else if (!(decVal % 10000)) 8493 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 8494 floatVal, value & 0x80 ? '-' : ' ', 8495 decVal / 10000000, 8496 decVal % 10000000 / 10000); 8497 else 8498 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 8499 floatVal, value & 0x80 ? '-' : ' ', 8500 decVal / 10000000, decVal % 10000000); 8501 break; 8502 } 8503 case 'k': 8504 { 8505 int from = (given & (1 << 7)) ? 32 : 16; 8506 func (stream, "%ld", from - value); 8507 } 8508 break; 8509 8510 case 'f': 8511 if (value > 7) 8512 func (stream, "#%s", arm_fp_const[value & 7]); 8513 else 8514 func (stream, "f%ld", value); 8515 break; 8516 8517 case 'w': 8518 if (width == 2) 8519 func (stream, "%s", iwmmxt_wwnames[value]); 8520 else 8521 func (stream, "%s", iwmmxt_wwssnames[value]); 8522 break; 8523 8524 case 'g': 8525 func (stream, "%s", iwmmxt_regnames[value]); 8526 break; 8527 case 'G': 8528 func (stream, "%s", iwmmxt_cregnames[value]); 8529 break; 8530 8531 case 'x': 8532 func (stream, "0x%lx", (value & 0xffffffffUL)); 8533 break; 8534 8535 case 'c': 8536 switch (value) 8537 { 8538 case 0: 8539 func (stream, "eq"); 8540 break; 8541 8542 case 1: 8543 func (stream, "vs"); 8544 break; 8545 8546 case 2: 8547 func (stream, "ge"); 8548 break; 8549 8550 case 3: 8551 func (stream, "gt"); 8552 break; 8553 8554 default: 8555 func (stream, "??"); 8556 break; 8557 } 8558 break; 8559 8560 case '`': 8561 c++; 8562 if (value == 0) 8563 func (stream, "%c", *c); 8564 break; 8565 case '\'': 8566 c++; 8567 if (value == ((1ul << width) - 1)) 8568 func (stream, "%c", *c); 8569 break; 8570 case '?': 8571 func (stream, "%c", c[(1 << width) - (int) value]); 8572 c += 1 << width; 8573 break; 8574 default: 8575 abort (); 8576 } 8577 } 8578 break; 8579 8580 case 'y': 8581 case 'z': 8582 { 8583 int single = *c++ == 'y'; 8584 int regno; 8585 8586 switch (*c) 8587 { 8588 case '4': /* Sm pair */ 8589 case '0': /* Sm, Dm */ 8590 regno = given & 0x0000000f; 8591 if (single) 8592 { 8593 regno <<= 1; 8594 regno += (given >> 5) & 1; 8595 } 8596 else 8597 regno += ((given >> 5) & 1) << 4; 8598 break; 8599 8600 case '1': /* Sd, Dd */ 8601 regno = (given >> 12) & 0x0000000f; 8602 if (single) 8603 { 8604 regno <<= 1; 8605 regno += (given >> 22) & 1; 8606 } 8607 else 8608 regno += ((given >> 22) & 1) << 4; 8609 break; 8610 8611 case '2': /* Sn, Dn */ 8612 regno = (given >> 16) & 0x0000000f; 8613 if (single) 8614 { 8615 regno <<= 1; 8616 regno += (given >> 7) & 1; 8617 } 8618 else 8619 regno += ((given >> 7) & 1) << 4; 8620 break; 8621 8622 case '3': /* List */ 8623 func (stream, "{"); 8624 regno = (given >> 12) & 0x0000000f; 8625 if (single) 8626 { 8627 regno <<= 1; 8628 regno += (given >> 22) & 1; 8629 } 8630 else 8631 regno += ((given >> 22) & 1) << 4; 8632 break; 8633 8634 default: 8635 abort (); 8636 } 8637 8638 func (stream, "%c%d", single ? 's' : 'd', regno); 8639 8640 if (*c == '3') 8641 { 8642 int count = given & 0xff; 8643 8644 if (single == 0) 8645 count >>= 1; 8646 8647 if (--count) 8648 { 8649 func (stream, "-%c%d", 8650 single ? 's' : 'd', 8651 regno + count); 8652 } 8653 8654 func (stream, "}"); 8655 } 8656 else if (*c == '4') 8657 func (stream, ", %c%d", single ? 's' : 'd', 8658 regno + 1); 8659 } 8660 break; 8661 8662 case 'L': 8663 switch (given & 0x00400100) 8664 { 8665 case 0x00000000: func (stream, "b"); break; 8666 case 0x00400000: func (stream, "h"); break; 8667 case 0x00000100: func (stream, "w"); break; 8668 case 0x00400100: func (stream, "d"); break; 8669 default: 8670 break; 8671 } 8672 break; 8673 8674 case 'Z': 8675 { 8676 /* given (20, 23) | given (0, 3) */ 8677 value = ((given >> 16) & 0xf0) | (given & 0xf); 8678 func (stream, "%d", (int) value); 8679 } 8680 break; 8681 8682 case 'l': 8683 /* This is like the 'A' operator, except that if 8684 the width field "M" is zero, then the offset is 8685 *not* multiplied by four. */ 8686 { 8687 int offset = given & 0xff; 8688 int multiplier = (given & 0x00000100) ? 4 : 1; 8689 8690 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 8691 8692 if (multiplier > 1) 8693 { 8694 value_in_comment = offset * multiplier; 8695 if (NEGATIVE_BIT_SET) 8696 value_in_comment = - value_in_comment; 8697 } 8698 8699 if (offset) 8700 { 8701 if (PRE_BIT_SET) 8702 func (stream, ", #%s%d]%s", 8703 NEGATIVE_BIT_SET ? "-" : "", 8704 offset * multiplier, 8705 WRITEBACK_BIT_SET ? "!" : ""); 8706 else 8707 func (stream, "], #%s%d", 8708 NEGATIVE_BIT_SET ? "-" : "", 8709 offset * multiplier); 8710 } 8711 else 8712 func (stream, "]"); 8713 } 8714 break; 8715 8716 case 'r': 8717 { 8718 int imm4 = (given >> 4) & 0xf; 8719 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 8720 int ubit = ! NEGATIVE_BIT_SET; 8721 const char *rm = arm_regnames [given & 0xf]; 8722 const char *rn = arm_regnames [(given >> 16) & 0xf]; 8723 8724 switch (puw_bits) 8725 { 8726 case 1: 8727 case 3: 8728 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 8729 if (imm4) 8730 func (stream, ", lsl #%d", imm4); 8731 break; 8732 8733 case 4: 8734 case 5: 8735 case 6: 8736 case 7: 8737 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 8738 if (imm4 > 0) 8739 func (stream, ", lsl #%d", imm4); 8740 func (stream, "]"); 8741 if (puw_bits == 5 || puw_bits == 7) 8742 func (stream, "!"); 8743 break; 8744 8745 default: 8746 func (stream, "INVALID"); 8747 } 8748 } 8749 break; 8750 8751 case 'i': 8752 { 8753 long imm5; 8754 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 8755 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 8756 } 8757 break; 8758 8759 default: 8760 abort (); 8761 } 8762 } 8763 else 8764 func (stream, "%c", *c); 8765 } 8766 8767 if (value_in_comment > 32 || value_in_comment < -16) 8768 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 8769 8770 if (is_unpredictable) 8771 func (stream, UNPREDICTABLE_INSTRUCTION); 8772 8773 return true; 8774 } 8775 return false; 8776} 8777 8778static bool 8779print_insn_coprocessor (bfd_vma pc, 8780 struct disassemble_info *info, 8781 long given, 8782 bool thumb) 8783{ 8784 return print_insn_coprocessor_1 (coprocessor_opcodes, 8785 pc, info, given, thumb); 8786} 8787 8788static bool 8789print_insn_generic_coprocessor (bfd_vma pc, 8790 struct disassemble_info *info, 8791 long given, 8792 bool thumb) 8793{ 8794 return print_insn_coprocessor_1 (generic_coprocessor_opcodes, 8795 pc, info, given, thumb); 8796} 8797 8798/* Decodes and prints ARM addressing modes. Returns the offset 8799 used in the address, if any, if it is worthwhile printing the 8800 offset as a hexadecimal value in a comment at the end of the 8801 line of disassembly. */ 8802 8803static signed long 8804print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 8805{ 8806 void *stream = info->stream; 8807 fprintf_ftype func = info->fprintf_func; 8808 bfd_vma offset = 0; 8809 8810 if (((given & 0x000f0000) == 0x000f0000) 8811 && ((given & 0x02000000) == 0)) 8812 { 8813 offset = given & 0xfff; 8814 8815 func (stream, "[pc"); 8816 8817 if (PRE_BIT_SET) 8818 { 8819 /* Pre-indexed. Elide offset of positive zero when 8820 non-writeback. */ 8821 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8822 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8823 8824 if (NEGATIVE_BIT_SET) 8825 offset = -offset; 8826 8827 offset += pc + 8; 8828 8829 /* Cope with the possibility of write-back 8830 being used. Probably a very dangerous thing 8831 for the programmer to do, but who are we to 8832 argue ? */ 8833 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 8834 } 8835 else /* Post indexed. */ 8836 { 8837 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8838 8839 /* Ie ignore the offset. */ 8840 offset = pc + 8; 8841 } 8842 8843 func (stream, "\t; "); 8844 info->print_address_func (offset, info); 8845 offset = 0; 8846 } 8847 else 8848 { 8849 func (stream, "[%s", 8850 arm_regnames[(given >> 16) & 0xf]); 8851 8852 if (PRE_BIT_SET) 8853 { 8854 if ((given & 0x02000000) == 0) 8855 { 8856 /* Elide offset of positive zero when non-writeback. */ 8857 offset = given & 0xfff; 8858 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 8859 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8860 } 8861 else 8862 { 8863 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 8864 arm_decode_shift (given, func, stream, true); 8865 } 8866 8867 func (stream, "]%s", 8868 WRITEBACK_BIT_SET ? "!" : ""); 8869 } 8870 else 8871 { 8872 if ((given & 0x02000000) == 0) 8873 { 8874 /* Always show offset. */ 8875 offset = given & 0xfff; 8876 func (stream, "], #%s%d", 8877 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 8878 } 8879 else 8880 { 8881 func (stream, "], %s", 8882 NEGATIVE_BIT_SET ? "-" : ""); 8883 arm_decode_shift (given, func, stream, true); 8884 } 8885 } 8886 if (NEGATIVE_BIT_SET) 8887 offset = -offset; 8888 } 8889 8890 return (signed long) offset; 8891} 8892 8893 8894/* Print one cde instruction on INFO->STREAM. 8895 Return TRUE if the instuction matched, FALSE if this is not a 8896 recognised cde instruction. */ 8897static bool 8898print_insn_cde (struct disassemble_info *info, long given, bool thumb) 8899{ 8900 const struct cdeopcode32 *insn; 8901 void *stream = info->stream; 8902 fprintf_ftype func = info->fprintf_func; 8903 8904 if (thumb) 8905 { 8906 /* Manually extract the coprocessor code from a known point. 8907 This position is the same across all CDE instructions. */ 8908 for (insn = cde_opcodes; insn->assembler; insn++) 8909 { 8910 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask; 8911 uint16_t coproc_mask = 1 << coproc; 8912 if (! (coproc_mask & cde_coprocs)) 8913 continue; 8914 8915 if ((given & insn->mask) == insn->value) 8916 { 8917 bool is_unpredictable = false; 8918 const char *c; 8919 8920 for (c = insn->assembler; *c; c++) 8921 { 8922 if (*c == '%') 8923 { 8924 switch (*++c) 8925 { 8926 case '%': 8927 func (stream, "%%"); 8928 break; 8929 8930 case '0': case '1': case '2': case '3': case '4': 8931 case '5': case '6': case '7': case '8': case '9': 8932 { 8933 int width; 8934 unsigned long value; 8935 8936 c = arm_decode_bitfield (c, given, &value, &width); 8937 8938 switch (*c) 8939 { 8940 case 'S': 8941 if (value > 10) 8942 is_unpredictable = true; 8943 /* Fall through. */ 8944 case 'R': 8945 if (value == 13) 8946 is_unpredictable = true; 8947 /* Fall through. */ 8948 case 'r': 8949 func (stream, "%s", arm_regnames[value]); 8950 break; 8951 8952 case 'n': 8953 if (value == 15) 8954 func (stream, "%s", "APSR_nzcv"); 8955 else 8956 func (stream, "%s", arm_regnames[value]); 8957 break; 8958 8959 case 'T': 8960 func (stream, "%s", arm_regnames[value + 1]); 8961 break; 8962 8963 case 'd': 8964 func (stream, "%ld", value); 8965 break; 8966 8967 case 'V': 8968 if (given & (1 << 6)) 8969 func (stream, "q%ld", value >> 1); 8970 else if (given & (1 << 24)) 8971 func (stream, "d%ld", value); 8972 else 8973 { 8974 /* Encoding for S register is different than for D and 8975 Q registers. S registers are encoded using the top 8976 single bit in position 22 as the lowest bit of the 8977 register number, while for Q and D it represents the 8978 highest bit of the register number. */ 8979 uint8_t top_bit = (value >> 4) & 1; 8980 uint8_t tmp = (value << 1) & 0x1e; 8981 uint8_t res = tmp | top_bit; 8982 func (stream, "s%u", res); 8983 } 8984 break; 8985 8986 default: 8987 abort (); 8988 } 8989 } 8990 break; 8991 8992 case 'p': 8993 { 8994 uint8_t proc_number = (given >> 8) & 0x7; 8995 func (stream, "p%u", proc_number); 8996 break; 8997 } 8998 8999 case 'a': 9000 { 9001 uint8_t a_offset = 28; 9002 if (given & (1 << a_offset)) 9003 func (stream, "a"); 9004 break; 9005 } 9006 default: 9007 abort (); 9008 } 9009 } 9010 else 9011 func (stream, "%c", *c); 9012 } 9013 9014 if (is_unpredictable) 9015 func (stream, UNPREDICTABLE_INSTRUCTION); 9016 9017 return true; 9018 } 9019 } 9020 return false; 9021 } 9022 else 9023 return false; 9024} 9025 9026 9027/* Print one neon instruction on INFO->STREAM. 9028 Return TRUE if the instuction matched, FALSE if this is not a 9029 recognised neon instruction. */ 9030 9031static bool 9032print_insn_neon (struct disassemble_info *info, long given, bool thumb) 9033{ 9034 const struct opcode32 *insn; 9035 void *stream = info->stream; 9036 fprintf_ftype func = info->fprintf_func; 9037 9038 if (thumb) 9039 { 9040 if ((given & 0xef000000) == 0xef000000) 9041 { 9042 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 9043 unsigned long bit28 = given & (1 << 28); 9044 9045 given &= 0x00ffffff; 9046 if (bit28) 9047 given |= 0xf3000000; 9048 else 9049 given |= 0xf2000000; 9050 } 9051 else if ((given & 0xff000000) == 0xf9000000) 9052 given ^= 0xf9000000 ^ 0xf4000000; 9053 /* BFloat16 neon instructions without special top byte handling. */ 9054 else if ((given & 0xff000000) == 0xfe000000 9055 || (given & 0xff000000) == 0xfc000000) 9056 ; 9057 /* vdup is also a valid neon instruction. */ 9058 else if ((given & 0xff900f5f) != 0xee800b10) 9059 return false; 9060 } 9061 9062 for (insn = neon_opcodes; insn->assembler; insn++) 9063 { 9064 unsigned long cond_mask = insn->mask; 9065 unsigned long cond_value = insn->value; 9066 int cond; 9067 9068 if (thumb) 9069 { 9070 if ((cond_mask & 0xf0000000) == 0) { 9071 /* For the entries in neon_opcodes, an opcode mask/value with 9072 the high 4 bits equal to 0 indicates a conditional 9073 instruction. For thumb however, we need to include those 9074 bits in the instruction matching. */ 9075 cond_mask |= 0xf0000000; 9076 /* Furthermore, the thumb encoding of a conditional instruction 9077 will have the high 4 bits equal to 0xe. */ 9078 cond_value |= 0xe0000000; 9079 } 9080 if (ifthen_state) 9081 cond = IFTHEN_COND; 9082 else 9083 cond = COND_UNCOND; 9084 } 9085 else 9086 { 9087 if ((given & 0xf0000000) == 0xf0000000) 9088 { 9089 /* If the instruction is unconditional, update the mask to only 9090 match against unconditional opcode values. */ 9091 cond_mask |= 0xf0000000; 9092 cond = COND_UNCOND; 9093 } 9094 else 9095 { 9096 cond = (given >> 28) & 0xf; 9097 if (cond == 0xe) 9098 cond = COND_UNCOND; 9099 } 9100 } 9101 9102 if ((given & cond_mask) == cond_value) 9103 { 9104 signed long value_in_comment = 0; 9105 bool is_unpredictable = false; 9106 const char *c; 9107 9108 for (c = insn->assembler; *c; c++) 9109 { 9110 if (*c == '%') 9111 { 9112 switch (*++c) 9113 { 9114 case '%': 9115 func (stream, "%%"); 9116 break; 9117 9118 case 'u': 9119 if (thumb && ifthen_state) 9120 is_unpredictable = true; 9121 9122 /* Fall through. */ 9123 case 'c': 9124 func (stream, "%s", arm_conditional[cond]); 9125 break; 9126 9127 case 'A': 9128 { 9129 static const unsigned char enc[16] = 9130 { 9131 0x4, 0x14, /* st4 0,1 */ 9132 0x4, /* st1 2 */ 9133 0x4, /* st2 3 */ 9134 0x3, /* st3 4 */ 9135 0x13, /* st3 5 */ 9136 0x3, /* st1 6 */ 9137 0x1, /* st1 7 */ 9138 0x2, /* st2 8 */ 9139 0x12, /* st2 9 */ 9140 0x2, /* st1 10 */ 9141 0, 0, 0, 0, 0 9142 }; 9143 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9144 int rn = ((given >> 16) & 0xf); 9145 int rm = ((given >> 0) & 0xf); 9146 int align = ((given >> 4) & 0x3); 9147 int type = ((given >> 8) & 0xf); 9148 int n = enc[type] & 0xf; 9149 int stride = (enc[type] >> 4) + 1; 9150 int ix; 9151 9152 func (stream, "{"); 9153 if (stride > 1) 9154 for (ix = 0; ix != n; ix++) 9155 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 9156 else if (n == 1) 9157 func (stream, "d%d", rd); 9158 else 9159 func (stream, "d%d-d%d", rd, rd + n - 1); 9160 func (stream, "}, [%s", arm_regnames[rn]); 9161 if (align) 9162 func (stream, " :%d", 32 << align); 9163 func (stream, "]"); 9164 if (rm == 0xd) 9165 func (stream, "!"); 9166 else if (rm != 0xf) 9167 func (stream, ", %s", arm_regnames[rm]); 9168 } 9169 break; 9170 9171 case 'B': 9172 { 9173 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9174 int rn = ((given >> 16) & 0xf); 9175 int rm = ((given >> 0) & 0xf); 9176 int idx_align = ((given >> 4) & 0xf); 9177 int align = 0; 9178 int size = ((given >> 10) & 0x3); 9179 int idx = idx_align >> (size + 1); 9180 int length = ((given >> 8) & 3) + 1; 9181 int stride = 1; 9182 int i; 9183 9184 if (length > 1 && size > 0) 9185 stride = (idx_align & (1 << size)) ? 2 : 1; 9186 9187 switch (length) 9188 { 9189 case 1: 9190 { 9191 int amask = (1 << size) - 1; 9192 if ((idx_align & (1 << size)) != 0) 9193 return false; 9194 if (size > 0) 9195 { 9196 if ((idx_align & amask) == amask) 9197 align = 8 << size; 9198 else if ((idx_align & amask) != 0) 9199 return false; 9200 } 9201 } 9202 break; 9203 9204 case 2: 9205 if (size == 2 && (idx_align & 2) != 0) 9206 return false; 9207 align = (idx_align & 1) ? 16 << size : 0; 9208 break; 9209 9210 case 3: 9211 if ((size == 2 && (idx_align & 3) != 0) 9212 || (idx_align & 1) != 0) 9213 return false; 9214 break; 9215 9216 case 4: 9217 if (size == 2) 9218 { 9219 if ((idx_align & 3) == 3) 9220 return false; 9221 align = (idx_align & 3) * 64; 9222 } 9223 else 9224 align = (idx_align & 1) ? 32 << size : 0; 9225 break; 9226 9227 default: 9228 abort (); 9229 } 9230 9231 func (stream, "{"); 9232 for (i = 0; i < length; i++) 9233 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 9234 rd + i * stride, idx); 9235 func (stream, "}, [%s", arm_regnames[rn]); 9236 if (align) 9237 func (stream, " :%d", align); 9238 func (stream, "]"); 9239 if (rm == 0xd) 9240 func (stream, "!"); 9241 else if (rm != 0xf) 9242 func (stream, ", %s", arm_regnames[rm]); 9243 } 9244 break; 9245 9246 case 'C': 9247 { 9248 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 9249 int rn = ((given >> 16) & 0xf); 9250 int rm = ((given >> 0) & 0xf); 9251 int align = ((given >> 4) & 0x1); 9252 int size = ((given >> 6) & 0x3); 9253 int type = ((given >> 8) & 0x3); 9254 int n = type + 1; 9255 int stride = ((given >> 5) & 0x1); 9256 int ix; 9257 9258 if (stride && (n == 1)) 9259 n++; 9260 else 9261 stride++; 9262 9263 func (stream, "{"); 9264 if (stride > 1) 9265 for (ix = 0; ix != n; ix++) 9266 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 9267 else if (n == 1) 9268 func (stream, "d%d[]", rd); 9269 else 9270 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 9271 func (stream, "}, [%s", arm_regnames[rn]); 9272 if (align) 9273 { 9274 align = (8 * (type + 1)) << size; 9275 if (type == 3) 9276 align = (size > 1) ? align >> 1 : align; 9277 if (type == 2 || (type == 0 && !size)) 9278 func (stream, " :<bad align %d>", align); 9279 else 9280 func (stream, " :%d", align); 9281 } 9282 func (stream, "]"); 9283 if (rm == 0xd) 9284 func (stream, "!"); 9285 else if (rm != 0xf) 9286 func (stream, ", %s", arm_regnames[rm]); 9287 } 9288 break; 9289 9290 case 'D': 9291 { 9292 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 9293 int size = (given >> 20) & 3; 9294 int reg = raw_reg & ((4 << size) - 1); 9295 int ix = raw_reg >> size >> 2; 9296 9297 func (stream, "d%d[%d]", reg, ix); 9298 } 9299 break; 9300 9301 case 'E': 9302 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 9303 { 9304 int bits = 0; 9305 int cmode = (given >> 8) & 0xf; 9306 int op = (given >> 5) & 0x1; 9307 unsigned long value = 0, hival = 0; 9308 unsigned shift; 9309 int size = 0; 9310 int isfloat = 0; 9311 9312 bits |= ((given >> 24) & 1) << 7; 9313 bits |= ((given >> 16) & 7) << 4; 9314 bits |= ((given >> 0) & 15) << 0; 9315 9316 if (cmode < 8) 9317 { 9318 shift = (cmode >> 1) & 3; 9319 value = (unsigned long) bits << (8 * shift); 9320 size = 32; 9321 } 9322 else if (cmode < 12) 9323 { 9324 shift = (cmode >> 1) & 1; 9325 value = (unsigned long) bits << (8 * shift); 9326 size = 16; 9327 } 9328 else if (cmode < 14) 9329 { 9330 shift = (cmode & 1) + 1; 9331 value = (unsigned long) bits << (8 * shift); 9332 value |= (1ul << (8 * shift)) - 1; 9333 size = 32; 9334 } 9335 else if (cmode == 14) 9336 { 9337 if (op) 9338 { 9339 /* Bit replication into bytes. */ 9340 int ix; 9341 unsigned long mask; 9342 9343 value = 0; 9344 hival = 0; 9345 for (ix = 7; ix >= 0; ix--) 9346 { 9347 mask = ((bits >> ix) & 1) ? 0xff : 0; 9348 if (ix <= 3) 9349 value = (value << 8) | mask; 9350 else 9351 hival = (hival << 8) | mask; 9352 } 9353 size = 64; 9354 } 9355 else 9356 { 9357 /* Byte replication. */ 9358 value = (unsigned long) bits; 9359 size = 8; 9360 } 9361 } 9362 else if (!op) 9363 { 9364 /* Floating point encoding. */ 9365 int tmp; 9366 9367 value = (unsigned long) (bits & 0x7f) << 19; 9368 value |= (unsigned long) (bits & 0x80) << 24; 9369 tmp = bits & 0x40 ? 0x3c : 0x40; 9370 value |= (unsigned long) tmp << 24; 9371 size = 32; 9372 isfloat = 1; 9373 } 9374 else 9375 { 9376 func (stream, "<illegal constant %.8x:%x:%x>", 9377 bits, cmode, op); 9378 size = 32; 9379 break; 9380 } 9381 switch (size) 9382 { 9383 case 8: 9384 func (stream, "#%ld\t; 0x%.2lx", value, value); 9385 break; 9386 9387 case 16: 9388 func (stream, "#%ld\t; 0x%.4lx", value, value); 9389 break; 9390 9391 case 32: 9392 if (isfloat) 9393 { 9394 unsigned char valbytes[4]; 9395 double fvalue; 9396 9397 /* Do this a byte at a time so we don't have to 9398 worry about the host's endianness. */ 9399 valbytes[0] = value & 0xff; 9400 valbytes[1] = (value >> 8) & 0xff; 9401 valbytes[2] = (value >> 16) & 0xff; 9402 valbytes[3] = (value >> 24) & 0xff; 9403 9404 floatformat_to_double 9405 (& floatformat_ieee_single_little, valbytes, 9406 & fvalue); 9407 9408 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 9409 value); 9410 } 9411 else 9412 func (stream, "#%ld\t; 0x%.8lx", 9413 (long) (((value & 0x80000000L) != 0) 9414 ? value | ~0xffffffffL : value), 9415 value); 9416 break; 9417 9418 case 64: 9419 func (stream, "#0x%.8lx%.8lx", hival, value); 9420 break; 9421 9422 default: 9423 abort (); 9424 } 9425 } 9426 break; 9427 9428 case 'F': 9429 { 9430 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 9431 int num = (given >> 8) & 0x3; 9432 9433 if (!num) 9434 func (stream, "{d%d}", regno); 9435 else if (num + regno >= 32) 9436 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 9437 else 9438 func (stream, "{d%d-d%d}", regno, regno + num); 9439 } 9440 break; 9441 9442 9443 case '0': case '1': case '2': case '3': case '4': 9444 case '5': case '6': case '7': case '8': case '9': 9445 { 9446 int width; 9447 unsigned long value; 9448 9449 c = arm_decode_bitfield (c, given, &value, &width); 9450 9451 switch (*c) 9452 { 9453 case 'r': 9454 func (stream, "%s", arm_regnames[value]); 9455 break; 9456 case 'd': 9457 func (stream, "%ld", value); 9458 value_in_comment = value; 9459 break; 9460 case 'e': 9461 func (stream, "%ld", (1ul << width) - value); 9462 break; 9463 9464 case 'S': 9465 case 'T': 9466 case 'U': 9467 /* Various width encodings. */ 9468 { 9469 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 9470 int limit; 9471 unsigned low, high; 9472 9473 c++; 9474 if (*c >= '0' && *c <= '9') 9475 limit = *c - '0'; 9476 else if (*c >= 'a' && *c <= 'f') 9477 limit = *c - 'a' + 10; 9478 else 9479 abort (); 9480 low = limit >> 2; 9481 high = limit & 3; 9482 9483 if (value < low || value > high) 9484 func (stream, "<illegal width %d>", base << value); 9485 else 9486 func (stream, "%d", base << value); 9487 } 9488 break; 9489 case 'R': 9490 if (given & (1 << 6)) 9491 goto Q; 9492 /* FALLTHROUGH */ 9493 case 'D': 9494 func (stream, "d%ld", value); 9495 break; 9496 case 'Q': 9497 Q: 9498 if (value & 1) 9499 func (stream, "<illegal reg q%ld.5>", value >> 1); 9500 else 9501 func (stream, "q%ld", value >> 1); 9502 break; 9503 9504 case '`': 9505 c++; 9506 if (value == 0) 9507 func (stream, "%c", *c); 9508 break; 9509 case '\'': 9510 c++; 9511 if (value == ((1ul << width) - 1)) 9512 func (stream, "%c", *c); 9513 break; 9514 case '?': 9515 func (stream, "%c", c[(1 << width) - (int) value]); 9516 c += 1 << width; 9517 break; 9518 default: 9519 abort (); 9520 } 9521 } 9522 break; 9523 9524 default: 9525 abort (); 9526 } 9527 } 9528 else 9529 func (stream, "%c", *c); 9530 } 9531 9532 if (value_in_comment > 32 || value_in_comment < -16) 9533 func (stream, "\t; 0x%lx", value_in_comment); 9534 9535 if (is_unpredictable) 9536 func (stream, UNPREDICTABLE_INSTRUCTION); 9537 9538 return true; 9539 } 9540 } 9541 return false; 9542} 9543 9544/* Print one mve instruction on INFO->STREAM. 9545 Return TRUE if the instuction matched, FALSE if this is not a 9546 recognised mve instruction. */ 9547 9548static bool 9549print_insn_mve (struct disassemble_info *info, long given) 9550{ 9551 const struct mopcode32 *insn; 9552 void *stream = info->stream; 9553 fprintf_ftype func = info->fprintf_func; 9554 9555 for (insn = mve_opcodes; insn->assembler; insn++) 9556 { 9557 if (((given & insn->mask) == insn->value) 9558 && !is_mve_encoding_conflict (given, insn->mve_op)) 9559 { 9560 signed long value_in_comment = 0; 9561 bool is_unpredictable = false; 9562 bool is_undefined = false; 9563 const char *c; 9564 enum mve_unpredictable unpredictable_cond = UNPRED_NONE; 9565 enum mve_undefined undefined_cond = UNDEF_NONE; 9566 9567 /* Most vector mve instruction are illegal in a it block. 9568 There are a few exceptions; check for them. */ 9569 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op)) 9570 { 9571 is_unpredictable = true; 9572 unpredictable_cond = UNPRED_IT_BLOCK; 9573 } 9574 else if (is_mve_unpredictable (given, insn->mve_op, 9575 &unpredictable_cond)) 9576 is_unpredictable = true; 9577 9578 if (is_mve_undefined (given, insn->mve_op, &undefined_cond)) 9579 is_undefined = true; 9580 9581 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV, 9582 i.e "VMOV Qd, Qm". */ 9583 if ((insn->mve_op == MVE_VORR_REG) 9584 && (arm_decode_field (given, 1, 3) 9585 == arm_decode_field (given, 17, 19))) 9586 continue; 9587 9588 for (c = insn->assembler; *c; c++) 9589 { 9590 if (*c == '%') 9591 { 9592 switch (*++c) 9593 { 9594 case '%': 9595 func (stream, "%%"); 9596 break; 9597 9598 case 'a': 9599 /* Don't print anything for '+' as it is implied. */ 9600 if (arm_decode_field (given, 23, 23) == 0) 9601 func (stream, "-"); 9602 break; 9603 9604 case 'c': 9605 if (ifthen_state) 9606 func (stream, "%s", arm_conditional[IFTHEN_COND]); 9607 break; 9608 9609 case 'd': 9610 print_mve_vld_str_addr (info, given, insn->mve_op); 9611 break; 9612 9613 case 'i': 9614 { 9615 long mve_mask = mve_extract_pred_mask (given); 9616 func (stream, "%s", mve_predicatenames[mve_mask]); 9617 } 9618 break; 9619 9620 case 'j': 9621 { 9622 unsigned int imm5 = 0; 9623 imm5 |= arm_decode_field (given, 6, 7); 9624 imm5 |= (arm_decode_field (given, 12, 14) << 2); 9625 func (stream, "#%u", (imm5 == 0) ? 32 : imm5); 9626 } 9627 break; 9628 9629 case 'k': 9630 func (stream, "#%u", 9631 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); 9632 break; 9633 9634 case 'n': 9635 print_vec_condition (info, given, insn->mve_op); 9636 break; 9637 9638 case 'o': 9639 if (arm_decode_field (given, 0, 0) == 1) 9640 { 9641 unsigned long size 9642 = arm_decode_field (given, 4, 4) 9643 | (arm_decode_field (given, 6, 6) << 1); 9644 9645 func (stream, ", uxtw #%lu", size); 9646 } 9647 break; 9648 9649 case 'm': 9650 print_mve_rounding_mode (info, given, insn->mve_op); 9651 break; 9652 9653 case 's': 9654 print_mve_vcvt_size (info, given, insn->mve_op); 9655 break; 9656 9657 case 'u': 9658 { 9659 unsigned long op1 = arm_decode_field (given, 21, 22); 9660 9661 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP)) 9662 { 9663 /* Check for signed. */ 9664 if (arm_decode_field (given, 23, 23) == 0) 9665 { 9666 /* We don't print 's' for S32. */ 9667 if ((arm_decode_field (given, 5, 6) == 0) 9668 && ((op1 == 0) || (op1 == 1))) 9669 ; 9670 else 9671 func (stream, "s"); 9672 } 9673 else 9674 func (stream, "u"); 9675 } 9676 else 9677 { 9678 if (arm_decode_field (given, 28, 28) == 0) 9679 func (stream, "s"); 9680 else 9681 func (stream, "u"); 9682 } 9683 } 9684 break; 9685 9686 case 'v': 9687 print_instruction_predicate (info); 9688 break; 9689 9690 case 'w': 9691 if (arm_decode_field (given, 21, 21) == 1) 9692 func (stream, "!"); 9693 break; 9694 9695 case 'B': 9696 print_mve_register_blocks (info, given, insn->mve_op); 9697 break; 9698 9699 case 'E': 9700 /* SIMD encoded constant for mov, mvn, vorr, vbic. */ 9701 9702 print_simd_imm8 (info, given, 28, insn); 9703 break; 9704 9705 case 'N': 9706 print_mve_vmov_index (info, given); 9707 break; 9708 9709 case 'T': 9710 if (arm_decode_field (given, 12, 12) == 0) 9711 func (stream, "b"); 9712 else 9713 func (stream, "t"); 9714 break; 9715 9716 case 'X': 9717 if (arm_decode_field (given, 12, 12) == 1) 9718 func (stream, "x"); 9719 break; 9720 9721 case '0': case '1': case '2': case '3': case '4': 9722 case '5': case '6': case '7': case '8': case '9': 9723 { 9724 int width; 9725 unsigned long value; 9726 9727 c = arm_decode_bitfield (c, given, &value, &width); 9728 9729 switch (*c) 9730 { 9731 case 'Z': 9732 if (value == 13) 9733 is_unpredictable = true; 9734 else if (value == 15) 9735 func (stream, "zr"); 9736 else 9737 func (stream, "%s", arm_regnames[value]); 9738 break; 9739 9740 case 'c': 9741 func (stream, "%s", arm_conditional[value]); 9742 break; 9743 9744 case 'C': 9745 value ^= 1; 9746 func (stream, "%s", arm_conditional[value]); 9747 break; 9748 9749 case 'S': 9750 if (value == 13 || value == 15) 9751 is_unpredictable = true; 9752 else 9753 func (stream, "%s", arm_regnames[value]); 9754 break; 9755 9756 case 's': 9757 print_mve_size (info, 9758 value, 9759 insn->mve_op); 9760 break; 9761 case 'I': 9762 if (value == 1) 9763 func (stream, "i"); 9764 break; 9765 case 'A': 9766 if (value == 1) 9767 func (stream, "a"); 9768 break; 9769 case 'h': 9770 { 9771 unsigned int odd_reg = (value << 1) | 1; 9772 func (stream, "%s", arm_regnames[odd_reg]); 9773 } 9774 break; 9775 case 'i': 9776 { 9777 unsigned long imm 9778 = arm_decode_field (given, 0, 6); 9779 unsigned long mod_imm = imm; 9780 9781 switch (insn->mve_op) 9782 { 9783 case MVE_VLDRW_GATHER_T5: 9784 case MVE_VSTRW_SCATTER_T5: 9785 mod_imm = mod_imm << 2; 9786 break; 9787 case MVE_VSTRD_SCATTER_T6: 9788 case MVE_VLDRD_GATHER_T6: 9789 mod_imm = mod_imm << 3; 9790 break; 9791 9792 default: 9793 break; 9794 } 9795 9796 func (stream, "%lu", mod_imm); 9797 } 9798 break; 9799 case 'k': 9800 func (stream, "%lu", 64 - value); 9801 break; 9802 case 'l': 9803 { 9804 unsigned int even_reg = value << 1; 9805 func (stream, "%s", arm_regnames[even_reg]); 9806 } 9807 break; 9808 case 'u': 9809 switch (value) 9810 { 9811 case 0: 9812 func (stream, "1"); 9813 break; 9814 case 1: 9815 func (stream, "2"); 9816 break; 9817 case 2: 9818 func (stream, "4"); 9819 break; 9820 case 3: 9821 func (stream, "8"); 9822 break; 9823 default: 9824 break; 9825 } 9826 break; 9827 case 'o': 9828 print_mve_rotate (info, value, width); 9829 break; 9830 case 'r': 9831 func (stream, "%s", arm_regnames[value]); 9832 break; 9833 case 'd': 9834 if (insn->mve_op == MVE_VQSHL_T2 9835 || insn->mve_op == MVE_VQSHLU_T3 9836 || insn->mve_op == MVE_VRSHR 9837 || insn->mve_op == MVE_VRSHRN 9838 || insn->mve_op == MVE_VSHL_T1 9839 || insn->mve_op == MVE_VSHLL_T1 9840 || insn->mve_op == MVE_VSHR 9841 || insn->mve_op == MVE_VSHRN 9842 || insn->mve_op == MVE_VSLI 9843 || insn->mve_op == MVE_VSRI) 9844 print_mve_shift_n (info, given, insn->mve_op); 9845 else if (insn->mve_op == MVE_VSHLL_T2) 9846 { 9847 switch (value) 9848 { 9849 case 0x00: 9850 func (stream, "8"); 9851 break; 9852 case 0x01: 9853 func (stream, "16"); 9854 break; 9855 case 0x10: 9856 print_mve_undefined (info, UNDEF_SIZE_0); 9857 break; 9858 default: 9859 assert (0); 9860 break; 9861 } 9862 } 9863 else 9864 { 9865 if (insn->mve_op == MVE_VSHLC && value == 0) 9866 value = 32; 9867 func (stream, "%ld", value); 9868 value_in_comment = value; 9869 } 9870 break; 9871 case 'F': 9872 func (stream, "s%ld", value); 9873 break; 9874 case 'Q': 9875 if (value & 0x8) 9876 func (stream, "<illegal reg q%ld.5>", value); 9877 else 9878 func (stream, "q%ld", value); 9879 break; 9880 case 'x': 9881 func (stream, "0x%08lx", value); 9882 break; 9883 default: 9884 abort (); 9885 } 9886 break; 9887 default: 9888 abort (); 9889 } 9890 } 9891 } 9892 else 9893 func (stream, "%c", *c); 9894 } 9895 9896 if (value_in_comment > 32 || value_in_comment < -16) 9897 func (stream, "\t; 0x%lx", value_in_comment); 9898 9899 if (is_unpredictable) 9900 print_mve_unpredictable (info, unpredictable_cond); 9901 9902 if (is_undefined) 9903 print_mve_undefined (info, undefined_cond); 9904 9905 if (!vpt_block_state.in_vpt_block 9906 && !ifthen_state 9907 && is_vpt_instruction (given)) 9908 mark_inside_vpt_block (given); 9909 else if (vpt_block_state.in_vpt_block) 9910 update_vpt_block_state (); 9911 9912 return true; 9913 } 9914 } 9915 return false; 9916} 9917 9918 9919/* Return the name of a v7A special register. */ 9920 9921static const char * 9922banked_regname (unsigned reg) 9923{ 9924 switch (reg) 9925 { 9926 case 15: return "CPSR"; 9927 case 32: return "R8_usr"; 9928 case 33: return "R9_usr"; 9929 case 34: return "R10_usr"; 9930 case 35: return "R11_usr"; 9931 case 36: return "R12_usr"; 9932 case 37: return "SP_usr"; 9933 case 38: return "LR_usr"; 9934 case 40: return "R8_fiq"; 9935 case 41: return "R9_fiq"; 9936 case 42: return "R10_fiq"; 9937 case 43: return "R11_fiq"; 9938 case 44: return "R12_fiq"; 9939 case 45: return "SP_fiq"; 9940 case 46: return "LR_fiq"; 9941 case 48: return "LR_irq"; 9942 case 49: return "SP_irq"; 9943 case 50: return "LR_svc"; 9944 case 51: return "SP_svc"; 9945 case 52: return "LR_abt"; 9946 case 53: return "SP_abt"; 9947 case 54: return "LR_und"; 9948 case 55: return "SP_und"; 9949 case 60: return "LR_mon"; 9950 case 61: return "SP_mon"; 9951 case 62: return "ELR_hyp"; 9952 case 63: return "SP_hyp"; 9953 case 79: return "SPSR"; 9954 case 110: return "SPSR_fiq"; 9955 case 112: return "SPSR_irq"; 9956 case 114: return "SPSR_svc"; 9957 case 116: return "SPSR_abt"; 9958 case 118: return "SPSR_und"; 9959 case 124: return "SPSR_mon"; 9960 case 126: return "SPSR_hyp"; 9961 default: return NULL; 9962 } 9963} 9964 9965/* Return the name of the DMB/DSB option. */ 9966static const char * 9967data_barrier_option (unsigned option) 9968{ 9969 switch (option & 0xf) 9970 { 9971 case 0xf: return "sy"; 9972 case 0xe: return "st"; 9973 case 0xd: return "ld"; 9974 case 0xb: return "ish"; 9975 case 0xa: return "ishst"; 9976 case 0x9: return "ishld"; 9977 case 0x7: return "un"; 9978 case 0x6: return "unst"; 9979 case 0x5: return "nshld"; 9980 case 0x3: return "osh"; 9981 case 0x2: return "oshst"; 9982 case 0x1: return "oshld"; 9983 default: return NULL; 9984 } 9985} 9986 9987/* Print one ARM instruction from PC on INFO->STREAM. */ 9988 9989static void 9990print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 9991{ 9992 const struct opcode32 *insn; 9993 void *stream = info->stream; 9994 fprintf_ftype func = info->fprintf_func; 9995 struct arm_private_data *private_data = info->private_data; 9996 9997 if (print_insn_coprocessor (pc, info, given, false)) 9998 return; 9999 10000 if (print_insn_neon (info, given, false)) 10001 return; 10002 10003 if (print_insn_generic_coprocessor (pc, info, given, false)) 10004 return; 10005 10006 for (insn = arm_opcodes; insn->assembler; insn++) 10007 { 10008 if ((given & insn->mask) != insn->value) 10009 continue; 10010 10011 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 10012 continue; 10013 10014 /* Special case: an instruction with all bits set in the condition field 10015 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 10016 or by the catchall at the end of the table. */ 10017 if ((given & 0xF0000000) != 0xF0000000 10018 || (insn->mask & 0xF0000000) == 0xF0000000 10019 || (insn->mask == 0 && insn->value == 0)) 10020 { 10021 unsigned long u_reg = 16; 10022 unsigned long U_reg = 16; 10023 bool is_unpredictable = false; 10024 signed long value_in_comment = 0; 10025 const char *c; 10026 10027 for (c = insn->assembler; *c; c++) 10028 { 10029 if (*c == '%') 10030 { 10031 bool allow_unpredictable = false; 10032 10033 switch (*++c) 10034 { 10035 case '%': 10036 func (stream, "%%"); 10037 break; 10038 10039 case 'a': 10040 value_in_comment = print_arm_address (pc, info, given); 10041 break; 10042 10043 case 'P': 10044 /* Set P address bit and use normal address 10045 printing routine. */ 10046 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 10047 break; 10048 10049 case 'S': 10050 allow_unpredictable = true; 10051 /* Fall through. */ 10052 case 's': 10053 if ((given & 0x004f0000) == 0x004f0000) 10054 { 10055 /* PC relative with immediate offset. */ 10056 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 10057 10058 if (PRE_BIT_SET) 10059 { 10060 /* Elide positive zero offset. */ 10061 if (offset || NEGATIVE_BIT_SET) 10062 func (stream, "[pc, #%s%d]\t; ", 10063 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10064 else 10065 func (stream, "[pc]\t; "); 10066 if (NEGATIVE_BIT_SET) 10067 offset = -offset; 10068 info->print_address_func (offset + pc + 8, info); 10069 } 10070 else 10071 { 10072 /* Always show the offset. */ 10073 func (stream, "[pc], #%s%d", 10074 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 10075 if (! allow_unpredictable) 10076 is_unpredictable = true; 10077 } 10078 } 10079 else 10080 { 10081 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 10082 10083 func (stream, "[%s", 10084 arm_regnames[(given >> 16) & 0xf]); 10085 10086 if (PRE_BIT_SET) 10087 { 10088 if (IMMEDIATE_BIT_SET) 10089 { 10090 /* Elide offset for non-writeback 10091 positive zero. */ 10092 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 10093 || offset) 10094 func (stream, ", #%s%d", 10095 NEGATIVE_BIT_SET ? "-" : "", offset); 10096 10097 if (NEGATIVE_BIT_SET) 10098 offset = -offset; 10099 10100 value_in_comment = offset; 10101 } 10102 else 10103 { 10104 /* Register Offset or Register Pre-Indexed. */ 10105 func (stream, ", %s%s", 10106 NEGATIVE_BIT_SET ? "-" : "", 10107 arm_regnames[given & 0xf]); 10108 10109 /* Writing back to the register that is the source/ 10110 destination of the load/store is unpredictable. */ 10111 if (! allow_unpredictable 10112 && WRITEBACK_BIT_SET 10113 && ((given & 0xf) == ((given >> 12) & 0xf))) 10114 is_unpredictable = true; 10115 } 10116 10117 func (stream, "]%s", 10118 WRITEBACK_BIT_SET ? "!" : ""); 10119 } 10120 else 10121 { 10122 if (IMMEDIATE_BIT_SET) 10123 { 10124 /* Immediate Post-indexed. */ 10125 /* PR 10924: Offset must be printed, even if it is zero. */ 10126 func (stream, "], #%s%d", 10127 NEGATIVE_BIT_SET ? "-" : "", offset); 10128 if (NEGATIVE_BIT_SET) 10129 offset = -offset; 10130 value_in_comment = offset; 10131 } 10132 else 10133 { 10134 /* Register Post-indexed. */ 10135 func (stream, "], %s%s", 10136 NEGATIVE_BIT_SET ? "-" : "", 10137 arm_regnames[given & 0xf]); 10138 10139 /* Writing back to the register that is the source/ 10140 destination of the load/store is unpredictable. */ 10141 if (! allow_unpredictable 10142 && (given & 0xf) == ((given >> 12) & 0xf)) 10143 is_unpredictable = true; 10144 } 10145 10146 if (! allow_unpredictable) 10147 { 10148 /* Writeback is automatically implied by post- addressing. 10149 Setting the W bit is unnecessary and ARM specify it as 10150 being unpredictable. */ 10151 if (WRITEBACK_BIT_SET 10152 /* Specifying the PC register as the post-indexed 10153 registers is also unpredictable. */ 10154 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 10155 is_unpredictable = true; 10156 } 10157 } 10158 } 10159 break; 10160 10161 case 'b': 10162 { 10163 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 10164 bfd_vma target = disp * 4 + pc + 8; 10165 info->print_address_func (target, info); 10166 10167 /* Fill in instruction information. */ 10168 info->insn_info_valid = 1; 10169 info->insn_type = dis_branch; 10170 info->target = target; 10171 } 10172 break; 10173 10174 case 'c': 10175 if (((given >> 28) & 0xf) != 0xe) 10176 func (stream, "%s", 10177 arm_conditional [(given >> 28) & 0xf]); 10178 break; 10179 10180 case 'm': 10181 { 10182 int started = 0; 10183 int reg; 10184 10185 func (stream, "{"); 10186 for (reg = 0; reg < 16; reg++) 10187 if ((given & (1 << reg)) != 0) 10188 { 10189 if (started) 10190 func (stream, ", "); 10191 started = 1; 10192 func (stream, "%s", arm_regnames[reg]); 10193 } 10194 func (stream, "}"); 10195 if (! started) 10196 is_unpredictable = true; 10197 } 10198 break; 10199 10200 case 'q': 10201 arm_decode_shift (given, func, stream, false); 10202 break; 10203 10204 case 'o': 10205 if ((given & 0x02000000) != 0) 10206 { 10207 unsigned int rotate = (given & 0xf00) >> 7; 10208 unsigned int immed = (given & 0xff); 10209 unsigned int a, i; 10210 10211 a = (immed << ((32 - rotate) & 31) 10212 | immed >> rotate) & 0xffffffff; 10213 /* If there is another encoding with smaller rotate, 10214 the rotate should be specified directly. */ 10215 for (i = 0; i < 32; i += 2) 10216 if ((a << i | a >> ((32 - i) & 31)) <= 0xff) 10217 break; 10218 10219 if (i != rotate) 10220 func (stream, "#%d, %d", immed, rotate); 10221 else 10222 func (stream, "#%d", a); 10223 value_in_comment = a; 10224 } 10225 else 10226 arm_decode_shift (given, func, stream, true); 10227 break; 10228 10229 case 'p': 10230 if ((given & 0x0000f000) == 0x0000f000) 10231 { 10232 arm_feature_set arm_ext_v6 = 10233 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 10234 10235 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 10236 mechanism for setting PSR flag bits. They are 10237 obsolete in V6 onwards. */ 10238 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 10239 arm_ext_v6)) 10240 func (stream, "p"); 10241 else 10242 is_unpredictable = true; 10243 } 10244 break; 10245 10246 case 't': 10247 if ((given & 0x01200000) == 0x00200000) 10248 func (stream, "t"); 10249 break; 10250 10251 case 'A': 10252 { 10253 int offset = given & 0xff; 10254 10255 value_in_comment = offset * 4; 10256 if (NEGATIVE_BIT_SET) 10257 value_in_comment = - value_in_comment; 10258 10259 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 10260 10261 if (PRE_BIT_SET) 10262 { 10263 if (offset) 10264 func (stream, ", #%d]%s", 10265 (int) value_in_comment, 10266 WRITEBACK_BIT_SET ? "!" : ""); 10267 else 10268 func (stream, "]"); 10269 } 10270 else 10271 { 10272 func (stream, "]"); 10273 10274 if (WRITEBACK_BIT_SET) 10275 { 10276 if (offset) 10277 func (stream, ", #%d", (int) value_in_comment); 10278 } 10279 else 10280 { 10281 func (stream, ", {%d}", (int) offset); 10282 value_in_comment = offset; 10283 } 10284 } 10285 } 10286 break; 10287 10288 case 'B': 10289 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 10290 { 10291 bfd_vma address; 10292 bfd_vma offset = 0; 10293 10294 if (! NEGATIVE_BIT_SET) 10295 /* Is signed, hi bits should be ones. */ 10296 offset = (-1) ^ 0x00ffffff; 10297 10298 /* Offset is (SignExtend(offset field)<<2). */ 10299 offset += given & 0x00ffffff; 10300 offset <<= 2; 10301 address = offset + pc + 8; 10302 10303 if (given & 0x01000000) 10304 /* H bit allows addressing to 2-byte boundaries. */ 10305 address += 2; 10306 10307 info->print_address_func (address, info); 10308 10309 /* Fill in instruction information. */ 10310 info->insn_info_valid = 1; 10311 info->insn_type = dis_branch; 10312 info->target = address; 10313 } 10314 break; 10315 10316 case 'C': 10317 if ((given & 0x02000200) == 0x200) 10318 { 10319 const char * name; 10320 unsigned sysm = (given & 0x004f0000) >> 16; 10321 10322 sysm |= (given & 0x300) >> 4; 10323 name = banked_regname (sysm); 10324 10325 if (name != NULL) 10326 func (stream, "%s", name); 10327 else 10328 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 10329 } 10330 else 10331 { 10332 func (stream, "%cPSR_", 10333 (given & 0x00400000) ? 'S' : 'C'); 10334 if (given & 0x80000) 10335 func (stream, "f"); 10336 if (given & 0x40000) 10337 func (stream, "s"); 10338 if (given & 0x20000) 10339 func (stream, "x"); 10340 if (given & 0x10000) 10341 func (stream, "c"); 10342 } 10343 break; 10344 10345 case 'U': 10346 if ((given & 0xf0) == 0x60) 10347 { 10348 switch (given & 0xf) 10349 { 10350 case 0xf: func (stream, "sy"); break; 10351 default: 10352 func (stream, "#%d", (int) given & 0xf); 10353 break; 10354 } 10355 } 10356 else 10357 { 10358 const char * opt = data_barrier_option (given & 0xf); 10359 if (opt != NULL) 10360 func (stream, "%s", opt); 10361 else 10362 func (stream, "#%d", (int) given & 0xf); 10363 } 10364 break; 10365 10366 case '0': case '1': case '2': case '3': case '4': 10367 case '5': case '6': case '7': case '8': case '9': 10368 { 10369 int width; 10370 unsigned long value; 10371 10372 c = arm_decode_bitfield (c, given, &value, &width); 10373 10374 switch (*c) 10375 { 10376 case 'R': 10377 if (value == 15) 10378 is_unpredictable = true; 10379 /* Fall through. */ 10380 case 'r': 10381 case 'T': 10382 /* We want register + 1 when decoding T. */ 10383 if (*c == 'T') 10384 value = (value + 1) & 0xf; 10385 10386 if (c[1] == 'u') 10387 { 10388 /* Eat the 'u' character. */ 10389 ++ c; 10390 10391 if (u_reg == value) 10392 is_unpredictable = true; 10393 u_reg = value; 10394 } 10395 if (c[1] == 'U') 10396 { 10397 /* Eat the 'U' character. */ 10398 ++ c; 10399 10400 if (U_reg == value) 10401 is_unpredictable = true; 10402 U_reg = value; 10403 } 10404 func (stream, "%s", arm_regnames[value]); 10405 break; 10406 case 'd': 10407 func (stream, "%ld", value); 10408 value_in_comment = value; 10409 break; 10410 case 'b': 10411 func (stream, "%ld", value * 8); 10412 value_in_comment = value * 8; 10413 break; 10414 case 'W': 10415 func (stream, "%ld", value + 1); 10416 value_in_comment = value + 1; 10417 break; 10418 case 'x': 10419 func (stream, "0x%08lx", value); 10420 10421 /* Some SWI instructions have special 10422 meanings. */ 10423 if ((given & 0x0fffffff) == 0x0FF00000) 10424 func (stream, "\t; IMB"); 10425 else if ((given & 0x0fffffff) == 0x0FF00001) 10426 func (stream, "\t; IMBRange"); 10427 break; 10428 case 'X': 10429 func (stream, "%01lx", value & 0xf); 10430 value_in_comment = value; 10431 break; 10432 case '`': 10433 c++; 10434 if (value == 0) 10435 func (stream, "%c", *c); 10436 break; 10437 case '\'': 10438 c++; 10439 if (value == ((1ul << width) - 1)) 10440 func (stream, "%c", *c); 10441 break; 10442 case '?': 10443 func (stream, "%c", c[(1 << width) - (int) value]); 10444 c += 1 << width; 10445 break; 10446 default: 10447 abort (); 10448 } 10449 } 10450 break; 10451 10452 case 'e': 10453 { 10454 int imm; 10455 10456 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 10457 func (stream, "%d", imm); 10458 value_in_comment = imm; 10459 } 10460 break; 10461 10462 case 'E': 10463 /* LSB and WIDTH fields of BFI or BFC. The machine- 10464 language instruction encodes LSB and MSB. */ 10465 { 10466 long msb = (given & 0x001f0000) >> 16; 10467 long lsb = (given & 0x00000f80) >> 7; 10468 long w = msb - lsb + 1; 10469 10470 if (w > 0) 10471 func (stream, "#%lu, #%lu", lsb, w); 10472 else 10473 func (stream, "(invalid: %lu:%lu)", lsb, msb); 10474 } 10475 break; 10476 10477 case 'R': 10478 /* Get the PSR/banked register name. */ 10479 { 10480 const char * name; 10481 unsigned sysm = (given & 0x004f0000) >> 16; 10482 10483 sysm |= (given & 0x300) >> 4; 10484 name = banked_regname (sysm); 10485 10486 if (name != NULL) 10487 func (stream, "%s", name); 10488 else 10489 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 10490 } 10491 break; 10492 10493 case 'V': 10494 /* 16-bit unsigned immediate from a MOVT or MOVW 10495 instruction, encoded in bits 0:11 and 15:19. */ 10496 { 10497 long hi = (given & 0x000f0000) >> 4; 10498 long lo = (given & 0x00000fff); 10499 long imm16 = hi | lo; 10500 10501 func (stream, "#%lu", imm16); 10502 value_in_comment = imm16; 10503 } 10504 break; 10505 10506 default: 10507 abort (); 10508 } 10509 } 10510 else 10511 func (stream, "%c", *c); 10512 } 10513 10514 if (value_in_comment > 32 || value_in_comment < -16) 10515 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 10516 10517 if (is_unpredictable) 10518 func (stream, UNPREDICTABLE_INSTRUCTION); 10519 10520 return; 10521 } 10522 } 10523 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 10524 return; 10525} 10526 10527/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 10528 10529static void 10530print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 10531{ 10532 const struct opcode16 *insn; 10533 void *stream = info->stream; 10534 fprintf_ftype func = info->fprintf_func; 10535 10536 for (insn = thumb_opcodes; insn->assembler; insn++) 10537 if ((given & insn->mask) == insn->value) 10538 { 10539 signed long value_in_comment = 0; 10540 const char *c = insn->assembler; 10541 10542 for (; *c; c++) 10543 { 10544 int domaskpc = 0; 10545 int domasklr = 0; 10546 10547 if (*c != '%') 10548 { 10549 func (stream, "%c", *c); 10550 continue; 10551 } 10552 10553 switch (*++c) 10554 { 10555 case '%': 10556 func (stream, "%%"); 10557 break; 10558 10559 case 'c': 10560 if (ifthen_state) 10561 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10562 break; 10563 10564 case 'C': 10565 if (ifthen_state) 10566 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10567 else 10568 func (stream, "s"); 10569 break; 10570 10571 case 'I': 10572 { 10573 unsigned int tmp; 10574 10575 ifthen_next_state = given & 0xff; 10576 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 10577 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 10578 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 10579 } 10580 break; 10581 10582 case 'x': 10583 if (ifthen_next_state) 10584 func (stream, "\t; unpredictable branch in IT block\n"); 10585 break; 10586 10587 case 'X': 10588 if (ifthen_state) 10589 func (stream, "\t; unpredictable <IT:%s>", 10590 arm_conditional[IFTHEN_COND]); 10591 break; 10592 10593 case 'S': 10594 { 10595 long reg; 10596 10597 reg = (given >> 3) & 0x7; 10598 if (given & (1 << 6)) 10599 reg += 8; 10600 10601 func (stream, "%s", arm_regnames[reg]); 10602 } 10603 break; 10604 10605 case 'D': 10606 { 10607 long reg; 10608 10609 reg = given & 0x7; 10610 if (given & (1 << 7)) 10611 reg += 8; 10612 10613 func (stream, "%s", arm_regnames[reg]); 10614 } 10615 break; 10616 10617 case 'N': 10618 if (given & (1 << 8)) 10619 domasklr = 1; 10620 /* Fall through. */ 10621 case 'O': 10622 if (*c == 'O' && (given & (1 << 8))) 10623 domaskpc = 1; 10624 /* Fall through. */ 10625 case 'M': 10626 { 10627 int started = 0; 10628 int reg; 10629 10630 func (stream, "{"); 10631 10632 /* It would be nice if we could spot 10633 ranges, and generate the rS-rE format: */ 10634 for (reg = 0; (reg < 8); reg++) 10635 if ((given & (1 << reg)) != 0) 10636 { 10637 if (started) 10638 func (stream, ", "); 10639 started = 1; 10640 func (stream, "%s", arm_regnames[reg]); 10641 } 10642 10643 if (domasklr) 10644 { 10645 if (started) 10646 func (stream, ", "); 10647 started = 1; 10648 func (stream, "%s", arm_regnames[14] /* "lr" */); 10649 } 10650 10651 if (domaskpc) 10652 { 10653 if (started) 10654 func (stream, ", "); 10655 func (stream, "%s", arm_regnames[15] /* "pc" */); 10656 } 10657 10658 func (stream, "}"); 10659 } 10660 break; 10661 10662 case 'W': 10663 /* Print writeback indicator for a LDMIA. We are doing a 10664 writeback if the base register is not in the register 10665 mask. */ 10666 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 10667 func (stream, "!"); 10668 break; 10669 10670 case 'b': 10671 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 10672 { 10673 bfd_vma address = (pc + 4 10674 + ((given & 0x00f8) >> 2) 10675 + ((given & 0x0200) >> 3)); 10676 info->print_address_func (address, info); 10677 10678 /* Fill in instruction information. */ 10679 info->insn_info_valid = 1; 10680 info->insn_type = dis_branch; 10681 info->target = address; 10682 } 10683 break; 10684 10685 case 's': 10686 /* Right shift immediate -- bits 6..10; 1-31 print 10687 as themselves, 0 prints as 32. */ 10688 { 10689 long imm = (given & 0x07c0) >> 6; 10690 if (imm == 0) 10691 imm = 32; 10692 func (stream, "#%ld", imm); 10693 } 10694 break; 10695 10696 case '0': case '1': case '2': case '3': case '4': 10697 case '5': case '6': case '7': case '8': case '9': 10698 { 10699 int bitstart = *c++ - '0'; 10700 int bitend = 0; 10701 10702 while (*c >= '0' && *c <= '9') 10703 bitstart = (bitstart * 10) + *c++ - '0'; 10704 10705 switch (*c) 10706 { 10707 case '-': 10708 { 10709 bfd_vma reg; 10710 10711 c++; 10712 while (*c >= '0' && *c <= '9') 10713 bitend = (bitend * 10) + *c++ - '0'; 10714 if (!bitend) 10715 abort (); 10716 reg = given >> bitstart; 10717 reg &= ((bfd_vma) 2 << (bitend - bitstart)) - 1; 10718 10719 switch (*c) 10720 { 10721 case 'r': 10722 func (stream, "%s", arm_regnames[reg]); 10723 break; 10724 10725 case 'd': 10726 func (stream, "%ld", (long) reg); 10727 value_in_comment = reg; 10728 break; 10729 10730 case 'H': 10731 func (stream, "%ld", (long) (reg << 1)); 10732 value_in_comment = reg << 1; 10733 break; 10734 10735 case 'W': 10736 func (stream, "%ld", (long) (reg << 2)); 10737 value_in_comment = reg << 2; 10738 break; 10739 10740 case 'a': 10741 /* PC-relative address -- the bottom two 10742 bits of the address are dropped 10743 before the calculation. */ 10744 info->print_address_func 10745 (((pc + 4) & ~3) + (reg << 2), info); 10746 value_in_comment = 0; 10747 break; 10748 10749 case 'x': 10750 func (stream, "0x%04lx", (long) reg); 10751 break; 10752 10753 case 'B': 10754 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 10755 bfd_vma target = reg * 2 + pc + 4; 10756 info->print_address_func (target, info); 10757 value_in_comment = 0; 10758 10759 /* Fill in instruction information. */ 10760 info->insn_info_valid = 1; 10761 info->insn_type = dis_branch; 10762 info->target = target; 10763 break; 10764 10765 case 'c': 10766 func (stream, "%s", arm_conditional [reg]); 10767 break; 10768 10769 default: 10770 abort (); 10771 } 10772 } 10773 break; 10774 10775 case '\'': 10776 c++; 10777 if ((given & (1 << bitstart)) != 0) 10778 func (stream, "%c", *c); 10779 break; 10780 10781 case '?': 10782 ++c; 10783 if ((given & (1 << bitstart)) != 0) 10784 func (stream, "%c", *c++); 10785 else 10786 func (stream, "%c", *++c); 10787 break; 10788 10789 default: 10790 abort (); 10791 } 10792 } 10793 break; 10794 10795 default: 10796 abort (); 10797 } 10798 } 10799 10800 if (value_in_comment > 32 || value_in_comment < -16) 10801 func (stream, "\t; 0x%lx", value_in_comment); 10802 return; 10803 } 10804 10805 /* No match. */ 10806 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given); 10807 return; 10808} 10809 10810/* Return the name of an V7M special register. */ 10811 10812static const char * 10813psr_name (int regno) 10814{ 10815 switch (regno) 10816 { 10817 case 0x0: return "APSR"; 10818 case 0x1: return "IAPSR"; 10819 case 0x2: return "EAPSR"; 10820 case 0x3: return "PSR"; 10821 case 0x5: return "IPSR"; 10822 case 0x6: return "EPSR"; 10823 case 0x7: return "IEPSR"; 10824 case 0x8: return "MSP"; 10825 case 0x9: return "PSP"; 10826 case 0xa: return "MSPLIM"; 10827 case 0xb: return "PSPLIM"; 10828 case 0x10: return "PRIMASK"; 10829 case 0x11: return "BASEPRI"; 10830 case 0x12: return "BASEPRI_MAX"; 10831 case 0x13: return "FAULTMASK"; 10832 case 0x14: return "CONTROL"; 10833 case 0x88: return "MSP_NS"; 10834 case 0x89: return "PSP_NS"; 10835 case 0x8a: return "MSPLIM_NS"; 10836 case 0x8b: return "PSPLIM_NS"; 10837 case 0x90: return "PRIMASK_NS"; 10838 case 0x91: return "BASEPRI_NS"; 10839 case 0x93: return "FAULTMASK_NS"; 10840 case 0x94: return "CONTROL_NS"; 10841 case 0x98: return "SP_NS"; 10842 default: return "<unknown>"; 10843 } 10844} 10845 10846/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 10847 10848static void 10849print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 10850{ 10851 const struct opcode32 *insn; 10852 void *stream = info->stream; 10853 fprintf_ftype func = info->fprintf_func; 10854 bool is_mve = is_mve_architecture (info); 10855 10856 if (print_insn_coprocessor (pc, info, given, true)) 10857 return; 10858 10859 if (!is_mve && print_insn_neon (info, given, true)) 10860 return; 10861 10862 if (is_mve && print_insn_mve (info, given)) 10863 return; 10864 10865 if (print_insn_cde (info, given, true)) 10866 return; 10867 10868 if (print_insn_generic_coprocessor (pc, info, given, true)) 10869 return; 10870 10871 for (insn = thumb32_opcodes; insn->assembler; insn++) 10872 if ((given & insn->mask) == insn->value) 10873 { 10874 bool is_clrm = false; 10875 bool is_unpredictable = false; 10876 signed long value_in_comment = 0; 10877 const char *c = insn->assembler; 10878 10879 for (; *c; c++) 10880 { 10881 if (*c != '%') 10882 { 10883 func (stream, "%c", *c); 10884 continue; 10885 } 10886 10887 switch (*++c) 10888 { 10889 case '%': 10890 func (stream, "%%"); 10891 break; 10892 10893 case 'c': 10894 if (ifthen_state) 10895 func (stream, "%s", arm_conditional[IFTHEN_COND]); 10896 break; 10897 10898 case 'x': 10899 if (ifthen_next_state) 10900 func (stream, "\t; unpredictable branch in IT block\n"); 10901 break; 10902 10903 case 'X': 10904 if (ifthen_state) 10905 func (stream, "\t; unpredictable <IT:%s>", 10906 arm_conditional[IFTHEN_COND]); 10907 break; 10908 10909 case 'I': 10910 { 10911 unsigned int imm12 = 0; 10912 10913 imm12 |= (given & 0x000000ffu); 10914 imm12 |= (given & 0x00007000u) >> 4; 10915 imm12 |= (given & 0x04000000u) >> 15; 10916 func (stream, "#%u", imm12); 10917 value_in_comment = imm12; 10918 } 10919 break; 10920 10921 case 'M': 10922 { 10923 unsigned int bits = 0, imm, imm8, mod; 10924 10925 bits |= (given & 0x000000ffu); 10926 bits |= (given & 0x00007000u) >> 4; 10927 bits |= (given & 0x04000000u) >> 15; 10928 imm8 = (bits & 0x0ff); 10929 mod = (bits & 0xf00) >> 8; 10930 switch (mod) 10931 { 10932 case 0: imm = imm8; break; 10933 case 1: imm = ((imm8 << 16) | imm8); break; 10934 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 10935 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 10936 default: 10937 mod = (bits & 0xf80) >> 7; 10938 imm8 = (bits & 0x07f) | 0x80; 10939 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 10940 } 10941 func (stream, "#%u", imm); 10942 value_in_comment = imm; 10943 } 10944 break; 10945 10946 case 'J': 10947 { 10948 unsigned int imm = 0; 10949 10950 imm |= (given & 0x000000ffu); 10951 imm |= (given & 0x00007000u) >> 4; 10952 imm |= (given & 0x04000000u) >> 15; 10953 imm |= (given & 0x000f0000u) >> 4; 10954 func (stream, "#%u", imm); 10955 value_in_comment = imm; 10956 } 10957 break; 10958 10959 case 'K': 10960 { 10961 unsigned int imm = 0; 10962 10963 imm |= (given & 0x000f0000u) >> 16; 10964 imm |= (given & 0x00000ff0u) >> 0; 10965 imm |= (given & 0x0000000fu) << 12; 10966 func (stream, "#%u", imm); 10967 value_in_comment = imm; 10968 } 10969 break; 10970 10971 case 'H': 10972 { 10973 unsigned int imm = 0; 10974 10975 imm |= (given & 0x000f0000u) >> 4; 10976 imm |= (given & 0x00000fffu) >> 0; 10977 func (stream, "#%u", imm); 10978 value_in_comment = imm; 10979 } 10980 break; 10981 10982 case 'V': 10983 { 10984 unsigned int imm = 0; 10985 10986 imm |= (given & 0x00000fffu); 10987 imm |= (given & 0x000f0000u) >> 4; 10988 func (stream, "#%u", imm); 10989 value_in_comment = imm; 10990 } 10991 break; 10992 10993 case 'S': 10994 { 10995 unsigned int reg = (given & 0x0000000fu); 10996 unsigned int stp = (given & 0x00000030u) >> 4; 10997 unsigned int imm = 0; 10998 imm |= (given & 0x000000c0u) >> 6; 10999 imm |= (given & 0x00007000u) >> 10; 11000 11001 func (stream, "%s", arm_regnames[reg]); 11002 switch (stp) 11003 { 11004 case 0: 11005 if (imm > 0) 11006 func (stream, ", lsl #%u", imm); 11007 break; 11008 11009 case 1: 11010 if (imm == 0) 11011 imm = 32; 11012 func (stream, ", lsr #%u", imm); 11013 break; 11014 11015 case 2: 11016 if (imm == 0) 11017 imm = 32; 11018 func (stream, ", asr #%u", imm); 11019 break; 11020 11021 case 3: 11022 if (imm == 0) 11023 func (stream, ", rrx"); 11024 else 11025 func (stream, ", ror #%u", imm); 11026 } 11027 } 11028 break; 11029 11030 case 'a': 11031 { 11032 unsigned int Rn = (given & 0x000f0000) >> 16; 11033 unsigned int U = ! NEGATIVE_BIT_SET; 11034 unsigned int op = (given & 0x00000f00) >> 8; 11035 unsigned int i12 = (given & 0x00000fff); 11036 unsigned int i8 = (given & 0x000000ff); 11037 bool writeback = false, postind = false; 11038 bfd_vma offset = 0; 11039 11040 func (stream, "[%s", arm_regnames[Rn]); 11041 if (U) /* 12-bit positive immediate offset. */ 11042 { 11043 offset = i12; 11044 if (Rn != 15) 11045 value_in_comment = offset; 11046 } 11047 else if (Rn == 15) /* 12-bit negative immediate offset. */ 11048 offset = - (int) i12; 11049 else if (op == 0x0) /* Shifted register offset. */ 11050 { 11051 unsigned int Rm = (i8 & 0x0f); 11052 unsigned int sh = (i8 & 0x30) >> 4; 11053 11054 func (stream, ", %s", arm_regnames[Rm]); 11055 if (sh) 11056 func (stream, ", lsl #%u", sh); 11057 func (stream, "]"); 11058 break; 11059 } 11060 else switch (op) 11061 { 11062 case 0xE: /* 8-bit positive immediate offset. */ 11063 offset = i8; 11064 break; 11065 11066 case 0xC: /* 8-bit negative immediate offset. */ 11067 offset = -i8; 11068 break; 11069 11070 case 0xF: /* 8-bit + preindex with wb. */ 11071 offset = i8; 11072 writeback = true; 11073 break; 11074 11075 case 0xD: /* 8-bit - preindex with wb. */ 11076 offset = -i8; 11077 writeback = true; 11078 break; 11079 11080 case 0xB: /* 8-bit + postindex. */ 11081 offset = i8; 11082 postind = true; 11083 break; 11084 11085 case 0x9: /* 8-bit - postindex. */ 11086 offset = -i8; 11087 postind = true; 11088 break; 11089 11090 default: 11091 func (stream, ", <undefined>]"); 11092 goto skip; 11093 } 11094 11095 if (postind) 11096 func (stream, "], #%d", (int) offset); 11097 else 11098 { 11099 if (offset) 11100 func (stream, ", #%d", (int) offset); 11101 func (stream, writeback ? "]!" : "]"); 11102 } 11103 11104 if (Rn == 15) 11105 { 11106 func (stream, "\t; "); 11107 info->print_address_func (((pc + 4) & ~3) + offset, info); 11108 } 11109 } 11110 skip: 11111 break; 11112 11113 case 'A': 11114 { 11115 unsigned int U = ! NEGATIVE_BIT_SET; 11116 unsigned int W = WRITEBACK_BIT_SET; 11117 unsigned int Rn = (given & 0x000f0000) >> 16; 11118 unsigned int off = (given & 0x000000ff); 11119 11120 func (stream, "[%s", arm_regnames[Rn]); 11121 11122 if (PRE_BIT_SET) 11123 { 11124 if (off || !U) 11125 { 11126 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 11127 value_in_comment = off * 4 * (U ? 1 : -1); 11128 } 11129 func (stream, "]"); 11130 if (W) 11131 func (stream, "!"); 11132 } 11133 else 11134 { 11135 func (stream, "], "); 11136 if (W) 11137 { 11138 func (stream, "#%c%u", U ? '+' : '-', off * 4); 11139 value_in_comment = off * 4 * (U ? 1 : -1); 11140 } 11141 else 11142 { 11143 func (stream, "{%u}", off); 11144 value_in_comment = off; 11145 } 11146 } 11147 } 11148 break; 11149 11150 case 'w': 11151 { 11152 unsigned int Sbit = (given & 0x01000000) >> 24; 11153 unsigned int type = (given & 0x00600000) >> 21; 11154 11155 switch (type) 11156 { 11157 case 0: func (stream, Sbit ? "sb" : "b"); break; 11158 case 1: func (stream, Sbit ? "sh" : "h"); break; 11159 case 2: 11160 if (Sbit) 11161 func (stream, "??"); 11162 break; 11163 case 3: 11164 func (stream, "??"); 11165 break; 11166 } 11167 } 11168 break; 11169 11170 case 'n': 11171 is_clrm = true; 11172 /* Fall through. */ 11173 case 'm': 11174 { 11175 int started = 0; 11176 int reg; 11177 11178 func (stream, "{"); 11179 for (reg = 0; reg < 16; reg++) 11180 if ((given & (1 << reg)) != 0) 11181 { 11182 if (started) 11183 func (stream, ", "); 11184 started = 1; 11185 if (is_clrm && reg == 13) 11186 func (stream, "(invalid: %s)", arm_regnames[reg]); 11187 else if (is_clrm && reg == 15) 11188 func (stream, "%s", "APSR"); 11189 else 11190 func (stream, "%s", arm_regnames[reg]); 11191 } 11192 func (stream, "}"); 11193 } 11194 break; 11195 11196 case 'E': 11197 { 11198 unsigned int msb = (given & 0x0000001f); 11199 unsigned int lsb = 0; 11200 11201 lsb |= (given & 0x000000c0u) >> 6; 11202 lsb |= (given & 0x00007000u) >> 10; 11203 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 11204 } 11205 break; 11206 11207 case 'F': 11208 { 11209 unsigned int width = (given & 0x0000001f) + 1; 11210 unsigned int lsb = 0; 11211 11212 lsb |= (given & 0x000000c0u) >> 6; 11213 lsb |= (given & 0x00007000u) >> 10; 11214 func (stream, "#%u, #%u", lsb, width); 11215 } 11216 break; 11217 11218 case 'G': 11219 { 11220 unsigned int boff = (((given & 0x07800000) >> 23) << 1); 11221 func (stream, "%x", boff); 11222 } 11223 break; 11224 11225 case 'W': 11226 { 11227 unsigned int immA = (given & 0x001f0000u) >> 16; 11228 unsigned int immB = (given & 0x000007feu) >> 1; 11229 unsigned int immC = (given & 0x00000800u) >> 11; 11230 bfd_vma offset = 0; 11231 11232 offset |= immA << 12; 11233 offset |= immB << 2; 11234 offset |= immC << 1; 11235 /* Sign extend. */ 11236 offset = (offset & 0x10000) ? offset - (1 << 17) : offset; 11237 11238 info->print_address_func (pc + 4 + offset, info); 11239 } 11240 break; 11241 11242 case 'Y': 11243 { 11244 unsigned int immA = (given & 0x007f0000u) >> 16; 11245 unsigned int immB = (given & 0x000007feu) >> 1; 11246 unsigned int immC = (given & 0x00000800u) >> 11; 11247 bfd_vma offset = 0; 11248 11249 offset |= immA << 12; 11250 offset |= immB << 2; 11251 offset |= immC << 1; 11252 /* Sign extend. */ 11253 offset = (offset & 0x40000) ? offset - (1 << 19) : offset; 11254 11255 info->print_address_func (pc + 4 + offset, info); 11256 } 11257 break; 11258 11259 case 'Z': 11260 { 11261 unsigned int immA = (given & 0x00010000u) >> 16; 11262 unsigned int immB = (given & 0x000007feu) >> 1; 11263 unsigned int immC = (given & 0x00000800u) >> 11; 11264 bfd_vma offset = 0; 11265 11266 offset |= immA << 12; 11267 offset |= immB << 2; 11268 offset |= immC << 1; 11269 /* Sign extend. */ 11270 offset = (offset & 0x1000) ? offset - (1 << 13) : offset; 11271 11272 info->print_address_func (pc + 4 + offset, info); 11273 11274 unsigned int T = (given & 0x00020000u) >> 17; 11275 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1); 11276 unsigned int boffset = (T == 1) ? 4 : 2; 11277 func (stream, ", "); 11278 func (stream, "%x", endoffset + boffset); 11279 } 11280 break; 11281 11282 case 'Q': 11283 { 11284 unsigned int immh = (given & 0x000007feu) >> 1; 11285 unsigned int imml = (given & 0x00000800u) >> 11; 11286 bfd_vma imm32 = 0; 11287 11288 imm32 |= immh << 2; 11289 imm32 |= imml << 1; 11290 11291 info->print_address_func (pc + 4 + imm32, info); 11292 } 11293 break; 11294 11295 case 'P': 11296 { 11297 unsigned int immh = (given & 0x000007feu) >> 1; 11298 unsigned int imml = (given & 0x00000800u) >> 11; 11299 bfd_vma imm32 = 0; 11300 11301 imm32 |= immh << 2; 11302 imm32 |= imml << 1; 11303 11304 info->print_address_func (pc + 4 - imm32, info); 11305 } 11306 break; 11307 11308 case 'b': 11309 { 11310 unsigned int S = (given & 0x04000000u) >> 26; 11311 unsigned int J1 = (given & 0x00002000u) >> 13; 11312 unsigned int J2 = (given & 0x00000800u) >> 11; 11313 bfd_vma offset = 0; 11314 11315 offset |= !S << 20; 11316 offset |= J2 << 19; 11317 offset |= J1 << 18; 11318 offset |= (given & 0x003f0000) >> 4; 11319 offset |= (given & 0x000007ff) << 1; 11320 offset -= (1 << 20); 11321 11322 bfd_vma target = pc + 4 + offset; 11323 info->print_address_func (target, info); 11324 11325 /* Fill in instruction information. */ 11326 info->insn_info_valid = 1; 11327 info->insn_type = dis_branch; 11328 info->target = target; 11329 } 11330 break; 11331 11332 case 'B': 11333 { 11334 unsigned int S = (given & 0x04000000u) >> 26; 11335 unsigned int I1 = (given & 0x00002000u) >> 13; 11336 unsigned int I2 = (given & 0x00000800u) >> 11; 11337 bfd_vma offset = 0; 11338 11339 offset |= !S << 24; 11340 offset |= !(I1 ^ S) << 23; 11341 offset |= !(I2 ^ S) << 22; 11342 offset |= (given & 0x03ff0000u) >> 4; 11343 offset |= (given & 0x000007ffu) << 1; 11344 offset -= (1 << 24); 11345 offset += pc + 4; 11346 11347 /* BLX target addresses are always word aligned. */ 11348 if ((given & 0x00001000u) == 0) 11349 offset &= ~2u; 11350 11351 info->print_address_func (offset, info); 11352 11353 /* Fill in instruction information. */ 11354 info->insn_info_valid = 1; 11355 info->insn_type = dis_branch; 11356 info->target = offset; 11357 } 11358 break; 11359 11360 case 's': 11361 { 11362 unsigned int shift = 0; 11363 11364 shift |= (given & 0x000000c0u) >> 6; 11365 shift |= (given & 0x00007000u) >> 10; 11366 if (WRITEBACK_BIT_SET) 11367 func (stream, ", asr #%u", shift); 11368 else if (shift) 11369 func (stream, ", lsl #%u", shift); 11370 /* else print nothing - lsl #0 */ 11371 } 11372 break; 11373 11374 case 'R': 11375 { 11376 unsigned int rot = (given & 0x00000030) >> 4; 11377 11378 if (rot) 11379 func (stream, ", ror #%u", rot * 8); 11380 } 11381 break; 11382 11383 case 'U': 11384 if ((given & 0xf0) == 0x60) 11385 { 11386 switch (given & 0xf) 11387 { 11388 case 0xf: func (stream, "sy"); break; 11389 default: 11390 func (stream, "#%d", (int) given & 0xf); 11391 break; 11392 } 11393 } 11394 else 11395 { 11396 const char * opt = data_barrier_option (given & 0xf); 11397 if (opt != NULL) 11398 func (stream, "%s", opt); 11399 else 11400 func (stream, "#%d", (int) given & 0xf); 11401 } 11402 break; 11403 11404 case 'C': 11405 if ((given & 0xff) == 0) 11406 { 11407 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 11408 if (given & 0x800) 11409 func (stream, "f"); 11410 if (given & 0x400) 11411 func (stream, "s"); 11412 if (given & 0x200) 11413 func (stream, "x"); 11414 if (given & 0x100) 11415 func (stream, "c"); 11416 } 11417 else if ((given & 0x20) == 0x20) 11418 { 11419 char const* name; 11420 unsigned sysm = (given & 0xf00) >> 8; 11421 11422 sysm |= (given & 0x30); 11423 sysm |= (given & 0x00100000) >> 14; 11424 name = banked_regname (sysm); 11425 11426 if (name != NULL) 11427 func (stream, "%s", name); 11428 else 11429 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 11430 } 11431 else 11432 { 11433 func (stream, "%s", psr_name (given & 0xff)); 11434 } 11435 break; 11436 11437 case 'D': 11438 if (((given & 0xff) == 0) 11439 || ((given & 0x20) == 0x20)) 11440 { 11441 char const* name; 11442 unsigned sm = (given & 0xf0000) >> 16; 11443 11444 sm |= (given & 0x30); 11445 sm |= (given & 0x00100000) >> 14; 11446 name = banked_regname (sm); 11447 11448 if (name != NULL) 11449 func (stream, "%s", name); 11450 else 11451 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 11452 } 11453 else 11454 func (stream, "%s", psr_name (given & 0xff)); 11455 break; 11456 11457 case '0': case '1': case '2': case '3': case '4': 11458 case '5': case '6': case '7': case '8': case '9': 11459 { 11460 int width; 11461 unsigned long val; 11462 11463 c = arm_decode_bitfield (c, given, &val, &width); 11464 11465 switch (*c) 11466 { 11467 case 's': 11468 if (val <= 3) 11469 func (stream, "%s", mve_vec_sizename[val]); 11470 else 11471 func (stream, "<undef size>"); 11472 break; 11473 11474 case 'd': 11475 func (stream, "%lu", val); 11476 value_in_comment = val; 11477 break; 11478 11479 case 'D': 11480 func (stream, "%lu", val + 1); 11481 value_in_comment = val + 1; 11482 break; 11483 11484 case 'W': 11485 func (stream, "%lu", val * 4); 11486 value_in_comment = val * 4; 11487 break; 11488 11489 case 'S': 11490 if (val == 13) 11491 is_unpredictable = true; 11492 /* Fall through. */ 11493 case 'R': 11494 if (val == 15) 11495 is_unpredictable = true; 11496 /* Fall through. */ 11497 case 'r': 11498 func (stream, "%s", arm_regnames[val]); 11499 break; 11500 11501 case 'c': 11502 func (stream, "%s", arm_conditional[val]); 11503 break; 11504 11505 case '\'': 11506 c++; 11507 if (val == ((1ul << width) - 1)) 11508 func (stream, "%c", *c); 11509 break; 11510 11511 case '`': 11512 c++; 11513 if (val == 0) 11514 func (stream, "%c", *c); 11515 break; 11516 11517 case '?': 11518 func (stream, "%c", c[(1 << width) - (int) val]); 11519 c += 1 << width; 11520 break; 11521 11522 case 'x': 11523 func (stream, "0x%lx", val & 0xffffffffUL); 11524 break; 11525 11526 default: 11527 abort (); 11528 } 11529 } 11530 break; 11531 11532 case 'L': 11533 /* PR binutils/12534 11534 If we have a PC relative offset in an LDRD or STRD 11535 instructions then display the decoded address. */ 11536 if (((given >> 16) & 0xf) == 0xf) 11537 { 11538 bfd_vma offset = (given & 0xff) * 4; 11539 11540 if ((given & (1 << 23)) == 0) 11541 offset = - offset; 11542 func (stream, "\t; "); 11543 info->print_address_func ((pc & ~3) + 4 + offset, info); 11544 } 11545 break; 11546 11547 default: 11548 abort (); 11549 } 11550 } 11551 11552 if (value_in_comment > 32 || value_in_comment < -16) 11553 func (stream, "\t; 0x%lx", value_in_comment); 11554 11555 if (is_unpredictable) 11556 func (stream, UNPREDICTABLE_INSTRUCTION); 11557 11558 return; 11559 } 11560 11561 /* No match. */ 11562 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); 11563 return; 11564} 11565 11566/* Print data bytes on INFO->STREAM. */ 11567 11568static void 11569print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 11570 struct disassemble_info *info, 11571 long given) 11572{ 11573 switch (info->bytes_per_chunk) 11574 { 11575 case 1: 11576 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 11577 break; 11578 case 2: 11579 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 11580 break; 11581 case 4: 11582 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 11583 break; 11584 default: 11585 abort (); 11586 } 11587} 11588 11589/* Disallow mapping symbols ($a, $b, $d, $t etc) from 11590 being displayed in symbol relative addresses. 11591 11592 Also disallow private symbol, with __tagsym$$ prefix, 11593 from ARM RVCT toolchain being displayed. */ 11594 11595bool 11596arm_symbol_is_valid (asymbol * sym, 11597 struct disassemble_info * info ATTRIBUTE_UNUSED) 11598{ 11599 const char * name; 11600 11601 if (sym == NULL) 11602 return false; 11603 11604 name = bfd_asymbol_name (sym); 11605 11606 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 11607} 11608 11609/* Parse the string of disassembler options. */ 11610 11611static void 11612parse_arm_disassembler_options (const char *options) 11613{ 11614 const char *opt; 11615 11616 force_thumb = false; 11617 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 11618 { 11619 if (startswith (opt, "reg-names-")) 11620 { 11621 unsigned int i; 11622 for (i = 0; i < NUM_ARM_OPTIONS; i++) 11623 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 11624 { 11625 regname_selected = i; 11626 break; 11627 } 11628 11629 if (i >= NUM_ARM_OPTIONS) 11630 /* xgettext: c-format */ 11631 opcodes_error_handler (_("unrecognised register name set: %s"), 11632 opt); 11633 } 11634 else if (startswith (opt, "force-thumb")) 11635 force_thumb = 1; 11636 else if (startswith (opt, "no-force-thumb")) 11637 force_thumb = 0; 11638 else if (startswith (opt, "coproc")) 11639 { 11640 const char *procptr = opt + sizeof ("coproc") - 1; 11641 char *endptr; 11642 uint8_t coproc_number = strtol (procptr, &endptr, 10); 11643 if (endptr != procptr + 1 || coproc_number > 7) 11644 { 11645 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"), 11646 opt); 11647 continue; 11648 } 11649 if (*endptr != '=') 11650 { 11651 opcodes_error_handler (_("coproc must have an argument: %s"), 11652 opt); 11653 continue; 11654 } 11655 endptr += 1; 11656 if (startswith (endptr, "generic")) 11657 cde_coprocs &= ~(1 << coproc_number); 11658 else if (startswith (endptr, "cde") 11659 || startswith (endptr, "CDE")) 11660 cde_coprocs |= (1 << coproc_number); 11661 else 11662 { 11663 opcodes_error_handler ( 11664 _("coprocN argument takes options \"generic\"," 11665 " \"cde\", or \"CDE\": %s"), opt); 11666 } 11667 } 11668 else 11669 /* xgettext: c-format */ 11670 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 11671 } 11672 11673 return; 11674} 11675 11676static bool 11677mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 11678 enum map_type *map_symbol); 11679 11680/* Search back through the insn stream to determine if this instruction is 11681 conditionally executed. */ 11682 11683static void 11684find_ifthen_state (bfd_vma pc, 11685 struct disassemble_info *info, 11686 bool little) 11687{ 11688 unsigned char b[2]; 11689 unsigned int insn; 11690 int status; 11691 /* COUNT is twice the number of instructions seen. It will be odd if we 11692 just crossed an instruction boundary. */ 11693 int count; 11694 int it_count; 11695 unsigned int seen_it; 11696 bfd_vma addr; 11697 11698 ifthen_address = pc; 11699 ifthen_state = 0; 11700 11701 addr = pc; 11702 count = 1; 11703 it_count = 0; 11704 seen_it = 0; 11705 /* Scan backwards looking for IT instructions, keeping track of where 11706 instruction boundaries are. We don't know if something is actually an 11707 IT instruction until we find a definite instruction boundary. */ 11708 for (;;) 11709 { 11710 if (addr == 0 || info->symbol_at_address_func (addr, info)) 11711 { 11712 /* A symbol must be on an instruction boundary, and will not 11713 be within an IT block. */ 11714 if (seen_it && (count & 1)) 11715 break; 11716 11717 return; 11718 } 11719 addr -= 2; 11720 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 11721 if (status) 11722 return; 11723 11724 if (little) 11725 insn = (b[0]) | (b[1] << 8); 11726 else 11727 insn = (b[1]) | (b[0] << 8); 11728 if (seen_it) 11729 { 11730 if ((insn & 0xf800) < 0xe800) 11731 { 11732 /* Addr + 2 is an instruction boundary. See if this matches 11733 the expected boundary based on the position of the last 11734 IT candidate. */ 11735 if (count & 1) 11736 break; 11737 seen_it = 0; 11738 } 11739 } 11740 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 11741 { 11742 enum map_type type = MAP_ARM; 11743 bool found = mapping_symbol_for_insn (addr, info, &type); 11744 11745 if (!found || (found && type == MAP_THUMB)) 11746 { 11747 /* This could be an IT instruction. */ 11748 seen_it = insn; 11749 it_count = count >> 1; 11750 } 11751 } 11752 if ((insn & 0xf800) >= 0xe800) 11753 count++; 11754 else 11755 count = (count + 2) | 1; 11756 /* IT blocks contain at most 4 instructions. */ 11757 if (count >= 8 && !seen_it) 11758 return; 11759 } 11760 /* We found an IT instruction. */ 11761 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 11762 if ((ifthen_state & 0xf) == 0) 11763 ifthen_state = 0; 11764} 11765 11766/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 11767 mapping symbol. */ 11768 11769static int 11770is_mapping_symbol (struct disassemble_info *info, int n, 11771 enum map_type *map_type) 11772{ 11773 const char *name; 11774 11775 name = bfd_asymbol_name (info->symtab[n]); 11776 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 11777 && (name[2] == 0 || name[2] == '.')) 11778 { 11779 *map_type = ((name[1] == 'a') ? MAP_ARM 11780 : (name[1] == 't') ? MAP_THUMB 11781 : MAP_DATA); 11782 return true; 11783 } 11784 11785 return false; 11786} 11787 11788/* Try to infer the code type (ARM or Thumb) from a mapping symbol. 11789 Returns nonzero if *MAP_TYPE was set. */ 11790 11791static int 11792get_map_sym_type (struct disassemble_info *info, 11793 int n, 11794 enum map_type *map_type) 11795{ 11796 /* If the symbol is in a different section, ignore it. */ 11797 if (info->section != NULL && info->section != info->symtab[n]->section) 11798 return false; 11799 11800 return is_mapping_symbol (info, n, map_type); 11801} 11802 11803/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 11804 Returns nonzero if *MAP_TYPE was set. */ 11805 11806static int 11807get_sym_code_type (struct disassemble_info *info, 11808 int n, 11809 enum map_type *map_type) 11810{ 11811 elf_symbol_type *es; 11812 unsigned int type; 11813 11814 /* If the symbol is in a different section, ignore it. */ 11815 if (info->section != NULL && info->section != info->symtab[n]->section) 11816 return false; 11817 11818 es = *(elf_symbol_type **)(info->symtab + n); 11819 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 11820 11821 /* If the symbol has function type then use that. */ 11822 if (type == STT_FUNC || type == STT_GNU_IFUNC) 11823 { 11824 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 11825 == ST_BRANCH_TO_THUMB) 11826 *map_type = MAP_THUMB; 11827 else 11828 *map_type = MAP_ARM; 11829 return true; 11830 } 11831 11832 return false; 11833} 11834 11835/* Search the mapping symbol state for instruction at pc. This is only 11836 applicable for elf target. 11837 11838 There is an assumption Here, info->private_data contains the correct AND 11839 up-to-date information about current scan process. The information will be 11840 used to speed this search process. 11841 11842 Return TRUE if the mapping state can be determined, and map_symbol 11843 will be updated accordingly. Otherwise, return FALSE. */ 11844 11845static bool 11846mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 11847 enum map_type *map_symbol) 11848{ 11849 bfd_vma addr, section_vma = 0; 11850 int n, last_sym = -1; 11851 bool found = false; 11852 bool can_use_search_opt_p = false; 11853 11854 /* Default to DATA. A text section is required by the ABI to contain an 11855 INSN mapping symbol at the start. A data section has no such 11856 requirement, hence if no mapping symbol is found the section must 11857 contain only data. This however isn't very useful if the user has 11858 fully stripped the binaries. If this is the case use the section 11859 attributes to determine the default. If we have no section default to 11860 INSN as well, as we may be disassembling some raw bytes on a baremetal 11861 HEX file or similar. */ 11862 enum map_type type = MAP_DATA; 11863 if ((info->section && info->section->flags & SEC_CODE) || !info->section) 11864 type = MAP_ARM; 11865 struct arm_private_data *private_data; 11866 11867 if (info->private_data == NULL 11868 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 11869 return false; 11870 11871 private_data = info->private_data; 11872 11873 /* First, look for mapping symbols. */ 11874 if (info->symtab_size != 0) 11875 { 11876 if (pc <= private_data->last_mapping_addr) 11877 private_data->last_mapping_sym = -1; 11878 11879 /* Start scanning at the start of the function, or wherever 11880 we finished last time. */ 11881 n = info->symtab_pos + 1; 11882 11883 /* If the last stop offset is different from the current one it means we 11884 are disassembling a different glob of bytes. As such the optimization 11885 would not be safe and we should start over. */ 11886 can_use_search_opt_p 11887 = private_data->last_mapping_sym >= 0 11888 && info->stop_offset == private_data->last_stop_offset; 11889 11890 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 11891 n = private_data->last_mapping_sym; 11892 11893 /* Look down while we haven't passed the location being disassembled. 11894 The reason for this is that there's no defined order between a symbol 11895 and an mapping symbol that may be at the same address. We may have to 11896 look at least one position ahead. */ 11897 for (; n < info->symtab_size; n++) 11898 { 11899 addr = bfd_asymbol_value (info->symtab[n]); 11900 if (addr > pc) 11901 break; 11902 if (get_map_sym_type (info, n, &type)) 11903 { 11904 last_sym = n; 11905 found = true; 11906 } 11907 } 11908 11909 if (!found) 11910 { 11911 n = info->symtab_pos; 11912 if (n >= private_data->last_mapping_sym && can_use_search_opt_p) 11913 n = private_data->last_mapping_sym; 11914 11915 /* No mapping symbol found at this address. Look backwards 11916 for a preceeding one, but don't go pass the section start 11917 otherwise a data section with no mapping symbol can pick up 11918 a text mapping symbol of a preceeding section. The documentation 11919 says section can be NULL, in which case we will seek up all the 11920 way to the top. */ 11921 if (info->section) 11922 section_vma = info->section->vma; 11923 11924 for (; n >= 0; n--) 11925 { 11926 addr = bfd_asymbol_value (info->symtab[n]); 11927 if (addr < section_vma) 11928 break; 11929 11930 if (get_map_sym_type (info, n, &type)) 11931 { 11932 last_sym = n; 11933 found = true; 11934 break; 11935 } 11936 } 11937 } 11938 } 11939 11940 /* If no mapping symbol was found, try looking up without a mapping 11941 symbol. This is done by walking up from the current PC to the nearest 11942 symbol. We don't actually have to loop here since symtab_pos will 11943 contain the nearest symbol already. */ 11944 if (!found) 11945 { 11946 n = info->symtab_pos; 11947 if (n >= 0 && get_sym_code_type (info, n, &type)) 11948 { 11949 last_sym = n; 11950 found = true; 11951 } 11952 } 11953 11954 private_data->last_mapping_sym = last_sym; 11955 private_data->last_type = type; 11956 private_data->last_stop_offset = info->stop_offset; 11957 11958 *map_symbol = type; 11959 return found; 11960} 11961 11962/* Given a bfd_mach_arm_XXX value, this function fills in the fields 11963 of the supplied arm_feature_set structure with bitmasks indicating 11964 the supported base architectures and coprocessor extensions. 11965 11966 FIXME: This could more efficiently implemented as a constant array, 11967 although it would also be less robust. */ 11968 11969static void 11970select_arm_features (unsigned long mach, 11971 arm_feature_set * features) 11972{ 11973 arm_feature_set arch_fset; 11974 const arm_feature_set fpu_any = FPU_ANY; 11975 11976#undef ARM_SET_FEATURES 11977#define ARM_SET_FEATURES(FSET) \ 11978 { \ 11979 const arm_feature_set fset = FSET; \ 11980 arch_fset = fset; \ 11981 } 11982 11983 /* When several architecture versions share the same bfd_mach_arm_XXX value 11984 the most featureful is chosen. */ 11985 switch (mach) 11986 { 11987 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 11988 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 11989 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 11990 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 11991 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 11992 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 11993 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 11994 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 11995 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 11996 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 11997 case bfd_mach_arm_ep9312: 11998 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 11999 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 12000 break; 12001 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 12002 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 12003 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; 12004 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; 12005 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; 12006 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; 12007 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; 12008 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; 12009 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; 12010 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; 12011 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; 12012 case bfd_mach_arm_8: 12013 { 12014 /* Add bits for extensions that Armv8.6-A recognizes. */ 12015 arm_feature_set armv8_6_ext_fset 12016 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); 12017 ARM_SET_FEATURES (ARM_ARCH_V8_6A); 12018 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); 12019 break; 12020 } 12021 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; 12022 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; 12023 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; 12024 case bfd_mach_arm_8_1M_MAIN: 12025 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); 12026 arm_feature_set mve_all 12027 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP); 12028 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all); 12029 force_thumb = 1; 12030 break; 12031 case bfd_mach_arm_9: ARM_SET_FEATURES (ARM_ARCH_V9A); break; 12032 /* If the machine type is unknown allow all architecture types and all 12033 extensions, with the exception of MVE as that clashes with NEON. */ 12034 case bfd_mach_arm_unknown: 12035 ARM_SET_FEATURES (ARM_ARCH_UNKNOWN); 12036 break; 12037 default: 12038 abort (); 12039 } 12040#undef ARM_SET_FEATURES 12041 12042 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch 12043 and thus on bfd_mach_arm_XXX value. Therefore for a given 12044 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ 12045 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); 12046} 12047 12048 12049/* NOTE: There are no checks in these routines that 12050 the relevant number of data bytes exist. */ 12051 12052static int 12053print_insn (bfd_vma pc, struct disassemble_info *info, bool little) 12054{ 12055 unsigned char b[4]; 12056 unsigned long given; 12057 int status; 12058 int is_thumb = false; 12059 int is_data = false; 12060 int little_code; 12061 unsigned int size = 4; 12062 void (*printer) (bfd_vma, struct disassemble_info *, long); 12063 bool found = false; 12064 struct arm_private_data *private_data; 12065 12066 /* Clear instruction information field. */ 12067 info->insn_info_valid = 0; 12068 info->branch_delay_insns = 0; 12069 info->data_size = 0; 12070 info->insn_type = dis_noninsn; 12071 info->target = 0; 12072 info->target2 = 0; 12073 12074 if (info->disassembler_options) 12075 { 12076 parse_arm_disassembler_options (info->disassembler_options); 12077 12078 /* To avoid repeated parsing of these options, we remove them here. */ 12079 info->disassembler_options = NULL; 12080 } 12081 12082 /* PR 10288: Control which instructions will be disassembled. */ 12083 if (info->private_data == NULL) 12084 { 12085 static struct arm_private_data private; 12086 12087 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 12088 /* If the user did not use the -m command line switch then default to 12089 disassembling all types of ARM instruction. 12090 12091 The info->mach value has to be ignored as this will be based on 12092 the default archictecture for the target and/or hints in the notes 12093 section, but it will never be greater than the current largest arm 12094 machine value (iWMMXt2), which is only equivalent to the V5TE 12095 architecture. ARM architectures have advanced beyond the machine 12096 value encoding, and these newer architectures would be ignored if 12097 the machine value was used. 12098 12099 Ie the -m switch is used to restrict which instructions will be 12100 disassembled. If it is necessary to use the -m switch to tell 12101 objdump that an ARM binary is being disassembled, eg because the 12102 input is a raw binary file, but it is also desired to disassemble 12103 all ARM instructions then use "-marm". This will select the 12104 "unknown" arm architecture which is compatible with any ARM 12105 instruction. */ 12106 info->mach = bfd_mach_arm_unknown; 12107 12108 /* Compute the architecture bitmask from the machine number. 12109 Note: This assumes that the machine number will not change 12110 during disassembly.... */ 12111 select_arm_features (info->mach, & private.features); 12112 12113 private.last_mapping_sym = -1; 12114 private.last_mapping_addr = 0; 12115 private.last_stop_offset = 0; 12116 12117 info->private_data = & private; 12118 } 12119 12120 private_data = info->private_data; 12121 12122 /* Decide if our code is going to be little-endian, despite what the 12123 function argument might say. */ 12124 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 12125 12126 /* For ELF, consult the symbol table to determine what kind of code 12127 or data we have. */ 12128 if (info->symtab_size != 0 12129 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 12130 { 12131 bfd_vma addr; 12132 int n; 12133 int last_sym = -1; 12134 enum map_type type = MAP_ARM; 12135 12136 found = mapping_symbol_for_insn (pc, info, &type); 12137 last_sym = private_data->last_mapping_sym; 12138 12139 is_thumb = (private_data->last_type == MAP_THUMB); 12140 is_data = (private_data->last_type == MAP_DATA); 12141 12142 /* Look a little bit ahead to see if we should print out 12143 two or four bytes of data. If there's a symbol, 12144 mapping or otherwise, after two bytes then don't 12145 print more. */ 12146 if (is_data) 12147 { 12148 size = 4 - (pc & 3); 12149 for (n = last_sym + 1; n < info->symtab_size; n++) 12150 { 12151 addr = bfd_asymbol_value (info->symtab[n]); 12152 if (addr > pc 12153 && (info->section == NULL 12154 || info->section == info->symtab[n]->section)) 12155 { 12156 if (addr - pc < size) 12157 size = addr - pc; 12158 break; 12159 } 12160 } 12161 /* If the next symbol is after three bytes, we need to 12162 print only part of the data, so that we can use either 12163 .byte or .short. */ 12164 if (size == 3) 12165 size = (pc & 1) ? 1 : 2; 12166 } 12167 } 12168 12169 if (info->symbols != NULL) 12170 { 12171 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 12172 { 12173 coff_symbol_type * cs; 12174 12175 cs = coffsymbol (*info->symbols); 12176 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 12177 || cs->native->u.syment.n_sclass == C_THUMBSTAT 12178 || cs->native->u.syment.n_sclass == C_THUMBLABEL 12179 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 12180 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 12181 } 12182 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 12183 && !found) 12184 { 12185 /* If no mapping symbol has been found then fall back to the type 12186 of the function symbol. */ 12187 elf_symbol_type * es; 12188 unsigned int type; 12189 12190 es = *(elf_symbol_type **)(info->symbols); 12191 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 12192 12193 is_thumb = 12194 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 12195 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 12196 } 12197 else if (bfd_asymbol_flavour (*info->symbols) 12198 == bfd_target_mach_o_flavour) 12199 { 12200 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 12201 12202 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 12203 } 12204 } 12205 12206 if (force_thumb) 12207 is_thumb = true; 12208 12209 if (is_data) 12210 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12211 else 12212 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 12213 12214 info->bytes_per_line = 4; 12215 12216 /* PR 10263: Disassemble data if requested to do so by the user. */ 12217 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 12218 { 12219 int i; 12220 12221 /* Size was already set above. */ 12222 info->bytes_per_chunk = size; 12223 printer = print_insn_data; 12224 12225 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 12226 given = 0; 12227 if (little) 12228 for (i = size - 1; i >= 0; i--) 12229 given = b[i] | (given << 8); 12230 else 12231 for (i = 0; i < (int) size; i++) 12232 given = b[i] | (given << 8); 12233 } 12234 else if (!is_thumb) 12235 { 12236 /* In ARM mode endianness is a straightforward issue: the instruction 12237 is four bytes long and is either ordered 0123 or 3210. */ 12238 printer = print_insn_arm; 12239 info->bytes_per_chunk = 4; 12240 size = 4; 12241 12242 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 12243 if (little_code) 12244 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24); 12245 else 12246 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24); 12247 } 12248 else 12249 { 12250 /* In Thumb mode we have the additional wrinkle of two 12251 instruction lengths. Fortunately, the bits that determine 12252 the length of the current instruction are always to be found 12253 in the first two bytes. */ 12254 printer = print_insn_thumb16; 12255 info->bytes_per_chunk = 2; 12256 size = 2; 12257 12258 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 12259 if (little_code) 12260 given = (b[0]) | (b[1] << 8); 12261 else 12262 given = (b[1]) | (b[0] << 8); 12263 12264 if (!status) 12265 { 12266 /* These bit patterns signal a four-byte Thumb 12267 instruction. */ 12268 if ((given & 0xF800) == 0xF800 12269 || (given & 0xF800) == 0xF000 12270 || (given & 0xF800) == 0xE800) 12271 { 12272 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 12273 if (little_code) 12274 given = (b[0]) | (b[1] << 8) | (given << 16); 12275 else 12276 given = (b[1]) | (b[0] << 8) | (given << 16); 12277 12278 printer = print_insn_thumb32; 12279 size = 4; 12280 } 12281 } 12282 12283 if (ifthen_address != pc) 12284 find_ifthen_state (pc, info, little_code); 12285 12286 if (ifthen_state) 12287 { 12288 if ((ifthen_state & 0xf) == 0x8) 12289 ifthen_next_state = 0; 12290 else 12291 ifthen_next_state = (ifthen_state & 0xe0) 12292 | ((ifthen_state & 0xf) << 1); 12293 } 12294 } 12295 12296 if (status) 12297 { 12298 info->memory_error_func (status, pc, info); 12299 return -1; 12300 } 12301 if (info->flags & INSN_HAS_RELOC) 12302 /* If the instruction has a reloc associated with it, then 12303 the offset field in the instruction will actually be the 12304 addend for the reloc. (We are using REL type relocs). 12305 In such cases, we can ignore the pc when computing 12306 addresses, since the addend is not currently pc-relative. */ 12307 pc = 0; 12308 12309 printer (pc, info, given); 12310 12311 if (is_thumb) 12312 { 12313 ifthen_state = ifthen_next_state; 12314 ifthen_address += size; 12315 } 12316 return size; 12317} 12318 12319int 12320print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 12321{ 12322 /* Detect BE8-ness and record it in the disassembler info. */ 12323 if (info->flavour == bfd_target_elf_flavour 12324 && info->section != NULL 12325 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 12326 info->endian_code = BFD_ENDIAN_LITTLE; 12327 12328 return print_insn (pc, info, false); 12329} 12330 12331int 12332print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 12333{ 12334 return print_insn (pc, info, true); 12335} 12336 12337const disasm_options_and_args_t * 12338disassembler_options_arm (void) 12339{ 12340 static disasm_options_and_args_t *opts_and_args; 12341 12342 if (opts_and_args == NULL) 12343 { 12344 disasm_options_t *opts; 12345 unsigned int i; 12346 12347 opts_and_args = XNEW (disasm_options_and_args_t); 12348 opts_and_args->args = NULL; 12349 12350 opts = &opts_and_args->options; 12351 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12352 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 12353 opts->arg = NULL; 12354 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12355 { 12356 opts->name[i] = regnames[i].name; 12357 if (regnames[i].description != NULL) 12358 opts->description[i] = _(regnames[i].description); 12359 else 12360 opts->description[i] = NULL; 12361 } 12362 /* The array we return must be NULL terminated. */ 12363 opts->name[i] = NULL; 12364 opts->description[i] = NULL; 12365 } 12366 12367 return opts_and_args; 12368} 12369 12370void 12371print_arm_disassembler_options (FILE *stream) 12372{ 12373 unsigned int i, max_len = 0; 12374 fprintf (stream, _("\n\ 12375The following ARM specific disassembler options are supported for use with\n\ 12376the -M switch:\n")); 12377 12378 for (i = 0; i < NUM_ARM_OPTIONS; i++) 12379 { 12380 unsigned int len = strlen (regnames[i].name); 12381 if (max_len < len) 12382 max_len = len; 12383 } 12384 12385 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 12386 fprintf (stream, " %s%*c %s\n", 12387 regnames[i].name, 12388 (int)(max_len - strlen (regnames[i].name)), ' ', 12389 _(regnames[i].description)); 12390} 12391