1/* Copyright (C) 2021 Free Software Foundation, Inc. 2 Contributed by Oracle. 3 4 This file is part of GNU Binutils. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21/* Hardware counter profiling: cpu types */ 22 23#ifndef __HWC_CPUS_H 24#define __HWC_CPUS_H 25 26#define MAX_PICS 20 /* Max # of HW ctrs that can be enabled simultaneously */ 27 28 /* type for specifying CPU register number */ 29 typedef int regno_t; 30#define REGNO_ANY ((regno_t)-1) 31#define REGNO_INVALID ((regno_t)-2) 32 33 /* --- Utilities for use with regno_t and reg_list[] --- */ 34#define REG_LIST_IS_EMPTY(reg_list) (!(reg_list) || (reg_list)[0] == REGNO_ANY) 35#define REG_LIST_EOL(regno) ((regno)==REGNO_ANY) 36#define REG_LIST_SINGLE_VALID_ENTRY(reg_list) \ 37 (((reg_list) && (reg_list)[1] == REGNO_ANY && \ 38 (reg_list)[0] != REGNO_ANY ) ? (reg_list)[0] : REGNO_ANY) 39 40 /* enum for specifying unknown or uninitialized CPU */ 41 enum 42 { 43 CPUVER_GENERIC = 0, 44 CPUVER_UNDEFINED = -1 45 }; 46 47 // Note: changing an values below may make older HWC experiments unreadable. 48 // --- Sun/Oracle SPARC --- 49#define CPC_ULTRA1 1000 50#define CPC_ULTRA2 1001 51#define CPC_ULTRA3 1002 52#define CPC_ULTRA3_PLUS 1003 53#define CPC_ULTRA3_I 1004 54#define CPC_ULTRA4_PLUS 1005 /* Panther */ 55#define CPC_ULTRA4 1017 /* Jaguar */ 56#define CPC_ULTRA_T1 1100 /* Niagara1 */ 57#define CPC_ULTRA_T2 1101 /* Niagara2 */ 58#define CPC_ULTRA_T2P 1102 59#define CPC_ULTRA_T3 1103 60#define CPC_SPARC_T4 1104 61#define CPC_SPARC_T5 1110 62#define CPC_SPARC_T6 1120 63// #define CPC_SPARC_T7 1130 // use CPC_SPARC_M7 64#define CPC_SPARC_M4 1204 /* Obsolete */ 65#define CPC_SPARC_M5 1210 66#define CPC_SPARC_M6 1220 67#define CPC_SPARC_M7 1230 68#define CPC_SPARC_M8 1240 69 70 // --- Intel --- 71 // Pentium 72#define CPC_PENTIUM 2000 73#define CPC_PENTIUM_MMX 2001 74#define CPC_PENTIUM_PRO 2002 75#define CPC_PENTIUM_PRO_MMX 2003 76#define CPC_PENTIUM_4 2017 77#define CPC_PENTIUM_4_HT 2027 78 79 // Core Microarchitecture (Merom/Menryn) 80#define CPC_INTEL_CORE2 2028 81#define CPC_INTEL_NEHALEM 2040 82#define CPC_INTEL_WESTMERE 2042 83#define CPC_INTEL_SANDYBRIDGE 2045 84#define CPC_INTEL_IVYBRIDGE 2047 85#define CPC_INTEL_ATOM 2050 /* Atom*/ 86#define CPC_INTEL_HASWELL 2060 87#define CPC_INTEL_BROADWELL 2070 88#define CPC_INTEL_SKYLAKE 2080 89#define CPC_INTEL_UNKNOWN 2499 90#define CPC_AMD_K8C 2500 /* Opteron, Athlon... */ 91#define CPC_AMD_FAM_10H 2501 /* Barcelona, Shanghai... */ 92#define CPC_AMD_FAM_11H 2502 /* Griffin... */ 93#define CPC_AMD_FAM_15H 2503 94#define CPC_KPROF 3003 // OBSOLETE (To support 12.3 and earlier) 95#define CPC_FOX 3004 /* pseudo-chip */ 96 97 // --- Fujitsu --- 98#define CPC_SPARC64_III 3000 99#define CPC_SPARC64_V 3002 100#define CPC_SPARC64_VI 4003 /* OPL-C */ 101#define CPC_SPARC64_VII 4004 /* Jupiter */ 102#define CPC_SPARC64_X 4006 /* Athena */ 103#define CPC_SPARC64_XII 4010 /* Athena++ */ 104 105// aarch64. Constants from arch/arm64/include/asm/cputype.h 106enum { 107 ARM_CPU_IMP_ARM = 0x41, 108 ARM_CPU_IMP_BRCM = 0x42, 109 ARM_CPU_IMP_CAVIUM = 0x43, 110 ARM_CPU_IMP_APM = 0x50, 111 ARM_CPU_IMP_QCOM = 0x51 112}; 113 114#define AARCH64_VENDORSTR_ARM "ARM" 115 116 /* strings below must match those returned by cpc_getcpuver() */ 117 typedef struct 118 { 119 int cpc2_cpuver; 120 const char * cpc2_cciname; 121 } libcpc2_cpu_lookup_t; 122#define LIBCPC2_CPU_LOOKUP_LIST \ 123 {CPC_AMD_K8C , "AMD Opteron & Athlon64"}, \ 124 {CPC_AMD_FAM_10H , "AMD Family 10h"}, \ 125 {CPC_AMD_FAM_11H , "AMD Family 11h"}, \ 126 {CPC_AMD_FAM_15H , "AMD Family 15h Model 01h"}, \ 127 {CPC_AMD_FAM_15H , "AMD Family 15h Model 02h"},/*future*/ \ 128 {CPC_AMD_FAM_15H , "AMD Family 15h Model 03h"},/*future*/ \ 129 {CPC_PENTIUM_4_HT , "Pentium 4 with HyperThreading"}, \ 130 {CPC_PENTIUM_4 , "Pentium 4"}, \ 131 {CPC_PENTIUM_PRO_MMX , "Pentium Pro with MMX, Pentium II"}, \ 132 {CPC_PENTIUM_PRO , "Pentium Pro, Pentium II"}, \ 133 {CPC_PENTIUM_MMX , "Pentium with MMX"}, \ 134 {CPC_PENTIUM , "Pentium"}, \ 135 {CPC_INTEL_CORE2 , "Core Microarchitecture"}, \ 136 /* Merom: F6M15: Clovertown, Kentsfield, Conroe, Merom, Woodcrest */ \ 137 /* Merom: F6M22: Merom Conroe */ \ 138 /* Penryn: F6M23: Yorkfield, Wolfdale, Penryn, Harpertown */ \ 139 /* Penryn: F6M29: Dunnington */ \ 140 {CPC_INTEL_NEHALEM , "Intel Arch PerfMon v3 on Family 6 Model 26"},/*Bloomfield, Nehalem EP*/ \ 141 {CPC_INTEL_NEHALEM , "Intel Arch PerfMon v3 on Family 6 Model 30"},/*Clarksfield, Lynnfield, Jasper Forest*/ \ 142 {CPC_INTEL_NEHALEM , "Intel Arch PerfMon v3 on Family 6 Model 31"},/*(TBD)*/ \ 143 {CPC_INTEL_NEHALEM , "Intel Arch PerfMon v3 on Family 6 Model 46"},/*Nehalem EX*/ \ 144 {CPC_INTEL_WESTMERE , "Intel Arch PerfMon v3 on Family 6 Model 37"},/*Arrandale, Clarskdale*/ \ 145 {CPC_INTEL_WESTMERE , "Intel Arch PerfMon v3 on Family 6 Model 44"},/*Gulftown, Westmere EP*/ \ 146 {CPC_INTEL_WESTMERE , "Intel Arch PerfMon v3 on Family 6 Model 47"},/*Westmere EX*/ \ 147 {CPC_INTEL_SANDYBRIDGE , "Intel Arch PerfMon v3 on Family 6 Model 42"},/*Sandy Bridge*/ \ 148 {CPC_INTEL_SANDYBRIDGE , "Intel Arch PerfMon v3 on Family 6 Model 45"},/*Sandy Bridge E, SandyBridge-EN, SandyBridge EP*/ \ 149 {CPC_INTEL_IVYBRIDGE , "Intel Arch PerfMon v3 on Family 6 Model 58"},/*Ivy Bridge*/ \ 150 {CPC_INTEL_IVYBRIDGE , "Intel Arch PerfMon v3 on Family 6 Model 62"},/*(TBD)*/ \ 151 {CPC_INTEL_ATOM , "Intel Arch PerfMon v3 on Family 6 Model 28"},/*Atom*/ \ 152 {CPC_INTEL_HASWELL , "Intel Arch PerfMon v3 on Family 6 Model 60"},/*Haswell*/ \ 153 {CPC_INTEL_HASWELL , "Intel Arch PerfMon v3 on Family 6 Model 63"},/*Haswell*/ \ 154 {CPC_INTEL_HASWELL , "Intel Arch PerfMon v3 on Family 6 Model 69"},/*Haswell*/ \ 155 {CPC_INTEL_HASWELL , "Intel Arch PerfMon v3 on Family 6 Model 70"},/*Haswell*/ \ 156 {CPC_INTEL_BROADWELL , "Intel Arch PerfMon v3 on Family 6 Model 61"},/*Broadwell*/ \ 157 {CPC_INTEL_BROADWELL , "Intel Arch PerfMon v3 on Family 6 Model 71"},/*Broadwell*/ \ 158 {CPC_INTEL_BROADWELL , "Intel Arch PerfMon v3 on Family 6 Model 79"},/*Broadwell*/ \ 159 {CPC_INTEL_BROADWELL , "Intel Arch PerfMon v3 on Family 6 Model 86"},/*Broadwell*/ \ 160 {CPC_INTEL_SKYLAKE , "Intel Arch PerfMon v4 on Family 6 Model 78"},/*Skylake*/ \ 161 {CPC_INTEL_SKYLAKE , "Intel Arch PerfMon v4 on Family 6 Model 85"},/*Skylake*/ \ 162 {CPC_INTEL_SKYLAKE , "Intel Arch PerfMon v4 on Family 6 Model 94"},/*Skylake*/ \ 163 {CPC_INTEL_UNKNOWN , "Intel Arch PerfMon"},/*Not yet in table*/ \ 164 {CPC_SPARC64_III , "SPARC64 III"/*?*/}, \ 165 {CPC_SPARC64_V , "SPARC64 V"/*?*/}, \ 166 {CPC_SPARC64_VI , "SPARC64 VI"}, \ 167 {CPC_SPARC64_VII , "SPARC64 VI & VII"}, \ 168 {CPC_SPARC64_X , "SPARC64 X"}, \ 169 {CPC_SPARC64_XII , "SPARC64 XII"}, \ 170 {CPC_ULTRA_T1 , "UltraSPARC T1"}, \ 171 {CPC_ULTRA_T2 , "UltraSPARC T2"}, \ 172 {CPC_ULTRA_T2P , "UltraSPARC T2+"}, \ 173 {CPC_ULTRA_T3 , "SPARC T3"}, \ 174 {CPC_SPARC_T4 , "SPARC T4"}, \ 175 {CPC_SPARC_M4 , "SPARC M4"}, \ 176 {CPC_SPARC_T5 , "SPARC T5"}, \ 177 {CPC_SPARC_M5 , "SPARC M5"}, \ 178 {CPC_SPARC_T6 , "SPARC T6"}, \ 179 {CPC_SPARC_M6 , "SPARC M6"}, \ 180 {CPC_SPARC_M7 , "SPARC T7"}, \ 181 {CPC_SPARC_M7 , "SPARC 3e40"}, \ 182 {CPC_SPARC_M7 , "SPARC M7"}, \ 183 {CPC_SPARC_M8 , "SPARC 3e50"}, \ 184 {CPC_ULTRA4_PLUS , "UltraSPARC IV+"}, \ 185 {CPC_ULTRA4 , "UltraSPARC IV"}, \ 186 {CPC_ULTRA3_I , "UltraSPARC IIIi"}, \ 187 {CPC_ULTRA3_I , "UltraSPARC IIIi & IIIi+"}, \ 188 {CPC_ULTRA3_PLUS , "UltraSPARC III+"}, \ 189 {CPC_ULTRA3_PLUS , "UltraSPARC III+ & IV"}, \ 190 {CPC_ULTRA3 , "UltraSPARC III"}, \ 191 {CPC_ULTRA2 , "UltraSPARC I&II"}, \ 192 {CPC_ULTRA1 , "UltraSPARC I&II"}, \ 193 {ARM_CPU_IMP_APM , AARCH64_VENDORSTR_ARM}, \ 194 {0, NULL} 195 /* init like this: 196 static libcpc2_cpu_lookup_t cpu_table[]={LIBCPC2_CPU_LOOKUP_LIST}; 197 */ 198#endif 199