1/* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright (C) 1993-2020 Free Software Foundation, Inc. 3 Contributed by the OSF and Ralph Campbell. 4 Written by Keith Knowles and Ralph Campbell, working independently. 5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 6 Support. 7 8 This file is part of GAS. 9 10 GAS is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 GAS is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GAS; see the file COPYING. If not, write to the Free 22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 23 02110-1301, USA. */ 24 25#include "as.h" 26#include "config.h" 27#include "subsegs.h" 28#include "safe-ctype.h" 29 30#include "opcode/mips.h" 31#include "itbl-ops.h" 32#include "dwarf2dbg.h" 33#include "dw2gencfi.h" 34 35/* Check assumptions made in this file. */ 36typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; 37typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; 38 39#ifdef DEBUG 40#define DBG(x) printf x 41#else 42#define DBG(x) 43#endif 44 45#define streq(a, b) (strcmp (a, b) == 0) 46 47#define SKIP_SPACE_TABS(S) \ 48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) 49 50/* Clean up namespace so we can include obj-elf.h too. */ 51static int mips_output_flavor (void); 52static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 53#undef OBJ_PROCESS_STAB 54#undef OUTPUT_FLAVOR 55#undef S_GET_ALIGN 56#undef S_GET_SIZE 57#undef S_SET_ALIGN 58#undef S_SET_SIZE 59#undef obj_frob_file 60#undef obj_frob_file_after_relocs 61#undef obj_frob_symbol 62#undef obj_pop_insert 63#undef obj_sec_sym_ok_for_reloc 64#undef OBJ_COPY_SYMBOL_ATTRIBUTES 65 66#include "obj-elf.h" 67/* Fix any of them that we actually care about. */ 68#undef OUTPUT_FLAVOR 69#define OUTPUT_FLAVOR mips_output_flavor() 70 71#include "elf/mips.h" 72 73#ifndef ECOFF_DEBUGGING 74#define NO_ECOFF_DEBUGGING 75#define ECOFF_DEBUGGING 0 76#endif 77 78int mips_flag_mdebug = -1; 79 80/* Control generation of .pdr sections. Off by default on IRIX: the native 81 linker doesn't know about and discards them, but relocations against them 82 remain, leading to rld crashes. */ 83#ifdef TE_IRIX 84int mips_flag_pdr = FALSE; 85#else 86int mips_flag_pdr = TRUE; 87#endif 88 89#include "ecoff.h" 90 91static char *mips_regmask_frag; 92static char *mips_flags_frag; 93 94#define ZERO 0 95#define ATREG 1 96#define S0 16 97#define S7 23 98#define TREG 24 99#define PIC_CALL_REG 25 100#define KT0 26 101#define KT1 27 102#define GP 28 103#define SP 29 104#define FP 30 105#define RA 31 106 107#define ILLEGAL_REG (32) 108 109#define AT mips_opts.at 110 111extern int target_big_endian; 112 113/* The name of the readonly data section. */ 114#define RDATA_SECTION_NAME ".rodata" 115 116/* Ways in which an instruction can be "appended" to the output. */ 117enum append_method { 118 /* Just add it normally. */ 119 APPEND_ADD, 120 121 /* Add it normally and then add a nop. */ 122 APPEND_ADD_WITH_NOP, 123 124 /* Turn an instruction with a delay slot into a "compact" version. */ 125 APPEND_ADD_COMPACT, 126 127 /* Insert the instruction before the last one. */ 128 APPEND_SWAP 129}; 130 131/* Information about an instruction, including its format, operands 132 and fixups. */ 133struct mips_cl_insn 134{ 135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */ 136 const struct mips_opcode *insn_mo; 137 138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is 139 a copy of INSN_MO->match with the operands filled in. If we have 140 decided to use an extended MIPS16 instruction, this includes the 141 extension. */ 142 unsigned long insn_opcode; 143 144 /* The name if this is an label. */ 145 char label[16]; 146 147 /* The target label name if this is an branch. */ 148 char target[16]; 149 150 /* The frag that contains the instruction. */ 151 struct frag *frag; 152 153 /* The offset into FRAG of the first instruction byte. */ 154 long where; 155 156 /* The relocs associated with the instruction, if any. */ 157 fixS *fixp[3]; 158 159 /* True if this entry cannot be moved from its current position. */ 160 unsigned int fixed_p : 1; 161 162 /* True if this instruction occurred in a .set noreorder block. */ 163 unsigned int noreorder_p : 1; 164 165 /* True for mips16 instructions that jump to an absolute address. */ 166 unsigned int mips16_absolute_jump_p : 1; 167 168 /* True if this instruction is complete. */ 169 unsigned int complete_p : 1; 170 171 /* True if this instruction is cleared from history by unconditional 172 branch. */ 173 unsigned int cleared_p : 1; 174}; 175 176/* The ABI to use. */ 177enum mips_abi_level 178{ 179 NO_ABI = 0, 180 O32_ABI, 181 O64_ABI, 182 N32_ABI, 183 N64_ABI, 184 EABI_ABI 185}; 186 187/* MIPS ABI we are using for this output file. */ 188static enum mips_abi_level mips_abi = NO_ABI; 189 190/* Whether or not we have code that can call pic code. */ 191int mips_abicalls = FALSE; 192 193/* Whether or not we have code which can be put into a shared 194 library. */ 195static bfd_boolean mips_in_shared = TRUE; 196 197/* This is the set of options which may be modified by the .set 198 pseudo-op. We use a struct so that .set push and .set pop are more 199 reliable. */ 200 201struct mips_set_options 202{ 203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 204 if it has not been initialized. Changed by `.set mipsN', and the 205 -mipsN command line option, and the default CPU. */ 206 int isa; 207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set 208 <asename>', by command line options, and based on the default 209 architecture. */ 210 int ase; 211 /* Whether we are assembling for the mips16 processor. 0 if we are 212 not, 1 if we are, and -1 if the value has not been initialized. 213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 214 -nomips16 command line options, and the default CPU. */ 215 int mips16; 216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, 217 1 if we are, and -1 if the value has not been initialized. Changed 218 by `.set micromips' and `.set nomicromips', and the -mmicromips 219 and -mno-micromips command line options, and the default CPU. */ 220 int micromips; 221 /* Non-zero if we should not reorder instructions. Changed by `.set 222 reorder' and `.set noreorder'. */ 223 int noreorder; 224 /* Non-zero if we should not permit the register designated "assembler 225 temporary" to be used in instructions. The value is the register 226 number, normally $at ($1). Changed by `.set at=REG', `.set noat' 227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ 228 unsigned int at; 229 /* Non-zero if we should warn when a macro instruction expands into 230 more than one machine instruction. Changed by `.set nomacro' and 231 `.set macro'. */ 232 int warn_about_macros; 233 /* Non-zero if we should not move instructions. Changed by `.set 234 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 235 int nomove; 236 /* Non-zero if we should not optimize branches by moving the target 237 of the branch into the delay slot. Actually, we don't perform 238 this optimization anyhow. Changed by `.set bopt' and `.set 239 nobopt'. */ 240 int nobopt; 241 /* Non-zero if we should not autoextend mips16 instructions. 242 Changed by `.set autoextend' and `.set noautoextend'. */ 243 int noautoextend; 244 /* True if we should only emit 32-bit microMIPS instructions. 245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32 246 and -mno-insn32 command line options. */ 247 bfd_boolean insn32; 248 /* Restrict general purpose registers and floating point registers 249 to 32 bit. This is initially determined when -mgp32 or -mfp32 250 is passed but can changed if the assembler code uses .set mipsN. */ 251 int gp; 252 int fp; 253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 254 command line option, and the default CPU. */ 255 int arch; 256 /* True if ".set sym32" is in effect. */ 257 bfd_boolean sym32; 258 /* True if floating-point operations are not allowed. Changed by .set 259 softfloat or .set hardfloat, by command line options -msoft-float or 260 -mhard-float. The default is false. */ 261 bfd_boolean soft_float; 262 263 /* True if only single-precision floating-point operations are allowed. 264 Changed by .set singlefloat or .set doublefloat, command-line options 265 -msingle-float or -mdouble-float. The default is false. */ 266 bfd_boolean single_float; 267 268 /* 1 if single-precision operations on odd-numbered registers are 269 allowed. */ 270 int oddspreg; 271 272 /* The set of ASEs that should be enabled for the user specified 273 architecture. This cannot be inferred from 'arch' for all cores 274 as processors only have a unique 'arch' if they add architecture 275 specific instructions (UDI). */ 276 int init_ase; 277}; 278 279/* Specifies whether module level options have been checked yet. */ 280static bfd_boolean file_mips_opts_checked = FALSE; 281 282/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the 283 value has not been initialized. Changed by `.nan legacy' and 284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line 285 options, and the default CPU. */ 286static int mips_nan2008 = -1; 287 288/* This is the struct we use to hold the module level set of options. 289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and 290 fp fields to -1 to indicate that they have not been initialized. */ 291 292static struct mips_set_options file_mips_opts = 293{ 294 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 295 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 298 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, 299 /* init_ase */ 0 300}; 301 302/* This is similar to file_mips_opts, but for the current set of options. */ 303 304static struct mips_set_options mips_opts = 305{ 306 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, 307 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, 308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, 309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, 310 /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1, 311 /* init_ase */ 0 312}; 313 314/* Which bits of file_ase were explicitly set or cleared by ASE options. */ 315static unsigned int file_ase_explicit; 316 317/* These variables are filled in with the masks of registers used. 318 The object format code reads them and puts them in the appropriate 319 place. */ 320unsigned long mips_gprmask; 321unsigned long mips_cprmask[4]; 322 323/* True if any MIPS16 code was produced. */ 324static int file_ase_mips16; 325 326#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ 327 || mips_opts.isa == ISA_MIPS32R2 \ 328 || mips_opts.isa == ISA_MIPS32R3 \ 329 || mips_opts.isa == ISA_MIPS32R5 \ 330 || mips_opts.isa == ISA_MIPS64 \ 331 || mips_opts.isa == ISA_MIPS64R2 \ 332 || mips_opts.isa == ISA_MIPS64R3 \ 333 || mips_opts.isa == ISA_MIPS64R5) 334 335/* True if any microMIPS code was produced. */ 336static int file_ase_micromips; 337 338/* True if we want to create R_MIPS_JALR for jalr $25. */ 339#ifdef TE_IRIX 340#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI 341#else 342/* As a GNU extension, we use R_MIPS_JALR for o32 too. However, 343 because there's no place for any addend, the only acceptable 344 expression is a bare symbol. */ 345#define MIPS_JALR_HINT_P(EXPR) \ 346 (!HAVE_IN_PLACE_ADDENDS \ 347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) 348#endif 349 350/* The argument of the -march= flag. The architecture we are assembling. */ 351static const char *mips_arch_string; 352 353/* The argument of the -mtune= flag. The architecture for which we 354 are optimizing. */ 355static int mips_tune = CPU_UNKNOWN; 356static const char *mips_tune_string; 357 358/* True when generating 32-bit code for a 64-bit processor. */ 359static int mips_32bitmode = 0; 360 361/* True if the given ABI requires 32-bit registers. */ 362#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 363 364/* Likewise 64-bit registers. */ 365#define ABI_NEEDS_64BIT_REGS(ABI) \ 366 ((ABI) == N32_ABI \ 367 || (ABI) == N64_ABI \ 368 || (ABI) == O64_ABI) 369 370#define ISA_IS_R6(ISA) \ 371 ((ISA) == ISA_MIPS32R6 \ 372 || (ISA) == ISA_MIPS64R6) 373 374/* Return true if ISA supports 64 bit wide gp registers. */ 375#define ISA_HAS_64BIT_REGS(ISA) \ 376 ((ISA) == ISA_MIPS3 \ 377 || (ISA) == ISA_MIPS4 \ 378 || (ISA) == ISA_MIPS5 \ 379 || (ISA) == ISA_MIPS64 \ 380 || (ISA) == ISA_MIPS64R2 \ 381 || (ISA) == ISA_MIPS64R3 \ 382 || (ISA) == ISA_MIPS64R5 \ 383 || (ISA) == ISA_MIPS64R6) 384 385/* Return true if ISA supports 64 bit wide float registers. */ 386#define ISA_HAS_64BIT_FPRS(ISA) \ 387 ((ISA) == ISA_MIPS3 \ 388 || (ISA) == ISA_MIPS4 \ 389 || (ISA) == ISA_MIPS5 \ 390 || (ISA) == ISA_MIPS32R2 \ 391 || (ISA) == ISA_MIPS32R3 \ 392 || (ISA) == ISA_MIPS32R5 \ 393 || (ISA) == ISA_MIPS32R6 \ 394 || (ISA) == ISA_MIPS64 \ 395 || (ISA) == ISA_MIPS64R2 \ 396 || (ISA) == ISA_MIPS64R3 \ 397 || (ISA) == ISA_MIPS64R5 \ 398 || (ISA) == ISA_MIPS64R6) 399 400/* Return true if ISA supports 64-bit right rotate (dror et al.) 401 instructions. */ 402#define ISA_HAS_DROR(ISA) \ 403 ((ISA) == ISA_MIPS64R2 \ 404 || (ISA) == ISA_MIPS64R3 \ 405 || (ISA) == ISA_MIPS64R5 \ 406 || (ISA) == ISA_MIPS64R6 \ 407 || (mips_opts.micromips \ 408 && ISA_HAS_64BIT_REGS (ISA)) \ 409 ) 410 411/* Return true if ISA supports 32-bit right rotate (ror et al.) 412 instructions. */ 413#define ISA_HAS_ROR(ISA) \ 414 ((ISA) == ISA_MIPS32R2 \ 415 || (ISA) == ISA_MIPS32R3 \ 416 || (ISA) == ISA_MIPS32R5 \ 417 || (ISA) == ISA_MIPS32R6 \ 418 || (ISA) == ISA_MIPS64R2 \ 419 || (ISA) == ISA_MIPS64R3 \ 420 || (ISA) == ISA_MIPS64R5 \ 421 || (ISA) == ISA_MIPS64R6 \ 422 || (mips_opts.ase & ASE_SMARTMIPS) \ 423 || mips_opts.micromips \ 424 ) 425 426/* Return true if ISA supports single-precision floats in odd registers. */ 427#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ 428 (((ISA) == ISA_MIPS32 \ 429 || (ISA) == ISA_MIPS32R2 \ 430 || (ISA) == ISA_MIPS32R3 \ 431 || (ISA) == ISA_MIPS32R5 \ 432 || (ISA) == ISA_MIPS32R6 \ 433 || (ISA) == ISA_MIPS64 \ 434 || (ISA) == ISA_MIPS64R2 \ 435 || (ISA) == ISA_MIPS64R3 \ 436 || (ISA) == ISA_MIPS64R5 \ 437 || (ISA) == ISA_MIPS64R6 \ 438 || (CPU) == CPU_R5900) \ 439 && ((CPU) != CPU_GS464 \ 440 || (CPU) != CPU_GS464E \ 441 || (CPU) != CPU_GS264E)) 442 443/* Return true if ISA supports move to/from high part of a 64-bit 444 floating-point register. */ 445#define ISA_HAS_MXHC1(ISA) \ 446 ((ISA) == ISA_MIPS32R2 \ 447 || (ISA) == ISA_MIPS32R3 \ 448 || (ISA) == ISA_MIPS32R5 \ 449 || (ISA) == ISA_MIPS32R6 \ 450 || (ISA) == ISA_MIPS64R2 \ 451 || (ISA) == ISA_MIPS64R3 \ 452 || (ISA) == ISA_MIPS64R5 \ 453 || (ISA) == ISA_MIPS64R6) 454 455/* Return true if ISA supports legacy NAN. */ 456#define ISA_HAS_LEGACY_NAN(ISA) \ 457 ((ISA) == ISA_MIPS1 \ 458 || (ISA) == ISA_MIPS2 \ 459 || (ISA) == ISA_MIPS3 \ 460 || (ISA) == ISA_MIPS4 \ 461 || (ISA) == ISA_MIPS5 \ 462 || (ISA) == ISA_MIPS32 \ 463 || (ISA) == ISA_MIPS32R2 \ 464 || (ISA) == ISA_MIPS32R3 \ 465 || (ISA) == ISA_MIPS32R5 \ 466 || (ISA) == ISA_MIPS64 \ 467 || (ISA) == ISA_MIPS64R2 \ 468 || (ISA) == ISA_MIPS64R3 \ 469 || (ISA) == ISA_MIPS64R5) 470 471#define GPR_SIZE \ 472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ 473 ? 32 \ 474 : mips_opts.gp) 475 476#define FPR_SIZE \ 477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ 478 ? 32 \ 479 : mips_opts.fp) 480 481#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 482 483#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 484 485/* True if relocations are stored in-place. */ 486#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 487 488/* The ABI-derived address size. */ 489#define HAVE_64BIT_ADDRESSES \ 490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) 491#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) 492 493/* The size of symbolic constants (i.e., expressions of the form 494 "SYMBOL" or "SYMBOL + OFFSET"). */ 495#define HAVE_32BIT_SYMBOLS \ 496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) 497#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) 498 499/* Addresses are loaded in different ways, depending on the address size 500 in use. The n32 ABI Documentation also mandates the use of additions 501 with overflow checking, but existing implementations don't follow it. */ 502#define ADDRESS_ADD_INSN \ 503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 504 505#define ADDRESS_ADDI_INSN \ 506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 507 508#define ADDRESS_LOAD_INSN \ 509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 510 511#define ADDRESS_STORE_INSN \ 512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 513 514/* Return true if the given CPU supports the MIPS16 ASE. */ 515#define CPU_HAS_MIPS16(cpu) \ 516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 518 519/* Return true if the given CPU supports the microMIPS ASE. */ 520#define CPU_HAS_MICROMIPS(cpu) 0 521 522/* True if CPU has a dror instruction. */ 523#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 524 525/* True if CPU has a ror instruction. */ 526#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 527 528/* True if CPU is in the Octeon family. */ 529#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ 530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) 531 532/* True if CPU has seq/sne and seqi/snei instructions. */ 533#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) 534 535/* True, if CPU has support for ldc1 and sdc1. */ 536#define CPU_HAS_LDC1_SDC1(CPU) \ 537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) 538 539/* True if mflo and mfhi can be immediately followed by instructions 540 which write to the HI and LO registers. 541 542 According to MIPS specifications, MIPS ISAs I, II, and III need 543 (at least) two instructions between the reads of HI/LO and 544 instructions which write them, and later ISAs do not. Contradicting 545 the MIPS specifications, some MIPS IV processor user manuals (e.g. 546 the UM for the NEC Vr5000) document needing the instructions between 547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 548 MIPS64 and later ISAs to have the interlocks, plus any specific 549 earlier-ISA CPUs for which CPU documentation declares that the 550 instructions are really interlocked. */ 551#define hilo_interlocks \ 552 (mips_opts.isa == ISA_MIPS32 \ 553 || mips_opts.isa == ISA_MIPS32R2 \ 554 || mips_opts.isa == ISA_MIPS32R3 \ 555 || mips_opts.isa == ISA_MIPS32R5 \ 556 || mips_opts.isa == ISA_MIPS32R6 \ 557 || mips_opts.isa == ISA_MIPS64 \ 558 || mips_opts.isa == ISA_MIPS64R2 \ 559 || mips_opts.isa == ISA_MIPS64R3 \ 560 || mips_opts.isa == ISA_MIPS64R5 \ 561 || mips_opts.isa == ISA_MIPS64R6 \ 562 || mips_opts.arch == CPU_R4010 \ 563 || mips_opts.arch == CPU_R5900 \ 564 || mips_opts.arch == CPU_R10000 \ 565 || mips_opts.arch == CPU_R12000 \ 566 || mips_opts.arch == CPU_R14000 \ 567 || mips_opts.arch == CPU_R16000 \ 568 || mips_opts.arch == CPU_RM7000 \ 569 || mips_opts.arch == CPU_VR5500 \ 570 || mips_opts.micromips \ 571 ) 572 573/* Whether the processor uses hardware interlocks to protect reads 574 from the GPRs after they are loaded from memory, and thus does not 575 require nops to be inserted. This applies to instructions marked 576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA 577 level I and microMIPS mode instructions are always interlocked. */ 578#define gpr_interlocks \ 579 (mips_opts.isa != ISA_MIPS1 \ 580 || mips_opts.arch == CPU_R3900 \ 581 || mips_opts.arch == CPU_R5900 \ 582 || mips_opts.micromips \ 583 ) 584 585/* Whether the processor uses hardware interlocks to avoid delays 586 required by coprocessor instructions, and thus does not require 587 nops to be inserted. This applies to instructions marked 588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between 589 instructions marked INSN_WRITE_COND_CODE and ones marked 590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 591 levels I, II, and III and microMIPS mode instructions are always 592 interlocked. */ 593/* Itbl support may require additional care here. */ 594#define cop_interlocks \ 595 ((mips_opts.isa != ISA_MIPS1 \ 596 && mips_opts.isa != ISA_MIPS2 \ 597 && mips_opts.isa != ISA_MIPS3) \ 598 || mips_opts.arch == CPU_R4300 \ 599 || mips_opts.micromips \ 600 ) 601 602/* Whether the processor uses hardware interlocks to protect reads 603 from coprocessor registers after they are loaded from memory, and 604 thus does not require nops to be inserted. This applies to 605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 606 requires at MIPS ISA level I and microMIPS mode instructions are 607 always interlocked. */ 608#define cop_mem_interlocks \ 609 (mips_opts.isa != ISA_MIPS1 \ 610 || mips_opts.micromips \ 611 ) 612 613/* Is this a mfhi or mflo instruction? */ 614#define MF_HILO_INSN(PINFO) \ 615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 616 617/* Whether code compression (either of the MIPS16 or the microMIPS ASEs) 618 has been selected. This implies, in particular, that addresses of text 619 labels have their LSB set. */ 620#define HAVE_CODE_COMPRESSION \ 621 ((mips_opts.mips16 | mips_opts.micromips) != 0) 622 623/* The minimum and maximum signed values that can be stored in a GPR. */ 624#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) 625#define GPR_SMIN (-GPR_SMAX - 1) 626 627/* MIPS PIC level. */ 628 629enum mips_pic_level mips_pic; 630 631/* 1 if we should generate 32 bit offsets from the $gp register in 632 SVR4_PIC mode. Currently has no meaning in other modes. */ 633static int mips_big_got = 0; 634 635/* 1 if trap instructions should used for overflow rather than break 636 instructions. */ 637static int mips_trap = 0; 638 639/* 1 if double width floating point constants should not be constructed 640 by assembling two single width halves into two single width floating 641 point registers which just happen to alias the double width destination 642 register. On some architectures this aliasing can be disabled by a bit 643 in the status register, and the setting of this bit cannot be determined 644 automatically at assemble time. */ 645static int mips_disable_float_construction; 646 647/* Non-zero if any .set noreorder directives were used. */ 648 649static int mips_any_noreorder; 650 651/* Non-zero if nops should be inserted when the register referenced in 652 an mfhi/mflo instruction is read in the next two instructions. */ 653static int mips_7000_hilo_fix; 654 655/* The size of objects in the small data section. */ 656static unsigned int g_switch_value = 8; 657/* Whether the -G option was used. */ 658static int g_switch_seen = 0; 659 660#define N_RMASK 0xc4 661#define N_VFP 0xd4 662 663/* If we can determine in advance that GP optimization won't be 664 possible, we can skip the relaxation stuff that tries to produce 665 GP-relative references. This makes delay slot optimization work 666 better. 667 668 This function can only provide a guess, but it seems to work for 669 gcc output. It needs to guess right for gcc, otherwise gcc 670 will put what it thinks is a GP-relative instruction in a branch 671 delay slot. 672 673 I don't know if a fix is needed for the SVR4_PIC mode. I've only 674 fixed it for the non-PIC mode. KR 95/04/07 */ 675static int nopic_need_relax (symbolS *, int); 676 677/* Handle of the OPCODE hash table. */ 678static struct hash_control *op_hash = NULL; 679 680/* The opcode hash table we use for the mips16. */ 681static struct hash_control *mips16_op_hash = NULL; 682 683/* The opcode hash table we use for the microMIPS ASE. */ 684static struct hash_control *micromips_op_hash = NULL; 685 686/* This array holds the chars that always start a comment. If the 687 pre-processor is disabled, these aren't very useful. */ 688const char comment_chars[] = "#"; 689 690/* This array holds the chars that only start a comment at the beginning of 691 a line. If the line seems to have the form '# 123 filename' 692 .line and .file directives will appear in the pre-processed output. */ 693/* Note that input_file.c hand checks for '#' at the beginning of the 694 first line of the input file. This is because the compiler outputs 695 #NO_APP at the beginning of its output. */ 696/* Also note that C style comments are always supported. */ 697const char line_comment_chars[] = "#"; 698 699/* This array holds machine specific line separator characters. */ 700const char line_separator_chars[] = ";"; 701 702/* Chars that can be used to separate mant from exp in floating point nums. */ 703const char EXP_CHARS[] = "eE"; 704 705/* Chars that mean this number is a floating point constant. 706 As in 0f12.456 707 or 0d1.2345e12. */ 708const char FLT_CHARS[] = "rRsSfFdDxXpP"; 709 710/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 711 changed in read.c . Ideally it shouldn't have to know about it at all, 712 but nothing is ideal around here. */ 713 714/* Types of printf format used for instruction-related error messages. 715 "I" means int ("%d") and "S" means string ("%s"). */ 716enum mips_insn_error_format 717{ 718 ERR_FMT_PLAIN, 719 ERR_FMT_I, 720 ERR_FMT_SS, 721}; 722 723/* Information about an error that was found while assembling the current 724 instruction. */ 725struct mips_insn_error 726{ 727 /* We sometimes need to match an instruction against more than one 728 opcode table entry. Errors found during this matching are reported 729 against a particular syntactic argument rather than against the 730 instruction as a whole. We grade these messages so that errors 731 against argument N have a greater priority than an error against 732 any argument < N, since the former implies that arguments up to N 733 were acceptable and that the opcode entry was therefore a closer match. 734 If several matches report an error against the same argument, 735 we only use that error if it is the same in all cases. 736 737 min_argnum is the minimum argument number for which an error message 738 should be accepted. It is 0 if MSG is against the instruction as 739 a whole. */ 740 int min_argnum; 741 742 /* The printf()-style message, including its format and arguments. */ 743 enum mips_insn_error_format format; 744 const char *msg; 745 union 746 { 747 int i; 748 const char *ss[2]; 749 } u; 750}; 751 752/* The error that should be reported for the current instruction. */ 753static struct mips_insn_error insn_error; 754 755static int auto_align = 1; 756 757/* When outputting SVR4 PIC code, the assembler needs to know the 758 offset in the stack frame from which to restore the $gp register. 759 This is set by the .cprestore pseudo-op, and saved in this 760 variable. */ 761static offsetT mips_cprestore_offset = -1; 762 763/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 764 more optimizations, it can use a register value instead of a memory-saved 765 offset and even an other register than $gp as global pointer. */ 766static offsetT mips_cpreturn_offset = -1; 767static int mips_cpreturn_register = -1; 768static int mips_gp_register = GP; 769static int mips_gprel_offset = 0; 770 771/* Whether mips_cprestore_offset has been set in the current function 772 (or whether it has already been warned about, if not). */ 773static int mips_cprestore_valid = 0; 774 775/* This is the register which holds the stack frame, as set by the 776 .frame pseudo-op. This is needed to implement .cprestore. */ 777static int mips_frame_reg = SP; 778 779/* Whether mips_frame_reg has been set in the current function 780 (or whether it has already been warned about, if not). */ 781static int mips_frame_reg_valid = 0; 782 783/* To output NOP instructions correctly, we need to keep information 784 about the previous two instructions. */ 785 786/* Whether we are optimizing. The default value of 2 means to remove 787 unneeded NOPs and swap branch instructions when possible. A value 788 of 1 means to not swap branches. A value of 0 means to always 789 insert NOPs. */ 790static int mips_optimize = 2; 791 792/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 793 equivalent to seeing no -g option at all. */ 794static int mips_debug = 0; 795 796/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ 797#define MAX_VR4130_NOPS 4 798 799/* The maximum number of NOPs needed to fill delay slots. */ 800#define MAX_DELAY_NOPS 2 801 802/* The maximum number of NOPs needed for any purpose. */ 803#define MAX_NOPS 4 804 805/* The maximum range of context length of ll/sc. */ 806#define MAX_LLSC_RANGE 20 807 808/* A list of previous instructions, with index 0 being the most recent. 809 We need to look back MAX_NOPS instructions when filling delay slots 810 or working around processor errata. We need to look back one 811 instruction further if we're thinking about using history[0] to 812 fill a branch delay slot. */ 813static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE]; 814 815/* Arrays of operands for each instruction. */ 816#define MAX_OPERANDS 6 817struct mips_operand_array 818{ 819 const struct mips_operand *operand[MAX_OPERANDS]; 820}; 821static struct mips_operand_array *mips_operands; 822static struct mips_operand_array *mips16_operands; 823static struct mips_operand_array *micromips_operands; 824 825/* Nop instructions used by emit_nop. */ 826static struct mips_cl_insn nop_insn; 827static struct mips_cl_insn mips16_nop_insn; 828static struct mips_cl_insn micromips_nop16_insn; 829static struct mips_cl_insn micromips_nop32_insn; 830 831/* Sync instructions used by insert sync. */ 832static struct mips_cl_insn sync_insn; 833 834/* The appropriate nop for the current mode. */ 835#define NOP_INSN (mips_opts.mips16 \ 836 ? &mips16_nop_insn \ 837 : (mips_opts.micromips \ 838 ? (mips_opts.insn32 \ 839 ? µmips_nop32_insn \ 840 : µmips_nop16_insn) \ 841 : &nop_insn)) 842 843/* The size of NOP_INSN in bytes. */ 844#define NOP_INSN_SIZE ((mips_opts.mips16 \ 845 || (mips_opts.micromips && !mips_opts.insn32)) \ 846 ? 2 : 4) 847 848/* If this is set, it points to a frag holding nop instructions which 849 were inserted before the start of a noreorder section. If those 850 nops turn out to be unnecessary, the size of the frag can be 851 decreased. */ 852static fragS *prev_nop_frag; 853 854/* The number of nop instructions we created in prev_nop_frag. */ 855static int prev_nop_frag_holds; 856 857/* The number of nop instructions that we know we need in 858 prev_nop_frag. */ 859static int prev_nop_frag_required; 860 861/* The number of instructions we've seen since prev_nop_frag. */ 862static int prev_nop_frag_since; 863 864/* Relocations against symbols are sometimes done in two parts, with a HI 865 relocation and a LO relocation. Each relocation has only 16 bits of 866 space to store an addend. This means that in order for the linker to 867 handle carries correctly, it must be able to locate both the HI and 868 the LO relocation. This means that the relocations must appear in 869 order in the relocation table. 870 871 In order to implement this, we keep track of each unmatched HI 872 relocation. We then sort them so that they immediately precede the 873 corresponding LO relocation. */ 874 875struct mips_hi_fixup 876{ 877 /* Next HI fixup. */ 878 struct mips_hi_fixup *next; 879 /* This fixup. */ 880 fixS *fixp; 881 /* The section this fixup is in. */ 882 segT seg; 883}; 884 885/* The list of unmatched HI relocs. */ 886 887static struct mips_hi_fixup *mips_hi_fixup_list; 888 889/* The frag containing the last explicit relocation operator. 890 Null if explicit relocations have not been used. */ 891 892static fragS *prev_reloc_op_frag; 893 894/* Map mips16 register numbers to normal MIPS register numbers. */ 895 896static const unsigned int mips16_to_32_reg_map[] = 897{ 898 16, 17, 2, 3, 4, 5, 6, 7 899}; 900 901/* Map microMIPS register numbers to normal MIPS register numbers. */ 902 903#define micromips_to_32_reg_d_map mips16_to_32_reg_map 904 905/* The microMIPS registers with type h. */ 906static const unsigned int micromips_to_32_reg_h_map1[] = 907{ 908 5, 5, 6, 4, 4, 4, 4, 4 909}; 910static const unsigned int micromips_to_32_reg_h_map2[] = 911{ 912 6, 7, 7, 21, 22, 5, 6, 7 913}; 914 915/* The microMIPS registers with type m. */ 916static const unsigned int micromips_to_32_reg_m_map[] = 917{ 918 0, 17, 2, 3, 16, 18, 19, 20 919}; 920 921#define micromips_to_32_reg_n_map micromips_to_32_reg_m_map 922 923/* Classifies the kind of instructions we're interested in when 924 implementing -mfix-vr4120. */ 925enum fix_vr4120_class 926{ 927 FIX_VR4120_MACC, 928 FIX_VR4120_DMACC, 929 FIX_VR4120_MULT, 930 FIX_VR4120_DMULT, 931 FIX_VR4120_DIV, 932 FIX_VR4120_MTHILO, 933 NUM_FIX_VR4120_CLASSES 934}; 935 936/* ...likewise -mtrap-zero-jump. */ 937static bfd_boolean mips_trap_zero_jump; 938 939/* ...likewise -mfix-loongson2f-jump. */ 940static bfd_boolean mips_fix_loongson2f_jump; 941 942/* ...likewise -mfix-loongson2f-nop. */ 943static bfd_boolean mips_fix_loongson2f_nop; 944 945/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ 946static bfd_boolean mips_fix_loongson2f; 947 948/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if 949 there must be at least one other instruction between an instruction 950 of type X and an instruction of type Y. */ 951static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; 952 953/* True if -mfix-vr4120 is in force. */ 954static int mips_fix_vr4120; 955 956/* ...likewise -mfix-vr4130. */ 957static int mips_fix_vr4130; 958 959/* ...likewise -mfix-24k. */ 960static int mips_fix_24k; 961 962/* ...likewise -mfix-rm7000 */ 963static int mips_fix_rm7000; 964 965/* ...likewise -mfix-cn63xxp1 */ 966static bfd_boolean mips_fix_cn63xxp1; 967 968/* ...likewise -mfix-r5900 */ 969static bfd_boolean mips_fix_r5900; 970static bfd_boolean mips_fix_r5900_explicit; 971 972/* ...likewise -mfix-loongson3-llsc. */ 973static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC; 974 975/* We don't relax branches by default, since this causes us to expand 976 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 977 fail to compute the offset before expanding the macro to the most 978 efficient expansion. */ 979 980static int mips_relax_branch; 981 982static int mips_fix_loongson2f_btb; 983 984/* TRUE if checks are suppressed for invalid branches between ISA modes. 985 Needed for broken assembly produced by some GCC versions and some 986 sloppy code out there, where branches to data labels are present. */ 987static bfd_boolean mips_ignore_branch_isa; 988 989/* The expansion of many macros depends on the type of symbol that 990 they refer to. For example, when generating position-dependent code, 991 a macro that refers to a symbol may have two different expansions, 992 one which uses GP-relative addresses and one which uses absolute 993 addresses. When generating SVR4-style PIC, a macro may have 994 different expansions for local and global symbols. 995 996 We handle these situations by generating both sequences and putting 997 them in variant frags. In position-dependent code, the first sequence 998 will be the GP-relative one and the second sequence will be the 999 absolute one. In SVR4 PIC, the first sequence will be for global 1000 symbols and the second will be for local symbols. 1001 1002 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 1003 SECOND are the lengths of the two sequences in bytes. These fields 1004 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 1005 the subtype has the following flags: 1006 1007 RELAX_PIC 1008 Set if generating PIC code. 1009 1010 RELAX_USE_SECOND 1011 Set if it has been decided that we should use the second 1012 sequence instead of the first. 1013 1014 RELAX_SECOND_LONGER 1015 Set in the first variant frag if the macro's second implementation 1016 is longer than its first. This refers to the macro as a whole, 1017 not an individual relaxation. 1018 1019 RELAX_NOMACRO 1020 Set in the first variant frag if the macro appeared in a .set nomacro 1021 block and if one alternative requires a warning but the other does not. 1022 1023 RELAX_DELAY_SLOT 1024 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 1025 delay slot. 1026 1027 RELAX_DELAY_SLOT_16BIT 1028 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a 1029 16-bit instruction. 1030 1031 RELAX_DELAY_SLOT_SIZE_FIRST 1032 Like RELAX_DELAY_SLOT, but indicates that the first implementation of 1033 the macro is of the wrong size for the branch delay slot. 1034 1035 RELAX_DELAY_SLOT_SIZE_SECOND 1036 Like RELAX_DELAY_SLOT, but indicates that the second implementation of 1037 the macro is of the wrong size for the branch delay slot. 1038 1039 The frag's "opcode" points to the first fixup for relaxable code. 1040 1041 Relaxable macros are generated using a sequence such as: 1042 1043 relax_start (SYMBOL); 1044 ... generate first expansion ... 1045 relax_switch (); 1046 ... generate second expansion ... 1047 relax_end (); 1048 1049 The code and fixups for the unwanted alternative are discarded 1050 by md_convert_frag. */ 1051#define RELAX_ENCODE(FIRST, SECOND, PIC) \ 1052 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) 1053 1054#define RELAX_FIRST(X) (((X) >> 8) & 0xff) 1055#define RELAX_SECOND(X) ((X) & 0xff) 1056#define RELAX_PIC(X) (((X) & 0x10000) != 0) 1057#define RELAX_USE_SECOND 0x20000 1058#define RELAX_SECOND_LONGER 0x40000 1059#define RELAX_NOMACRO 0x80000 1060#define RELAX_DELAY_SLOT 0x100000 1061#define RELAX_DELAY_SLOT_16BIT 0x200000 1062#define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 1063#define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 1064 1065/* Branch without likely bit. If label is out of range, we turn: 1066 1067 beq reg1, reg2, label 1068 delay slot 1069 1070 into 1071 1072 bne reg1, reg2, 0f 1073 nop 1074 j label 1075 0: delay slot 1076 1077 with the following opcode replacements: 1078 1079 beq <-> bne 1080 blez <-> bgtz 1081 bltz <-> bgez 1082 bc1f <-> bc1t 1083 1084 bltzal <-> bgezal (with jal label instead of j label) 1085 1086 Even though keeping the delay slot instruction in the delay slot of 1087 the branch would be more efficient, it would be very tricky to do 1088 correctly, because we'd have to introduce a variable frag *after* 1089 the delay slot instruction, and expand that instead. Let's do it 1090 the easy way for now, even if the branch-not-taken case now costs 1091 one additional instruction. Out-of-range branches are not supposed 1092 to be common, anyway. 1093 1094 Branch likely. If label is out of range, we turn: 1095 1096 beql reg1, reg2, label 1097 delay slot (annulled if branch not taken) 1098 1099 into 1100 1101 beql reg1, reg2, 1f 1102 nop 1103 beql $0, $0, 2f 1104 nop 1105 1: j[al] label 1106 delay slot (executed only if branch taken) 1107 2: 1108 1109 It would be possible to generate a shorter sequence by losing the 1110 likely bit, generating something like: 1111 1112 bne reg1, reg2, 0f 1113 nop 1114 j[al] label 1115 delay slot (executed only if branch taken) 1116 0: 1117 1118 beql -> bne 1119 bnel -> beq 1120 blezl -> bgtz 1121 bgtzl -> blez 1122 bltzl -> bgez 1123 bgezl -> bltz 1124 bc1fl -> bc1t 1125 bc1tl -> bc1f 1126 1127 bltzall -> bgezal (with jal label instead of j label) 1128 bgezall -> bltzal (ditto) 1129 1130 1131 but it's not clear that it would actually improve performance. */ 1132#define RELAX_BRANCH_ENCODE(at, pic, \ 1133 uncond, likely, link, toofar) \ 1134 ((relax_substateT) \ 1135 (0xc0000000 \ 1136 | ((at) & 0x1f) \ 1137 | ((pic) ? 0x20 : 0) \ 1138 | ((toofar) ? 0x40 : 0) \ 1139 | ((link) ? 0x80 : 0) \ 1140 | ((likely) ? 0x100 : 0) \ 1141 | ((uncond) ? 0x200 : 0))) 1142#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 1143#define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) 1144#define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) 1145#define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) 1146#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) 1147#define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) 1148#define RELAX_BRANCH_AT(i) ((i) & 0x1f) 1149 1150/* For mips16 code, we use an entirely different form of relaxation. 1151 mips16 supports two versions of most instructions which take 1152 immediate values: a small one which takes some small value, and a 1153 larger one which takes a 16 bit value. Since branches also follow 1154 this pattern, relaxing these values is required. 1155 1156 We can assemble both mips16 and normal MIPS code in a single 1157 object. Therefore, we need to support this type of relaxation at 1158 the same time that we support the relaxation described above. We 1159 use the high bit of the subtype field to distinguish these cases. 1160 1161 The information we store for this type of relaxation is the 1162 argument code found in the opcode file for this relocation, whether 1163 the user explicitly requested a small or extended form, and whether 1164 the relocation is in a jump or jal delay slot. That tells us the 1165 size of the value, and how it should be stored. We also store 1166 whether the fragment is considered to be extended or not. We also 1167 store whether this is known to be a branch to a different section, 1168 whether we have tried to relax this frag yet, and whether we have 1169 ever extended a PC relative fragment because of a shift count. */ 1170#define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ 1171 small, ext, \ 1172 dslot, jal_dslot) \ 1173 (0x80000000 \ 1174 | ((type) & 0xff) \ 1175 | ((e2) ? 0x100 : 0) \ 1176 | ((pic) ? 0x200 : 0) \ 1177 | ((sym32) ? 0x400 : 0) \ 1178 | ((nomacro) ? 0x800 : 0) \ 1179 | ((small) ? 0x1000 : 0) \ 1180 | ((ext) ? 0x2000 : 0) \ 1181 | ((dslot) ? 0x4000 : 0) \ 1182 | ((jal_dslot) ? 0x8000 : 0)) 1183 1184#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 1185#define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 1186#define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) 1187#define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) 1188#define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) 1189#define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) 1190#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) 1191#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) 1192#define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) 1193#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) 1194 1195#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) 1196#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) 1197#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) 1198#define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) 1199#define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) 1200#define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) 1201#define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) 1202#define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) 1203#define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) 1204 1205/* For microMIPS code, we use relaxation similar to one we use for 1206 MIPS16 code. Some instructions that take immediate values support 1207 two encodings: a small one which takes some small value, and a 1208 larger one which takes a 16 bit value. As some branches also follow 1209 this pattern, relaxing these values is required. 1210 1211 We can assemble both microMIPS and normal MIPS code in a single 1212 object. Therefore, we need to support this type of relaxation at 1213 the same time that we support the relaxation described above. We 1214 use one of the high bits of the subtype field to distinguish these 1215 cases. 1216 1217 The information we store for this type of relaxation is the argument 1218 code found in the opcode file for this relocation, the register 1219 selected as the assembler temporary, whether in the 32-bit 1220 instruction mode, whether the branch is unconditional, whether it is 1221 compact, whether there is no delay-slot instruction available to fill 1222 in, whether it stores the link address implicitly in $ra, whether 1223 relaxation of out-of-range 32-bit branches to a sequence of 1224 instructions is enabled, and whether the displacement of a branch is 1225 too large to fit as an immediate argument of a 16-bit and a 32-bit 1226 branch, respectively. */ 1227#define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ 1228 uncond, compact, link, nods, \ 1229 relax32, toofar16, toofar32) \ 1230 (0x40000000 \ 1231 | ((type) & 0xff) \ 1232 | (((at) & 0x1f) << 8) \ 1233 | ((insn32) ? 0x2000 : 0) \ 1234 | ((pic) ? 0x4000 : 0) \ 1235 | ((uncond) ? 0x8000 : 0) \ 1236 | ((compact) ? 0x10000 : 0) \ 1237 | ((link) ? 0x20000 : 0) \ 1238 | ((nods) ? 0x40000 : 0) \ 1239 | ((relax32) ? 0x80000 : 0) \ 1240 | ((toofar16) ? 0x100000 : 0) \ 1241 | ((toofar32) ? 0x200000 : 0)) 1242#define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) 1243#define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) 1244#define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) 1245#define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) 1246#define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) 1247#define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) 1248#define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) 1249#define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) 1250#define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) 1251#define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) 1252 1253#define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) 1254#define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) 1255#define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) 1256#define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) 1257#define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) 1258#define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) 1259 1260/* Sign-extend 16-bit value X. */ 1261#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) 1262 1263/* Is the given value a sign-extended 32-bit value? */ 1264#define IS_SEXT_32BIT_NUM(x) \ 1265 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 1266 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 1267 1268/* Is the given value a sign-extended 16-bit value? */ 1269#define IS_SEXT_16BIT_NUM(x) \ 1270 (((x) &~ (offsetT) 0x7fff) == 0 \ 1271 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 1272 1273/* Is the given value a sign-extended 12-bit value? */ 1274#define IS_SEXT_12BIT_NUM(x) \ 1275 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) 1276 1277/* Is the given value a sign-extended 9-bit value? */ 1278#define IS_SEXT_9BIT_NUM(x) \ 1279 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) 1280 1281/* Is the given value a zero-extended 32-bit value? Or a negated one? */ 1282#define IS_ZEXT_32BIT_NUM(x) \ 1283 (((x) &~ (offsetT) 0xffffffff) == 0 \ 1284 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 1285 1286/* Extract bits MASK << SHIFT from STRUCT and shift them right 1287 SHIFT places. */ 1288#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ 1289 (((STRUCT) >> (SHIFT)) & (MASK)) 1290 1291/* Extract the operand given by FIELD from mips_cl_insn INSN. */ 1292#define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ 1293 (!(MICROMIPS) \ 1294 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ 1295 : EXTRACT_BITS ((INSN).insn_opcode, \ 1296 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) 1297#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ 1298 EXTRACT_BITS ((INSN).insn_opcode, \ 1299 MIPS16OP_MASK_##FIELD, \ 1300 MIPS16OP_SH_##FIELD) 1301 1302/* The MIPS16 EXTEND opcode, shifted left 16 places. */ 1303#define MIPS16_EXTEND (0xf000U << 16) 1304 1305/* Whether or not we are emitting a branch-likely macro. */ 1306static bfd_boolean emit_branch_likely_macro = FALSE; 1307 1308/* Global variables used when generating relaxable macros. See the 1309 comment above RELAX_ENCODE for more details about how relaxation 1310 is used. */ 1311static struct { 1312 /* 0 if we're not emitting a relaxable macro. 1313 1 if we're emitting the first of the two relaxation alternatives. 1314 2 if we're emitting the second alternative. */ 1315 int sequence; 1316 1317 /* The first relaxable fixup in the current frag. (In other words, 1318 the first fixup that refers to relaxable code.) */ 1319 fixS *first_fixup; 1320 1321 /* sizes[0] says how many bytes of the first alternative are stored in 1322 the current frag. Likewise sizes[1] for the second alternative. */ 1323 unsigned int sizes[2]; 1324 1325 /* The symbol on which the choice of sequence depends. */ 1326 symbolS *symbol; 1327} mips_relax; 1328 1329/* Global variables used to decide whether a macro needs a warning. */ 1330static struct { 1331 /* True if the macro is in a branch delay slot. */ 1332 bfd_boolean delay_slot_p; 1333 1334 /* Set to the length in bytes required if the macro is in a delay slot 1335 that requires a specific length of instruction, otherwise zero. */ 1336 unsigned int delay_slot_length; 1337 1338 /* For relaxable macros, sizes[0] is the length of the first alternative 1339 in bytes and sizes[1] is the length of the second alternative. 1340 For non-relaxable macros, both elements give the length of the 1341 macro in bytes. */ 1342 unsigned int sizes[2]; 1343 1344 /* For relaxable macros, first_insn_sizes[0] is the length of the first 1345 instruction of the first alternative in bytes and first_insn_sizes[1] 1346 is the length of the first instruction of the second alternative. 1347 For non-relaxable macros, both elements give the length of the first 1348 instruction in bytes. 1349 1350 Set to zero if we haven't yet seen the first instruction. */ 1351 unsigned int first_insn_sizes[2]; 1352 1353 /* For relaxable macros, insns[0] is the number of instructions for the 1354 first alternative and insns[1] is the number of instructions for the 1355 second alternative. 1356 1357 For non-relaxable macros, both elements give the number of 1358 instructions for the macro. */ 1359 unsigned int insns[2]; 1360 1361 /* The first variant frag for this macro. */ 1362 fragS *first_frag; 1363} mips_macro_warning; 1364 1365/* Prototypes for static functions. */ 1366 1367enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 1368 1369static void append_insn 1370 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, 1371 bfd_boolean expansionp); 1372static void mips_no_prev_insn (void); 1373static void macro_build (expressionS *, const char *, const char *, ...); 1374static void mips16_macro_build 1375 (expressionS *, const char *, const char *, va_list *); 1376static void load_register (int, expressionS *, int); 1377static void macro_build (expressionS *, const char *, const char *, ...); 1378static void macro_start (void); 1379static void macro_end (void); 1380static void macro (struct mips_cl_insn *ip, char *str); 1381static void mips16_macro (struct mips_cl_insn * ip); 1382static void mips_ip (char *str, struct mips_cl_insn * ip); 1383static void mips16_ip (char *str, struct mips_cl_insn * ip); 1384static unsigned long mips16_immed_extend (offsetT, unsigned int); 1385static void mips16_immed 1386 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, 1387 unsigned int, unsigned long *); 1388static size_t my_getSmallExpression 1389 (expressionS *, bfd_reloc_code_real_type *, char *); 1390static void my_getExpression (expressionS *, char *); 1391static void s_align (int); 1392static void s_change_sec (int); 1393static void s_change_section (int); 1394static void s_cons (int); 1395static void s_float_cons (int); 1396static void s_mips_globl (int); 1397static void s_option (int); 1398static void s_mipsset (int); 1399static void s_abicalls (int); 1400static void s_cpload (int); 1401static void s_cpsetup (int); 1402static void s_cplocal (int); 1403static void s_cprestore (int); 1404static void s_cpreturn (int); 1405static void s_dtprelword (int); 1406static void s_dtpreldword (int); 1407static void s_tprelword (int); 1408static void s_tpreldword (int); 1409static void s_gpvalue (int); 1410static void s_gpword (int); 1411static void s_gpdword (int); 1412static void s_ehword (int); 1413static void s_cpadd (int); 1414static void s_insn (int); 1415static void s_nan (int); 1416static void s_module (int); 1417static void s_mips_ent (int); 1418static void s_mips_end (int); 1419static void s_mips_frame (int); 1420static void s_mips_mask (int reg_type); 1421static void s_mips_stab (int); 1422static void s_mips_weakext (int); 1423static void s_mips_file (int); 1424static void s_mips_loc (int); 1425static bfd_boolean pic_need_relax (symbolS *); 1426static int relaxed_branch_length (fragS *, asection *, int); 1427static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); 1428static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); 1429static void file_mips_check_options (void); 1430 1431/* Table and functions used to map between CPU/ISA names, and 1432 ISA levels, and CPU numbers. */ 1433 1434struct mips_cpu_info 1435{ 1436 const char *name; /* CPU or ISA name. */ 1437 int flags; /* MIPS_CPU_* flags. */ 1438 int ase; /* Set of ASEs implemented by the CPU. */ 1439 int isa; /* ISA level. */ 1440 int cpu; /* CPU number (default CPU if ISA). */ 1441}; 1442 1443#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ 1444 1445static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 1446static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 1447static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 1448 1449/* Command-line options. */ 1450const char *md_shortopts = "O::g::G:"; 1451 1452enum options 1453 { 1454 OPTION_MARCH = OPTION_MD_BASE, 1455 OPTION_MTUNE, 1456 OPTION_MIPS1, 1457 OPTION_MIPS2, 1458 OPTION_MIPS3, 1459 OPTION_MIPS4, 1460 OPTION_MIPS5, 1461 OPTION_MIPS32, 1462 OPTION_MIPS64, 1463 OPTION_MIPS32R2, 1464 OPTION_MIPS32R3, 1465 OPTION_MIPS32R5, 1466 OPTION_MIPS32R6, 1467 OPTION_MIPS64R2, 1468 OPTION_MIPS64R3, 1469 OPTION_MIPS64R5, 1470 OPTION_MIPS64R6, 1471 OPTION_MIPS16, 1472 OPTION_NO_MIPS16, 1473 OPTION_MIPS3D, 1474 OPTION_NO_MIPS3D, 1475 OPTION_MDMX, 1476 OPTION_NO_MDMX, 1477 OPTION_DSP, 1478 OPTION_NO_DSP, 1479 OPTION_MT, 1480 OPTION_NO_MT, 1481 OPTION_VIRT, 1482 OPTION_NO_VIRT, 1483 OPTION_MSA, 1484 OPTION_NO_MSA, 1485 OPTION_SMARTMIPS, 1486 OPTION_NO_SMARTMIPS, 1487 OPTION_DSPR2, 1488 OPTION_NO_DSPR2, 1489 OPTION_DSPR3, 1490 OPTION_NO_DSPR3, 1491 OPTION_EVA, 1492 OPTION_NO_EVA, 1493 OPTION_XPA, 1494 OPTION_NO_XPA, 1495 OPTION_MICROMIPS, 1496 OPTION_NO_MICROMIPS, 1497 OPTION_MCU, 1498 OPTION_NO_MCU, 1499 OPTION_MIPS16E2, 1500 OPTION_NO_MIPS16E2, 1501 OPTION_CRC, 1502 OPTION_NO_CRC, 1503 OPTION_M4650, 1504 OPTION_NO_M4650, 1505 OPTION_M4010, 1506 OPTION_NO_M4010, 1507 OPTION_M4100, 1508 OPTION_NO_M4100, 1509 OPTION_M3900, 1510 OPTION_NO_M3900, 1511 OPTION_M7000_HILO_FIX, 1512 OPTION_MNO_7000_HILO_FIX, 1513 OPTION_FIX_24K, 1514 OPTION_NO_FIX_24K, 1515 OPTION_FIX_RM7000, 1516 OPTION_NO_FIX_RM7000, 1517 OPTION_FIX_LOONGSON3_LLSC, 1518 OPTION_NO_FIX_LOONGSON3_LLSC, 1519 OPTION_FIX_LOONGSON2F_JUMP, 1520 OPTION_NO_FIX_LOONGSON2F_JUMP, 1521 OPTION_FIX_LOONGSON2F_NOP, 1522 OPTION_NO_FIX_LOONGSON2F_NOP, 1523 OPTION_FIX_VR4120, 1524 OPTION_NO_FIX_VR4120, 1525 OPTION_FIX_VR4130, 1526 OPTION_NO_FIX_VR4130, 1527 OPTION_FIX_CN63XXP1, 1528 OPTION_NO_FIX_CN63XXP1, 1529 OPTION_FIX_R5900, 1530 OPTION_NO_FIX_R5900, 1531 OPTION_TRAP, 1532 OPTION_BREAK, 1533 OPTION_EB, 1534 OPTION_EL, 1535 OPTION_FP32, 1536 OPTION_GP32, 1537 OPTION_CONSTRUCT_FLOATS, 1538 OPTION_NO_CONSTRUCT_FLOATS, 1539 OPTION_FP64, 1540 OPTION_FPXX, 1541 OPTION_GP64, 1542 OPTION_RELAX_BRANCH, 1543 OPTION_NO_RELAX_BRANCH, 1544 OPTION_IGNORE_BRANCH_ISA, 1545 OPTION_NO_IGNORE_BRANCH_ISA, 1546 OPTION_INSN32, 1547 OPTION_NO_INSN32, 1548 OPTION_MSHARED, 1549 OPTION_MNO_SHARED, 1550 OPTION_MSYM32, 1551 OPTION_MNO_SYM32, 1552 OPTION_SOFT_FLOAT, 1553 OPTION_HARD_FLOAT, 1554 OPTION_SINGLE_FLOAT, 1555 OPTION_DOUBLE_FLOAT, 1556 OPTION_32, 1557 OPTION_CALL_SHARED, 1558 OPTION_CALL_NONPIC, 1559 OPTION_NON_SHARED, 1560 OPTION_XGOT, 1561 OPTION_MABI, 1562 OPTION_N32, 1563 OPTION_64, 1564 OPTION_MDEBUG, 1565 OPTION_NO_MDEBUG, 1566 OPTION_PDR, 1567 OPTION_NO_PDR, 1568 OPTION_MVXWORKS_PIC, 1569 OPTION_NAN, 1570 OPTION_ODD_SPREG, 1571 OPTION_NO_ODD_SPREG, 1572 OPTION_GINV, 1573 OPTION_NO_GINV, 1574 OPTION_LOONGSON_MMI, 1575 OPTION_NO_LOONGSON_MMI, 1576 OPTION_LOONGSON_CAM, 1577 OPTION_NO_LOONGSON_CAM, 1578 OPTION_LOONGSON_EXT, 1579 OPTION_NO_LOONGSON_EXT, 1580 OPTION_LOONGSON_EXT2, 1581 OPTION_NO_LOONGSON_EXT2, 1582 OPTION_FIX_LOONGSON2F_BTB, 1583 OPTION_NO_FIX_LOONGSON2F_BTB, 1584 OPTION_END_OF_ENUM 1585 }; 1586 1587struct option md_longopts[] = 1588{ 1589 /* Options which specify architecture. */ 1590 {"march", required_argument, NULL, OPTION_MARCH}, 1591 {"mtune", required_argument, NULL, OPTION_MTUNE}, 1592 {"mips0", no_argument, NULL, OPTION_MIPS1}, 1593 {"mips1", no_argument, NULL, OPTION_MIPS1}, 1594 {"mips2", no_argument, NULL, OPTION_MIPS2}, 1595 {"mips3", no_argument, NULL, OPTION_MIPS3}, 1596 {"mips4", no_argument, NULL, OPTION_MIPS4}, 1597 {"mips5", no_argument, NULL, OPTION_MIPS5}, 1598 {"mips32", no_argument, NULL, OPTION_MIPS32}, 1599 {"mips64", no_argument, NULL, OPTION_MIPS64}, 1600 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 1601 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, 1602 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, 1603 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, 1604 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 1605 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, 1606 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, 1607 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, 1608 1609 /* Options which specify Application Specific Extensions (ASEs). */ 1610 {"mips16", no_argument, NULL, OPTION_MIPS16}, 1611 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 1612 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 1613 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 1614 {"mdmx", no_argument, NULL, OPTION_MDMX}, 1615 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 1616 {"mdsp", no_argument, NULL, OPTION_DSP}, 1617 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, 1618 {"mmt", no_argument, NULL, OPTION_MT}, 1619 {"mno-mt", no_argument, NULL, OPTION_NO_MT}, 1620 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, 1621 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, 1622 {"mdspr2", no_argument, NULL, OPTION_DSPR2}, 1623 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, 1624 {"mdspr3", no_argument, NULL, OPTION_DSPR3}, 1625 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, 1626 {"meva", no_argument, NULL, OPTION_EVA}, 1627 {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, 1628 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, 1629 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, 1630 {"mmcu", no_argument, NULL, OPTION_MCU}, 1631 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, 1632 {"mvirt", no_argument, NULL, OPTION_VIRT}, 1633 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, 1634 {"mmsa", no_argument, NULL, OPTION_MSA}, 1635 {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, 1636 {"mxpa", no_argument, NULL, OPTION_XPA}, 1637 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, 1638 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, 1639 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, 1640 {"mcrc", no_argument, NULL, OPTION_CRC}, 1641 {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, 1642 {"mginv", no_argument, NULL, OPTION_GINV}, 1643 {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, 1644 {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, 1645 {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, 1646 {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, 1647 {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, 1648 {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, 1649 {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, 1650 {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, 1651 {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, 1652 1653 /* Old-style architecture options. Don't add more of these. */ 1654 {"m4650", no_argument, NULL, OPTION_M4650}, 1655 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 1656 {"m4010", no_argument, NULL, OPTION_M4010}, 1657 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 1658 {"m4100", no_argument, NULL, OPTION_M4100}, 1659 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 1660 {"m3900", no_argument, NULL, OPTION_M3900}, 1661 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 1662 1663 /* Options which enable bug fixes. */ 1664 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 1665 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1666 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 1667 {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC}, 1668 {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC}, 1669 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, 1670 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, 1671 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, 1672 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, 1673 {"mfix-loongson2f-btb", no_argument, NULL, OPTION_FIX_LOONGSON2F_BTB}, 1674 {"mno-fix-loongson2f-btb", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_BTB}, 1675 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 1676 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 1677 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, 1678 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, 1679 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, 1680 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, 1681 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, 1682 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, 1683 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, 1684 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, 1685 {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, 1686 {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, 1687 1688 /* Miscellaneous options. */ 1689 {"trap", no_argument, NULL, OPTION_TRAP}, 1690 {"no-break", no_argument, NULL, OPTION_TRAP}, 1691 {"break", no_argument, NULL, OPTION_BREAK}, 1692 {"no-trap", no_argument, NULL, OPTION_BREAK}, 1693 {"EB", no_argument, NULL, OPTION_EB}, 1694 {"EL", no_argument, NULL, OPTION_EL}, 1695 {"mfp32", no_argument, NULL, OPTION_FP32}, 1696 {"mgp32", no_argument, NULL, OPTION_GP32}, 1697 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 1698 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 1699 {"mfp64", no_argument, NULL, OPTION_FP64}, 1700 {"mfpxx", no_argument, NULL, OPTION_FPXX}, 1701 {"mgp64", no_argument, NULL, OPTION_GP64}, 1702 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 1703 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 1704 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, 1705 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, 1706 {"minsn32", no_argument, NULL, OPTION_INSN32}, 1707 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, 1708 {"mshared", no_argument, NULL, OPTION_MSHARED}, 1709 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, 1710 {"msym32", no_argument, NULL, OPTION_MSYM32}, 1711 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, 1712 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, 1713 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, 1714 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, 1715 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, 1716 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, 1717 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, 1718 1719 /* Strictly speaking this next option is ELF specific, 1720 but we allow it for other ports as well in order to 1721 make testing easier. */ 1722 {"32", no_argument, NULL, OPTION_32}, 1723 1724 /* ELF-specific options. */ 1725 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 1726 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 1727 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, 1728 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 1729 {"xgot", no_argument, NULL, OPTION_XGOT}, 1730 {"mabi", required_argument, NULL, OPTION_MABI}, 1731 {"n32", no_argument, NULL, OPTION_N32}, 1732 {"64", no_argument, NULL, OPTION_64}, 1733 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 1734 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 1735 {"mpdr", no_argument, NULL, OPTION_PDR}, 1736 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 1737 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, 1738 {"mnan", required_argument, NULL, OPTION_NAN}, 1739 1740 {NULL, no_argument, NULL, 0} 1741}; 1742size_t md_longopts_size = sizeof (md_longopts); 1743 1744/* Information about either an Application Specific Extension or an 1745 optional architecture feature that, for simplicity, we treat in the 1746 same way as an ASE. */ 1747struct mips_ase 1748{ 1749 /* The name of the ASE, used in both the command-line and .set options. */ 1750 const char *name; 1751 1752 /* The associated ASE_* flags. If the ASE is available on both 32-bit 1753 and 64-bit architectures, the flags here refer to the subset that 1754 is available on both. */ 1755 unsigned int flags; 1756 1757 /* The ASE_* flag used for instructions that are available on 64-bit 1758 architectures but that are not included in FLAGS. */ 1759 unsigned int flags64; 1760 1761 /* The command-line options that turn the ASE on and off. */ 1762 int option_on; 1763 int option_off; 1764 1765 /* The minimum required architecture revisions for MIPS32, MIPS64, 1766 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ 1767 int mips32_rev; 1768 int mips64_rev; 1769 int micromips32_rev; 1770 int micromips64_rev; 1771 1772 /* The architecture where the ASE was removed or -1 if the extension has not 1773 been removed. */ 1774 int rem_rev; 1775}; 1776 1777/* A table of all supported ASEs. */ 1778static const struct mips_ase mips_ases[] = { 1779 { "dsp", ASE_DSP, ASE_DSP64, 1780 OPTION_DSP, OPTION_NO_DSP, 1781 2, 2, 2, 2, 1782 -1 }, 1783 1784 { "dspr2", ASE_DSP | ASE_DSPR2, 0, 1785 OPTION_DSPR2, OPTION_NO_DSPR2, 1786 2, 2, 2, 2, 1787 -1 }, 1788 1789 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, 1790 OPTION_DSPR3, OPTION_NO_DSPR3, 1791 6, 6, -1, -1, 1792 -1 }, 1793 1794 { "eva", ASE_EVA, 0, 1795 OPTION_EVA, OPTION_NO_EVA, 1796 2, 2, 2, 2, 1797 -1 }, 1798 1799 { "mcu", ASE_MCU, 0, 1800 OPTION_MCU, OPTION_NO_MCU, 1801 2, 2, 2, 2, 1802 -1 }, 1803 1804 /* Deprecated in MIPS64r5, but we don't implement that yet. */ 1805 { "mdmx", ASE_MDMX, 0, 1806 OPTION_MDMX, OPTION_NO_MDMX, 1807 -1, 1, -1, -1, 1808 6 }, 1809 1810 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ 1811 { "mips3d", ASE_MIPS3D, 0, 1812 OPTION_MIPS3D, OPTION_NO_MIPS3D, 1813 2, 1, -1, -1, 1814 6 }, 1815 1816 { "mt", ASE_MT, 0, 1817 OPTION_MT, OPTION_NO_MT, 1818 2, 2, -1, -1, 1819 -1 }, 1820 1821 { "smartmips", ASE_SMARTMIPS, 0, 1822 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, 1823 1, -1, -1, -1, 1824 6 }, 1825 1826 { "virt", ASE_VIRT, ASE_VIRT64, 1827 OPTION_VIRT, OPTION_NO_VIRT, 1828 2, 2, 2, 2, 1829 -1 }, 1830 1831 { "msa", ASE_MSA, ASE_MSA64, 1832 OPTION_MSA, OPTION_NO_MSA, 1833 2, 2, 2, 2, 1834 -1 }, 1835 1836 { "xpa", ASE_XPA, 0, 1837 OPTION_XPA, OPTION_NO_XPA, 1838 2, 2, 2, 2, 1839 -1 }, 1840 1841 { "mips16e2", ASE_MIPS16E2, 0, 1842 OPTION_MIPS16E2, OPTION_NO_MIPS16E2, 1843 2, 2, -1, -1, 1844 6 }, 1845 1846 { "crc", ASE_CRC, ASE_CRC64, 1847 OPTION_CRC, OPTION_NO_CRC, 1848 6, 6, -1, -1, 1849 -1 }, 1850 1851 { "ginv", ASE_GINV, 0, 1852 OPTION_GINV, OPTION_NO_GINV, 1853 6, 6, 6, 6, 1854 -1 }, 1855 1856 { "loongson-mmi", ASE_LOONGSON_MMI, 0, 1857 OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, 1858 0, 0, -1, -1, 1859 -1 }, 1860 1861 { "loongson-cam", ASE_LOONGSON_CAM, 0, 1862 OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, 1863 0, 0, -1, -1, 1864 -1 }, 1865 1866 { "loongson-ext", ASE_LOONGSON_EXT, 0, 1867 OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, 1868 0, 0, -1, -1, 1869 -1 }, 1870 1871 { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, 1872 OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, 1873 0, 0, -1, -1, 1874 -1 }, 1875}; 1876 1877/* The set of ASEs that require -mfp64. */ 1878#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) 1879 1880/* Groups of ASE_* flags that represent different revisions of an ASE. */ 1881static const unsigned int mips_ase_groups[] = { 1882 ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 1883 ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 1884}; 1885 1886/* Pseudo-op table. 1887 1888 The following pseudo-ops from the Kane and Heinrich MIPS book 1889 should be defined here, but are currently unsupported: .alias, 1890 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 1891 1892 The following pseudo-ops from the Kane and Heinrich MIPS book are 1893 specific to the type of debugging information being generated, and 1894 should be defined by the object format: .aent, .begin, .bend, 1895 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 1896 .vreg. 1897 1898 The following pseudo-ops from the Kane and Heinrich MIPS book are 1899 not MIPS CPU specific, but are also not specific to the object file 1900 format. This file is probably the best place to define them, but 1901 they are not currently supported: .asm0, .endr, .lab, .struct. */ 1902 1903static const pseudo_typeS mips_pseudo_table[] = 1904{ 1905 /* MIPS specific pseudo-ops. */ 1906 {"option", s_option, 0}, 1907 {"set", s_mipsset, 0}, 1908 {"rdata", s_change_sec, 'r'}, 1909 {"sdata", s_change_sec, 's'}, 1910 {"livereg", s_ignore, 0}, 1911 {"abicalls", s_abicalls, 0}, 1912 {"cpload", s_cpload, 0}, 1913 {"cpsetup", s_cpsetup, 0}, 1914 {"cplocal", s_cplocal, 0}, 1915 {"cprestore", s_cprestore, 0}, 1916 {"cpreturn", s_cpreturn, 0}, 1917 {"dtprelword", s_dtprelword, 0}, 1918 {"dtpreldword", s_dtpreldword, 0}, 1919 {"tprelword", s_tprelword, 0}, 1920 {"tpreldword", s_tpreldword, 0}, 1921 {"gpvalue", s_gpvalue, 0}, 1922 {"gpword", s_gpword, 0}, 1923 {"gpdword", s_gpdword, 0}, 1924 {"ehword", s_ehword, 0}, 1925 {"cpadd", s_cpadd, 0}, 1926 {"insn", s_insn, 0}, 1927 {"nan", s_nan, 0}, 1928 {"module", s_module, 0}, 1929 1930 /* Relatively generic pseudo-ops that happen to be used on MIPS 1931 chips. */ 1932 {"asciiz", stringer, 8 + 1}, 1933 {"bss", s_change_sec, 'b'}, 1934 {"err", s_err, 0}, 1935 {"half", s_cons, 1}, 1936 {"dword", s_cons, 3}, 1937 {"weakext", s_mips_weakext, 0}, 1938 {"origin", s_org, 0}, 1939 {"repeat", s_rept, 0}, 1940 1941 /* For MIPS this is non-standard, but we define it for consistency. */ 1942 {"sbss", s_change_sec, 'B'}, 1943 1944 /* These pseudo-ops are defined in read.c, but must be overridden 1945 here for one reason or another. */ 1946 {"align", s_align, 0}, 1947 {"byte", s_cons, 0}, 1948 {"data", s_change_sec, 'd'}, 1949 {"double", s_float_cons, 'd'}, 1950 {"float", s_float_cons, 'f'}, 1951 {"globl", s_mips_globl, 0}, 1952 {"global", s_mips_globl, 0}, 1953 {"hword", s_cons, 1}, 1954 {"int", s_cons, 2}, 1955 {"long", s_cons, 2}, 1956 {"octa", s_cons, 4}, 1957 {"quad", s_cons, 3}, 1958 {"section", s_change_section, 0}, 1959 {"short", s_cons, 1}, 1960 {"single", s_float_cons, 'f'}, 1961 {"stabd", s_mips_stab, 'd'}, 1962 {"stabn", s_mips_stab, 'n'}, 1963 {"stabs", s_mips_stab, 's'}, 1964 {"text", s_change_sec, 't'}, 1965 {"word", s_cons, 2}, 1966 1967 { "extern", ecoff_directive_extern, 0}, 1968 1969 { NULL, NULL, 0 }, 1970}; 1971 1972static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1973{ 1974 /* These pseudo-ops should be defined by the object file format. 1975 However, a.out doesn't support them, so we have versions here. */ 1976 {"aent", s_mips_ent, 1}, 1977 {"bgnb", s_ignore, 0}, 1978 {"end", s_mips_end, 0}, 1979 {"endb", s_ignore, 0}, 1980 {"ent", s_mips_ent, 0}, 1981 {"file", s_mips_file, 0}, 1982 {"fmask", s_mips_mask, 'F'}, 1983 {"frame", s_mips_frame, 0}, 1984 {"loc", s_mips_loc, 0}, 1985 {"mask", s_mips_mask, 'R'}, 1986 {"verstamp", s_ignore, 0}, 1987 { NULL, NULL, 0 }, 1988}; 1989 1990/* Export the ABI address size for use by TC_ADDRESS_BYTES for the 1991 purpose of the `.dc.a' internal pseudo-op. */ 1992 1993int 1994mips_address_bytes (void) 1995{ 1996 file_mips_check_options (); 1997 return HAVE_64BIT_ADDRESSES ? 8 : 4; 1998} 1999 2000extern void pop_insert (const pseudo_typeS *); 2001 2002void 2003mips_pop_insert (void) 2004{ 2005 pop_insert (mips_pseudo_table); 2006 if (! ECOFF_DEBUGGING) 2007 pop_insert (mips_nonecoff_pseudo_table); 2008} 2009 2010/* Symbols labelling the current insn. */ 2011 2012struct insn_label_list 2013{ 2014 struct insn_label_list *next; 2015 symbolS *label; 2016}; 2017 2018static struct insn_label_list *free_insn_labels; 2019#define label_list tc_segment_info_data.labels 2020 2021static void mips_clear_insn_labels (void); 2022static void mips_mark_labels (void); 2023static void mips_compressed_mark_labels (void); 2024 2025static inline void 2026mips_clear_insn_labels (void) 2027{ 2028 struct insn_label_list **pl; 2029 segment_info_type *si; 2030 2031 if (now_seg) 2032 { 2033 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 2034 ; 2035 2036 si = seg_info (now_seg); 2037 *pl = si->label_list; 2038 si->label_list = NULL; 2039 } 2040} 2041 2042/* Mark instruction labels in MIPS16/microMIPS mode. */ 2043 2044static inline void 2045mips_mark_labels (void) 2046{ 2047 if (HAVE_CODE_COMPRESSION) 2048 mips_compressed_mark_labels (); 2049} 2050 2051static char *expr_end; 2052 2053/* An expression in a macro instruction. This is set by mips_ip and 2054 mips16_ip and when populated is always an O_constant. */ 2055 2056static expressionS imm_expr; 2057 2058/* The relocatable field in an instruction and the relocs associated 2059 with it. These variables are used for instructions like LUI and 2060 JAL as well as true offsets. They are also used for address 2061 operands in macros. */ 2062 2063static expressionS offset_expr; 2064static bfd_reloc_code_real_type offset_reloc[3] 2065 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 2066 2067/* This is set to the resulting size of the instruction to be produced 2068 by mips16_ip if an explicit extension is used or by mips_ip if an 2069 explicit size is supplied. */ 2070 2071static unsigned int forced_insn_length; 2072 2073/* True if we are assembling an instruction. All dot symbols defined during 2074 this time should be treated as code labels. */ 2075 2076static bfd_boolean mips_assembling_insn; 2077 2078/* The pdr segment for per procedure frame/regmask info. Not used for 2079 ECOFF debugging. */ 2080 2081static segT pdr_seg; 2082 2083/* The default target format to use. */ 2084 2085#if defined (TE_FreeBSD) 2086#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" 2087#elif defined (TE_TMIPS) 2088#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" 2089#else 2090#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" 2091#endif 2092 2093const char * 2094mips_target_format (void) 2095{ 2096 switch (OUTPUT_FLAVOR) 2097 { 2098 case bfd_target_elf_flavour: 2099#ifdef TE_VXWORKS 2100 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) 2101 return (target_big_endian 2102 ? "elf32-bigmips-vxworks" 2103 : "elf32-littlemips-vxworks"); 2104#endif 2105 return (target_big_endian 2106 ? (HAVE_64BIT_OBJECTS 2107 ? ELF_TARGET ("elf64-", "big") 2108 : (HAVE_NEWABI 2109 ? ELF_TARGET ("elf32-n", "big") 2110 : ELF_TARGET ("elf32-", "big"))) 2111 : (HAVE_64BIT_OBJECTS 2112 ? ELF_TARGET ("elf64-", "little") 2113 : (HAVE_NEWABI 2114 ? ELF_TARGET ("elf32-n", "little") 2115 : ELF_TARGET ("elf32-", "little")))); 2116 default: 2117 abort (); 2118 return NULL; 2119 } 2120} 2121 2122/* Return the ISA revision that is currently in use, or 0 if we are 2123 generating code for MIPS V or below. */ 2124 2125static int 2126mips_isa_rev (void) 2127{ 2128 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) 2129 return 2; 2130 2131 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) 2132 return 3; 2133 2134 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) 2135 return 5; 2136 2137 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) 2138 return 6; 2139 2140 /* microMIPS implies revision 2 or above. */ 2141 if (mips_opts.micromips) 2142 return 2; 2143 2144 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) 2145 return 1; 2146 2147 return 0; 2148} 2149 2150/* Return the mask of all ASEs that are revisions of those in FLAGS. */ 2151 2152static unsigned int 2153mips_ase_mask (unsigned int flags) 2154{ 2155 unsigned int i; 2156 2157 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) 2158 if (flags & mips_ase_groups[i]) 2159 flags |= mips_ase_groups[i]; 2160 return flags; 2161} 2162 2163/* Check whether the current ISA supports ASE. Issue a warning if 2164 appropriate. */ 2165 2166static void 2167mips_check_isa_supports_ase (const struct mips_ase *ase) 2168{ 2169 const char *base; 2170 int min_rev, size; 2171 static unsigned int warned_isa; 2172 static unsigned int warned_fp32; 2173 2174 if (ISA_HAS_64BIT_REGS (mips_opts.isa)) 2175 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; 2176 else 2177 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; 2178 if ((min_rev < 0 || mips_isa_rev () < min_rev) 2179 && (warned_isa & ase->flags) != ase->flags) 2180 { 2181 warned_isa |= ase->flags; 2182 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2183 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2184 if (min_rev < 0) 2185 as_warn (_("the %d-bit %s architecture does not support the" 2186 " `%s' extension"), size, base, ase->name); 2187 else 2188 as_warn (_("the `%s' extension requires %s%d revision %d or greater"), 2189 ase->name, base, size, min_rev); 2190 } 2191 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) 2192 && (warned_isa & ase->flags) != ase->flags) 2193 { 2194 warned_isa |= ase->flags; 2195 base = mips_opts.micromips ? "microMIPS" : "MIPS"; 2196 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; 2197 as_warn (_("the `%s' extension was removed in %s%d revision %d"), 2198 ase->name, base, size, ase->rem_rev); 2199 } 2200 2201 if ((ase->flags & FP64_ASES) 2202 && mips_opts.fp != 64 2203 && (warned_fp32 & ase->flags) != ase->flags) 2204 { 2205 warned_fp32 |= ase->flags; 2206 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); 2207 } 2208} 2209 2210/* Check all enabled ASEs to see whether they are supported by the 2211 chosen architecture. */ 2212 2213static void 2214mips_check_isa_supports_ases (void) 2215{ 2216 unsigned int i, mask; 2217 2218 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2219 { 2220 mask = mips_ase_mask (mips_ases[i].flags); 2221 if ((mips_opts.ase & mask) == mips_ases[i].flags) 2222 mips_check_isa_supports_ase (&mips_ases[i]); 2223 } 2224} 2225 2226/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags 2227 that were affected. */ 2228 2229static unsigned int 2230mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, 2231 bfd_boolean enabled_p) 2232{ 2233 unsigned int mask; 2234 2235 mask = mips_ase_mask (ase->flags); 2236 opts->ase &= ~mask; 2237 2238 /* Clear combination ASE flags, which need to be recalculated based on 2239 updated regular ASE settings. */ 2240 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); 2241 2242 if (enabled_p) 2243 opts->ase |= ase->flags; 2244 2245 /* The Virtualization ASE has eXtended Physical Addressing (XPA) 2246 instructions which are only valid when both ASEs are enabled. 2247 This sets the ASE_XPA_VIRT flag when both ASEs are present. */ 2248 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) 2249 { 2250 opts->ase |= ASE_XPA_VIRT; 2251 mask |= ASE_XPA_VIRT; 2252 } 2253 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) 2254 { 2255 opts->ase |= ASE_MIPS16E2_MT; 2256 mask |= ASE_MIPS16E2_MT; 2257 } 2258 2259 /* The EVA Extension has instructions which are only valid when the R6 ISA 2260 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are 2261 present. */ 2262 if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa)) 2263 { 2264 opts->ase |= ASE_EVA_R6; 2265 mask |= ASE_EVA_R6; 2266 } 2267 2268 return mask; 2269} 2270 2271/* Return the ASE called NAME, or null if none. */ 2272 2273static const struct mips_ase * 2274mips_lookup_ase (const char *name) 2275{ 2276 unsigned int i; 2277 2278 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 2279 if (strcmp (name, mips_ases[i].name) == 0) 2280 return &mips_ases[i]; 2281 return NULL; 2282} 2283 2284/* Return the length of a microMIPS instruction in bytes. If bits of 2285 the mask beyond the low 16 are 0, then it is a 16-bit instruction, 2286 otherwise it is a 32-bit instruction. */ 2287 2288static inline unsigned int 2289micromips_insn_length (const struct mips_opcode *mo) 2290{ 2291 return mips_opcode_32bit_p (mo) ? 4 : 2; 2292} 2293 2294/* Return the length of MIPS16 instruction OPCODE. */ 2295 2296static inline unsigned int 2297mips16_opcode_length (unsigned long opcode) 2298{ 2299 return (opcode >> 16) == 0 ? 2 : 4; 2300} 2301 2302/* Return the length of instruction INSN. */ 2303 2304static inline unsigned int 2305insn_length (const struct mips_cl_insn *insn) 2306{ 2307 if (mips_opts.micromips) 2308 return micromips_insn_length (insn->insn_mo); 2309 else if (mips_opts.mips16) 2310 return mips16_opcode_length (insn->insn_opcode); 2311 else 2312 return 4; 2313} 2314 2315/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 2316 2317static void 2318create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) 2319{ 2320 size_t i; 2321 2322 insn->insn_mo = mo; 2323 insn->insn_opcode = mo->match; 2324 insn->frag = NULL; 2325 insn->where = 0; 2326 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2327 insn->fixp[i] = NULL; 2328 insn->fixed_p = (mips_opts.noreorder > 0); 2329 insn->noreorder_p = (mips_opts.noreorder > 0); 2330 insn->mips16_absolute_jump_p = 0; 2331 insn->complete_p = 0; 2332 insn->cleared_p = 0; 2333} 2334 2335/* Get a list of all the operands in INSN. */ 2336 2337static const struct mips_operand_array * 2338insn_operands (const struct mips_cl_insn *insn) 2339{ 2340 if (insn->insn_mo >= &mips_opcodes[0] 2341 && insn->insn_mo < &mips_opcodes[NUMOPCODES]) 2342 return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; 2343 2344 if (insn->insn_mo >= &mips16_opcodes[0] 2345 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) 2346 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; 2347 2348 if (insn->insn_mo >= µmips_opcodes[0] 2349 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) 2350 return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; 2351 2352 abort (); 2353} 2354 2355/* Get a description of operand OPNO of INSN. */ 2356 2357static const struct mips_operand * 2358insn_opno (const struct mips_cl_insn *insn, unsigned opno) 2359{ 2360 const struct mips_operand_array *operands; 2361 2362 operands = insn_operands (insn); 2363 if (opno >= MAX_OPERANDS || !operands->operand[opno]) 2364 abort (); 2365 return operands->operand[opno]; 2366} 2367 2368/* Install UVAL as the value of OPERAND in INSN. */ 2369 2370static inline void 2371insn_insert_operand (struct mips_cl_insn *insn, 2372 const struct mips_operand *operand, unsigned int uval) 2373{ 2374 if (mips_opts.mips16 2375 && operand->type == OP_INT && operand->lsb == 0 2376 && mips_opcode_32bit_p (insn->insn_mo)) 2377 insn->insn_opcode |= mips16_immed_extend (uval, operand->size); 2378 else 2379 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); 2380} 2381 2382/* Extract the value of OPERAND from INSN. */ 2383 2384static inline unsigned 2385insn_extract_operand (const struct mips_cl_insn *insn, 2386 const struct mips_operand *operand) 2387{ 2388 return mips_extract_operand (operand, insn->insn_opcode); 2389} 2390 2391/* Record the current MIPS16/microMIPS mode in now_seg. */ 2392 2393static void 2394mips_record_compressed_mode (void) 2395{ 2396 segment_info_type *si; 2397 2398 si = seg_info (now_seg); 2399 if (si->tc_segment_info_data.mips16 != mips_opts.mips16) 2400 si->tc_segment_info_data.mips16 = mips_opts.mips16; 2401 if (si->tc_segment_info_data.micromips != mips_opts.micromips) 2402 si->tc_segment_info_data.micromips = mips_opts.micromips; 2403} 2404 2405/* Read a standard MIPS instruction from BUF. */ 2406 2407static unsigned long 2408read_insn (char *buf) 2409{ 2410 if (target_big_endian) 2411 return bfd_getb32 ((bfd_byte *) buf); 2412 else 2413 return bfd_getl32 ((bfd_byte *) buf); 2414} 2415 2416/* Write standard MIPS instruction INSN to BUF. Return a pointer to 2417 the next byte. */ 2418 2419static char * 2420write_insn (char *buf, unsigned int insn) 2421{ 2422 md_number_to_chars (buf, insn, 4); 2423 return buf + 4; 2424} 2425 2426/* Read a microMIPS or MIPS16 opcode from BUF, given that it 2427 has length LENGTH. */ 2428 2429static unsigned long 2430read_compressed_insn (char *buf, unsigned int length) 2431{ 2432 unsigned long insn; 2433 unsigned int i; 2434 2435 insn = 0; 2436 for (i = 0; i < length; i += 2) 2437 { 2438 insn <<= 16; 2439 if (target_big_endian) 2440 insn |= bfd_getb16 ((char *) buf); 2441 else 2442 insn |= bfd_getl16 ((char *) buf); 2443 buf += 2; 2444 } 2445 return insn; 2446} 2447 2448/* Write microMIPS or MIPS16 instruction INSN to BUF, given that the 2449 instruction is LENGTH bytes long. Return a pointer to the next byte. */ 2450 2451static char * 2452write_compressed_insn (char *buf, unsigned int insn, unsigned int length) 2453{ 2454 unsigned int i; 2455 2456 for (i = 0; i < length; i += 2) 2457 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); 2458 return buf + length; 2459} 2460 2461/* Install INSN at the location specified by its "frag" and "where" fields. */ 2462 2463static void 2464install_insn (const struct mips_cl_insn *insn) 2465{ 2466 char *f = insn->frag->fr_literal + insn->where; 2467 if (HAVE_CODE_COMPRESSION) 2468 write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); 2469 else 2470 write_insn (f, insn->insn_opcode); 2471 mips_record_compressed_mode (); 2472} 2473 2474/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 2475 and install the opcode in the new location. */ 2476 2477static void 2478move_insn (struct mips_cl_insn *insn, fragS *frag, long where) 2479{ 2480 size_t i; 2481 2482 insn->frag = frag; 2483 insn->where = where; 2484 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) 2485 if (insn->fixp[i] != NULL) 2486 { 2487 insn->fixp[i]->fx_frag = frag; 2488 insn->fixp[i]->fx_where = where; 2489 } 2490 install_insn (insn); 2491} 2492 2493/* Add INSN to the end of the output. */ 2494 2495static void 2496add_fixed_insn (struct mips_cl_insn *insn) 2497{ 2498 char *f = frag_more (insn_length (insn)); 2499 move_insn (insn, frag_now, f - frag_now->fr_literal); 2500} 2501 2502/* Start a variant frag and move INSN to the start of the variant part, 2503 marking it as fixed. The other arguments are as for frag_var. */ 2504 2505static void 2506add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, 2507 relax_substateT subtype, symbolS *symbol, offsetT offset) 2508{ 2509 frag_grow (max_chars); 2510 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 2511 insn->fixed_p = 1; 2512 frag_var (rs_machine_dependent, max_chars, var, 2513 subtype, symbol, offset, NULL); 2514} 2515 2516/* Insert N copies of INSN into the history buffer, starting at 2517 position FIRST. Neither FIRST nor N need to be clipped. */ 2518 2519static void 2520insert_into_history (unsigned int first, unsigned int n, 2521 const struct mips_cl_insn *insn) 2522{ 2523 if (mips_relax.sequence != 2) 2524 { 2525 unsigned int i; 2526 2527 for (i = ARRAY_SIZE (history); i-- > first;) 2528 if (i >= first + n) 2529 history[i] = history[i - n]; 2530 else 2531 history[i] = *insn; 2532 } 2533} 2534 2535/* Clear the error in insn_error. */ 2536 2537static void 2538clear_insn_error (void) 2539{ 2540 memset (&insn_error, 0, sizeof (insn_error)); 2541} 2542 2543/* Possibly record error message MSG for the current instruction. 2544 If the error is about a particular argument, ARGNUM is the 1-based 2545 number of that argument, otherwise it is 0. FORMAT is the format 2546 of MSG. Return true if MSG was used, false if the current message 2547 was kept. */ 2548 2549static bfd_boolean 2550set_insn_error_format (int argnum, enum mips_insn_error_format format, 2551 const char *msg) 2552{ 2553 if (argnum == 0) 2554 { 2555 /* Give priority to errors against specific arguments, and to 2556 the first whole-instruction message. */ 2557 if (insn_error.msg) 2558 return FALSE; 2559 } 2560 else 2561 { 2562 /* Keep insn_error if it is against a later argument. */ 2563 if (argnum < insn_error.min_argnum) 2564 return FALSE; 2565 2566 /* If both errors are against the same argument but are different, 2567 give up on reporting a specific error for this argument. 2568 See the comment about mips_insn_error for details. */ 2569 if (argnum == insn_error.min_argnum 2570 && insn_error.msg 2571 && strcmp (insn_error.msg, msg) != 0) 2572 { 2573 insn_error.msg = 0; 2574 insn_error.min_argnum += 1; 2575 return FALSE; 2576 } 2577 } 2578 insn_error.min_argnum = argnum; 2579 insn_error.format = format; 2580 insn_error.msg = msg; 2581 return TRUE; 2582} 2583 2584/* Record an instruction error with no % format fields. ARGNUM and MSG are 2585 as for set_insn_error_format. */ 2586 2587static void 2588set_insn_error (int argnum, const char *msg) 2589{ 2590 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); 2591} 2592 2593/* Record an instruction error with one %d field I. ARGNUM and MSG are 2594 as for set_insn_error_format. */ 2595 2596static void 2597set_insn_error_i (int argnum, const char *msg, int i) 2598{ 2599 if (set_insn_error_format (argnum, ERR_FMT_I, msg)) 2600 insn_error.u.i = i; 2601} 2602 2603/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG 2604 are as for set_insn_error_format. */ 2605 2606static void 2607set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) 2608{ 2609 if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) 2610 { 2611 insn_error.u.ss[0] = s1; 2612 insn_error.u.ss[1] = s2; 2613 } 2614} 2615 2616/* Report the error in insn_error, which is against assembly code STR. */ 2617 2618static void 2619report_insn_error (const char *str) 2620{ 2621 const char *msg = concat (insn_error.msg, " `%s'", NULL); 2622 2623 switch (insn_error.format) 2624 { 2625 case ERR_FMT_PLAIN: 2626 as_bad (msg, str); 2627 break; 2628 2629 case ERR_FMT_I: 2630 as_bad (msg, insn_error.u.i, str); 2631 break; 2632 2633 case ERR_FMT_SS: 2634 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); 2635 break; 2636 } 2637 2638 free ((char *) msg); 2639} 2640 2641/* Initialize vr4120_conflicts. There is a bit of duplication here: 2642 the idea is to make it obvious at a glance that each errata is 2643 included. */ 2644 2645static void 2646init_vr4120_conflicts (void) 2647{ 2648#define CONFLICT(FIRST, SECOND) \ 2649 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND 2650 2651 /* Errata 21 - [D]DIV[U] after [D]MACC */ 2652 CONFLICT (MACC, DIV); 2653 CONFLICT (DMACC, DIV); 2654 2655 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ 2656 CONFLICT (DMULT, DMULT); 2657 CONFLICT (DMULT, DMACC); 2658 CONFLICT (DMACC, DMULT); 2659 CONFLICT (DMACC, DMACC); 2660 2661 /* Errata 24 - MT{LO,HI} after [D]MACC */ 2662 CONFLICT (MACC, MTHILO); 2663 CONFLICT (DMACC, MTHILO); 2664 2665 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU 2666 instruction is executed immediately after a MACC or DMACC 2667 instruction, the result of [either instruction] is incorrect." */ 2668 CONFLICT (MACC, MULT); 2669 CONFLICT (MACC, DMULT); 2670 CONFLICT (DMACC, MULT); 2671 CONFLICT (DMACC, DMULT); 2672 2673 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is 2674 executed immediately after a DMULT, DMULTU, DIV, DIVU, 2675 DDIV or DDIVU instruction, the result of the MACC or 2676 DMACC instruction is incorrect.". */ 2677 CONFLICT (DMULT, MACC); 2678 CONFLICT (DMULT, DMACC); 2679 CONFLICT (DIV, MACC); 2680 CONFLICT (DIV, DMACC); 2681 2682#undef CONFLICT 2683} 2684 2685struct regname { 2686 const char *name; 2687 unsigned int num; 2688}; 2689 2690#define RNUM_MASK 0x00000ff 2691#define RTYPE_MASK 0x0ffff00 2692#define RTYPE_NUM 0x0000100 2693#define RTYPE_FPU 0x0000200 2694#define RTYPE_FCC 0x0000400 2695#define RTYPE_VEC 0x0000800 2696#define RTYPE_GP 0x0001000 2697#define RTYPE_CP0 0x0002000 2698#define RTYPE_PC 0x0004000 2699#define RTYPE_ACC 0x0008000 2700#define RTYPE_CCC 0x0010000 2701#define RTYPE_VI 0x0020000 2702#define RTYPE_VF 0x0040000 2703#define RTYPE_R5900_I 0x0080000 2704#define RTYPE_R5900_Q 0x0100000 2705#define RTYPE_R5900_R 0x0200000 2706#define RTYPE_R5900_ACC 0x0400000 2707#define RTYPE_MSA 0x0800000 2708#define RWARN 0x8000000 2709 2710#define GENERIC_REGISTER_NUMBERS \ 2711 {"$0", RTYPE_NUM | 0}, \ 2712 {"$1", RTYPE_NUM | 1}, \ 2713 {"$2", RTYPE_NUM | 2}, \ 2714 {"$3", RTYPE_NUM | 3}, \ 2715 {"$4", RTYPE_NUM | 4}, \ 2716 {"$5", RTYPE_NUM | 5}, \ 2717 {"$6", RTYPE_NUM | 6}, \ 2718 {"$7", RTYPE_NUM | 7}, \ 2719 {"$8", RTYPE_NUM | 8}, \ 2720 {"$9", RTYPE_NUM | 9}, \ 2721 {"$10", RTYPE_NUM | 10}, \ 2722 {"$11", RTYPE_NUM | 11}, \ 2723 {"$12", RTYPE_NUM | 12}, \ 2724 {"$13", RTYPE_NUM | 13}, \ 2725 {"$14", RTYPE_NUM | 14}, \ 2726 {"$15", RTYPE_NUM | 15}, \ 2727 {"$16", RTYPE_NUM | 16}, \ 2728 {"$17", RTYPE_NUM | 17}, \ 2729 {"$18", RTYPE_NUM | 18}, \ 2730 {"$19", RTYPE_NUM | 19}, \ 2731 {"$20", RTYPE_NUM | 20}, \ 2732 {"$21", RTYPE_NUM | 21}, \ 2733 {"$22", RTYPE_NUM | 22}, \ 2734 {"$23", RTYPE_NUM | 23}, \ 2735 {"$24", RTYPE_NUM | 24}, \ 2736 {"$25", RTYPE_NUM | 25}, \ 2737 {"$26", RTYPE_NUM | 26}, \ 2738 {"$27", RTYPE_NUM | 27}, \ 2739 {"$28", RTYPE_NUM | 28}, \ 2740 {"$29", RTYPE_NUM | 29}, \ 2741 {"$30", RTYPE_NUM | 30}, \ 2742 {"$31", RTYPE_NUM | 31} 2743 2744#define FPU_REGISTER_NAMES \ 2745 {"$f0", RTYPE_FPU | 0}, \ 2746 {"$f1", RTYPE_FPU | 1}, \ 2747 {"$f2", RTYPE_FPU | 2}, \ 2748 {"$f3", RTYPE_FPU | 3}, \ 2749 {"$f4", RTYPE_FPU | 4}, \ 2750 {"$f5", RTYPE_FPU | 5}, \ 2751 {"$f6", RTYPE_FPU | 6}, \ 2752 {"$f7", RTYPE_FPU | 7}, \ 2753 {"$f8", RTYPE_FPU | 8}, \ 2754 {"$f9", RTYPE_FPU | 9}, \ 2755 {"$f10", RTYPE_FPU | 10}, \ 2756 {"$f11", RTYPE_FPU | 11}, \ 2757 {"$f12", RTYPE_FPU | 12}, \ 2758 {"$f13", RTYPE_FPU | 13}, \ 2759 {"$f14", RTYPE_FPU | 14}, \ 2760 {"$f15", RTYPE_FPU | 15}, \ 2761 {"$f16", RTYPE_FPU | 16}, \ 2762 {"$f17", RTYPE_FPU | 17}, \ 2763 {"$f18", RTYPE_FPU | 18}, \ 2764 {"$f19", RTYPE_FPU | 19}, \ 2765 {"$f20", RTYPE_FPU | 20}, \ 2766 {"$f21", RTYPE_FPU | 21}, \ 2767 {"$f22", RTYPE_FPU | 22}, \ 2768 {"$f23", RTYPE_FPU | 23}, \ 2769 {"$f24", RTYPE_FPU | 24}, \ 2770 {"$f25", RTYPE_FPU | 25}, \ 2771 {"$f26", RTYPE_FPU | 26}, \ 2772 {"$f27", RTYPE_FPU | 27}, \ 2773 {"$f28", RTYPE_FPU | 28}, \ 2774 {"$f29", RTYPE_FPU | 29}, \ 2775 {"$f30", RTYPE_FPU | 30}, \ 2776 {"$f31", RTYPE_FPU | 31} 2777 2778#define FPU_CONDITION_CODE_NAMES \ 2779 {"$fcc0", RTYPE_FCC | 0}, \ 2780 {"$fcc1", RTYPE_FCC | 1}, \ 2781 {"$fcc2", RTYPE_FCC | 2}, \ 2782 {"$fcc3", RTYPE_FCC | 3}, \ 2783 {"$fcc4", RTYPE_FCC | 4}, \ 2784 {"$fcc5", RTYPE_FCC | 5}, \ 2785 {"$fcc6", RTYPE_FCC | 6}, \ 2786 {"$fcc7", RTYPE_FCC | 7} 2787 2788#define COPROC_CONDITION_CODE_NAMES \ 2789 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ 2790 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ 2791 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ 2792 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ 2793 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ 2794 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ 2795 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ 2796 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} 2797 2798#define N32N64_SYMBOLIC_REGISTER_NAMES \ 2799 {"$a4", RTYPE_GP | 8}, \ 2800 {"$a5", RTYPE_GP | 9}, \ 2801 {"$a6", RTYPE_GP | 10}, \ 2802 {"$a7", RTYPE_GP | 11}, \ 2803 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ 2804 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ 2805 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ 2806 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ 2807 {"$t0", RTYPE_GP | 12}, \ 2808 {"$t1", RTYPE_GP | 13}, \ 2809 {"$t2", RTYPE_GP | 14}, \ 2810 {"$t3", RTYPE_GP | 15} 2811 2812#define O32_SYMBOLIC_REGISTER_NAMES \ 2813 {"$t0", RTYPE_GP | 8}, \ 2814 {"$t1", RTYPE_GP | 9}, \ 2815 {"$t2", RTYPE_GP | 10}, \ 2816 {"$t3", RTYPE_GP | 11}, \ 2817 {"$t4", RTYPE_GP | 12}, \ 2818 {"$t5", RTYPE_GP | 13}, \ 2819 {"$t6", RTYPE_GP | 14}, \ 2820 {"$t7", RTYPE_GP | 15}, \ 2821 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ 2822 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ 2823 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ 2824 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ 2825 2826/* Remaining symbolic register names. */ 2827#define SYMBOLIC_REGISTER_NAMES \ 2828 {"$zero", RTYPE_GP | 0}, \ 2829 {"$at", RTYPE_GP | 1}, \ 2830 {"$AT", RTYPE_GP | 1}, \ 2831 {"$v0", RTYPE_GP | 2}, \ 2832 {"$v1", RTYPE_GP | 3}, \ 2833 {"$a0", RTYPE_GP | 4}, \ 2834 {"$a1", RTYPE_GP | 5}, \ 2835 {"$a2", RTYPE_GP | 6}, \ 2836 {"$a3", RTYPE_GP | 7}, \ 2837 {"$s0", RTYPE_GP | 16}, \ 2838 {"$s1", RTYPE_GP | 17}, \ 2839 {"$s2", RTYPE_GP | 18}, \ 2840 {"$s3", RTYPE_GP | 19}, \ 2841 {"$s4", RTYPE_GP | 20}, \ 2842 {"$s5", RTYPE_GP | 21}, \ 2843 {"$s6", RTYPE_GP | 22}, \ 2844 {"$s7", RTYPE_GP | 23}, \ 2845 {"$t8", RTYPE_GP | 24}, \ 2846 {"$t9", RTYPE_GP | 25}, \ 2847 {"$k0", RTYPE_GP | 26}, \ 2848 {"$kt0", RTYPE_GP | 26}, \ 2849 {"$k1", RTYPE_GP | 27}, \ 2850 {"$kt1", RTYPE_GP | 27}, \ 2851 {"$gp", RTYPE_GP | 28}, \ 2852 {"$sp", RTYPE_GP | 29}, \ 2853 {"$s8", RTYPE_GP | 30}, \ 2854 {"$fp", RTYPE_GP | 30}, \ 2855 {"$ra", RTYPE_GP | 31} 2856 2857#define MIPS16_SPECIAL_REGISTER_NAMES \ 2858 {"$pc", RTYPE_PC | 0} 2859 2860#define MDMX_VECTOR_REGISTER_NAMES \ 2861 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \ 2862 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \ 2863 {"$v2", RTYPE_VEC | 2}, \ 2864 {"$v3", RTYPE_VEC | 3}, \ 2865 {"$v4", RTYPE_VEC | 4}, \ 2866 {"$v5", RTYPE_VEC | 5}, \ 2867 {"$v6", RTYPE_VEC | 6}, \ 2868 {"$v7", RTYPE_VEC | 7}, \ 2869 {"$v8", RTYPE_VEC | 8}, \ 2870 {"$v9", RTYPE_VEC | 9}, \ 2871 {"$v10", RTYPE_VEC | 10}, \ 2872 {"$v11", RTYPE_VEC | 11}, \ 2873 {"$v12", RTYPE_VEC | 12}, \ 2874 {"$v13", RTYPE_VEC | 13}, \ 2875 {"$v14", RTYPE_VEC | 14}, \ 2876 {"$v15", RTYPE_VEC | 15}, \ 2877 {"$v16", RTYPE_VEC | 16}, \ 2878 {"$v17", RTYPE_VEC | 17}, \ 2879 {"$v18", RTYPE_VEC | 18}, \ 2880 {"$v19", RTYPE_VEC | 19}, \ 2881 {"$v20", RTYPE_VEC | 20}, \ 2882 {"$v21", RTYPE_VEC | 21}, \ 2883 {"$v22", RTYPE_VEC | 22}, \ 2884 {"$v23", RTYPE_VEC | 23}, \ 2885 {"$v24", RTYPE_VEC | 24}, \ 2886 {"$v25", RTYPE_VEC | 25}, \ 2887 {"$v26", RTYPE_VEC | 26}, \ 2888 {"$v27", RTYPE_VEC | 27}, \ 2889 {"$v28", RTYPE_VEC | 28}, \ 2890 {"$v29", RTYPE_VEC | 29}, \ 2891 {"$v30", RTYPE_VEC | 30}, \ 2892 {"$v31", RTYPE_VEC | 31} 2893 2894#define R5900_I_NAMES \ 2895 {"$I", RTYPE_R5900_I | 0} 2896 2897#define R5900_Q_NAMES \ 2898 {"$Q", RTYPE_R5900_Q | 0} 2899 2900#define R5900_R_NAMES \ 2901 {"$R", RTYPE_R5900_R | 0} 2902 2903#define R5900_ACC_NAMES \ 2904 {"$ACC", RTYPE_R5900_ACC | 0 } 2905 2906#define MIPS_DSP_ACCUMULATOR_NAMES \ 2907 {"$ac0", RTYPE_ACC | 0}, \ 2908 {"$ac1", RTYPE_ACC | 1}, \ 2909 {"$ac2", RTYPE_ACC | 2}, \ 2910 {"$ac3", RTYPE_ACC | 3} 2911 2912static const struct regname reg_names[] = { 2913 GENERIC_REGISTER_NUMBERS, 2914 FPU_REGISTER_NAMES, 2915 FPU_CONDITION_CODE_NAMES, 2916 COPROC_CONDITION_CODE_NAMES, 2917 2918 /* The $txx registers depends on the abi, 2919 these will be added later into the symbol table from 2920 one of the tables below once mips_abi is set after 2921 parsing of arguments from the command line. */ 2922 SYMBOLIC_REGISTER_NAMES, 2923 2924 MIPS16_SPECIAL_REGISTER_NAMES, 2925 MDMX_VECTOR_REGISTER_NAMES, 2926 R5900_I_NAMES, 2927 R5900_Q_NAMES, 2928 R5900_R_NAMES, 2929 R5900_ACC_NAMES, 2930 MIPS_DSP_ACCUMULATOR_NAMES, 2931 {0, 0} 2932}; 2933 2934static const struct regname reg_names_o32[] = { 2935 O32_SYMBOLIC_REGISTER_NAMES, 2936 {0, 0} 2937}; 2938 2939static const struct regname reg_names_n32n64[] = { 2940 N32N64_SYMBOLIC_REGISTER_NAMES, 2941 {0, 0} 2942}; 2943 2944/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be 2945 interpreted as vector registers 0 and 1. If SYMVAL is the value of one 2946 of these register symbols, return the associated vector register, 2947 otherwise return SYMVAL itself. */ 2948 2949static unsigned int 2950mips_prefer_vec_regno (unsigned int symval) 2951{ 2952 if ((symval & -2) == (RTYPE_GP | 2)) 2953 return RTYPE_VEC | (symval & 1); 2954 return symval; 2955} 2956 2957/* Return true if string [S, E) is a valid register name, storing its 2958 symbol value in *SYMVAL_PTR if so. */ 2959 2960static bfd_boolean 2961mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) 2962{ 2963 char save_c; 2964 symbolS *symbol; 2965 2966 /* Terminate name. */ 2967 save_c = *e; 2968 *e = '\0'; 2969 2970 /* Look up the name. */ 2971 symbol = symbol_find (s); 2972 *e = save_c; 2973 2974 if (!symbol || S_GET_SEGMENT (symbol) != reg_section) 2975 return FALSE; 2976 2977 *symval_ptr = S_GET_VALUE (symbol); 2978 return TRUE; 2979} 2980 2981/* Return true if the string at *SPTR is a valid register name. Allow it 2982 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR 2983 is nonnull. 2984 2985 When returning true, move *SPTR past the register, store the 2986 register's symbol value in *SYMVAL_PTR and the channel mask in 2987 *CHANNELS_PTR (if nonnull). The symbol value includes the register 2988 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask 2989 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ 2990 2991static bfd_boolean 2992mips_parse_register (char **sptr, unsigned int *symval_ptr, 2993 unsigned int *channels_ptr) 2994{ 2995 char *s, *e, *m; 2996 const char *q; 2997 unsigned int channels, symval, bit; 2998 2999 /* Find end of name. */ 3000 s = e = *sptr; 3001 if (is_name_beginner (*e)) 3002 ++e; 3003 while (is_part_of_name (*e)) 3004 ++e; 3005 3006 channels = 0; 3007 if (!mips_parse_register_1 (s, e, &symval)) 3008 { 3009 if (!channels_ptr) 3010 return FALSE; 3011 3012 /* Eat characters from the end of the string that are valid 3013 channel suffixes. The preceding register must be $ACC or 3014 end with a digit, so there is no ambiguity. */ 3015 bit = 1; 3016 m = e; 3017 for (q = "wzyx"; *q; q++, bit <<= 1) 3018 if (m > s && m[-1] == *q) 3019 { 3020 --m; 3021 channels |= bit; 3022 } 3023 3024 if (channels == 0 3025 || !mips_parse_register_1 (s, m, &symval) 3026 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) 3027 return FALSE; 3028 } 3029 3030 *sptr = e; 3031 *symval_ptr = symval; 3032 if (channels_ptr) 3033 *channels_ptr = channels; 3034 return TRUE; 3035} 3036 3037/* Check if SPTR points at a valid register specifier according to TYPES. 3038 If so, then return 1, advance S to consume the specifier and store 3039 the register's number in REGNOP, otherwise return 0. */ 3040 3041static int 3042reg_lookup (char **s, unsigned int types, unsigned int *regnop) 3043{ 3044 unsigned int regno; 3045 3046 if (mips_parse_register (s, ®no, NULL)) 3047 { 3048 if (types & RTYPE_VEC) 3049 regno = mips_prefer_vec_regno (regno); 3050 if (regno & types) 3051 regno &= RNUM_MASK; 3052 else 3053 regno = ~0; 3054 } 3055 else 3056 { 3057 if (types & RWARN) 3058 as_warn (_("unrecognized register name `%s'"), *s); 3059 regno = ~0; 3060 } 3061 if (regnop) 3062 *regnop = regno; 3063 return regno <= RNUM_MASK; 3064} 3065 3066/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated 3067 mask in *CHANNELS. Return a pointer to the first unconsumed character. */ 3068 3069static char * 3070mips_parse_vu0_channels (char *s, unsigned int *channels) 3071{ 3072 unsigned int i; 3073 3074 *channels = 0; 3075 for (i = 0; i < 4; i++) 3076 if (*s == "xyzw"[i]) 3077 { 3078 *channels |= 1 << (3 - i); 3079 ++s; 3080 } 3081 return s; 3082} 3083 3084/* Token types for parsed operand lists. */ 3085enum mips_operand_token_type { 3086 /* A plain register, e.g. $f2. */ 3087 OT_REG, 3088 3089 /* A 4-bit XYZW channel mask. */ 3090 OT_CHANNELS, 3091 3092 /* A constant vector index, e.g. [1]. */ 3093 OT_INTEGER_INDEX, 3094 3095 /* A register vector index, e.g. [$2]. */ 3096 OT_REG_INDEX, 3097 3098 /* A continuous range of registers, e.g. $s0-$s4. */ 3099 OT_REG_RANGE, 3100 3101 /* A (possibly relocated) expression. */ 3102 OT_INTEGER, 3103 3104 /* A floating-point value. */ 3105 OT_FLOAT, 3106 3107 /* A single character. This can be '(', ')' or ',', but '(' only appears 3108 before OT_REGs. */ 3109 OT_CHAR, 3110 3111 /* A doubled character, either "--" or "++". */ 3112 OT_DOUBLE_CHAR, 3113 3114 /* The end of the operand list. */ 3115 OT_END 3116}; 3117 3118/* A parsed operand token. */ 3119struct mips_operand_token 3120{ 3121 /* The type of token. */ 3122 enum mips_operand_token_type type; 3123 union 3124 { 3125 /* The register symbol value for an OT_REG or OT_REG_INDEX. */ 3126 unsigned int regno; 3127 3128 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ 3129 unsigned int channels; 3130 3131 /* The integer value of an OT_INTEGER_INDEX. */ 3132 addressT index; 3133 3134 /* The two register symbol values involved in an OT_REG_RANGE. */ 3135 struct { 3136 unsigned int regno1; 3137 unsigned int regno2; 3138 } reg_range; 3139 3140 /* The value of an OT_INTEGER. The value is represented as an 3141 expression and the relocation operators that were applied to 3142 that expression. The reloc entries are BFD_RELOC_UNUSED if no 3143 relocation operators were used. */ 3144 struct { 3145 expressionS value; 3146 bfd_reloc_code_real_type relocs[3]; 3147 } integer; 3148 3149 /* The binary data for an OT_FLOAT constant, and the number of bytes 3150 in the constant. */ 3151 struct { 3152 unsigned char data[8]; 3153 int length; 3154 } flt; 3155 3156 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ 3157 char ch; 3158 } u; 3159}; 3160 3161/* An obstack used to construct lists of mips_operand_tokens. */ 3162static struct obstack mips_operand_tokens; 3163 3164/* Give TOKEN type TYPE and add it to mips_operand_tokens. */ 3165 3166static void 3167mips_add_token (struct mips_operand_token *token, 3168 enum mips_operand_token_type type) 3169{ 3170 token->type = type; 3171 obstack_grow (&mips_operand_tokens, token, sizeof (*token)); 3172} 3173 3174/* Check whether S is '(' followed by a register name. Add OT_CHAR 3175 and OT_REG tokens for them if so, and return a pointer to the first 3176 unconsumed character. Return null otherwise. */ 3177 3178static char * 3179mips_parse_base_start (char *s) 3180{ 3181 struct mips_operand_token token; 3182 unsigned int regno, channels; 3183 bfd_boolean decrement_p; 3184 3185 if (*s != '(') 3186 return 0; 3187 3188 ++s; 3189 SKIP_SPACE_TABS (s); 3190 3191 /* Only match "--" as part of a base expression. In other contexts "--X" 3192 is a double negative. */ 3193 decrement_p = (s[0] == '-' && s[1] == '-'); 3194 if (decrement_p) 3195 { 3196 s += 2; 3197 SKIP_SPACE_TABS (s); 3198 } 3199 3200 /* Allow a channel specifier because that leads to better error messages 3201 than treating something like "$vf0x++" as an expression. */ 3202 if (!mips_parse_register (&s, ®no, &channels)) 3203 return 0; 3204 3205 token.u.ch = '('; 3206 mips_add_token (&token, OT_CHAR); 3207 3208 if (decrement_p) 3209 { 3210 token.u.ch = '-'; 3211 mips_add_token (&token, OT_DOUBLE_CHAR); 3212 } 3213 3214 token.u.regno = regno; 3215 mips_add_token (&token, OT_REG); 3216 3217 if (channels) 3218 { 3219 token.u.channels = channels; 3220 mips_add_token (&token, OT_CHANNELS); 3221 } 3222 3223 /* For consistency, only match "++" as part of base expressions too. */ 3224 SKIP_SPACE_TABS (s); 3225 if (s[0] == '+' && s[1] == '+') 3226 { 3227 s += 2; 3228 token.u.ch = '+'; 3229 mips_add_token (&token, OT_DOUBLE_CHAR); 3230 } 3231 3232 return s; 3233} 3234 3235/* Parse one or more tokens from S. Return a pointer to the first 3236 unconsumed character on success. Return null if an error was found 3237 and store the error text in insn_error. FLOAT_FORMAT is as for 3238 mips_parse_arguments. */ 3239 3240static char * 3241mips_parse_argument_token (char *s, char float_format) 3242{ 3243 char *end, *save_in; 3244 const char *err; 3245 unsigned int regno1, regno2, channels; 3246 struct mips_operand_token token; 3247 3248 /* First look for "($reg", since we want to treat that as an 3249 OT_CHAR and OT_REG rather than an expression. */ 3250 end = mips_parse_base_start (s); 3251 if (end) 3252 return end; 3253 3254 /* Handle other characters that end up as OT_CHARs. */ 3255 if (*s == ')' || *s == ',') 3256 { 3257 token.u.ch = *s; 3258 mips_add_token (&token, OT_CHAR); 3259 ++s; 3260 return s; 3261 } 3262 3263 /* Handle tokens that start with a register. */ 3264 if (mips_parse_register (&s, ®no1, &channels)) 3265 { 3266 if (channels) 3267 { 3268 /* A register and a VU0 channel suffix. */ 3269 token.u.regno = regno1; 3270 mips_add_token (&token, OT_REG); 3271 3272 token.u.channels = channels; 3273 mips_add_token (&token, OT_CHANNELS); 3274 return s; 3275 } 3276 3277 SKIP_SPACE_TABS (s); 3278 if (*s == '-') 3279 { 3280 /* A register range. */ 3281 ++s; 3282 SKIP_SPACE_TABS (s); 3283 if (!mips_parse_register (&s, ®no2, NULL)) 3284 { 3285 set_insn_error (0, _("invalid register range")); 3286 return 0; 3287 } 3288 3289 token.u.reg_range.regno1 = regno1; 3290 token.u.reg_range.regno2 = regno2; 3291 mips_add_token (&token, OT_REG_RANGE); 3292 return s; 3293 } 3294 3295 /* Add the register itself. */ 3296 token.u.regno = regno1; 3297 mips_add_token (&token, OT_REG); 3298 3299 /* Check for a vector index. */ 3300 if (*s == '[') 3301 { 3302 ++s; 3303 SKIP_SPACE_TABS (s); 3304 if (mips_parse_register (&s, &token.u.regno, NULL)) 3305 mips_add_token (&token, OT_REG_INDEX); 3306 else 3307 { 3308 expressionS element; 3309 3310 my_getExpression (&element, s); 3311 if (element.X_op != O_constant) 3312 { 3313 set_insn_error (0, _("vector element must be constant")); 3314 return 0; 3315 } 3316 s = expr_end; 3317 token.u.index = element.X_add_number; 3318 mips_add_token (&token, OT_INTEGER_INDEX); 3319 } 3320 SKIP_SPACE_TABS (s); 3321 if (*s != ']') 3322 { 3323 set_insn_error (0, _("missing `]'")); 3324 return 0; 3325 } 3326 ++s; 3327 } 3328 return s; 3329 } 3330 3331 if (float_format) 3332 { 3333 /* First try to treat expressions as floats. */ 3334 save_in = input_line_pointer; 3335 input_line_pointer = s; 3336 err = md_atof (float_format, (char *) token.u.flt.data, 3337 &token.u.flt.length); 3338 end = input_line_pointer; 3339 input_line_pointer = save_in; 3340 if (err && *err) 3341 { 3342 set_insn_error (0, err); 3343 return 0; 3344 } 3345 if (s != end) 3346 { 3347 mips_add_token (&token, OT_FLOAT); 3348 return end; 3349 } 3350 } 3351 3352 /* Treat everything else as an integer expression. */ 3353 token.u.integer.relocs[0] = BFD_RELOC_UNUSED; 3354 token.u.integer.relocs[1] = BFD_RELOC_UNUSED; 3355 token.u.integer.relocs[2] = BFD_RELOC_UNUSED; 3356 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); 3357 s = expr_end; 3358 mips_add_token (&token, OT_INTEGER); 3359 return s; 3360} 3361 3362/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' 3363 if expressions should be treated as 32-bit floating-point constants, 3364 'd' if they should be treated as 64-bit floating-point constants, 3365 or 0 if they should be treated as integer expressions (the usual case). 3366 3367 Return a list of tokens on success, otherwise return 0. The caller 3368 must obstack_free the list after use. */ 3369 3370static struct mips_operand_token * 3371mips_parse_arguments (char *s, char float_format) 3372{ 3373 struct mips_operand_token token; 3374 3375 SKIP_SPACE_TABS (s); 3376 while (*s) 3377 { 3378 s = mips_parse_argument_token (s, float_format); 3379 if (!s) 3380 { 3381 obstack_free (&mips_operand_tokens, 3382 obstack_finish (&mips_operand_tokens)); 3383 return 0; 3384 } 3385 SKIP_SPACE_TABS (s); 3386 } 3387 mips_add_token (&token, OT_END); 3388 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); 3389} 3390 3391/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE 3392 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ 3393 3394static bfd_boolean 3395is_opcode_valid (const struct mips_opcode *mo) 3396{ 3397 int isa = mips_opts.isa; 3398 int ase = mips_opts.ase; 3399 int fp_s, fp_d; 3400 unsigned int i; 3401 3402 if (ISA_HAS_64BIT_REGS (isa)) 3403 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 3404 if ((ase & mips_ases[i].flags) == mips_ases[i].flags) 3405 ase |= mips_ases[i].flags64; 3406 3407 if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) 3408 return FALSE; 3409 3410 /* Check whether the instruction or macro requires single-precision or 3411 double-precision floating-point support. Note that this information is 3412 stored differently in the opcode table for insns and macros. */ 3413 if (mo->pinfo == INSN_MACRO) 3414 { 3415 fp_s = mo->pinfo2 & INSN2_M_FP_S; 3416 fp_d = mo->pinfo2 & INSN2_M_FP_D; 3417 } 3418 else 3419 { 3420 fp_s = mo->pinfo & FP_S; 3421 fp_d = mo->pinfo & FP_D; 3422 } 3423 3424 if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) 3425 return FALSE; 3426 3427 if (fp_s && mips_opts.soft_float) 3428 return FALSE; 3429 3430 return TRUE; 3431} 3432 3433/* Return TRUE if the MIPS16 opcode MO is valid on the currently 3434 selected ISA and architecture. */ 3435 3436static bfd_boolean 3437is_opcode_valid_16 (const struct mips_opcode *mo) 3438{ 3439 int isa = mips_opts.isa; 3440 int ase = mips_opts.ase; 3441 unsigned int i; 3442 3443 if (ISA_HAS_64BIT_REGS (isa)) 3444 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 3445 if ((ase & mips_ases[i].flags) == mips_ases[i].flags) 3446 ase |= mips_ases[i].flags64; 3447 3448 return opcode_is_member (mo, isa, ase, mips_opts.arch); 3449} 3450 3451/* Return TRUE if the size of the microMIPS opcode MO matches one 3452 explicitly requested. Always TRUE in the standard MIPS mode. 3453 Use is_size_valid_16 for MIPS16 opcodes. */ 3454 3455static bfd_boolean 3456is_size_valid (const struct mips_opcode *mo) 3457{ 3458 if (!mips_opts.micromips) 3459 return TRUE; 3460 3461 if (mips_opts.insn32) 3462 { 3463 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) 3464 return FALSE; 3465 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) 3466 return FALSE; 3467 } 3468 if (!forced_insn_length) 3469 return TRUE; 3470 if (mo->pinfo == INSN_MACRO) 3471 return FALSE; 3472 return forced_insn_length == micromips_insn_length (mo); 3473} 3474 3475/* Return TRUE if the size of the MIPS16 opcode MO matches one 3476 explicitly requested. */ 3477 3478static bfd_boolean 3479is_size_valid_16 (const struct mips_opcode *mo) 3480{ 3481 if (!forced_insn_length) 3482 return TRUE; 3483 if (mo->pinfo == INSN_MACRO) 3484 return FALSE; 3485 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) 3486 return FALSE; 3487 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) 3488 return FALSE; 3489 return TRUE; 3490} 3491 3492/* Return TRUE if the microMIPS opcode MO is valid for the delay slot 3493 of the preceding instruction. Always TRUE in the standard MIPS mode. 3494 3495 We don't accept macros in 16-bit delay slots to avoid a case where 3496 a macro expansion fails because it relies on a preceding 32-bit real 3497 instruction to have matched and does not handle the operands correctly. 3498 The only macros that may expand to 16-bit instructions are JAL that 3499 cannot be placed in a delay slot anyway, and corner cases of BALIGN 3500 and BGT (that likewise cannot be placed in a delay slot) that decay to 3501 a NOP. In all these cases the macros precede any corresponding real 3502 instruction definitions in the opcode table, so they will match in the 3503 second pass where the size of the delay slot is ignored and therefore 3504 produce correct code. */ 3505 3506static bfd_boolean 3507is_delay_slot_valid (const struct mips_opcode *mo) 3508{ 3509 if (!mips_opts.micromips) 3510 return TRUE; 3511 3512 if (mo->pinfo == INSN_MACRO) 3513 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; 3514 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 3515 && micromips_insn_length (mo) != 4) 3516 return FALSE; 3517 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 3518 && micromips_insn_length (mo) != 2) 3519 return FALSE; 3520 3521 return TRUE; 3522} 3523 3524/* For consistency checking, verify that all bits of OPCODE are specified 3525 either by the match/mask part of the instruction definition, or by the 3526 operand list. Also build up a list of operands in OPERANDS. 3527 3528 INSN_BITS says which bits of the instruction are significant. 3529 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND 3530 provides the mips_operand description of each operand. DECODE_OPERAND 3531 is null for MIPS16 instructions. */ 3532 3533static int 3534validate_mips_insn (const struct mips_opcode *opcode, 3535 unsigned long insn_bits, 3536 const struct mips_operand *(*decode_operand) (const char *), 3537 struct mips_operand_array *operands) 3538{ 3539 const char *s; 3540 unsigned long used_bits, doubled, undefined, opno, mask; 3541 const struct mips_operand *operand; 3542 3543 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); 3544 if ((mask & opcode->match) != opcode->match) 3545 { 3546 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 3547 opcode->name, opcode->args); 3548 return 0; 3549 } 3550 used_bits = 0; 3551 opno = 0; 3552 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) 3553 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); 3554 for (s = opcode->args; *s; ++s) 3555 switch (*s) 3556 { 3557 case ',': 3558 case '(': 3559 case ')': 3560 break; 3561 3562 case '#': 3563 s++; 3564 break; 3565 3566 default: 3567 if (!decode_operand) 3568 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); 3569 else 3570 operand = decode_operand (s); 3571 if (!operand && opcode->pinfo != INSN_MACRO) 3572 { 3573 as_bad (_("internal: unknown operand type: %s %s"), 3574 opcode->name, opcode->args); 3575 return 0; 3576 } 3577 gas_assert (opno < MAX_OPERANDS); 3578 operands->operand[opno] = operand; 3579 if (!decode_operand && operand 3580 && operand->type == OP_INT && operand->lsb == 0 3581 && mips_opcode_32bit_p (opcode)) 3582 used_bits |= mips16_immed_extend (-1, operand->size); 3583 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) 3584 { 3585 used_bits = mips_insert_operand (operand, used_bits, -1); 3586 if (operand->type == OP_MDMX_IMM_REG) 3587 /* Bit 5 is the format selector (OB vs QH). The opcode table 3588 has separate entries for each format. */ 3589 used_bits &= ~(1 << (operand->lsb + 5)); 3590 if (operand->type == OP_ENTRY_EXIT_LIST) 3591 used_bits &= ~(mask & 0x700); 3592 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous 3593 operand field that cannot be fully described with LSB/SIZE. */ 3594 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) 3595 used_bits &= ~0x6000; 3596 } 3597 /* Skip prefix characters. */ 3598 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) 3599 ++s; 3600 opno += 1; 3601 break; 3602 } 3603 doubled = used_bits & mask & insn_bits; 3604 if (doubled) 3605 { 3606 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" 3607 " %s %s"), doubled, opcode->name, opcode->args); 3608 return 0; 3609 } 3610 used_bits |= mask; 3611 undefined = ~used_bits & insn_bits; 3612 if (opcode->pinfo != INSN_MACRO && undefined) 3613 { 3614 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), 3615 undefined, opcode->name, opcode->args); 3616 return 0; 3617 } 3618 used_bits &= ~insn_bits; 3619 if (used_bits) 3620 { 3621 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), 3622 used_bits, opcode->name, opcode->args); 3623 return 0; 3624 } 3625 return 1; 3626} 3627 3628/* The MIPS16 version of validate_mips_insn. */ 3629 3630static int 3631validate_mips16_insn (const struct mips_opcode *opcode, 3632 struct mips_operand_array *operands) 3633{ 3634 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; 3635 3636 return validate_mips_insn (opcode, insn_bits, 0, operands); 3637} 3638 3639/* The microMIPS version of validate_mips_insn. */ 3640 3641static int 3642validate_micromips_insn (const struct mips_opcode *opc, 3643 struct mips_operand_array *operands) 3644{ 3645 unsigned long insn_bits; 3646 unsigned long major; 3647 unsigned int length; 3648 3649 if (opc->pinfo == INSN_MACRO) 3650 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, 3651 operands); 3652 3653 length = micromips_insn_length (opc); 3654 if (length != 2 && length != 4) 3655 { 3656 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " 3657 "%s %s"), length, opc->name, opc->args); 3658 return 0; 3659 } 3660 major = opc->match >> (10 + 8 * (length - 2)); 3661 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) 3662 || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) 3663 { 3664 as_bad (_("internal error: bad microMIPS opcode " 3665 "(opcode/length mismatch): %s %s"), opc->name, opc->args); 3666 return 0; 3667 } 3668 3669 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ 3670 insn_bits = 1 << 4 * length; 3671 insn_bits <<= 4 * length; 3672 insn_bits -= 1; 3673 return validate_mips_insn (opc, insn_bits, decode_micromips_operand, 3674 operands); 3675} 3676 3677/* This function is called once, at assembler startup time. It should set up 3678 all the tables, etc. that the MD part of the assembler will need. */ 3679 3680void 3681md_begin (void) 3682{ 3683 const char *retval = NULL; 3684 int i = 0; 3685 int broken = 0; 3686 3687 if (mips_pic != NO_PIC) 3688 { 3689 if (g_switch_seen && g_switch_value != 0) 3690 as_bad (_("-G may not be used in position-independent code")); 3691 g_switch_value = 0; 3692 } 3693 else if (mips_abicalls) 3694 { 3695 if (g_switch_seen && g_switch_value != 0) 3696 as_bad (_("-G may not be used with abicalls")); 3697 g_switch_value = 0; 3698 } 3699 3700 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 3701 as_warn (_("could not set architecture and machine")); 3702 3703 op_hash = hash_new (); 3704 3705 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); 3706 for (i = 0; i < NUMOPCODES;) 3707 { 3708 const char *name = mips_opcodes[i].name; 3709 3710 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 3711 if (retval != NULL) 3712 { 3713 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 3714 mips_opcodes[i].name, retval); 3715 /* Probably a memory allocation problem? Give up now. */ 3716 as_fatal (_("broken assembler, no assembly attempted")); 3717 } 3718 do 3719 { 3720 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, 3721 decode_mips_operand, &mips_operands[i])) 3722 broken = 1; 3723 3724 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3725 { 3726 create_insn (&nop_insn, mips_opcodes + i); 3727 if (mips_fix_loongson2f_nop) 3728 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; 3729 nop_insn.fixed_p = 1; 3730 } 3731 3732 if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0) 3733 create_insn (&sync_insn, mips_opcodes + i); 3734 3735 ++i; 3736 } 3737 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 3738 } 3739 3740 mips16_op_hash = hash_new (); 3741 mips16_operands = XCNEWVEC (struct mips_operand_array, 3742 bfd_mips16_num_opcodes); 3743 3744 i = 0; 3745 while (i < bfd_mips16_num_opcodes) 3746 { 3747 const char *name = mips16_opcodes[i].name; 3748 3749 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 3750 if (retval != NULL) 3751 as_fatal (_("internal: can't hash `%s': %s"), 3752 mips16_opcodes[i].name, retval); 3753 do 3754 { 3755 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) 3756 broken = 1; 3757 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) 3758 { 3759 create_insn (&mips16_nop_insn, mips16_opcodes + i); 3760 mips16_nop_insn.fixed_p = 1; 3761 } 3762 ++i; 3763 } 3764 while (i < bfd_mips16_num_opcodes 3765 && strcmp (mips16_opcodes[i].name, name) == 0); 3766 } 3767 3768 micromips_op_hash = hash_new (); 3769 micromips_operands = XCNEWVEC (struct mips_operand_array, 3770 bfd_micromips_num_opcodes); 3771 3772 i = 0; 3773 while (i < bfd_micromips_num_opcodes) 3774 { 3775 const char *name = micromips_opcodes[i].name; 3776 3777 retval = hash_insert (micromips_op_hash, name, 3778 (void *) µmips_opcodes[i]); 3779 if (retval != NULL) 3780 as_fatal (_("internal: can't hash `%s': %s"), 3781 micromips_opcodes[i].name, retval); 3782 do 3783 { 3784 struct mips_cl_insn *micromips_nop_insn; 3785 3786 if (!validate_micromips_insn (µmips_opcodes[i], 3787 µmips_operands[i])) 3788 broken = 1; 3789 3790 if (micromips_opcodes[i].pinfo != INSN_MACRO) 3791 { 3792 if (micromips_insn_length (micromips_opcodes + i) == 2) 3793 micromips_nop_insn = µmips_nop16_insn; 3794 else if (micromips_insn_length (micromips_opcodes + i) == 4) 3795 micromips_nop_insn = µmips_nop32_insn; 3796 else 3797 continue; 3798 3799 if (micromips_nop_insn->insn_mo == NULL 3800 && strcmp (name, "nop") == 0) 3801 { 3802 create_insn (micromips_nop_insn, micromips_opcodes + i); 3803 micromips_nop_insn->fixed_p = 1; 3804 } 3805 } 3806 } 3807 while (++i < bfd_micromips_num_opcodes 3808 && strcmp (micromips_opcodes[i].name, name) == 0); 3809 } 3810 3811 if (broken) 3812 as_fatal (_("broken assembler, no assembly attempted")); 3813 3814 /* We add all the general register names to the symbol table. This 3815 helps us detect invalid uses of them. */ 3816 for (i = 0; reg_names[i].name; i++) 3817 symbol_table_insert (symbol_new (reg_names[i].name, reg_section, 3818 reg_names[i].num, /* & RNUM_MASK, */ 3819 &zero_address_frag)); 3820 if (HAVE_NEWABI) 3821 for (i = 0; reg_names_n32n64[i].name; i++) 3822 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, 3823 reg_names_n32n64[i].num, /* & RNUM_MASK, */ 3824 &zero_address_frag)); 3825 else 3826 for (i = 0; reg_names_o32[i].name; i++) 3827 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, 3828 reg_names_o32[i].num, /* & RNUM_MASK, */ 3829 &zero_address_frag)); 3830 3831 for (i = 0; i < 32; i++) 3832 { 3833 char regname[6]; 3834 3835 /* R5900 VU0 floating-point register. */ 3836 sprintf (regname, "$vf%d", i); 3837 symbol_table_insert (symbol_new (regname, reg_section, 3838 RTYPE_VF | i, &zero_address_frag)); 3839 3840 /* R5900 VU0 integer register. */ 3841 sprintf (regname, "$vi%d", i); 3842 symbol_table_insert (symbol_new (regname, reg_section, 3843 RTYPE_VI | i, &zero_address_frag)); 3844 3845 /* MSA register. */ 3846 sprintf (regname, "$w%d", i); 3847 symbol_table_insert (symbol_new (regname, reg_section, 3848 RTYPE_MSA | i, &zero_address_frag)); 3849 } 3850 3851 obstack_init (&mips_operand_tokens); 3852 3853 mips_no_prev_insn (); 3854 3855 mips_gprmask = 0; 3856 mips_cprmask[0] = 0; 3857 mips_cprmask[1] = 0; 3858 mips_cprmask[2] = 0; 3859 mips_cprmask[3] = 0; 3860 3861 /* set the default alignment for the text section (2**2) */ 3862 record_alignment (text_section, 2); 3863 3864 bfd_set_gp_size (stdoutput, g_switch_value); 3865 3866 /* On a native system other than VxWorks, sections must be aligned 3867 to 16 byte boundaries. When configured for an embedded ELF 3868 target, we don't bother. */ 3869 if (strncmp (TARGET_OS, "elf", 3) != 0 3870 && strncmp (TARGET_OS, "vxworks", 7) != 0) 3871 { 3872 bfd_set_section_alignment (text_section, 4); 3873 bfd_set_section_alignment (data_section, 4); 3874 bfd_set_section_alignment (bss_section, 4); 3875 } 3876 3877 /* Create a .reginfo section for register masks and a .mdebug 3878 section for debugging information. */ 3879 { 3880 segT seg; 3881 subsegT subseg; 3882 flagword flags; 3883 segT sec; 3884 3885 seg = now_seg; 3886 subseg = now_subseg; 3887 3888 /* The ABI says this section should be loaded so that the 3889 running program can access it. However, we don't load it 3890 if we are configured for an embedded target. */ 3891 flags = SEC_READONLY | SEC_DATA; 3892 if (strncmp (TARGET_OS, "elf", 3) != 0) 3893 flags |= SEC_ALLOC | SEC_LOAD; 3894 3895 if (mips_abi != N64_ABI) 3896 { 3897 sec = subseg_new (".reginfo", (subsegT) 0); 3898 3899 bfd_set_section_flags (sec, flags); 3900 bfd_set_section_alignment (sec, HAVE_NEWABI ? 3 : 2); 3901 3902 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 3903 } 3904 else 3905 { 3906 /* The 64-bit ABI uses a .MIPS.options section rather than 3907 .reginfo section. */ 3908 sec = subseg_new (".MIPS.options", (subsegT) 0); 3909 bfd_set_section_flags (sec, flags); 3910 bfd_set_section_alignment (sec, 3); 3911 3912 /* Set up the option header. */ 3913 { 3914 Elf_Internal_Options opthdr; 3915 char *f; 3916 3917 opthdr.kind = ODK_REGINFO; 3918 opthdr.size = (sizeof (Elf_External_Options) 3919 + sizeof (Elf64_External_RegInfo)); 3920 opthdr.section = 0; 3921 opthdr.info = 0; 3922 f = frag_more (sizeof (Elf_External_Options)); 3923 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 3924 (Elf_External_Options *) f); 3925 3926 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 3927 } 3928 } 3929 3930 sec = subseg_new (".MIPS.abiflags", (subsegT) 0); 3931 bfd_set_section_flags (sec, 3932 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); 3933 bfd_set_section_alignment (sec, 3); 3934 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); 3935 3936 if (ECOFF_DEBUGGING) 3937 { 3938 sec = subseg_new (".mdebug", (subsegT) 0); 3939 bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY); 3940 bfd_set_section_alignment (sec, 2); 3941 } 3942 else if (mips_flag_pdr) 3943 { 3944 pdr_seg = subseg_new (".pdr", (subsegT) 0); 3945 bfd_set_section_flags (pdr_seg, 3946 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); 3947 bfd_set_section_alignment (pdr_seg, 2); 3948 } 3949 3950 subseg_set (seg, subseg); 3951 } 3952 3953 if (mips_fix_vr4120) 3954 init_vr4120_conflicts (); 3955} 3956 3957static inline void 3958fpabi_incompatible_with (int fpabi, const char *what) 3959{ 3960 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), 3961 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3962} 3963 3964static inline void 3965fpabi_requires (int fpabi, const char *what) 3966{ 3967 as_warn (_(".gnu_attribute %d,%d requires `%s'"), 3968 Tag_GNU_MIPS_ABI_FP, fpabi, what); 3969} 3970 3971/* Check -mabi and register sizes against the specified FP ABI. */ 3972static void 3973check_fpabi (int fpabi) 3974{ 3975 switch (fpabi) 3976 { 3977 case Val_GNU_MIPS_ABI_FP_DOUBLE: 3978 if (file_mips_opts.soft_float) 3979 fpabi_incompatible_with (fpabi, "softfloat"); 3980 else if (file_mips_opts.single_float) 3981 fpabi_incompatible_with (fpabi, "singlefloat"); 3982 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) 3983 fpabi_incompatible_with (fpabi, "gp=64 fp=32"); 3984 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) 3985 fpabi_incompatible_with (fpabi, "gp=32 fp=64"); 3986 break; 3987 3988 case Val_GNU_MIPS_ABI_FP_XX: 3989 if (mips_abi != O32_ABI) 3990 fpabi_requires (fpabi, "-mabi=32"); 3991 else if (file_mips_opts.soft_float) 3992 fpabi_incompatible_with (fpabi, "softfloat"); 3993 else if (file_mips_opts.single_float) 3994 fpabi_incompatible_with (fpabi, "singlefloat"); 3995 else if (file_mips_opts.fp != 0) 3996 fpabi_requires (fpabi, "fp=xx"); 3997 break; 3998 3999 case Val_GNU_MIPS_ABI_FP_64A: 4000 case Val_GNU_MIPS_ABI_FP_64: 4001 if (mips_abi != O32_ABI) 4002 fpabi_requires (fpabi, "-mabi=32"); 4003 else if (file_mips_opts.soft_float) 4004 fpabi_incompatible_with (fpabi, "softfloat"); 4005 else if (file_mips_opts.single_float) 4006 fpabi_incompatible_with (fpabi, "singlefloat"); 4007 else if (file_mips_opts.fp != 64) 4008 fpabi_requires (fpabi, "fp=64"); 4009 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) 4010 fpabi_incompatible_with (fpabi, "nooddspreg"); 4011 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) 4012 fpabi_requires (fpabi, "nooddspreg"); 4013 break; 4014 4015 case Val_GNU_MIPS_ABI_FP_SINGLE: 4016 if (file_mips_opts.soft_float) 4017 fpabi_incompatible_with (fpabi, "softfloat"); 4018 else if (!file_mips_opts.single_float) 4019 fpabi_requires (fpabi, "singlefloat"); 4020 break; 4021 4022 case Val_GNU_MIPS_ABI_FP_SOFT: 4023 if (!file_mips_opts.soft_float) 4024 fpabi_requires (fpabi, "softfloat"); 4025 break; 4026 4027 case Val_GNU_MIPS_ABI_FP_OLD_64: 4028 as_warn (_(".gnu_attribute %d,%d is no longer supported"), 4029 Tag_GNU_MIPS_ABI_FP, fpabi); 4030 break; 4031 4032 case Val_GNU_MIPS_ABI_FP_NAN2008: 4033 /* Silently ignore compatibility value. */ 4034 break; 4035 4036 default: 4037 as_warn (_(".gnu_attribute %d,%d is not a recognized" 4038 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); 4039 break; 4040 } 4041} 4042 4043/* Perform consistency checks on the current options. */ 4044 4045static void 4046mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) 4047{ 4048 /* Check the size of integer registers agrees with the ABI and ISA. */ 4049 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) 4050 as_bad (_("`gp=64' used with a 32-bit processor")); 4051 else if (abi_checks 4052 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) 4053 as_bad (_("`gp=32' used with a 64-bit ABI")); 4054 else if (abi_checks 4055 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) 4056 as_bad (_("`gp=64' used with a 32-bit ABI")); 4057 4058 /* Check the size of the float registers agrees with the ABI and ISA. */ 4059 switch (opts->fp) 4060 { 4061 case 0: 4062 if (!CPU_HAS_LDC1_SDC1 (opts->arch)) 4063 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); 4064 else if (opts->single_float == 1) 4065 as_bad (_("`fp=xx' cannot be used with `singlefloat'")); 4066 break; 4067 case 64: 4068 if (!ISA_HAS_64BIT_FPRS (opts->isa)) 4069 as_bad (_("`fp=64' used with a 32-bit fpu")); 4070 else if (abi_checks 4071 && ABI_NEEDS_32BIT_REGS (mips_abi) 4072 && !ISA_HAS_MXHC1 (opts->isa)) 4073 as_warn (_("`fp=64' used with a 32-bit ABI")); 4074 break; 4075 case 32: 4076 if (abi_checks 4077 && ABI_NEEDS_64BIT_REGS (mips_abi)) 4078 as_warn (_("`fp=32' used with a 64-bit ABI")); 4079 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) 4080 as_bad (_("`fp=32' used with a MIPS R6 cpu")); 4081 break; 4082 default: 4083 as_bad (_("Unknown size of floating point registers")); 4084 break; 4085 } 4086 4087 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) 4088 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); 4089 4090 if (opts->micromips == 1 && opts->mips16 == 1) 4091 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); 4092 else if (ISA_IS_R6 (opts->isa) 4093 && (opts->micromips == 1 4094 || opts->mips16 == 1)) 4095 as_fatal (_("`%s' cannot be used with `%s'"), 4096 opts->micromips ? "micromips" : "mips16", 4097 mips_cpu_info_from_isa (opts->isa)->name); 4098 4099 if (ISA_IS_R6 (opts->isa) && mips_relax_branch) 4100 as_fatal (_("branch relaxation is not supported in `%s'"), 4101 mips_cpu_info_from_isa (opts->isa)->name); 4102} 4103 4104/* Perform consistency checks on the module level options exactly once. 4105 This is a deferred check that happens: 4106 at the first .set directive 4107 or, at the first pseudo op that generates code (inc .dc.a) 4108 or, at the first instruction 4109 or, at the end. */ 4110 4111static void 4112file_mips_check_options (void) 4113{ 4114 if (file_mips_opts_checked) 4115 return; 4116 4117 /* The following code determines the register size. 4118 Similar code was added to GCC 3.3 (see override_options() in 4119 config/mips/mips.c). The GAS and GCC code should be kept in sync 4120 as much as possible. */ 4121 4122 if (file_mips_opts.gp < 0) 4123 { 4124 /* Infer the integer register size from the ABI and processor. 4125 Restrict ourselves to 32-bit registers if that's all the 4126 processor has, or if the ABI cannot handle 64-bit registers. */ 4127 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) 4128 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) 4129 ? 32 : 64; 4130 } 4131 4132 if (file_mips_opts.fp < 0) 4133 { 4134 /* No user specified float register size. 4135 ??? GAS treats single-float processors as though they had 64-bit 4136 float registers (although it complains when double-precision 4137 instructions are used). As things stand, saying they have 32-bit 4138 registers would lead to spurious "register must be even" messages. 4139 So here we assume float registers are never smaller than the 4140 integer ones. */ 4141 if (file_mips_opts.gp == 64) 4142 /* 64-bit integer registers implies 64-bit float registers. */ 4143 file_mips_opts.fp = 64; 4144 else if ((file_mips_opts.ase & FP64_ASES) 4145 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) 4146 /* Handle ASEs that require 64-bit float registers, if possible. */ 4147 file_mips_opts.fp = 64; 4148 else if (ISA_IS_R6 (mips_opts.isa)) 4149 /* R6 implies 64-bit float registers. */ 4150 file_mips_opts.fp = 64; 4151 else 4152 /* 32-bit float registers. */ 4153 file_mips_opts.fp = 32; 4154 } 4155 4156 /* Disable operations on odd-numbered floating-point registers by default 4157 when using the FPXX ABI. */ 4158 if (file_mips_opts.oddspreg < 0) 4159 { 4160 if (file_mips_opts.fp == 0) 4161 file_mips_opts.oddspreg = 0; 4162 else 4163 file_mips_opts.oddspreg = 1; 4164 } 4165 4166 /* End of GCC-shared inference code. */ 4167 4168 /* This flag is set when we have a 64-bit capable CPU but use only 4169 32-bit wide registers. Note that EABI does not use it. */ 4170 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) 4171 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) 4172 || mips_abi == O32_ABI)) 4173 mips_32bitmode = 1; 4174 4175 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) 4176 as_bad (_("trap exception not supported at ISA 1")); 4177 4178 /* If the selected architecture includes support for ASEs, enable 4179 generation of code for them. */ 4180 if (file_mips_opts.mips16 == -1) 4181 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; 4182 if (file_mips_opts.micromips == -1) 4183 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) 4184 ? 1 : 0; 4185 4186 if (mips_nan2008 == -1) 4187 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; 4188 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) 4189 as_fatal (_("`%s' does not support legacy NaN"), 4190 mips_cpu_info_from_arch (file_mips_opts.arch)->name); 4191 4192 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from 4193 being selected implicitly. */ 4194 if (file_mips_opts.fp != 64) 4195 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; 4196 4197 /* If the user didn't explicitly select or deselect a particular ASE, 4198 use the default setting for the CPU. */ 4199 file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit); 4200 4201 /* Set up the current options. These may change throughout assembly. */ 4202 mips_opts = file_mips_opts; 4203 4204 mips_check_isa_supports_ases (); 4205 mips_check_options (&file_mips_opts, TRUE); 4206 file_mips_opts_checked = TRUE; 4207 4208 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) 4209 as_warn (_("could not set architecture and machine")); 4210} 4211 4212void 4213md_assemble (char *str) 4214{ 4215 struct mips_cl_insn insn; 4216 bfd_reloc_code_real_type unused_reloc[3] 4217 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 4218 4219 file_mips_check_options (); 4220 4221 imm_expr.X_op = O_absent; 4222 offset_expr.X_op = O_absent; 4223 offset_reloc[0] = BFD_RELOC_UNUSED; 4224 offset_reloc[1] = BFD_RELOC_UNUSED; 4225 offset_reloc[2] = BFD_RELOC_UNUSED; 4226 4227 mips_mark_labels (); 4228 mips_assembling_insn = TRUE; 4229 clear_insn_error (); 4230 4231 if (mips_opts.mips16) 4232 mips16_ip (str, &insn); 4233 else 4234 { 4235 mips_ip (str, &insn); 4236 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 4237 str, insn.insn_opcode)); 4238 } 4239 4240 if (insn_error.msg) 4241 report_insn_error (str); 4242 else if (insn.insn_mo->pinfo == INSN_MACRO) 4243 { 4244 macro_start (); 4245 if (mips_opts.mips16) 4246 mips16_macro (&insn); 4247 else 4248 macro (&insn, str); 4249 macro_end (); 4250 } 4251 else 4252 { 4253 if (offset_expr.X_op != O_absent) 4254 append_insn (&insn, &offset_expr, offset_reloc, FALSE); 4255 else 4256 append_insn (&insn, NULL, unused_reloc, FALSE); 4257 } 4258 4259 mips_assembling_insn = FALSE; 4260} 4261 4262/* Convenience functions for abstracting away the differences between 4263 MIPS16 and non-MIPS16 relocations. */ 4264 4265static inline bfd_boolean 4266mips16_reloc_p (bfd_reloc_code_real_type reloc) 4267{ 4268 switch (reloc) 4269 { 4270 case BFD_RELOC_MIPS16_JMP: 4271 case BFD_RELOC_MIPS16_GPREL: 4272 case BFD_RELOC_MIPS16_GOT16: 4273 case BFD_RELOC_MIPS16_CALL16: 4274 case BFD_RELOC_MIPS16_HI16_S: 4275 case BFD_RELOC_MIPS16_HI16: 4276 case BFD_RELOC_MIPS16_LO16: 4277 case BFD_RELOC_MIPS16_16_PCREL_S1: 4278 return TRUE; 4279 4280 default: 4281 return FALSE; 4282 } 4283} 4284 4285static inline bfd_boolean 4286micromips_reloc_p (bfd_reloc_code_real_type reloc) 4287{ 4288 switch (reloc) 4289 { 4290 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4291 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4292 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4293 case BFD_RELOC_MICROMIPS_GPREL16: 4294 case BFD_RELOC_MICROMIPS_JMP: 4295 case BFD_RELOC_MICROMIPS_HI16: 4296 case BFD_RELOC_MICROMIPS_HI16_S: 4297 case BFD_RELOC_MICROMIPS_LO16: 4298 case BFD_RELOC_MICROMIPS_LITERAL: 4299 case BFD_RELOC_MICROMIPS_GOT16: 4300 case BFD_RELOC_MICROMIPS_CALL16: 4301 case BFD_RELOC_MICROMIPS_GOT_HI16: 4302 case BFD_RELOC_MICROMIPS_GOT_LO16: 4303 case BFD_RELOC_MICROMIPS_CALL_HI16: 4304 case BFD_RELOC_MICROMIPS_CALL_LO16: 4305 case BFD_RELOC_MICROMIPS_SUB: 4306 case BFD_RELOC_MICROMIPS_GOT_PAGE: 4307 case BFD_RELOC_MICROMIPS_GOT_OFST: 4308 case BFD_RELOC_MICROMIPS_GOT_DISP: 4309 case BFD_RELOC_MICROMIPS_HIGHEST: 4310 case BFD_RELOC_MICROMIPS_HIGHER: 4311 case BFD_RELOC_MICROMIPS_SCN_DISP: 4312 case BFD_RELOC_MICROMIPS_JALR: 4313 return TRUE; 4314 4315 default: 4316 return FALSE; 4317 } 4318} 4319 4320static inline bfd_boolean 4321jmp_reloc_p (bfd_reloc_code_real_type reloc) 4322{ 4323 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; 4324} 4325 4326static inline bfd_boolean 4327b_reloc_p (bfd_reloc_code_real_type reloc) 4328{ 4329 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 4330 || reloc == BFD_RELOC_MIPS_21_PCREL_S2 4331 || reloc == BFD_RELOC_16_PCREL_S2 4332 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 4333 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 4334 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 4335 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); 4336} 4337 4338static inline bfd_boolean 4339got16_reloc_p (bfd_reloc_code_real_type reloc) 4340{ 4341 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 4342 || reloc == BFD_RELOC_MICROMIPS_GOT16); 4343} 4344 4345static inline bfd_boolean 4346hi16_reloc_p (bfd_reloc_code_real_type reloc) 4347{ 4348 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S 4349 || reloc == BFD_RELOC_MICROMIPS_HI16_S); 4350} 4351 4352static inline bfd_boolean 4353lo16_reloc_p (bfd_reloc_code_real_type reloc) 4354{ 4355 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 4356 || reloc == BFD_RELOC_MICROMIPS_LO16); 4357} 4358 4359static inline bfd_boolean 4360jalr_reloc_p (bfd_reloc_code_real_type reloc) 4361{ 4362 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; 4363} 4364 4365static inline bfd_boolean 4366gprel16_reloc_p (bfd_reloc_code_real_type reloc) 4367{ 4368 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL 4369 || reloc == BFD_RELOC_MICROMIPS_GPREL16); 4370} 4371 4372/* Return true if RELOC is a PC-relative relocation that does not have 4373 full address range. */ 4374 4375static inline bfd_boolean 4376limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) 4377{ 4378 switch (reloc) 4379 { 4380 case BFD_RELOC_16_PCREL_S2: 4381 case BFD_RELOC_MIPS16_16_PCREL_S1: 4382 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 4383 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 4384 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 4385 case BFD_RELOC_MIPS_21_PCREL_S2: 4386 case BFD_RELOC_MIPS_26_PCREL_S2: 4387 case BFD_RELOC_MIPS_18_PCREL_S3: 4388 case BFD_RELOC_MIPS_19_PCREL_S2: 4389 return TRUE; 4390 4391 case BFD_RELOC_32_PCREL: 4392 case BFD_RELOC_HI16_S_PCREL: 4393 case BFD_RELOC_LO16_PCREL: 4394 return HAVE_64BIT_ADDRESSES; 4395 4396 default: 4397 return FALSE; 4398 } 4399} 4400 4401/* Return true if the given relocation might need a matching %lo(). 4402 This is only "might" because SVR4 R_MIPS_GOT16 relocations only 4403 need a matching %lo() when applied to local symbols. */ 4404 4405static inline bfd_boolean 4406reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 4407{ 4408 return (HAVE_IN_PLACE_ADDENDS 4409 && (hi16_reloc_p (reloc) 4410 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); 4411 all GOT16 relocations evaluate to "G". */ 4412 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); 4413} 4414 4415/* Return the type of %lo() reloc needed by RELOC, given that 4416 reloc_needs_lo_p. */ 4417 4418static inline bfd_reloc_code_real_type 4419matching_lo_reloc (bfd_reloc_code_real_type reloc) 4420{ 4421 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 4422 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 4423 : BFD_RELOC_LO16)); 4424} 4425 4426/* Return true if the given fixup is followed by a matching R_MIPS_LO16 4427 relocation. */ 4428 4429static inline bfd_boolean 4430fixup_has_matching_lo_p (fixS *fixp) 4431{ 4432 return (fixp->fx_next != NULL 4433 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) 4434 && fixp->fx_addsy == fixp->fx_next->fx_addsy 4435 && fixp->fx_offset == fixp->fx_next->fx_offset); 4436} 4437 4438/* Move all labels in LABELS to the current insertion point. TEXT_P 4439 says whether the labels refer to text or data. */ 4440 4441static void 4442mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) 4443{ 4444 struct insn_label_list *l; 4445 valueT val; 4446 4447 for (l = labels; l != NULL; l = l->next) 4448 { 4449 gas_assert (S_GET_SEGMENT (l->label) == now_seg); 4450 symbol_set_frag (l->label, frag_now); 4451 val = (valueT) frag_now_fix (); 4452 /* MIPS16/microMIPS text labels are stored as odd. 4453 We just carry the ISA mode bit forward. */ 4454 if (text_p && HAVE_CODE_COMPRESSION) 4455 val |= (S_GET_VALUE (l->label) & 0x1); 4456 S_SET_VALUE (l->label, val); 4457 } 4458} 4459 4460/* Move all labels in insn_labels to the current insertion point 4461 and treat them as text labels. */ 4462 4463static void 4464mips_move_text_labels (void) 4465{ 4466 mips_move_labels (seg_info (now_seg)->label_list, TRUE); 4467} 4468 4469/* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ 4470 4471static bfd_boolean 4472s_is_linkonce (symbolS *sym, segT from_seg) 4473{ 4474 bfd_boolean linkonce = FALSE; 4475 segT symseg = S_GET_SEGMENT (sym); 4476 4477 if (symseg != from_seg && !S_IS_LOCAL (sym)) 4478 { 4479 if ((bfd_section_flags (symseg) & SEC_LINK_ONCE)) 4480 linkonce = TRUE; 4481 /* The GNU toolchain uses an extension for ELF: a section 4482 beginning with the magic string .gnu.linkonce is a 4483 linkonce section. */ 4484 if (strncmp (segment_name (symseg), ".gnu.linkonce", 4485 sizeof ".gnu.linkonce" - 1) == 0) 4486 linkonce = TRUE; 4487 } 4488 return linkonce; 4489} 4490 4491/* Mark MIPS16 or microMIPS instruction label LABEL. This permits the 4492 linker to handle them specially, such as generating jalx instructions 4493 when needed. We also make them odd for the duration of the assembly, 4494 in order to generate the right sort of code. We will make them even 4495 in the adjust_symtab routine, while leaving them marked. This is 4496 convenient for the debugger and the disassembler. The linker knows 4497 to make them odd again. */ 4498 4499static void 4500mips_compressed_mark_label (symbolS *label) 4501{ 4502 gas_assert (HAVE_CODE_COMPRESSION); 4503 4504 if (mips_opts.mips16) 4505 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); 4506 else 4507 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); 4508 if ((S_GET_VALUE (label) & 1) == 0 4509 /* Don't adjust the address if the label is global or weak, or 4510 in a link-once section, since we'll be emitting symbol reloc 4511 references to it which will be patched up by the linker, and 4512 the final value of the symbol may or may not be MIPS16/microMIPS. */ 4513 && !S_IS_WEAK (label) 4514 && !S_IS_EXTERNAL (label) 4515 && !s_is_linkonce (label, now_seg)) 4516 S_SET_VALUE (label, S_GET_VALUE (label) | 1); 4517} 4518 4519/* Mark preceding MIPS16 or microMIPS instruction labels. */ 4520 4521static void 4522mips_compressed_mark_labels (void) 4523{ 4524 struct insn_label_list *l; 4525 4526 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) 4527 mips_compressed_mark_label (l->label); 4528} 4529 4530/* End the current frag. Make it a variant frag and record the 4531 relaxation info. */ 4532 4533static void 4534relax_close_frag (void) 4535{ 4536 mips_macro_warning.first_frag = frag_now; 4537 frag_var (rs_machine_dependent, 0, 0, 4538 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], 4539 mips_pic != NO_PIC), 4540 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 4541 4542 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 4543 mips_relax.first_fixup = 0; 4544} 4545 4546/* Start a new relaxation sequence whose expansion depends on SYMBOL. 4547 See the comment above RELAX_ENCODE for more details. */ 4548 4549static void 4550relax_start (symbolS *symbol) 4551{ 4552 gas_assert (mips_relax.sequence == 0); 4553 mips_relax.sequence = 1; 4554 mips_relax.symbol = symbol; 4555} 4556 4557/* Start generating the second version of a relaxable sequence. 4558 See the comment above RELAX_ENCODE for more details. */ 4559 4560static void 4561relax_switch (void) 4562{ 4563 gas_assert (mips_relax.sequence == 1); 4564 mips_relax.sequence = 2; 4565} 4566 4567/* End the current relaxable sequence. */ 4568 4569static void 4570relax_end (void) 4571{ 4572 gas_assert (mips_relax.sequence == 2); 4573 relax_close_frag (); 4574 mips_relax.sequence = 0; 4575} 4576 4577/* Return true if IP is a delayed branch or jump. */ 4578 4579static inline bfd_boolean 4580delayed_branch_p (const struct mips_cl_insn *ip) 4581{ 4582 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY 4583 | INSN_COND_BRANCH_DELAY 4584 | INSN_COND_BRANCH_LIKELY)) != 0; 4585} 4586 4587/* Return true if IP is a compact branch or jump. */ 4588 4589static inline bfd_boolean 4590compact_branch_p (const struct mips_cl_insn *ip) 4591{ 4592 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH 4593 | INSN2_COND_BRANCH)) != 0; 4594} 4595 4596/* Return true if IP is an unconditional branch or jump. */ 4597 4598static inline bfd_boolean 4599uncond_branch_p (const struct mips_cl_insn *ip) 4600{ 4601 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 4602 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); 4603} 4604 4605/* Return true if IP is a branch-likely instruction. */ 4606 4607static inline bfd_boolean 4608branch_likely_p (const struct mips_cl_insn *ip) 4609{ 4610 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; 4611} 4612 4613/* Return the type of nop that should be used to fill the delay slot 4614 of delayed branch IP. */ 4615 4616static struct mips_cl_insn * 4617get_delay_slot_nop (const struct mips_cl_insn *ip) 4618{ 4619 if (mips_opts.micromips 4620 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 4621 return µmips_nop32_insn; 4622 return NOP_INSN; 4623} 4624 4625/* Return a mask that has bit N set if OPCODE reads the register(s) 4626 in operand N. */ 4627 4628static unsigned int 4629insn_read_mask (const struct mips_opcode *opcode) 4630{ 4631 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; 4632} 4633 4634/* Return a mask that has bit N set if OPCODE writes to the register(s) 4635 in operand N. */ 4636 4637static unsigned int 4638insn_write_mask (const struct mips_opcode *opcode) 4639{ 4640 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; 4641} 4642 4643/* Return a mask of the registers specified by operand OPERAND of INSN. 4644 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4645 is set. */ 4646 4647static unsigned int 4648operand_reg_mask (const struct mips_cl_insn *insn, 4649 const struct mips_operand *operand, 4650 unsigned int type_mask) 4651{ 4652 unsigned int uval, vsel; 4653 4654 switch (operand->type) 4655 { 4656 case OP_INT: 4657 case OP_MAPPED_INT: 4658 case OP_MSB: 4659 case OP_PCREL: 4660 case OP_PERF_REG: 4661 case OP_ADDIUSP_INT: 4662 case OP_ENTRY_EXIT_LIST: 4663 case OP_REPEAT_DEST_REG: 4664 case OP_REPEAT_PREV_REG: 4665 case OP_PC: 4666 case OP_VU0_SUFFIX: 4667 case OP_VU0_MATCH_SUFFIX: 4668 case OP_IMM_INDEX: 4669 abort (); 4670 4671 case OP_REG28: 4672 return 1 << 28; 4673 4674 case OP_REG: 4675 case OP_OPTIONAL_REG: 4676 { 4677 const struct mips_reg_operand *reg_op; 4678 4679 reg_op = (const struct mips_reg_operand *) operand; 4680 if (!(type_mask & (1 << reg_op->reg_type))) 4681 return 0; 4682 uval = insn_extract_operand (insn, operand); 4683 return 1 << mips_decode_reg_operand (reg_op, uval); 4684 } 4685 4686 case OP_REG_PAIR: 4687 { 4688 const struct mips_reg_pair_operand *pair_op; 4689 4690 pair_op = (const struct mips_reg_pair_operand *) operand; 4691 if (!(type_mask & (1 << pair_op->reg_type))) 4692 return 0; 4693 uval = insn_extract_operand (insn, operand); 4694 return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); 4695 } 4696 4697 case OP_CLO_CLZ_DEST: 4698 if (!(type_mask & (1 << OP_REG_GP))) 4699 return 0; 4700 uval = insn_extract_operand (insn, operand); 4701 return (1 << (uval & 31)) | (1 << (uval >> 5)); 4702 4703 case OP_SAME_RS_RT: 4704 if (!(type_mask & (1 << OP_REG_GP))) 4705 return 0; 4706 uval = insn_extract_operand (insn, operand); 4707 gas_assert ((uval & 31) == (uval >> 5)); 4708 return 1 << (uval & 31); 4709 4710 case OP_CHECK_PREV: 4711 case OP_NON_ZERO_REG: 4712 if (!(type_mask & (1 << OP_REG_GP))) 4713 return 0; 4714 uval = insn_extract_operand (insn, operand); 4715 return 1 << (uval & 31); 4716 4717 case OP_LWM_SWM_LIST: 4718 abort (); 4719 4720 case OP_SAVE_RESTORE_LIST: 4721 abort (); 4722 4723 case OP_MDMX_IMM_REG: 4724 if (!(type_mask & (1 << OP_REG_VEC))) 4725 return 0; 4726 uval = insn_extract_operand (insn, operand); 4727 vsel = uval >> 5; 4728 if ((vsel & 0x18) == 0x18) 4729 return 0; 4730 return 1 << (uval & 31); 4731 4732 case OP_REG_INDEX: 4733 if (!(type_mask & (1 << OP_REG_GP))) 4734 return 0; 4735 return 1 << insn_extract_operand (insn, operand); 4736 } 4737 abort (); 4738} 4739 4740/* Return a mask of the registers specified by operands OPNO_MASK of INSN, 4741 where bit N of OPNO_MASK is set if operand N should be included. 4742 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK 4743 is set. */ 4744 4745static unsigned int 4746insn_reg_mask (const struct mips_cl_insn *insn, 4747 unsigned int type_mask, unsigned int opno_mask) 4748{ 4749 unsigned int opno, reg_mask; 4750 4751 opno = 0; 4752 reg_mask = 0; 4753 while (opno_mask != 0) 4754 { 4755 if (opno_mask & 1) 4756 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); 4757 opno_mask >>= 1; 4758 opno += 1; 4759 } 4760 return reg_mask; 4761} 4762 4763/* Return the mask of core registers that IP reads. */ 4764 4765static unsigned int 4766gpr_read_mask (const struct mips_cl_insn *ip) 4767{ 4768 unsigned long pinfo, pinfo2; 4769 unsigned int mask; 4770 4771 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); 4772 pinfo = ip->insn_mo->pinfo; 4773 pinfo2 = ip->insn_mo->pinfo2; 4774 if (pinfo & INSN_UDI) 4775 { 4776 /* UDI instructions have traditionally been assumed to read RS 4777 and RT. */ 4778 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); 4779 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); 4780 } 4781 if (pinfo & INSN_READ_GPR_24) 4782 mask |= 1 << 24; 4783 if (pinfo2 & INSN2_READ_GPR_16) 4784 mask |= 1 << 16; 4785 if (pinfo2 & INSN2_READ_SP) 4786 mask |= 1 << SP; 4787 if (pinfo2 & INSN2_READ_GPR_31) 4788 mask |= 1 << 31; 4789 /* Don't include register 0. */ 4790 return mask & ~1; 4791} 4792 4793/* Return the mask of core registers that IP writes. */ 4794 4795static unsigned int 4796gpr_write_mask (const struct mips_cl_insn *ip) 4797{ 4798 unsigned long pinfo, pinfo2; 4799 unsigned int mask; 4800 4801 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); 4802 pinfo = ip->insn_mo->pinfo; 4803 pinfo2 = ip->insn_mo->pinfo2; 4804 if (pinfo & INSN_WRITE_GPR_24) 4805 mask |= 1 << 24; 4806 if (pinfo & INSN_WRITE_GPR_31) 4807 mask |= 1 << 31; 4808 if (pinfo & INSN_UDI) 4809 /* UDI instructions have traditionally been assumed to write to RD. */ 4810 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); 4811 if (pinfo2 & INSN2_WRITE_SP) 4812 mask |= 1 << SP; 4813 /* Don't include register 0. */ 4814 return mask & ~1; 4815} 4816 4817/* Return the mask of floating-point registers that IP reads. */ 4818 4819static unsigned int 4820fpr_read_mask (const struct mips_cl_insn *ip) 4821{ 4822 unsigned long pinfo; 4823 unsigned int mask; 4824 4825 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4826 | (1 << OP_REG_MSA)), 4827 insn_read_mask (ip->insn_mo)); 4828 pinfo = ip->insn_mo->pinfo; 4829 /* Conservatively treat all operands to an FP_D instruction are doubles. 4830 (This is overly pessimistic for things like cvt.d.s.) */ 4831 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4832 mask |= mask << 1; 4833 return mask; 4834} 4835 4836/* Return the mask of floating-point registers that IP writes. */ 4837 4838static unsigned int 4839fpr_write_mask (const struct mips_cl_insn *ip) 4840{ 4841 unsigned long pinfo; 4842 unsigned int mask; 4843 4844 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) 4845 | (1 << OP_REG_MSA)), 4846 insn_write_mask (ip->insn_mo)); 4847 pinfo = ip->insn_mo->pinfo; 4848 /* Conservatively treat all operands to an FP_D instruction are doubles. 4849 (This is overly pessimistic for things like cvt.s.d.) */ 4850 if (FPR_SIZE != 64 && (pinfo & FP_D)) 4851 mask |= mask << 1; 4852 return mask; 4853} 4854 4855/* Operand OPNUM of INSN is an odd-numbered floating-point register. 4856 Check whether that is allowed. */ 4857 4858static bfd_boolean 4859mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) 4860{ 4861 const char *s = insn->name; 4862 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) 4863 || FPR_SIZE == 64) 4864 && mips_opts.oddspreg; 4865 4866 if (insn->pinfo == INSN_MACRO) 4867 /* Let a macro pass, we'll catch it later when it is expanded. */ 4868 return TRUE; 4869 4870 /* Single-precision coprocessor loads and moves are OK for 32-bit registers, 4871 otherwise it depends on oddspreg. */ 4872 if ((insn->pinfo & FP_S) 4873 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY 4874 | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) 4875 return FPR_SIZE == 32 || oddspreg; 4876 4877 /* Allow odd registers for single-precision ops and double-precision if the 4878 floating-point registers are 64-bit wide. */ 4879 switch (insn->pinfo & (FP_S | FP_D)) 4880 { 4881 case FP_S: 4882 case 0: 4883 return oddspreg; 4884 case FP_D: 4885 return FPR_SIZE == 64; 4886 default: 4887 break; 4888 } 4889 4890 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ 4891 s = strchr (insn->name, '.'); 4892 if (s != NULL && opnum == 2) 4893 s = strchr (s + 1, '.'); 4894 if (s != NULL && (s[1] == 'w' || s[1] == 's')) 4895 return oddspreg; 4896 4897 return FPR_SIZE == 64; 4898} 4899 4900/* Information about an instruction argument that we're trying to match. */ 4901struct mips_arg_info 4902{ 4903 /* The instruction so far. */ 4904 struct mips_cl_insn *insn; 4905 4906 /* The first unconsumed operand token. */ 4907 struct mips_operand_token *token; 4908 4909 /* The 1-based operand number, in terms of insn->insn_mo->args. */ 4910 int opnum; 4911 4912 /* The 1-based argument number, for error reporting. This does not 4913 count elided optional registers, etc.. */ 4914 int argnum; 4915 4916 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ 4917 unsigned int last_regno; 4918 4919 /* If the first operand was an OP_REG, this is the register that it 4920 specified, otherwise it is ILLEGAL_REG. */ 4921 unsigned int dest_regno; 4922 4923 /* The value of the last OP_INT operand. Only used for OP_MSB, 4924 where it gives the lsb position. */ 4925 unsigned int last_op_int; 4926 4927 /* If true, match routines should assume that no later instruction 4928 alternative matches and should therefore be as accommodating as 4929 possible. Match routines should not report errors if something 4930 is only invalid for !LAX_MATCH. */ 4931 bfd_boolean lax_match; 4932 4933 /* True if a reference to the current AT register was seen. */ 4934 bfd_boolean seen_at; 4935}; 4936 4937/* Record that the argument is out of range. */ 4938 4939static void 4940match_out_of_range (struct mips_arg_info *arg) 4941{ 4942 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); 4943} 4944 4945/* Record that the argument isn't constant but needs to be. */ 4946 4947static void 4948match_not_constant (struct mips_arg_info *arg) 4949{ 4950 set_insn_error_i (arg->argnum, _("operand %d must be constant"), 4951 arg->argnum); 4952} 4953 4954/* Try to match an OT_CHAR token for character CH. Consume the token 4955 and return true on success, otherwise return false. */ 4956 4957static bfd_boolean 4958match_char (struct mips_arg_info *arg, char ch) 4959{ 4960 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) 4961 { 4962 ++arg->token; 4963 if (ch == ',') 4964 arg->argnum += 1; 4965 return TRUE; 4966 } 4967 return FALSE; 4968} 4969 4970/* Try to get an expression from the next tokens in ARG. Consume the 4971 tokens and return true on success, storing the expression value in 4972 VALUE and relocation types in R. */ 4973 4974static bfd_boolean 4975match_expression (struct mips_arg_info *arg, expressionS *value, 4976 bfd_reloc_code_real_type *r) 4977{ 4978 /* If the next token is a '(' that was parsed as being part of a base 4979 expression, assume we have an elided offset. The later match will fail 4980 if this turns out to be wrong. */ 4981 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') 4982 { 4983 value->X_op = O_constant; 4984 value->X_add_number = 0; 4985 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; 4986 return TRUE; 4987 } 4988 4989 /* Reject register-based expressions such as "0+$2" and "(($2))". 4990 For plain registers the default error seems more appropriate. */ 4991 if (arg->token->type == OT_INTEGER 4992 && arg->token->u.integer.value.X_op == O_register) 4993 { 4994 set_insn_error (arg->argnum, _("register value used as expression")); 4995 return FALSE; 4996 } 4997 4998 if (arg->token->type == OT_INTEGER) 4999 { 5000 *value = arg->token->u.integer.value; 5001 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); 5002 ++arg->token; 5003 return TRUE; 5004 } 5005 5006 set_insn_error_i 5007 (arg->argnum, _("operand %d must be an immediate expression"), 5008 arg->argnum); 5009 return FALSE; 5010} 5011 5012/* Try to get a constant expression from the next tokens in ARG. Consume 5013 the tokens and return true on success, storing the constant value 5014 in *VALUE. */ 5015 5016static bfd_boolean 5017match_const_int (struct mips_arg_info *arg, offsetT *value) 5018{ 5019 expressionS ex; 5020 bfd_reloc_code_real_type r[3]; 5021 5022 if (!match_expression (arg, &ex, r)) 5023 return FALSE; 5024 5025 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) 5026 *value = ex.X_add_number; 5027 else 5028 { 5029 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) 5030 match_out_of_range (arg); 5031 else 5032 match_not_constant (arg); 5033 return FALSE; 5034 } 5035 return TRUE; 5036} 5037 5038/* Return the RTYPE_* flags for a register operand of type TYPE that 5039 appears in instruction OPCODE. */ 5040 5041static unsigned int 5042convert_reg_type (const struct mips_opcode *opcode, 5043 enum mips_reg_operand_type type) 5044{ 5045 switch (type) 5046 { 5047 case OP_REG_GP: 5048 return RTYPE_NUM | RTYPE_GP; 5049 5050 case OP_REG_FP: 5051 /* Allow vector register names for MDMX if the instruction is a 64-bit 5052 FPR load, store or move (including moves to and from GPRs). */ 5053 if ((mips_opts.ase & ASE_MDMX) 5054 && (opcode->pinfo & FP_D) 5055 && (opcode->pinfo & (INSN_COPROC_MOVE 5056 | INSN_COPROC_MEMORY_DELAY 5057 | INSN_LOAD_COPROC 5058 | INSN_LOAD_MEMORY 5059 | INSN_STORE_MEMORY))) 5060 return RTYPE_FPU | RTYPE_VEC; 5061 return RTYPE_FPU; 5062 5063 case OP_REG_CCC: 5064 if (opcode->pinfo & (FP_D | FP_S)) 5065 return RTYPE_CCC | RTYPE_FCC; 5066 return RTYPE_CCC; 5067 5068 case OP_REG_VEC: 5069 if (opcode->membership & INSN_5400) 5070 return RTYPE_FPU; 5071 return RTYPE_FPU | RTYPE_VEC; 5072 5073 case OP_REG_ACC: 5074 return RTYPE_ACC; 5075 5076 case OP_REG_COPRO: 5077 if (opcode->name[strlen (opcode->name) - 1] == '0') 5078 return RTYPE_NUM | RTYPE_CP0; 5079 return RTYPE_NUM; 5080 5081 case OP_REG_HW: 5082 return RTYPE_NUM; 5083 5084 case OP_REG_VI: 5085 return RTYPE_NUM | RTYPE_VI; 5086 5087 case OP_REG_VF: 5088 return RTYPE_NUM | RTYPE_VF; 5089 5090 case OP_REG_R5900_I: 5091 return RTYPE_R5900_I; 5092 5093 case OP_REG_R5900_Q: 5094 return RTYPE_R5900_Q; 5095 5096 case OP_REG_R5900_R: 5097 return RTYPE_R5900_R; 5098 5099 case OP_REG_R5900_ACC: 5100 return RTYPE_R5900_ACC; 5101 5102 case OP_REG_MSA: 5103 return RTYPE_MSA; 5104 5105 case OP_REG_MSA_CTRL: 5106 return RTYPE_NUM; 5107 } 5108 abort (); 5109} 5110 5111/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ 5112 5113static void 5114check_regno (struct mips_arg_info *arg, 5115 enum mips_reg_operand_type type, unsigned int regno) 5116{ 5117 if (AT && type == OP_REG_GP && regno == AT) 5118 arg->seen_at = TRUE; 5119 5120 if (type == OP_REG_FP 5121 && (regno & 1) != 0 5122 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) 5123 { 5124 /* This was a warning prior to introducing O32 FPXX and FP64 support 5125 so maintain a warning for FP32 but raise an error for the new 5126 cases. */ 5127 if (FPR_SIZE == 32) 5128 as_warn (_("float register should be even, was %d"), regno); 5129 else 5130 as_bad (_("float register should be even, was %d"), regno); 5131 } 5132 5133 if (type == OP_REG_CCC) 5134 { 5135 const char *name; 5136 size_t length; 5137 5138 name = arg->insn->insn_mo->name; 5139 length = strlen (name); 5140 if ((regno & 1) != 0 5141 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) 5142 || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) 5143 as_warn (_("condition code register should be even for %s, was %d"), 5144 name, regno); 5145 5146 if ((regno & 3) != 0 5147 && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) 5148 as_warn (_("condition code register should be 0 or 4 for %s, was %d"), 5149 name, regno); 5150 } 5151} 5152 5153/* ARG is a register with symbol value SYMVAL. Try to interpret it as 5154 a register of type TYPE. Return true on success, storing the register 5155 number in *REGNO and warning about any dubious uses. */ 5156 5157static bfd_boolean 5158match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, 5159 unsigned int symval, unsigned int *regno) 5160{ 5161 if (type == OP_REG_VEC) 5162 symval = mips_prefer_vec_regno (symval); 5163 if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) 5164 return FALSE; 5165 5166 *regno = symval & RNUM_MASK; 5167 check_regno (arg, type, *regno); 5168 return TRUE; 5169} 5170 5171/* Try to interpret the next token in ARG as a register of type TYPE. 5172 Consume the token and return true on success, storing the register 5173 number in *REGNO. Return false on failure. */ 5174 5175static bfd_boolean 5176match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, 5177 unsigned int *regno) 5178{ 5179 if (arg->token->type == OT_REG 5180 && match_regno (arg, type, arg->token->u.regno, regno)) 5181 { 5182 ++arg->token; 5183 return TRUE; 5184 } 5185 return FALSE; 5186} 5187 5188/* Try to interpret the next token in ARG as a range of registers of type TYPE. 5189 Consume the token and return true on success, storing the register numbers 5190 in *REGNO1 and *REGNO2. Return false on failure. */ 5191 5192static bfd_boolean 5193match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, 5194 unsigned int *regno1, unsigned int *regno2) 5195{ 5196 if (match_reg (arg, type, regno1)) 5197 { 5198 *regno2 = *regno1; 5199 return TRUE; 5200 } 5201 if (arg->token->type == OT_REG_RANGE 5202 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) 5203 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) 5204 && *regno1 <= *regno2) 5205 { 5206 ++arg->token; 5207 return TRUE; 5208 } 5209 return FALSE; 5210} 5211 5212/* OP_INT matcher. */ 5213 5214static bfd_boolean 5215match_int_operand (struct mips_arg_info *arg, 5216 const struct mips_operand *operand_base) 5217{ 5218 const struct mips_int_operand *operand; 5219 unsigned int uval; 5220 int min_val, max_val, factor; 5221 offsetT sval; 5222 5223 operand = (const struct mips_int_operand *) operand_base; 5224 factor = 1 << operand->shift; 5225 min_val = mips_int_operand_min (operand); 5226 max_val = mips_int_operand_max (operand); 5227 5228 if (operand_base->lsb == 0 5229 && operand_base->size == 16 5230 && operand->shift == 0 5231 && operand->bias == 0 5232 && (operand->max_val == 32767 || operand->max_val == 65535)) 5233 { 5234 /* The operand can be relocated. */ 5235 if (!match_expression (arg, &offset_expr, offset_reloc)) 5236 return FALSE; 5237 5238 if (offset_expr.X_op == O_big) 5239 { 5240 match_out_of_range (arg); 5241 return FALSE; 5242 } 5243 5244 if (offset_reloc[0] != BFD_RELOC_UNUSED) 5245 /* Relocation operators were used. Accept the argument and 5246 leave the relocation value in offset_expr and offset_relocs 5247 for the caller to process. */ 5248 return TRUE; 5249 5250 if (offset_expr.X_op != O_constant) 5251 { 5252 /* Accept non-constant operands if no later alternative matches, 5253 leaving it for the caller to process. */ 5254 if (!arg->lax_match) 5255 { 5256 match_not_constant (arg); 5257 return FALSE; 5258 } 5259 offset_reloc[0] = BFD_RELOC_LO16; 5260 return TRUE; 5261 } 5262 5263 /* Clear the global state; we're going to install the operand 5264 ourselves. */ 5265 sval = offset_expr.X_add_number; 5266 offset_expr.X_op = O_absent; 5267 5268 /* For compatibility with older assemblers, we accept 5269 0x8000-0xffff as signed 16-bit numbers when only 5270 signed numbers are allowed. */ 5271 if (sval > max_val) 5272 { 5273 max_val = ((1 << operand_base->size) - 1) << operand->shift; 5274 if (!arg->lax_match && sval <= max_val) 5275 { 5276 match_out_of_range (arg); 5277 return FALSE; 5278 } 5279 } 5280 } 5281 else 5282 { 5283 if (!match_const_int (arg, &sval)) 5284 return FALSE; 5285 } 5286 5287 arg->last_op_int = sval; 5288 5289 if (sval < min_val || sval > max_val || sval % factor) 5290 { 5291 match_out_of_range (arg); 5292 return FALSE; 5293 } 5294 5295 uval = (unsigned int) sval >> operand->shift; 5296 uval -= operand->bias; 5297 5298 /* Handle -mfix-cn63xxp1. */ 5299 if (arg->opnum == 1 5300 && mips_fix_cn63xxp1 5301 && !mips_opts.micromips 5302 && strcmp ("pref", arg->insn->insn_mo->name) == 0) 5303 switch (uval) 5304 { 5305 case 5: 5306 case 25: 5307 case 26: 5308 case 27: 5309 case 28: 5310 case 29: 5311 case 30: 5312 case 31: 5313 /* These are ok. */ 5314 break; 5315 5316 default: 5317 /* The rest must be changed to 28. */ 5318 uval = 28; 5319 break; 5320 } 5321 5322 insn_insert_operand (arg->insn, operand_base, uval); 5323 return TRUE; 5324} 5325 5326/* OP_MAPPED_INT matcher. */ 5327 5328static bfd_boolean 5329match_mapped_int_operand (struct mips_arg_info *arg, 5330 const struct mips_operand *operand_base) 5331{ 5332 const struct mips_mapped_int_operand *operand; 5333 unsigned int uval, num_vals; 5334 offsetT sval; 5335 5336 operand = (const struct mips_mapped_int_operand *) operand_base; 5337 if (!match_const_int (arg, &sval)) 5338 return FALSE; 5339 5340 num_vals = 1 << operand_base->size; 5341 for (uval = 0; uval < num_vals; uval++) 5342 if (operand->int_map[uval] == sval) 5343 break; 5344 if (uval == num_vals) 5345 { 5346 match_out_of_range (arg); 5347 return FALSE; 5348 } 5349 5350 insn_insert_operand (arg->insn, operand_base, uval); 5351 return TRUE; 5352} 5353 5354/* OP_MSB matcher. */ 5355 5356static bfd_boolean 5357match_msb_operand (struct mips_arg_info *arg, 5358 const struct mips_operand *operand_base) 5359{ 5360 const struct mips_msb_operand *operand; 5361 int min_val, max_val, max_high; 5362 offsetT size, sval, high; 5363 5364 operand = (const struct mips_msb_operand *) operand_base; 5365 min_val = operand->bias; 5366 max_val = min_val + (1 << operand_base->size) - 1; 5367 max_high = operand->opsize; 5368 5369 if (!match_const_int (arg, &size)) 5370 return FALSE; 5371 5372 high = size + arg->last_op_int; 5373 sval = operand->add_lsb ? high : size; 5374 5375 if (size < 0 || high > max_high || sval < min_val || sval > max_val) 5376 { 5377 match_out_of_range (arg); 5378 return FALSE; 5379 } 5380 insn_insert_operand (arg->insn, operand_base, sval - min_val); 5381 return TRUE; 5382} 5383 5384/* OP_REG matcher. */ 5385 5386static bfd_boolean 5387match_reg_operand (struct mips_arg_info *arg, 5388 const struct mips_operand *operand_base) 5389{ 5390 const struct mips_reg_operand *operand; 5391 unsigned int regno, uval, num_vals; 5392 5393 operand = (const struct mips_reg_operand *) operand_base; 5394 if (!match_reg (arg, operand->reg_type, ®no)) 5395 return FALSE; 5396 5397 if (operand->reg_map) 5398 { 5399 num_vals = 1 << operand->root.size; 5400 for (uval = 0; uval < num_vals; uval++) 5401 if (operand->reg_map[uval] == regno) 5402 break; 5403 if (num_vals == uval) 5404 return FALSE; 5405 } 5406 else 5407 uval = regno; 5408 5409 arg->last_regno = regno; 5410 if (arg->opnum == 1) 5411 arg->dest_regno = regno; 5412 insn_insert_operand (arg->insn, operand_base, uval); 5413 return TRUE; 5414} 5415 5416/* OP_REG_PAIR matcher. */ 5417 5418static bfd_boolean 5419match_reg_pair_operand (struct mips_arg_info *arg, 5420 const struct mips_operand *operand_base) 5421{ 5422 const struct mips_reg_pair_operand *operand; 5423 unsigned int regno1, regno2, uval, num_vals; 5424 5425 operand = (const struct mips_reg_pair_operand *) operand_base; 5426 if (!match_reg (arg, operand->reg_type, ®no1) 5427 || !match_char (arg, ',') 5428 || !match_reg (arg, operand->reg_type, ®no2)) 5429 return FALSE; 5430 5431 num_vals = 1 << operand_base->size; 5432 for (uval = 0; uval < num_vals; uval++) 5433 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) 5434 break; 5435 if (uval == num_vals) 5436 return FALSE; 5437 5438 insn_insert_operand (arg->insn, operand_base, uval); 5439 return TRUE; 5440} 5441 5442/* OP_PCREL matcher. The caller chooses the relocation type. */ 5443 5444static bfd_boolean 5445match_pcrel_operand (struct mips_arg_info *arg) 5446{ 5447 bfd_reloc_code_real_type r[3]; 5448 5449 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; 5450} 5451 5452/* OP_PERF_REG matcher. */ 5453 5454static bfd_boolean 5455match_perf_reg_operand (struct mips_arg_info *arg, 5456 const struct mips_operand *operand) 5457{ 5458 offsetT sval; 5459 5460 if (!match_const_int (arg, &sval)) 5461 return FALSE; 5462 5463 if (sval != 0 5464 && (sval != 1 5465 || (mips_opts.arch == CPU_R5900 5466 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 5467 || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) 5468 { 5469 set_insn_error (arg->argnum, _("invalid performance register")); 5470 return FALSE; 5471 } 5472 5473 insn_insert_operand (arg->insn, operand, sval); 5474 return TRUE; 5475} 5476 5477/* OP_ADDIUSP matcher. */ 5478 5479static bfd_boolean 5480match_addiusp_operand (struct mips_arg_info *arg, 5481 const struct mips_operand *operand) 5482{ 5483 offsetT sval; 5484 unsigned int uval; 5485 5486 if (!match_const_int (arg, &sval)) 5487 return FALSE; 5488 5489 if (sval % 4) 5490 { 5491 match_out_of_range (arg); 5492 return FALSE; 5493 } 5494 5495 sval /= 4; 5496 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) 5497 { 5498 match_out_of_range (arg); 5499 return FALSE; 5500 } 5501 5502 uval = (unsigned int) sval; 5503 uval = ((uval >> 1) & ~0xff) | (uval & 0xff); 5504 insn_insert_operand (arg->insn, operand, uval); 5505 return TRUE; 5506} 5507 5508/* OP_CLO_CLZ_DEST matcher. */ 5509 5510static bfd_boolean 5511match_clo_clz_dest_operand (struct mips_arg_info *arg, 5512 const struct mips_operand *operand) 5513{ 5514 unsigned int regno; 5515 5516 if (!match_reg (arg, OP_REG_GP, ®no)) 5517 return FALSE; 5518 5519 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5520 return TRUE; 5521} 5522 5523/* OP_CHECK_PREV matcher. */ 5524 5525static bfd_boolean 5526match_check_prev_operand (struct mips_arg_info *arg, 5527 const struct mips_operand *operand_base) 5528{ 5529 const struct mips_check_prev_operand *operand; 5530 unsigned int regno; 5531 5532 operand = (const struct mips_check_prev_operand *) operand_base; 5533 5534 if (!match_reg (arg, OP_REG_GP, ®no)) 5535 return FALSE; 5536 5537 if (!operand->zero_ok && regno == 0) 5538 return FALSE; 5539 5540 if ((operand->less_than_ok && regno < arg->last_regno) 5541 || (operand->greater_than_ok && regno > arg->last_regno) 5542 || (operand->equal_ok && regno == arg->last_regno)) 5543 { 5544 arg->last_regno = regno; 5545 insn_insert_operand (arg->insn, operand_base, regno); 5546 return TRUE; 5547 } 5548 5549 return FALSE; 5550} 5551 5552/* OP_SAME_RS_RT matcher. */ 5553 5554static bfd_boolean 5555match_same_rs_rt_operand (struct mips_arg_info *arg, 5556 const struct mips_operand *operand) 5557{ 5558 unsigned int regno; 5559 5560 if (!match_reg (arg, OP_REG_GP, ®no)) 5561 return FALSE; 5562 5563 if (regno == 0) 5564 { 5565 set_insn_error (arg->argnum, _("the source register must not be $0")); 5566 return FALSE; 5567 } 5568 5569 arg->last_regno = regno; 5570 5571 insn_insert_operand (arg->insn, operand, regno | (regno << 5)); 5572 return TRUE; 5573} 5574 5575/* OP_LWM_SWM_LIST matcher. */ 5576 5577static bfd_boolean 5578match_lwm_swm_list_operand (struct mips_arg_info *arg, 5579 const struct mips_operand *operand) 5580{ 5581 unsigned int reglist, sregs, ra, regno1, regno2; 5582 struct mips_arg_info reset; 5583 5584 reglist = 0; 5585 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5586 return FALSE; 5587 do 5588 { 5589 if (regno2 == FP && regno1 >= S0 && regno1 <= S7) 5590 { 5591 reglist |= 1 << FP; 5592 regno2 = S7; 5593 } 5594 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); 5595 reset = *arg; 5596 } 5597 while (match_char (arg, ',') 5598 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); 5599 *arg = reset; 5600 5601 if (operand->size == 2) 5602 { 5603 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: 5604 5605 s0, ra 5606 s0, s1, ra, s2, s3 5607 s0-s2, ra 5608 5609 and any permutations of these. */ 5610 if ((reglist & 0xfff1ffff) != 0x80010000) 5611 return FALSE; 5612 5613 sregs = (reglist >> 17) & 7; 5614 ra = 0; 5615 } 5616 else 5617 { 5618 /* The list must include at least one of ra and s0-sN, 5619 for 0 <= N <= 8. (Note that there is a gap between s7 and s8, 5620 which are $23 and $30 respectively.) E.g.: 5621 5622 ra 5623 s0 5624 ra, s0, s1, s2 5625 s0-s8 5626 s0-s5, ra 5627 5628 and any permutations of these. */ 5629 if ((reglist & 0x3f00ffff) != 0) 5630 return FALSE; 5631 5632 5633/* Fix NOP issue: Replace nops by "or at,at,zero". */ 5634 ra = (reglist >> 27) & 0x10; 5635 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); 5636 } 5637 sregs += 1; 5638 if ((sregs & -sregs) != sregs) 5639 return FALSE; 5640 5641 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); 5642 return TRUE; 5643} 5644 5645static void 5646trap_zero_jump (struct mips_cl_insn * ip) 5647{ 5648 if (strcmp (ip->insn_mo->name, "j") == 0 5649 || strcmp (ip->insn_mo->name, "jr") == 0 5650 || strcmp (ip->insn_mo->name, "jalr") == 0) 5651 { 5652 int sreg; 5653 5654 if (mips_opts.warn_about_macros) 5655 return; 5656 5657 sreg = EXTRACT_OPERAND (0, RS, *ip); 5658 if (mips_opts.isa == ISA_MIPS32 5659 || mips_opts.isa == ISA_MIPS32R2 5660 || mips_opts.isa == ISA_MIPS64 5661 || mips_opts.isa == ISA_MIPS64R2) 5662 { 5663 expressionS ep; 5664 ep.X_op = O_constant; 5665 ep.X_add_number = 4096; 5666 macro_build (&ep, "tltiu", "s,j", sreg, BFD_RELOC_LO16); 5667 } 5668 else if (mips_opts.isa != ISA_UNKNOWN 5669 && mips_opts.isa != ISA_MIPS1) 5670 macro_build (NULL, "teq", "s,t", sreg, 0); 5671 } 5672} 5673 5674/* OP_ENTRY_EXIT_LIST matcher. */ 5675 5676static unsigned int 5677match_entry_exit_operand (struct mips_arg_info *arg, 5678 const struct mips_operand *operand) 5679{ 5680 unsigned int mask; 5681 bfd_boolean is_exit; 5682 5683 /* The format is the same for both ENTRY and EXIT, but the constraints 5684 are different. */ 5685 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; 5686 mask = (is_exit ? 7 << 3 : 0); 5687 do 5688 { 5689 unsigned int regno1, regno2; 5690 bfd_boolean is_freg; 5691 5692 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5693 is_freg = FALSE; 5694 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) 5695 is_freg = TRUE; 5696 else 5697 return FALSE; 5698 5699 if (is_exit && is_freg && regno1 == 0 && regno2 < 2) 5700 { 5701 mask &= ~(7 << 3); 5702 mask |= (5 + regno2) << 3; 5703 } 5704 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) 5705 mask |= (regno2 - 3) << 3; 5706 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) 5707 mask |= (regno2 - 15) << 1; 5708 else if (regno1 == RA && regno2 == RA) 5709 mask |= 1; 5710 else 5711 return FALSE; 5712 } 5713 while (match_char (arg, ',')); 5714 5715 insn_insert_operand (arg->insn, operand, mask); 5716 return TRUE; 5717} 5718 5719/* Encode regular MIPS SAVE/RESTORE instruction operands according to 5720 the argument register mask AMASK, the number of static registers 5721 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 5722 respectively, and the frame size FRAME_SIZE. */ 5723 5724static unsigned int 5725mips_encode_save_restore (unsigned int amask, unsigned int nsreg, 5726 unsigned int ra, unsigned int s0, unsigned int s1, 5727 unsigned int frame_size) 5728{ 5729 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) 5730 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); 5731} 5732 5733/* Encode MIPS16 SAVE/RESTORE instruction operands according to the 5734 argument register mask AMASK, the number of static registers saved 5735 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 5736 respectively, and the frame size FRAME_SIZE. */ 5737 5738static unsigned int 5739mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, 5740 unsigned int ra, unsigned int s0, unsigned int s1, 5741 unsigned int frame_size) 5742{ 5743 unsigned int args; 5744 5745 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); 5746 if (nsreg || amask || frame_size == 0 || frame_size > 16) 5747 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) 5748 | ((frame_size & 0xf0) << 16)); 5749 return args; 5750} 5751 5752/* OP_SAVE_RESTORE_LIST matcher. */ 5753 5754static bfd_boolean 5755match_save_restore_list_operand (struct mips_arg_info *arg) 5756{ 5757 unsigned int opcode, args, statics, sregs; 5758 unsigned int num_frame_sizes, num_args, num_statics, num_sregs; 5759 unsigned int arg_mask, ra, s0, s1; 5760 offsetT frame_size; 5761 5762 opcode = arg->insn->insn_opcode; 5763 frame_size = 0; 5764 num_frame_sizes = 0; 5765 args = 0; 5766 statics = 0; 5767 sregs = 0; 5768 ra = 0; 5769 s0 = 0; 5770 s1 = 0; 5771 do 5772 { 5773 unsigned int regno1, regno2; 5774 5775 if (arg->token->type == OT_INTEGER) 5776 { 5777 /* Handle the frame size. */ 5778 if (!match_const_int (arg, &frame_size)) 5779 return FALSE; 5780 num_frame_sizes += 1; 5781 } 5782 else 5783 { 5784 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) 5785 return FALSE; 5786 5787 while (regno1 <= regno2) 5788 { 5789 if (regno1 >= 4 && regno1 <= 7) 5790 { 5791 if (num_frame_sizes == 0) 5792 /* args $a0-$a3 */ 5793 args |= 1 << (regno1 - 4); 5794 else 5795 /* statics $a0-$a3 */ 5796 statics |= 1 << (regno1 - 4); 5797 } 5798 else if (regno1 >= 16 && regno1 <= 23) 5799 /* $s0-$s7 */ 5800 sregs |= 1 << (regno1 - 16); 5801 else if (regno1 == 30) 5802 /* $s8 */ 5803 sregs |= 1 << 8; 5804 else if (regno1 == 31) 5805 /* Add $ra to insn. */ 5806 ra = 1; 5807 else 5808 return FALSE; 5809 regno1 += 1; 5810 if (regno1 == 24) 5811 regno1 = 30; 5812 } 5813 } 5814 } 5815 while (match_char (arg, ',')); 5816 5817 /* Encode args/statics combination. */ 5818 if (args & statics) 5819 return FALSE; 5820 else if (args == 0xf) 5821 /* All $a0-$a3 are args. */ 5822 arg_mask = MIPS_SVRS_ALL_ARGS; 5823 else if (statics == 0xf) 5824 /* All $a0-$a3 are statics. */ 5825 arg_mask = MIPS_SVRS_ALL_STATICS; 5826 else 5827 { 5828 /* Count arg registers. */ 5829 num_args = 0; 5830 while (args & 0x1) 5831 { 5832 args >>= 1; 5833 num_args += 1; 5834 } 5835 if (args != 0) 5836 return FALSE; 5837 5838 /* Count static registers. */ 5839 num_statics = 0; 5840 while (statics & 0x8) 5841 { 5842 statics = (statics << 1) & 0xf; 5843 num_statics += 1; 5844 } 5845 if (statics != 0) 5846 return FALSE; 5847 5848 /* Encode args/statics. */ 5849 arg_mask = (num_args << 2) | num_statics; 5850 } 5851 5852 /* Encode $s0/$s1. */ 5853 if (sregs & (1 << 0)) /* $s0 */ 5854 s0 = 1; 5855 if (sregs & (1 << 1)) /* $s1 */ 5856 s1 = 1; 5857 sregs >>= 2; 5858 5859 /* Encode $s2-$s8. */ 5860 num_sregs = 0; 5861 while (sregs & 1) 5862 { 5863 sregs >>= 1; 5864 num_sregs += 1; 5865 } 5866 if (sregs != 0) 5867 return FALSE; 5868 5869 /* Encode frame size. */ 5870 if (num_frame_sizes == 0) 5871 { 5872 set_insn_error (arg->argnum, _("missing frame size")); 5873 return FALSE; 5874 } 5875 if (num_frame_sizes > 1) 5876 { 5877 set_insn_error (arg->argnum, _("frame size specified twice")); 5878 return FALSE; 5879 } 5880 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) 5881 { 5882 set_insn_error (arg->argnum, _("invalid frame size")); 5883 return FALSE; 5884 } 5885 frame_size /= 8; 5886 5887 /* If the branch is itself the target of a branch, we can not swap. 5888 We cheat on this; all we check for is whether there is a label on 5889 this instruction. If there are any branches to anything other than 5890 a label, users must use .set noreorder. */ 5891 if (seg_info (now_seg)->label_list) 5892 return FALSE; 5893 5894 /* Finally build the instruction. */ 5895 if (mips_opts.mips16) 5896 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, 5897 frame_size); 5898 else if (!mips_opts.micromips) 5899 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, 5900 frame_size); 5901 else 5902 abort (); 5903 5904 arg->insn->insn_opcode = opcode; 5905 return TRUE; 5906} 5907 5908/* OP_MDMX_IMM_REG matcher. */ 5909 5910static bfd_boolean 5911match_mdmx_imm_reg_operand (struct mips_arg_info *arg, 5912 const struct mips_operand *operand) 5913{ 5914 unsigned int regno, uval; 5915 bfd_boolean is_qh; 5916 const struct mips_opcode *opcode; 5917 5918 /* The mips_opcode records whether this is an octobyte or quadhalf 5919 instruction. Start out with that bit in place. */ 5920 opcode = arg->insn->insn_mo; 5921 uval = mips_extract_operand (operand, opcode->match); 5922 is_qh = (uval != 0); 5923 5924 if (arg->token->type == OT_REG) 5925 { 5926 if ((opcode->membership & INSN_5400) 5927 && strcmp (opcode->name, "rzu.ob") == 0) 5928 { 5929 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), 5930 arg->argnum); 5931 return FALSE; 5932 } 5933 5934 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) 5935 return FALSE; 5936 ++arg->token; 5937 5938 /* Check whether this is a vector register or a broadcast of 5939 a single element. */ 5940 if (arg->token->type == OT_INTEGER_INDEX) 5941 { 5942 if (arg->token->u.index > (is_qh ? 3 : 7)) 5943 { 5944 set_insn_error (arg->argnum, _("invalid element selector")); 5945 return FALSE; 5946 } 5947 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; 5948 ++arg->token; 5949 } 5950 else 5951 { 5952 /* A full vector. */ 5953 if ((opcode->membership & INSN_5400) 5954 && (strcmp (opcode->name, "sll.ob") == 0 5955 || strcmp (opcode->name, "srl.ob") == 0)) 5956 { 5957 set_insn_error_i (arg->argnum, _("operand %d must be scalar"), 5958 arg->argnum); 5959 return FALSE; 5960 } 5961 5962 if (is_qh) 5963 uval |= MDMX_FMTSEL_VEC_QH << 5; 5964 else 5965 uval |= MDMX_FMTSEL_VEC_OB << 5; 5966 } 5967 uval |= regno; 5968 } 5969 else 5970 { 5971 offsetT sval; 5972 5973 if (!match_const_int (arg, &sval)) 5974 return FALSE; 5975 if (sval < 0 || sval > 31) 5976 { 5977 match_out_of_range (arg); 5978 return FALSE; 5979 } 5980 uval |= (sval & 31); 5981 if (is_qh) 5982 uval |= MDMX_FMTSEL_IMM_QH << 5; 5983 else 5984 uval |= MDMX_FMTSEL_IMM_OB << 5; 5985 } 5986 insn_insert_operand (arg->insn, operand, uval); 5987 return TRUE; 5988} 5989 5990/* OP_IMM_INDEX matcher. */ 5991 5992static bfd_boolean 5993match_imm_index_operand (struct mips_arg_info *arg, 5994 const struct mips_operand *operand) 5995{ 5996 unsigned int max_val; 5997 5998 if (arg->token->type != OT_INTEGER_INDEX) 5999 return FALSE; 6000 6001 max_val = (1 << operand->size) - 1; 6002 if (arg->token->u.index > max_val) 6003 { 6004 match_out_of_range (arg); 6005 return FALSE; 6006 } 6007 insn_insert_operand (arg->insn, operand, arg->token->u.index); 6008 ++arg->token; 6009 return TRUE; 6010} 6011 6012/* OP_REG_INDEX matcher. */ 6013 6014static bfd_boolean 6015match_reg_index_operand (struct mips_arg_info *arg, 6016 const struct mips_operand *operand) 6017{ 6018 unsigned int regno; 6019 6020 if (arg->token->type != OT_REG_INDEX) 6021 return FALSE; 6022 6023 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) 6024 return FALSE; 6025 6026 insn_insert_operand (arg->insn, operand, regno); 6027 ++arg->token; 6028 return TRUE; 6029} 6030 6031/* OP_PC matcher. */ 6032 6033static bfd_boolean 6034match_pc_operand (struct mips_arg_info *arg) 6035{ 6036 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) 6037 { 6038 ++arg->token; 6039 return TRUE; 6040 } 6041 return FALSE; 6042} 6043 6044/* OP_REG28 matcher. */ 6045 6046static bfd_boolean 6047match_reg28_operand (struct mips_arg_info *arg) 6048{ 6049 unsigned int regno; 6050 6051 if (arg->token->type == OT_REG 6052 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) 6053 && regno == GP) 6054 { 6055 ++arg->token; 6056 return TRUE; 6057 } 6058 return FALSE; 6059} 6060 6061/* OP_NON_ZERO_REG matcher. */ 6062 6063static bfd_boolean 6064match_non_zero_reg_operand (struct mips_arg_info *arg, 6065 const struct mips_operand *operand) 6066{ 6067 unsigned int regno; 6068 6069 if (!match_reg (arg, OP_REG_GP, ®no)) 6070 return FALSE; 6071 6072 if (regno == 0) 6073 { 6074 set_insn_error (arg->argnum, _("the source register must not be $0")); 6075 return FALSE; 6076 } 6077 6078 arg->last_regno = regno; 6079 insn_insert_operand (arg->insn, operand, regno); 6080 return TRUE; 6081} 6082 6083/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the 6084 register that we need to match. */ 6085 6086static bfd_boolean 6087match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) 6088{ 6089 unsigned int regno; 6090 6091 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; 6092} 6093 6094/* Try to match a floating-point constant from ARG for LI.S or LI.D. 6095 LENGTH is the length of the value in bytes (4 for float, 8 for double) 6096 and USING_GPRS says whether the destination is a GPR rather than an FPR. 6097 6098 Return the constant in IMM and OFFSET as follows: 6099 6100 - If the constant should be loaded via memory, set IMM to O_absent and 6101 OFFSET to the memory address. 6102 6103 - Otherwise, if the constant should be loaded into two 32-bit registers, 6104 set IMM to the O_constant to load into the high register and OFFSET 6105 to the corresponding value for the low register. 6106 6107 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. 6108 6109 These constants only appear as the last operand in an instruction, 6110 and every instruction that accepts them in any variant accepts them 6111 in all variants. This means we don't have to worry about backing out 6112 any changes if the instruction does not match. We just match 6113 unconditionally and report an error if the constant is invalid. */ 6114 6115static bfd_boolean 6116match_float_constant (struct mips_arg_info *arg, expressionS *imm, 6117 expressionS *offset, int length, bfd_boolean using_gprs) 6118{ 6119 char *p; 6120 segT seg, new_seg; 6121 subsegT subseg; 6122 const char *newname; 6123 unsigned char *data; 6124 6125 /* Where the constant is placed is based on how the MIPS assembler 6126 does things: 6127 6128 length == 4 && using_gprs -- immediate value only 6129 length == 8 && using_gprs -- .rdata or immediate value 6130 length == 4 && !using_gprs -- .lit4 or immediate value 6131 length == 8 && !using_gprs -- .lit8 or immediate value 6132 6133 The .lit4 and .lit8 sections are only used if permitted by the 6134 -G argument. */ 6135 if (arg->token->type != OT_FLOAT) 6136 { 6137 set_insn_error (arg->argnum, _("floating-point expression required")); 6138 return FALSE; 6139 } 6140 6141 gas_assert (arg->token->u.flt.length == length); 6142 data = arg->token->u.flt.data; 6143 ++arg->token; 6144 6145 /* Handle 32-bit constants for which an immediate value is best. */ 6146 if (length == 4 6147 && (using_gprs 6148 || g_switch_value < 4 6149 || (data[0] == 0 && data[1] == 0) 6150 || (data[2] == 0 && data[3] == 0))) 6151 { 6152 imm->X_op = O_constant; 6153 if (!target_big_endian) 6154 imm->X_add_number = bfd_getl32 (data); 6155 else 6156 imm->X_add_number = bfd_getb32 (data); 6157 offset->X_op = O_absent; 6158 return TRUE; 6159 } 6160 6161 /* Handle 64-bit constants for which an immediate value is best. */ 6162 if (length == 8 6163 && !mips_disable_float_construction 6164 /* Constants can only be constructed in GPRs and copied to FPRs if the 6165 GPRs are at least as wide as the FPRs or MTHC1 is available. 6166 Unlike most tests for 32-bit floating-point registers this check 6167 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not 6168 permit 64-bit moves without MXHC1. 6169 Force the constant into memory otherwise. */ 6170 && (using_gprs 6171 || GPR_SIZE == 64 6172 || ISA_HAS_MXHC1 (mips_opts.isa) 6173 || FPR_SIZE == 32) 6174 && ((data[0] == 0 && data[1] == 0) 6175 || (data[2] == 0 && data[3] == 0)) 6176 && ((data[4] == 0 && data[5] == 0) 6177 || (data[6] == 0 && data[7] == 0))) 6178 { 6179 /* The value is simple enough to load with a couple of instructions. 6180 If using 32-bit registers, set IMM to the high order 32 bits and 6181 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 6182 64 bit constant. */ 6183 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) 6184 { 6185 imm->X_op = O_constant; 6186 offset->X_op = O_constant; 6187 if (!target_big_endian) 6188 { 6189 imm->X_add_number = bfd_getl32 (data + 4); 6190 offset->X_add_number = bfd_getl32 (data); 6191 } 6192 else 6193 { 6194 imm->X_add_number = bfd_getb32 (data); 6195 offset->X_add_number = bfd_getb32 (data + 4); 6196 } 6197 if (offset->X_add_number == 0) 6198 offset->X_op = O_absent; 6199 } 6200 else 6201 { 6202 imm->X_op = O_constant; 6203 if (!target_big_endian) 6204 imm->X_add_number = bfd_getl64 (data); 6205 else 6206 imm->X_add_number = bfd_getb64 (data); 6207 offset->X_op = O_absent; 6208 } 6209 return TRUE; 6210 } 6211 6212 /* Switch to the right section. */ 6213 seg = now_seg; 6214 subseg = now_subseg; 6215 if (length == 4) 6216 { 6217 gas_assert (!using_gprs && g_switch_value >= 4); 6218 newname = ".lit4"; 6219 } 6220 else 6221 { 6222 if (using_gprs || g_switch_value < 8) 6223 newname = RDATA_SECTION_NAME; 6224 else 6225 newname = ".lit8"; 6226 } 6227 6228 new_seg = subseg_new (newname, (subsegT) 0); 6229 bfd_set_section_flags (new_seg, 6230 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); 6231 frag_align (length == 4 ? 2 : 3, 0, 0); 6232 if (strncmp (TARGET_OS, "elf", 3) != 0) 6233 record_alignment (new_seg, 4); 6234 else 6235 record_alignment (new_seg, length == 4 ? 2 : 3); 6236 if (seg == now_seg) 6237 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); 6238 6239 /* Set the argument to the current address in the section. */ 6240 imm->X_op = O_absent; 6241 offset->X_op = O_symbol; 6242 offset->X_add_symbol = symbol_temp_new_now (); 6243 offset->X_add_number = 0; 6244 6245 /* Put the floating point number into the section. */ 6246 p = frag_more (length); 6247 memcpy (p, data, length); 6248 6249 /* Switch back to the original section. */ 6250 subseg_set (seg, subseg); 6251 return TRUE; 6252} 6253 6254/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between 6255 them. */ 6256 6257static bfd_boolean 6258match_vu0_suffix_operand (struct mips_arg_info *arg, 6259 const struct mips_operand *operand, 6260 bfd_boolean match_p) 6261{ 6262 unsigned int uval; 6263 6264 /* The operand can be an XYZW mask or a single 2-bit channel index 6265 (with X being 0). */ 6266 gas_assert (operand->size == 2 || operand->size == 4); 6267 6268 /* The suffix can be omitted when it is already part of the opcode. */ 6269 if (arg->token->type != OT_CHANNELS) 6270 return match_p; 6271 6272 uval = arg->token->u.channels; 6273 if (operand->size == 2) 6274 { 6275 /* Check that a single bit is set and convert it into a 2-bit index. */ 6276 if ((uval & -uval) != uval) 6277 return FALSE; 6278 uval = 4 - ffs (uval); 6279 } 6280 6281 if (match_p && insn_extract_operand (arg->insn, operand) != uval) 6282 return FALSE; 6283 6284 ++arg->token; 6285 if (!match_p) 6286 insn_insert_operand (arg->insn, operand, uval); 6287 return TRUE; 6288} 6289 6290/* Try to match a token from ARG against OPERAND. Consume the token 6291 and return true on success, otherwise return false. */ 6292 6293static bfd_boolean 6294match_operand (struct mips_arg_info *arg, 6295 const struct mips_operand *operand) 6296{ 6297 switch (operand->type) 6298 { 6299 case OP_INT: 6300 return match_int_operand (arg, operand); 6301 6302 case OP_MAPPED_INT: 6303 return match_mapped_int_operand (arg, operand); 6304 6305 case OP_MSB: 6306 return match_msb_operand (arg, operand); 6307 6308 case OP_REG: 6309 case OP_OPTIONAL_REG: 6310 return match_reg_operand (arg, operand); 6311 6312 case OP_REG_PAIR: 6313 return match_reg_pair_operand (arg, operand); 6314 6315 case OP_PCREL: 6316 return match_pcrel_operand (arg); 6317 6318 case OP_PERF_REG: 6319 return match_perf_reg_operand (arg, operand); 6320 6321 case OP_ADDIUSP_INT: 6322 return match_addiusp_operand (arg, operand); 6323 6324 case OP_CLO_CLZ_DEST: 6325 return match_clo_clz_dest_operand (arg, operand); 6326 6327 case OP_LWM_SWM_LIST: 6328 return match_lwm_swm_list_operand (arg, operand); 6329 6330 case OP_ENTRY_EXIT_LIST: 6331 return match_entry_exit_operand (arg, operand); 6332 6333 case OP_SAVE_RESTORE_LIST: 6334 return match_save_restore_list_operand (arg); 6335 6336 case OP_MDMX_IMM_REG: 6337 return match_mdmx_imm_reg_operand (arg, operand); 6338 6339 case OP_REPEAT_DEST_REG: 6340 return match_tied_reg_operand (arg, arg->dest_regno); 6341 6342 case OP_REPEAT_PREV_REG: 6343 return match_tied_reg_operand (arg, arg->last_regno); 6344 6345 case OP_PC: 6346 return match_pc_operand (arg); 6347 6348 case OP_REG28: 6349 return match_reg28_operand (arg); 6350 6351 case OP_VU0_SUFFIX: 6352 return match_vu0_suffix_operand (arg, operand, FALSE); 6353 6354 case OP_VU0_MATCH_SUFFIX: 6355 return match_vu0_suffix_operand (arg, operand, TRUE); 6356 6357 case OP_IMM_INDEX: 6358 return match_imm_index_operand (arg, operand); 6359 6360 case OP_REG_INDEX: 6361 return match_reg_index_operand (arg, operand); 6362 6363 case OP_SAME_RS_RT: 6364 return match_same_rs_rt_operand (arg, operand); 6365 6366 case OP_CHECK_PREV: 6367 return match_check_prev_operand (arg, operand); 6368 6369 case OP_NON_ZERO_REG: 6370 return match_non_zero_reg_operand (arg, operand); 6371 } 6372 abort (); 6373} 6374 6375/* ARG is the state after successfully matching an instruction. 6376 Issue any queued-up warnings. */ 6377 6378static void 6379check_completed_insn (struct mips_arg_info *arg) 6380{ 6381 if (arg->seen_at) 6382 { 6383 if (AT == ATREG) 6384 as_warn (_("used $at without \".set noat\"")); 6385 else 6386 as_warn (_("used $%u with \".set at=$%u\""), AT, AT); 6387 } 6388} 6389 6390/* Return true if modifying general-purpose register REG needs a delay. */ 6391 6392static bfd_boolean 6393reg_needs_delay (unsigned int reg) 6394{ 6395 unsigned long prev_pinfo; 6396 6397 prev_pinfo = history[0].insn_mo->pinfo; 6398 if (!mips_opts.noreorder 6399 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) 6400 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) 6401 && (gpr_write_mask (&history[0]) & (1 << reg))) 6402 return TRUE; 6403 6404 return FALSE; 6405} 6406 6407/* Classify an instruction according to the FIX_VR4120_* enumeration. 6408 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected 6409 by VR4120 errata. */ 6410 6411static unsigned int 6412classify_vr4120_insn (const char *name) 6413{ 6414 if (strncmp (name, "macc", 4) == 0) 6415 return FIX_VR4120_MACC; 6416 if (strncmp (name, "dmacc", 5) == 0) 6417 return FIX_VR4120_DMACC; 6418 if (strncmp (name, "mult", 4) == 0) 6419 return FIX_VR4120_MULT; 6420 if (strncmp (name, "dmult", 5) == 0) 6421 return FIX_VR4120_DMULT; 6422 if (strstr (name, "div")) 6423 return FIX_VR4120_DIV; 6424 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) 6425 return FIX_VR4120_MTHILO; 6426 return NUM_FIX_VR4120_CLASSES; 6427} 6428 6429#define INSN_ERET 0x42000018 6430#define INSN_DERET 0x4200001f 6431#define INSN_DMULT 0x1c 6432#define INSN_DMULTU 0x1d 6433 6434/* Return the number of instructions that must separate INSN1 and INSN2, 6435 where INSN1 is the earlier instruction. Return the worst-case value 6436 for any INSN2 if INSN2 is null. */ 6437 6438static unsigned int 6439insns_between (const struct mips_cl_insn *insn1, 6440 const struct mips_cl_insn *insn2) 6441{ 6442 unsigned long pinfo1, pinfo2; 6443 unsigned int mask; 6444 6445 /* If INFO2 is null, pessimistically assume that all flags are set for 6446 the second instruction. */ 6447 pinfo1 = insn1->insn_mo->pinfo; 6448 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; 6449 6450 /* For most targets, write-after-read dependencies on the HI and LO 6451 registers must be separated by at least two instructions. */ 6452 if (!hilo_interlocks) 6453 { 6454 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) 6455 return 2; 6456 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) 6457 return 2; 6458 } 6459 6460 /* If we're working around r7000 errata, there must be two instructions 6461 between an mfhi or mflo and any instruction that uses the result. */ 6462 if (mips_7000_hilo_fix 6463 && !mips_opts.micromips 6464 && MF_HILO_INSN (pinfo1) 6465 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) 6466 return 2; 6467 6468 /* If we're working around 24K errata, one instruction is required 6469 if an ERET or DERET is followed by a branch instruction. */ 6470 if (mips_fix_24k && !mips_opts.micromips) 6471 { 6472 if (insn1->insn_opcode == INSN_ERET 6473 || insn1->insn_opcode == INSN_DERET) 6474 { 6475 if (insn2 == NULL 6476 || insn2->insn_opcode == INSN_ERET 6477 || insn2->insn_opcode == INSN_DERET 6478 || delayed_branch_p (insn2)) 6479 return 1; 6480 } 6481 } 6482 6483 /* If we're working around PMC RM7000 errata, there must be three 6484 nops between a dmult and a load instruction. */ 6485 if (mips_fix_rm7000 && !mips_opts.micromips) 6486 { 6487 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT 6488 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) 6489 { 6490 if (pinfo2 & INSN_LOAD_MEMORY) 6491 return 3; 6492 } 6493 } 6494 6495 /* If working around VR4120 errata, check for combinations that need 6496 a single intervening instruction. */ 6497 if (mips_fix_vr4120 && !mips_opts.micromips) 6498 { 6499 unsigned int class1, class2; 6500 6501 class1 = classify_vr4120_insn (insn1->insn_mo->name); 6502 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) 6503 { 6504 if (insn2 == NULL) 6505 return 1; 6506 class2 = classify_vr4120_insn (insn2->insn_mo->name); 6507 if (vr4120_conflicts[class1] & (1 << class2)) 6508 return 1; 6509 } 6510 } 6511 6512 if (!HAVE_CODE_COMPRESSION) 6513 { 6514 /* Check for GPR or coprocessor load delays. All such delays 6515 are on the RT register. */ 6516 /* Itbl support may require additional care here. */ 6517 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) 6518 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) 6519 { 6520 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) 6521 return 1; 6522 } 6523 6524 /* Check for generic coprocessor hazards. 6525 6526 This case is not handled very well. There is no special 6527 knowledge of CP0 handling, and the coprocessors other than 6528 the floating point unit are not distinguished at all. */ 6529 /* Itbl support may require additional care here. FIXME! 6530 Need to modify this to include knowledge about 6531 user specified delays! */ 6532 if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) 6533 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) 6534 { 6535 /* Handle cases where INSN1 writes to a known general coprocessor 6536 register. There must be a one instruction delay before INSN2 6537 if INSN2 reads that register, otherwise no delay is needed. */ 6538 mask = fpr_write_mask (insn1); 6539 if (mask != 0) 6540 { 6541 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) 6542 return 1; 6543 } 6544 else 6545 { 6546 /* Read-after-write dependencies on the control registers 6547 require a two-instruction gap. */ 6548 if ((pinfo1 & INSN_WRITE_COND_CODE) 6549 && (pinfo2 & INSN_READ_COND_CODE)) 6550 return 2; 6551 6552 /* We don't know exactly what INSN1 does. If INSN2 is 6553 also a coprocessor instruction, assume there must be 6554 a one instruction gap. */ 6555 if (pinfo2 & INSN_COP) 6556 return 1; 6557 } 6558 } 6559 6560 /* Check for read-after-write dependencies on the coprocessor 6561 control registers in cases where INSN1 does not need a general 6562 coprocessor delay. This means that INSN1 is a floating point 6563 comparison instruction. */ 6564 /* Itbl support may require additional care here. */ 6565 else if (!cop_interlocks 6566 && (pinfo1 & INSN_WRITE_COND_CODE) 6567 && (pinfo2 & INSN_READ_COND_CODE)) 6568 return 1; 6569 } 6570 6571 /* Forbidden slots can not contain Control Transfer Instructions (CTIs) 6572 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait 6573 and pause. */ 6574 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) 6575 && ((pinfo2 & INSN_NO_DELAY_SLOT) 6576 || (insn2 && delayed_branch_p (insn2)))) 6577 return 1; 6578 6579 return 0; 6580} 6581 6582/* Return the number of nops that would be needed to work around the 6583 VR4130 mflo/mfhi errata if instruction INSN immediately followed 6584 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards 6585 that are contained within the first IGNORE instructions of HIST. */ 6586 6587static int 6588nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, 6589 const struct mips_cl_insn *insn) 6590{ 6591 int i, j; 6592 unsigned int mask; 6593 6594 /* Check if the instruction writes to HI or LO. MTHI and MTLO 6595 are not affected by the errata. */ 6596 if (insn != 0 6597 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 6598 || strcmp (insn->insn_mo->name, "mtlo") == 0 6599 || strcmp (insn->insn_mo->name, "mthi") == 0)) 6600 return 0; 6601 6602 /* Search for the first MFLO or MFHI. */ 6603 for (i = 0; i < MAX_VR4130_NOPS; i++) 6604 if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) 6605 { 6606 /* Extract the destination register. */ 6607 mask = gpr_write_mask (&hist[i]); 6608 6609 /* No nops are needed if INSN reads that register. */ 6610 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) 6611 return 0; 6612 6613 /* ...or if any of the intervening instructions do. */ 6614 for (j = 0; j < i; j++) 6615 if (gpr_read_mask (&hist[j]) & mask) 6616 return 0; 6617 6618 if (i >= ignore) 6619 return MAX_VR4130_NOPS - i; 6620 } 6621 return 0; 6622} 6623 6624#define BASE_REG_EQ(INSN1, INSN2) \ 6625 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ 6626 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) 6627 6628/* Return the minimum alignment for this store instruction. */ 6629 6630static int 6631fix_24k_align_to (const struct mips_opcode *mo) 6632{ 6633 if (strcmp (mo->name, "sh") == 0) 6634 return 2; 6635 6636 if (strcmp (mo->name, "swc1") == 0 6637 || strcmp (mo->name, "swc2") == 0 6638 || strcmp (mo->name, "sw") == 0 6639 || strcmp (mo->name, "sc") == 0 6640 || strcmp (mo->name, "s.s") == 0) 6641 return 4; 6642 6643 if (strcmp (mo->name, "sdc1") == 0 6644 || strcmp (mo->name, "sdc2") == 0 6645 || strcmp (mo->name, "s.d") == 0) 6646 return 8; 6647 6648 /* sb, swl, swr */ 6649 return 1; 6650} 6651 6652struct fix_24k_store_info 6653 { 6654 /* Immediate offset, if any, for this store instruction. */ 6655 short off; 6656 /* Alignment required by this store instruction. */ 6657 int align_to; 6658 /* True for register offsets. */ 6659 int register_offset; 6660 }; 6661 6662/* Comparison function used by qsort. */ 6663 6664static int 6665fix_24k_sort (const void *a, const void *b) 6666{ 6667 const struct fix_24k_store_info *pos1 = a; 6668 const struct fix_24k_store_info *pos2 = b; 6669 6670 return (pos1->off - pos2->off); 6671} 6672 6673/* INSN is a store instruction. Try to record the store information 6674 in STINFO. Return false if the information isn't known. */ 6675 6676static bfd_boolean 6677fix_24k_record_store_info (struct fix_24k_store_info *stinfo, 6678 const struct mips_cl_insn *insn) 6679{ 6680 /* The instruction must have a known offset. */ 6681 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) 6682 return FALSE; 6683 6684 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; 6685 stinfo->align_to = fix_24k_align_to (insn->insn_mo); 6686 return TRUE; 6687} 6688 6689/* Return the number of nops that would be needed to work around the 24k 6690 "lost data on stores during refill" errata if instruction INSN 6691 immediately followed the 2 instructions described by HIST. 6692 Ignore hazards that are contained within the first IGNORE 6693 instructions of HIST. 6694 6695 Problem: The FSB (fetch store buffer) acts as an intermediate buffer 6696 for the data cache refills and store data. The following describes 6697 the scenario where the store data could be lost. 6698 6699 * A data cache miss, due to either a load or a store, causing fill 6700 data to be supplied by the memory subsystem 6701 * The first three doublewords of fill data are returned and written 6702 into the cache 6703 * A sequence of four stores occurs in consecutive cycles around the 6704 final doubleword of the fill: 6705 * Store A 6706 * Store B 6707 * Store C 6708 * Zero, One or more instructions 6709 * Store D 6710 6711 The four stores A-D must be to different doublewords of the line that 6712 is being filled. The fourth instruction in the sequence above permits 6713 the fill of the final doubleword to be transferred from the FSB into 6714 the cache. In the sequence above, the stores may be either integer 6715 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, 6716 swxc1, sdxc1, suxc1) stores, as long as the four stores are to 6717 different doublewords on the line. If the floating point unit is 6718 running in 1:2 mode, it is not possible to create the sequence above 6719 using only floating point store instructions. 6720 6721 In this case, the cache line being filled is incorrectly marked 6722 invalid, thereby losing the data from any store to the line that 6723 occurs between the original miss and the completion of the five 6724 cycle sequence shown above. 6725 6726 The workarounds are: 6727 6728 * Run the data cache in write-through mode. 6729 * Insert a non-store instruction between 6730 Store A and Store B or Store B and Store C. */ 6731 6732static int 6733nops_for_24k (int ignore, const struct mips_cl_insn *hist, 6734 const struct mips_cl_insn *insn) 6735{ 6736 struct fix_24k_store_info pos[3]; 6737 int align, i, base_offset; 6738 6739 if (ignore >= 2) 6740 return 0; 6741 6742 /* If the previous instruction wasn't a store, there's nothing to 6743 worry about. */ 6744 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6745 return 0; 6746 6747 /* If the instructions after the previous one are unknown, we have 6748 to assume the worst. */ 6749 if (!insn) 6750 return 1; 6751 6752 /* Check whether we are dealing with three consecutive stores. */ 6753 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 6754 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) 6755 return 0; 6756 6757 /* If we don't know the relationship between the store addresses, 6758 assume the worst. */ 6759 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) 6760 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) 6761 return 1; 6762 6763 if (!fix_24k_record_store_info (&pos[0], insn) 6764 || !fix_24k_record_store_info (&pos[1], &hist[0]) 6765 || !fix_24k_record_store_info (&pos[2], &hist[1])) 6766 return 1; 6767 6768 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); 6769 6770 /* Pick a value of ALIGN and X such that all offsets are adjusted by 6771 X bytes and such that the base register + X is known to be aligned 6772 to align bytes. */ 6773 6774 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) 6775 align = 8; 6776 else 6777 { 6778 align = pos[0].align_to; 6779 base_offset = pos[0].off; 6780 for (i = 1; i < 3; i++) 6781 if (align < pos[i].align_to) 6782 { 6783 align = pos[i].align_to; 6784 base_offset = pos[i].off; 6785 } 6786 for (i = 0; i < 3; i++) 6787 pos[i].off -= base_offset; 6788 } 6789 6790 pos[0].off &= ~align + 1; 6791 pos[1].off &= ~align + 1; 6792 pos[2].off &= ~align + 1; 6793 6794 /* If any two stores write to the same chunk, they also write to the 6795 same doubleword. The offsets are still sorted at this point. */ 6796 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) 6797 return 0; 6798 6799 /* A range of at least 9 bytes is needed for the stores to be in 6800 non-overlapping doublewords. */ 6801 if (pos[2].off - pos[0].off <= 8) 6802 return 0; 6803 6804 if (pos[2].off - pos[1].off >= 24 6805 || pos[1].off - pos[0].off >= 24 6806 || pos[2].off - pos[0].off >= 32) 6807 return 0; 6808 6809 return 1; 6810} 6811 6812/* Return the number of nops that would be needed if instruction INSN 6813 immediately followed the MAX_NOPS instructions given by HIST, 6814 where HIST[0] is the most recent instruction. Ignore hazards 6815 between INSN and the first IGNORE instructions in HIST. 6816 6817 If INSN is null, return the worse-case number of nops for any 6818 instruction. */ 6819 6820static int 6821nops_for_insn (int ignore, const struct mips_cl_insn *hist, 6822 const struct mips_cl_insn *insn) 6823{ 6824 int i, nops, tmp_nops; 6825 6826 nops = 0; 6827 for (i = ignore; i < MAX_DELAY_NOPS; i++) 6828 { 6829 tmp_nops = insns_between (hist + i, insn) - i; 6830 if (tmp_nops > nops) 6831 nops = tmp_nops; 6832 } 6833 6834 if (mips_fix_vr4130 && !mips_opts.micromips) 6835 { 6836 tmp_nops = nops_for_vr4130 (ignore, hist, insn); 6837 if (tmp_nops > nops) 6838 nops = tmp_nops; 6839 } 6840 6841 if (mips_fix_24k && !mips_opts.micromips) 6842 { 6843 tmp_nops = nops_for_24k (ignore, hist, insn); 6844 if (tmp_nops > nops) 6845 nops = tmp_nops; 6846 } 6847 6848 return nops; 6849} 6850 6851/* The variable arguments provide NUM_INSNS extra instructions that 6852 might be added to HIST. Return the largest number of nops that 6853 would be needed after the extended sequence, ignoring hazards 6854 in the first IGNORE instructions. */ 6855 6856static int 6857nops_for_sequence (int num_insns, int ignore, 6858 const struct mips_cl_insn *hist, ...) 6859{ 6860 va_list args; 6861 struct mips_cl_insn buffer[MAX_NOPS]; 6862 struct mips_cl_insn *cursor; 6863 int nops; 6864 6865 va_start (args, hist); 6866 cursor = buffer + num_insns; 6867 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); 6868 while (cursor > buffer) 6869 *--cursor = *va_arg (args, const struct mips_cl_insn *); 6870 6871 nops = nops_for_insn (ignore, buffer, NULL); 6872 va_end (args); 6873 return nops; 6874} 6875 6876/* Like nops_for_insn, but if INSN is a branch, take into account the 6877 worst-case delay for the branch target. */ 6878 6879static int 6880nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, 6881 const struct mips_cl_insn *insn) 6882{ 6883 int nops, tmp_nops; 6884 6885 nops = nops_for_insn (ignore, hist, insn); 6886 if (delayed_branch_p (insn)) 6887 { 6888 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, 6889 hist, insn, get_delay_slot_nop (insn)); 6890 if (tmp_nops > nops) 6891 nops = tmp_nops; 6892 } 6893 else if (compact_branch_p (insn)) 6894 { 6895 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); 6896 if (tmp_nops > nops) 6897 nops = tmp_nops; 6898 } 6899 return nops; 6900} 6901 6902/* Fix NOP issue: Replace nops by "or at,at,zero". */ 6903 6904static void 6905fix_loongson2f_nop (struct mips_cl_insn * ip) 6906{ 6907 gas_assert (!HAVE_CODE_COMPRESSION); 6908 if (strcmp (ip->insn_mo->name, "nop") == 0) 6909 ip->insn_opcode = LOONGSON2F_NOP_INSN; 6910} 6911 6912/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region 6913 jr target pc &= 'hffff_ffff_cfff_ffff. */ 6914 6915static void 6916fix_loongson2f_jump (struct mips_cl_insn * ip) 6917{ 6918 gas_assert (!HAVE_CODE_COMPRESSION); 6919 if (strcmp (ip->insn_mo->name, "j") == 0 6920 || strcmp (ip->insn_mo->name, "jr") == 0 6921 || strcmp (ip->insn_mo->name, "jalr") == 0) 6922 { 6923 int sreg; 6924 expressionS ep; 6925 6926 if (! mips_opts.at) 6927 return; 6928 6929 sreg = EXTRACT_OPERAND (0, RS, *ip); 6930 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) 6931 return; 6932 6933 ep.X_op = O_constant; 6934 ep.X_add_number = 0xcfff0000; 6935 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); 6936 ep.X_add_number = 0xffff; 6937 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); 6938 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); 6939 } 6940} 6941 6942static void 6943fix_loongson2f (struct mips_cl_insn * ip) 6944{ 6945 if (mips_fix_loongson2f_nop) 6946 fix_loongson2f_nop (ip); 6947 6948 if (mips_fix_loongson2f_jump) 6949 fix_loongson2f_jump (ip); 6950} 6951 6952/* Fix loongson3 llsc errata: Insert sync before ll/lld. */ 6953 6954static void 6955fix_loongson3_llsc (struct mips_cl_insn * ip) 6956{ 6957 gas_assert (!HAVE_CODE_COMPRESSION); 6958 6959 /* If is an local label and the insn is not sync, 6960 look forward that whether an branch between ll/sc jump to here 6961 if so, insert a sync. */ 6962 if (seg_info (now_seg)->label_list 6963 && S_IS_LOCAL (seg_info (now_seg)->label_list->label) 6964 && (strcmp (ip->insn_mo->name, "sync") != 0)) 6965 { 6966 const char *label_name = S_GET_NAME (seg_info (now_seg)->label_list->label); 6967 unsigned long lookback = ARRAY_SIZE (history); 6968 unsigned long i; 6969 6970 for (i = 0; i < lookback; i++) 6971 { 6972 if (streq (history[i].insn_mo->name, "ll") 6973 || streq (history[i].insn_mo->name, "lld")) 6974 break; 6975 6976 if (streq (history[i].insn_mo->name, "sc") 6977 || streq (history[i].insn_mo->name, "scd")) 6978 { 6979 unsigned long j; 6980 6981 for (j = i + 1; j < lookback; j++) 6982 { 6983 if (streq (history[i].insn_mo->name, "ll") 6984 || streq (history[i].insn_mo->name, "lld")) 6985 break; 6986 6987 if (delayed_branch_p (&history[j])) 6988 { 6989 if (streq (history[j].target, label_name)) 6990 { 6991 add_fixed_insn (&sync_insn); 6992 insert_into_history (0, 1, &sync_insn); 6993 i = lookback; 6994 break; 6995 } 6996 } 6997 } 6998 } 6999 } 7000 } 7001 /* If we find a sc, we look forward to look for an branch insn, 7002 and see whether it jump back and out of ll/sc. */ 7003 else if (streq(ip->insn_mo->name, "sc") || streq(ip->insn_mo->name, "scd")) 7004 { 7005 unsigned long lookback = ARRAY_SIZE (history) - 1; 7006 unsigned long i; 7007 7008 for (i = 0; i < lookback; i++) 7009 { 7010 if (streq (history[i].insn_mo->name, "ll") 7011 || streq (history[i].insn_mo->name, "lld")) 7012 break; 7013 7014 if (delayed_branch_p (&history[i])) 7015 { 7016 unsigned long j; 7017 7018 for (j = i + 1; j < lookback; j++) 7019 { 7020 if (streq (history[j].insn_mo->name, "ll") 7021 || streq (history[i].insn_mo->name, "lld")) 7022 break; 7023 } 7024 7025 for (; j < lookback; j++) 7026 { 7027 if (history[j].label[0] != '\0' 7028 && streq (history[j].label, history[i].target) 7029 && strcmp (history[j+1].insn_mo->name, "sync") != 0) 7030 { 7031 add_fixed_insn (&sync_insn); 7032 insert_into_history (++j, 1, &sync_insn); 7033 } 7034 } 7035 } 7036 } 7037 } 7038 7039 /* Skip if there is a sync before ll/lld. */ 7040 if ((strcmp (ip->insn_mo->name, "ll") == 0 7041 || strcmp (ip->insn_mo->name, "lld") == 0) 7042 && (strcmp (history[0].insn_mo->name, "sync") != 0)) 7043 { 7044 add_fixed_insn (&sync_insn); 7045 insert_into_history (0, 1, &sync_insn); 7046 } 7047} 7048 7049/* IP is a branch that has a delay slot, and we need to fill it 7050 automatically. Return true if we can do that by swapping IP 7051 with the previous instruction. 7052 ADDRESS_EXPR is an operand of the instruction to be used with 7053 RELOC_TYPE. */ 7054 7055static bfd_boolean 7056can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, 7057 bfd_reloc_code_real_type *reloc_type) 7058{ 7059 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; 7060 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; 7061 unsigned int fpr_read, prev_fpr_write; 7062 7063 /* -O2 and above is required for this optimization. */ 7064 if (mips_optimize < 2) 7065 return FALSE; 7066 7067 /* If we have seen .set volatile or .set nomove, don't optimize. */ 7068 if (mips_opts.nomove) 7069 return FALSE; 7070 7071 /* We can't swap if the previous instruction's position is fixed. */ 7072 if (history[0].fixed_p) 7073 return FALSE; 7074 7075 /* If the previous previous insn was in a .set noreorder, we can't 7076 swap. Actually, the MIPS assembler will swap in this situation. 7077 However, gcc configured -with-gnu-as will generate code like 7078 7079 .set noreorder 7080 lw $4,XXX 7081 .set reorder 7082 INSN 7083 bne $4,$0,foo 7084 7085 in which we can not swap the bne and INSN. If gcc is not configured 7086 -with-gnu-as, it does not output the .set pseudo-ops. */ 7087 if (history[1].noreorder_p) 7088 return FALSE; 7089 7090 /* If the previous instruction had a fixup in mips16 mode, we can not swap. 7091 This means that the previous instruction was a 4-byte one anyhow. */ 7092 if (mips_opts.mips16 && history[0].fixp[0]) 7093 return FALSE; 7094 7095 if (mips_fix_loongson2f) 7096 fix_loongson2f (ip); 7097 if (mips_trap_zero_jump) 7098 trap_zero_jump (ip); 7099 7100 /* If the branch is itself the target of a branch, we can not swap. 7101 We cheat on this; all we check for is whether there is a label on 7102 this instruction. If there are any branches to anything other than 7103 a label, users must use .set noreorder. */ 7104 if (seg_info (now_seg)->label_list) 7105 return FALSE; 7106 7107 /* If the previous instruction is in a variant frag other than this 7108 branch's one, we cannot do the swap. This does not apply to 7109 MIPS16 code, which uses variant frags for different purposes. */ 7110 if (!mips_opts.mips16 7111 && history[0].frag 7112 && history[0].frag->fr_type == rs_machine_dependent) 7113 return FALSE; 7114 7115 /* We do not swap with instructions that cannot architecturally 7116 be placed in a branch delay slot, such as SYNC or ERET. We 7117 also refrain from swapping with a trap instruction, since it 7118 complicates trap handlers to have the trap instruction be in 7119 a delay slot. */ 7120 prev_pinfo = history[0].insn_mo->pinfo; 7121 if (prev_pinfo & INSN_NO_DELAY_SLOT) 7122 return FALSE; 7123 7124 /* Check for conflicts between the branch and the instructions 7125 before the candidate delay slot. */ 7126 if (nops_for_insn (0, history + 1, ip) > 0) 7127 return FALSE; 7128 7129 /* Check for conflicts between the swapped sequence and the 7130 target of the branch. */ 7131 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) 7132 return FALSE; 7133 7134 /* If the branch reads a register that the previous 7135 instruction sets, we can not swap. */ 7136 gpr_read = gpr_read_mask (ip); 7137 prev_gpr_write = gpr_write_mask (&history[0]); 7138 if (gpr_read & prev_gpr_write) 7139 return FALSE; 7140 7141 fpr_read = fpr_read_mask (ip); 7142 prev_fpr_write = fpr_write_mask (&history[0]); 7143 if (fpr_read & prev_fpr_write) 7144 return FALSE; 7145 7146 /* If the branch writes a register that the previous 7147 instruction sets, we can not swap. */ 7148 gpr_write = gpr_write_mask (ip); 7149 if (gpr_write & prev_gpr_write) 7150 return FALSE; 7151 7152 /* If the branch writes a register that the previous 7153 instruction reads, we can not swap. */ 7154 prev_gpr_read = gpr_read_mask (&history[0]); 7155 if (gpr_write & prev_gpr_read) 7156 return FALSE; 7157 7158 /* If one instruction sets a condition code and the 7159 other one uses a condition code, we can not swap. */ 7160 pinfo = ip->insn_mo->pinfo; 7161 if ((pinfo & INSN_READ_COND_CODE) 7162 && (prev_pinfo & INSN_WRITE_COND_CODE)) 7163 return FALSE; 7164 if ((pinfo & INSN_WRITE_COND_CODE) 7165 && (prev_pinfo & INSN_READ_COND_CODE)) 7166 return FALSE; 7167 7168 /* If the previous instruction uses the PC, we can not swap. */ 7169 prev_pinfo2 = history[0].insn_mo->pinfo2; 7170 if (prev_pinfo2 & INSN2_READ_PC) 7171 return FALSE; 7172 7173 /* If the previous instruction has an incorrect size for a fixed 7174 branch delay slot in microMIPS mode, we cannot swap. */ 7175 pinfo2 = ip->insn_mo->pinfo2; 7176 if (mips_opts.micromips 7177 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) 7178 && insn_length (history) != 2) 7179 return FALSE; 7180 if (mips_opts.micromips 7181 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) 7182 && insn_length (history) != 4) 7183 return FALSE; 7184 7185 /* On the R5900 short loops need to be fixed by inserting a NOP in the 7186 branch delay slot. 7187 7188 The short loop bug under certain conditions causes loops to execute 7189 only once or twice. We must ensure that the assembler never 7190 generates loops that satisfy all of the following conditions: 7191 7192 - a loop consists of less than or equal to six instructions 7193 (including the branch delay slot); 7194 - a loop contains only one conditional branch instruction at the end 7195 of the loop; 7196 - a loop does not contain any other branch or jump instructions; 7197 - a branch delay slot of the loop is not NOP (EE 2.9 or later). 7198 7199 We need to do this because of a hardware bug in the R5900 chip. */ 7200 if (mips_fix_r5900 7201 /* Check if instruction has a parameter, ignore "j $31". */ 7202 && (address_expr != NULL) 7203 /* Parameter must be 16 bit. */ 7204 && (*reloc_type == BFD_RELOC_16_PCREL_S2) 7205 /* Branch to same segment. */ 7206 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) 7207 /* Branch to same code fragment. */ 7208 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) 7209 /* Can only calculate branch offset if value is known. */ 7210 && symbol_constant_p (address_expr->X_add_symbol) 7211 /* Check if branch is really conditional. */ 7212 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 7213 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ 7214 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 7215 { 7216 int distance; 7217 /* Check if loop is shorter than or equal to 6 instructions 7218 including branch and delay slot. */ 7219 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); 7220 if (distance <= 20) 7221 { 7222 int i; 7223 int rv; 7224 7225 rv = FALSE; 7226 /* When the loop includes branches or jumps, 7227 it is not a short loop. */ 7228 for (i = 0; i < (distance / 4); i++) 7229 { 7230 if ((history[i].cleared_p) 7231 || delayed_branch_p (&history[i])) 7232 { 7233 rv = TRUE; 7234 break; 7235 } 7236 } 7237 if (!rv) 7238 { 7239 /* Insert nop after branch to fix short loop. */ 7240 return FALSE; 7241 } 7242 } 7243 } 7244 7245 return TRUE; 7246} 7247 7248/* Fix jump through register issue on loongson2f processor for kernel code: 7249 force a BTB clear before the jump to prevent it from being incorrectly 7250 prefetched by the branch prediction engine. */ 7251 7252static void 7253macro_build_jrpatch (expressionS *ep, unsigned int sreg) 7254{ 7255 if (!mips_fix_loongson2f_btb) 7256 return; 7257 7258 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == AT) 7259 return; 7260 7261 if (!mips_opts.at) 7262 { 7263 as_warn (_("unable to apply loongson2f BTB workaround when .set noat")); 7264 return; 7265 } 7266 7267 /* li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE */ 7268 ep->X_op = O_constant; 7269 ep->X_add_number = 3; 7270 macro_build (ep, "ori", "t,r,i", AT, ZERO, BFD_RELOC_LO16); 7271 7272 /* dmtc0 $at, COP_0_DIAG */ 7273 macro_build (NULL, "dmtc0", "t,G", AT, 22); 7274 7275 /* Hide these two instructions to avoid getting a ``macro expanded into 7276 multiple instructions'' warning. */ 7277 if (mips_relax.sequence != 2) { 7278 mips_macro_warning.sizes[0] -= 2 * 4; 7279 mips_macro_warning.insns[0] -= 2; 7280 } 7281 if (mips_relax.sequence != 1) { 7282 mips_macro_warning.sizes[1] -= 2 * 4; 7283 mips_macro_warning.insns[1] -= 2; 7284 } 7285} 7286 7287/* Decide how we should add IP to the instruction stream. 7288 ADDRESS_EXPR is an operand of the instruction to be used with 7289 RELOC_TYPE. */ 7290 7291static enum append_method 7292get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, 7293 bfd_reloc_code_real_type *reloc_type) 7294{ 7295 /* The relaxed version of a macro sequence must be inherently 7296 hazard-free. */ 7297 if (mips_relax.sequence == 2) 7298 return APPEND_ADD; 7299 7300 /* We must not dabble with instructions in a ".set noreorder" block. */ 7301 if (mips_opts.noreorder) 7302 return APPEND_ADD; 7303 7304 /* Otherwise, it's our responsibility to fill branch delay slots. */ 7305 if (delayed_branch_p (ip)) 7306 { 7307 if (!branch_likely_p (ip) 7308 && can_swap_branch_p (ip, address_expr, reloc_type)) 7309 return APPEND_SWAP; 7310 7311 if (mips_opts.mips16 7312 && ISA_SUPPORTS_MIPS16E 7313 && gpr_read_mask (ip) != 0) 7314 return APPEND_ADD_COMPACT; 7315 7316 if (mips_opts.micromips 7317 && ((ip->insn_opcode & 0xffe0) == 0x4580 7318 || (!forced_insn_length 7319 && ((ip->insn_opcode & 0xfc00) == 0xcc00 7320 || (ip->insn_opcode & 0xdc00) == 0x8c00)) 7321 || (ip->insn_opcode & 0xdfe00000) == 0x94000000 7322 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) 7323 return APPEND_ADD_COMPACT; 7324 7325 return APPEND_ADD_WITH_NOP; 7326 } 7327 7328 return APPEND_ADD; 7329} 7330 7331/* IP is an instruction whose opcode we have just changed, END points 7332 to the end of the opcode table processed. Point IP->insn_mo to the 7333 new opcode's definition. */ 7334 7335static void 7336find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) 7337{ 7338 const struct mips_opcode *mo; 7339 7340 for (mo = ip->insn_mo; mo < end; mo++) 7341 if (mo->pinfo != INSN_MACRO 7342 && (ip->insn_opcode & mo->mask) == mo->match) 7343 { 7344 ip->insn_mo = mo; 7345 return; 7346 } 7347 abort (); 7348} 7349 7350/* IP is a MIPS16 instruction whose opcode we have just changed. 7351 Point IP->insn_mo to the new opcode's definition. */ 7352 7353static void 7354find_altered_mips16_opcode (struct mips_cl_insn *ip) 7355{ 7356 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); 7357} 7358 7359/* IP is a microMIPS instruction whose opcode we have just changed. 7360 Point IP->insn_mo to the new opcode's definition. */ 7361 7362static void 7363find_altered_micromips_opcode (struct mips_cl_insn *ip) 7364{ 7365 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); 7366} 7367 7368/* For microMIPS macros, we need to generate a local number label 7369 as the target of branches. */ 7370#define MICROMIPS_LABEL_CHAR '\037' 7371static unsigned long micromips_target_label; 7372static char micromips_target_name[32]; 7373 7374static char * 7375micromips_label_name (void) 7376{ 7377 char *p = micromips_target_name; 7378 char symbol_name_temporary[24]; 7379 unsigned long l; 7380 int i; 7381 7382 if (*p) 7383 return p; 7384 7385 i = 0; 7386 l = micromips_target_label; 7387#ifdef LOCAL_LABEL_PREFIX 7388 *p++ = LOCAL_LABEL_PREFIX; 7389#endif 7390 *p++ = 'L'; 7391 *p++ = MICROMIPS_LABEL_CHAR; 7392 do 7393 { 7394 symbol_name_temporary[i++] = l % 10 + '0'; 7395 l /= 10; 7396 } 7397 while (l != 0); 7398 while (i > 0) 7399 *p++ = symbol_name_temporary[--i]; 7400 *p = '\0'; 7401 7402 return micromips_target_name; 7403} 7404 7405static void 7406micromips_label_expr (expressionS *label_expr) 7407{ 7408 label_expr->X_op = O_symbol; 7409 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); 7410 label_expr->X_add_number = 0; 7411} 7412 7413static void 7414micromips_label_inc (void) 7415{ 7416 micromips_target_label++; 7417 *micromips_target_name = '\0'; 7418} 7419 7420static void 7421micromips_add_label (void) 7422{ 7423 symbolS *s; 7424 7425 s = colon (micromips_label_name ()); 7426 micromips_label_inc (); 7427 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); 7428} 7429 7430/* If assembling microMIPS code, then return the microMIPS reloc 7431 corresponding to the requested one if any. Otherwise return 7432 the reloc unchanged. */ 7433 7434static bfd_reloc_code_real_type 7435micromips_map_reloc (bfd_reloc_code_real_type reloc) 7436{ 7437 static const bfd_reloc_code_real_type relocs[][2] = 7438 { 7439 /* Keep sorted incrementally by the left-hand key. */ 7440 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, 7441 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, 7442 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, 7443 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, 7444 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, 7445 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, 7446 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, 7447 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, 7448 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, 7449 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, 7450 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, 7451 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, 7452 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, 7453 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, 7454 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, 7455 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, 7456 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, 7457 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, 7458 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, 7459 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, 7460 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, 7461 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, 7462 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, 7463 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, 7464 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, 7465 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, 7466 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } 7467 }; 7468 bfd_reloc_code_real_type r; 7469 size_t i; 7470 7471 if (!mips_opts.micromips) 7472 return reloc; 7473 for (i = 0; i < ARRAY_SIZE (relocs); i++) 7474 { 7475 r = relocs[i][0]; 7476 if (r > reloc) 7477 return reloc; 7478 if (r == reloc) 7479 return relocs[i][1]; 7480 } 7481 return reloc; 7482} 7483 7484/* Try to resolve relocation RELOC against constant OPERAND at assembly time. 7485 Return true on success, storing the resolved value in RESULT. */ 7486 7487static bfd_boolean 7488calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, 7489 offsetT *result) 7490{ 7491 switch (reloc) 7492 { 7493 case BFD_RELOC_MIPS_HIGHEST: 7494 case BFD_RELOC_MICROMIPS_HIGHEST: 7495 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; 7496 return TRUE; 7497 7498 case BFD_RELOC_MIPS_HIGHER: 7499 case BFD_RELOC_MICROMIPS_HIGHER: 7500 *result = ((operand + 0x80008000ull) >> 32) & 0xffff; 7501 return TRUE; 7502 7503 case BFD_RELOC_HI16_S: 7504 case BFD_RELOC_HI16_S_PCREL: 7505 case BFD_RELOC_MICROMIPS_HI16_S: 7506 case BFD_RELOC_MIPS16_HI16_S: 7507 *result = ((operand + 0x8000) >> 16) & 0xffff; 7508 return TRUE; 7509 7510 case BFD_RELOC_HI16: 7511 case BFD_RELOC_MICROMIPS_HI16: 7512 case BFD_RELOC_MIPS16_HI16: 7513 *result = (operand >> 16) & 0xffff; 7514 return TRUE; 7515 7516 case BFD_RELOC_LO16: 7517 case BFD_RELOC_LO16_PCREL: 7518 case BFD_RELOC_MICROMIPS_LO16: 7519 case BFD_RELOC_MIPS16_LO16: 7520 *result = operand & 0xffff; 7521 return TRUE; 7522 7523 case BFD_RELOC_UNUSED: 7524 *result = operand; 7525 return TRUE; 7526 7527 default: 7528 return FALSE; 7529 } 7530} 7531 7532/* Output an instruction. IP is the instruction information. 7533 ADDRESS_EXPR is an operand of the instruction to be used with 7534 RELOC_TYPE. EXPANSIONP is true if the instruction is part of 7535 a macro expansion. */ 7536 7537static void 7538append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 7539 bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) 7540{ 7541 unsigned long prev_pinfo2, pinfo; 7542 bfd_boolean relaxed_branch = FALSE; 7543 enum append_method method; 7544 bfd_boolean relax32; 7545 int branch_disp; 7546 7547 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) 7548 fix_loongson2f (ip); 7549 7550 ip->target[0] = '\0'; 7551 if (offset_expr.X_op == O_symbol) 7552 strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15); 7553 ip->label[0] = '\0'; 7554 if (seg_info (now_seg)->label_list) 7555 strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15); 7556 if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION) 7557 fix_loongson3_llsc (ip); 7558 7559 file_ase_mips16 |= mips_opts.mips16; 7560 file_ase_micromips |= mips_opts.micromips; 7561 7562 prev_pinfo2 = history[0].insn_mo->pinfo2; 7563 pinfo = ip->insn_mo->pinfo; 7564 7565 /* Don't raise alarm about `nods' frags as they'll fill in the right 7566 kind of nop in relaxation if required. */ 7567 if (mips_opts.micromips 7568 && !expansionp 7569 && !(history[0].frag 7570 && history[0].frag->fr_type == rs_machine_dependent 7571 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) 7572 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) 7573 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 7574 && micromips_insn_length (ip->insn_mo) != 2) 7575 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 7576 && micromips_insn_length (ip->insn_mo) != 4))) 7577 as_warn (_("wrong size instruction in a %u-bit branch delay slot"), 7578 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); 7579 7580 if (address_expr == NULL) 7581 ip->complete_p = 1; 7582 else if (reloc_type[0] <= BFD_RELOC_UNUSED 7583 && reloc_type[1] == BFD_RELOC_UNUSED 7584 && reloc_type[2] == BFD_RELOC_UNUSED 7585 && address_expr->X_op == O_constant) 7586 { 7587 switch (*reloc_type) 7588 { 7589 case BFD_RELOC_MIPS_JMP: 7590 { 7591 int shift; 7592 7593 /* Shift is 2, unusually, for microMIPS JALX. */ 7594 shift = (mips_opts.micromips 7595 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; 7596 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7597 as_bad (_("jump to misaligned address (0x%lx)"), 7598 (unsigned long) address_expr->X_add_number); 7599 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7600 & 0x3ffffff); 7601 ip->complete_p = 1; 7602 } 7603 break; 7604 7605 case BFD_RELOC_MIPS16_JMP: 7606 if ((address_expr->X_add_number & 3) != 0) 7607 as_bad (_("jump to misaligned address (0x%lx)"), 7608 (unsigned long) address_expr->X_add_number); 7609 ip->insn_opcode |= 7610 (((address_expr->X_add_number & 0x7c0000) << 3) 7611 | ((address_expr->X_add_number & 0xf800000) >> 7) 7612 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 7613 ip->complete_p = 1; 7614 break; 7615 7616 case BFD_RELOC_16_PCREL_S2: 7617 { 7618 int shift; 7619 7620 shift = mips_opts.micromips ? 1 : 2; 7621 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7622 as_bad (_("branch to misaligned address (0x%lx)"), 7623 (unsigned long) address_expr->X_add_number); 7624 if (!mips_relax_branch) 7625 { 7626 if ((address_expr->X_add_number + (1 << (shift + 15))) 7627 & ~((1 << (shift + 16)) - 1)) 7628 as_bad (_("branch address range overflow (0x%lx)"), 7629 (unsigned long) address_expr->X_add_number); 7630 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7631 & 0xffff); 7632 } 7633 } 7634 break; 7635 7636 case BFD_RELOC_MIPS_21_PCREL_S2: 7637 { 7638 int shift; 7639 7640 shift = 2; 7641 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7642 as_bad (_("branch to misaligned address (0x%lx)"), 7643 (unsigned long) address_expr->X_add_number); 7644 if ((address_expr->X_add_number + (1 << (shift + 20))) 7645 & ~((1 << (shift + 21)) - 1)) 7646 as_bad (_("branch address range overflow (0x%lx)"), 7647 (unsigned long) address_expr->X_add_number); 7648 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7649 & 0x1fffff); 7650 } 7651 break; 7652 7653 case BFD_RELOC_MIPS_26_PCREL_S2: 7654 { 7655 int shift; 7656 7657 shift = 2; 7658 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) 7659 as_bad (_("branch to misaligned address (0x%lx)"), 7660 (unsigned long) address_expr->X_add_number); 7661 if ((address_expr->X_add_number + (1 << (shift + 25))) 7662 & ~((1 << (shift + 26)) - 1)) 7663 as_bad (_("branch address range overflow (0x%lx)"), 7664 (unsigned long) address_expr->X_add_number); 7665 ip->insn_opcode |= ((address_expr->X_add_number >> shift) 7666 & 0x3ffffff); 7667 } 7668 break; 7669 7670 default: 7671 { 7672 offsetT value; 7673 7674 if (calculate_reloc (*reloc_type, address_expr->X_add_number, 7675 &value)) 7676 { 7677 ip->insn_opcode |= value & 0xffff; 7678 ip->complete_p = 1; 7679 } 7680 } 7681 break; 7682 } 7683 } 7684 7685 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 7686 { 7687 /* There are a lot of optimizations we could do that we don't. 7688 In particular, we do not, in general, reorder instructions. 7689 If you use gcc with optimization, it will reorder 7690 instructions and generally do much more optimization then we 7691 do here; repeating all that work in the assembler would only 7692 benefit hand written assembly code, and does not seem worth 7693 it. */ 7694 int nops = (mips_optimize == 0 7695 ? nops_for_insn (0, history, NULL) 7696 : nops_for_insn_or_target (0, history, ip)); 7697 if (nops > 0) 7698 { 7699 fragS *old_frag; 7700 unsigned long old_frag_offset; 7701 int i; 7702 7703 old_frag = frag_now; 7704 old_frag_offset = frag_now_fix (); 7705 7706 for (i = 0; i < nops; i++) 7707 add_fixed_insn (NOP_INSN); 7708 insert_into_history (0, nops, NOP_INSN); 7709 7710 if (listing) 7711 { 7712 listing_prev_line (); 7713 /* We may be at the start of a variant frag. In case we 7714 are, make sure there is enough space for the frag 7715 after the frags created by listing_prev_line. The 7716 argument to frag_grow here must be at least as large 7717 as the argument to all other calls to frag_grow in 7718 this file. We don't have to worry about being in the 7719 middle of a variant frag, because the variants insert 7720 all needed nop instructions themselves. */ 7721 frag_grow (40); 7722 } 7723 7724 mips_move_text_labels (); 7725 7726#ifndef NO_ECOFF_DEBUGGING 7727 if (ECOFF_DEBUGGING) 7728 ecoff_fix_loc (old_frag, old_frag_offset); 7729#endif 7730 } 7731 } 7732 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) 7733 { 7734 int nops; 7735 7736 /* Work out how many nops in prev_nop_frag are needed by IP, 7737 ignoring hazards generated by the first prev_nop_frag_since 7738 instructions. */ 7739 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); 7740 gas_assert (nops <= prev_nop_frag_holds); 7741 7742 /* Enforce NOPS as a minimum. */ 7743 if (nops > prev_nop_frag_required) 7744 prev_nop_frag_required = nops; 7745 7746 if (prev_nop_frag_holds == prev_nop_frag_required) 7747 { 7748 /* Settle for the current number of nops. Update the history 7749 accordingly (for the benefit of any future .set reorder code). */ 7750 prev_nop_frag = NULL; 7751 insert_into_history (prev_nop_frag_since, 7752 prev_nop_frag_holds, NOP_INSN); 7753 } 7754 else 7755 { 7756 /* Allow this instruction to replace one of the nops that was 7757 tentatively added to prev_nop_frag. */ 7758 prev_nop_frag->fr_fix -= NOP_INSN_SIZE; 7759 prev_nop_frag_holds--; 7760 prev_nop_frag_since++; 7761 } 7762 } 7763 7764 method = get_append_method (ip, address_expr, reloc_type); 7765 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; 7766 7767 dwarf2_emit_insn (0); 7768 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, 7769 so "move" the instruction address accordingly. 7770 7771 Also, it doesn't seem appropriate for the assembler to reorder .loc 7772 entries. If this instruction is a branch that we are going to swap 7773 with the previous instruction, the two instructions should be 7774 treated as a unit, and the debug information for both instructions 7775 should refer to the start of the branch sequence. Using the 7776 current position is certainly wrong when swapping a 32-bit branch 7777 and a 16-bit delay slot, since the current position would then be 7778 in the middle of a branch. */ 7779 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); 7780 7781 relax32 = (mips_relax_branch 7782 /* Don't try branch relaxation within .set nomacro, or within 7783 .set noat if we use $at for PIC computations. If it turns 7784 out that the branch was out-of-range, we'll get an error. */ 7785 && !mips_opts.warn_about_macros 7786 && (mips_opts.at || mips_pic == NO_PIC) 7787 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F 7788 as they have no complementing branches. */ 7789 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); 7790 7791 if (!HAVE_CODE_COMPRESSION 7792 && address_expr 7793 && relax32 7794 && *reloc_type == BFD_RELOC_16_PCREL_S2 7795 && delayed_branch_p (ip)) 7796 { 7797 relaxed_branch = TRUE; 7798 add_relaxed_insn (ip, (relaxed_branch_length 7799 (NULL, NULL, 7800 uncond_branch_p (ip) ? -1 7801 : branch_likely_p (ip) ? 1 7802 : 0)), 4, 7803 RELAX_BRANCH_ENCODE 7804 (AT, mips_pic != NO_PIC, 7805 uncond_branch_p (ip), 7806 branch_likely_p (ip), 7807 pinfo & INSN_WRITE_GPR_31, 7808 0), 7809 address_expr->X_add_symbol, 7810 address_expr->X_add_number); 7811 *reloc_type = BFD_RELOC_UNUSED; 7812 } 7813 else if (mips_opts.micromips 7814 && address_expr 7815 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) 7816 || *reloc_type > BFD_RELOC_UNUSED) 7817 && (delayed_branch_p (ip) || compact_branch_p (ip)) 7818 /* Don't try branch relaxation when users specify 7819 16-bit/32-bit instructions. */ 7820 && !forced_insn_length) 7821 { 7822 bfd_boolean relax16 = (method != APPEND_ADD_COMPACT 7823 && *reloc_type > BFD_RELOC_UNUSED); 7824 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; 7825 int uncond = uncond_branch_p (ip) ? -1 : 0; 7826 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; 7827 int nods = method == APPEND_ADD_WITH_NOP; 7828 int al = pinfo & INSN_WRITE_GPR_31; 7829 int length32 = nods ? 8 : 4; 7830 7831 gas_assert (address_expr != NULL); 7832 gas_assert (!mips_relax.sequence); 7833 7834 relaxed_branch = TRUE; 7835 if (nods) 7836 method = APPEND_ADD; 7837 if (relax32) 7838 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); 7839 add_relaxed_insn (ip, length32, relax16 ? 2 : 4, 7840 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, 7841 mips_pic != NO_PIC, 7842 uncond, compact, al, nods, 7843 relax32, 0, 0), 7844 address_expr->X_add_symbol, 7845 address_expr->X_add_number); 7846 *reloc_type = BFD_RELOC_UNUSED; 7847 } 7848 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) 7849 { 7850 bfd_boolean require_unextended; 7851 bfd_boolean require_extended; 7852 symbolS *symbol; 7853 offsetT offset; 7854 7855 if (forced_insn_length != 0) 7856 { 7857 require_unextended = forced_insn_length == 2; 7858 require_extended = forced_insn_length == 4; 7859 } 7860 else 7861 { 7862 require_unextended = (mips_opts.noautoextend 7863 && !mips_opcode_32bit_p (ip->insn_mo)); 7864 require_extended = 0; 7865 } 7866 7867 /* We need to set up a variant frag. */ 7868 gas_assert (address_expr != NULL); 7869 /* Pass any `O_symbol' expression unchanged as an `expr_section' 7870 symbol created by `make_expr_symbol' may not get a necessary 7871 external relocation produced. */ 7872 if (address_expr->X_op == O_symbol) 7873 { 7874 symbol = address_expr->X_add_symbol; 7875 offset = address_expr->X_add_number; 7876 } 7877 else 7878 { 7879 symbol = make_expr_symbol (address_expr); 7880 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); 7881 offset = 0; 7882 } 7883 add_relaxed_insn (ip, 12, 0, 7884 RELAX_MIPS16_ENCODE 7885 (*reloc_type - BFD_RELOC_UNUSED, 7886 mips_opts.ase & ASE_MIPS16E2, 7887 mips_pic != NO_PIC, 7888 HAVE_32BIT_SYMBOLS, 7889 mips_opts.warn_about_macros, 7890 require_unextended, require_extended, 7891 delayed_branch_p (&history[0]), 7892 history[0].mips16_absolute_jump_p), 7893 symbol, offset); 7894 } 7895 else if (mips_opts.mips16 && insn_length (ip) == 2) 7896 { 7897 if (!delayed_branch_p (ip)) 7898 /* Make sure there is enough room to swap this instruction with 7899 a following jump instruction. */ 7900 frag_grow (6); 7901 add_fixed_insn (ip); 7902 } 7903 else 7904 { 7905 if (mips_opts.mips16 7906 && mips_opts.noreorder 7907 && delayed_branch_p (&history[0])) 7908 as_warn (_("extended instruction in delay slot")); 7909 7910 if (mips_relax.sequence) 7911 { 7912 /* If we've reached the end of this frag, turn it into a variant 7913 frag and record the information for the instructions we've 7914 written so far. */ 7915 if (frag_room () < 4) 7916 relax_close_frag (); 7917 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); 7918 } 7919 7920 if (mips_relax.sequence != 2) 7921 { 7922 if (mips_macro_warning.first_insn_sizes[0] == 0) 7923 mips_macro_warning.first_insn_sizes[0] = insn_length (ip); 7924 mips_macro_warning.sizes[0] += insn_length (ip); 7925 mips_macro_warning.insns[0]++; 7926 } 7927 if (mips_relax.sequence != 1) 7928 { 7929 if (mips_macro_warning.first_insn_sizes[1] == 0) 7930 mips_macro_warning.first_insn_sizes[1] = insn_length (ip); 7931 mips_macro_warning.sizes[1] += insn_length (ip); 7932 mips_macro_warning.insns[1]++; 7933 } 7934 7935 if (mips_opts.mips16) 7936 { 7937 ip->fixed_p = 1; 7938 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); 7939 } 7940 add_fixed_insn (ip); 7941 } 7942 7943 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) 7944 { 7945 bfd_reloc_code_real_type final_type[3]; 7946 reloc_howto_type *howto0; 7947 reloc_howto_type *howto; 7948 int i; 7949 7950 /* Perform any necessary conversion to microMIPS relocations 7951 and find out how many relocations there actually are. */ 7952 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) 7953 final_type[i] = micromips_map_reloc (reloc_type[i]); 7954 7955 /* In a compound relocation, it is the final (outermost) 7956 operator that determines the relocated field. */ 7957 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); 7958 if (!howto) 7959 abort (); 7960 7961 if (i > 1) 7962 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); 7963 ip->fixp[0] = fix_new_exp (ip->frag, ip->where, 7964 bfd_get_reloc_size (howto), 7965 address_expr, 7966 howto0 && howto0->pc_relative, 7967 final_type[0]); 7968 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ 7969 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; 7970 7971 /* Tag symbols that have a R_MIPS16_26 relocation against them. */ 7972 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) 7973 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; 7974 7975 /* These relocations can have an addend that won't fit in 7976 4 octets for 64bit assembly. */ 7977 if (GPR_SIZE == 64 7978 && ! howto->partial_inplace 7979 && (reloc_type[0] == BFD_RELOC_16 7980 || reloc_type[0] == BFD_RELOC_32 7981 || reloc_type[0] == BFD_RELOC_MIPS_JMP 7982 || reloc_type[0] == BFD_RELOC_GPREL16 7983 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 7984 || reloc_type[0] == BFD_RELOC_GPREL32 7985 || reloc_type[0] == BFD_RELOC_64 7986 || reloc_type[0] == BFD_RELOC_CTOR 7987 || reloc_type[0] == BFD_RELOC_MIPS_SUB 7988 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 7989 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 7990 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 7991 || reloc_type[0] == BFD_RELOC_MIPS_REL16 7992 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT 7993 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL 7994 || hi16_reloc_p (reloc_type[0]) 7995 || lo16_reloc_p (reloc_type[0]))) 7996 ip->fixp[0]->fx_no_overflow = 1; 7997 7998 /* These relocations can have an addend that won't fit in 2 octets. */ 7999 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 8000 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) 8001 ip->fixp[0]->fx_no_overflow = 1; 8002 8003 if (mips_relax.sequence) 8004 { 8005 if (mips_relax.first_fixup == 0) 8006 mips_relax.first_fixup = ip->fixp[0]; 8007 } 8008 else if (reloc_needs_lo_p (*reloc_type)) 8009 { 8010 struct mips_hi_fixup *hi_fixup; 8011 8012 /* Reuse the last entry if it already has a matching %lo. */ 8013 hi_fixup = mips_hi_fixup_list; 8014 if (hi_fixup == 0 8015 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 8016 { 8017 hi_fixup = XNEW (struct mips_hi_fixup); 8018 hi_fixup->next = mips_hi_fixup_list; 8019 mips_hi_fixup_list = hi_fixup; 8020 } 8021 hi_fixup->fixp = ip->fixp[0]; 8022 hi_fixup->seg = now_seg; 8023 } 8024 8025 /* Add fixups for the second and third relocations, if given. 8026 Note that the ABI allows the second relocation to be 8027 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 8028 moment we only use RSS_UNDEF, but we could add support 8029 for the others if it ever becomes necessary. */ 8030 for (i = 1; i < 3; i++) 8031 if (reloc_type[i] != BFD_RELOC_UNUSED) 8032 { 8033 ip->fixp[i] = fix_new (ip->frag, ip->where, 8034 ip->fixp[0]->fx_size, NULL, 0, 8035 FALSE, final_type[i]); 8036 8037 /* Use fx_tcbit to mark compound relocs. */ 8038 ip->fixp[0]->fx_tcbit = 1; 8039 ip->fixp[i]->fx_tcbit = 1; 8040 } 8041 } 8042 8043 /* Update the register mask information. */ 8044 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); 8045 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); 8046 8047 switch (method) 8048 { 8049 case APPEND_ADD: 8050 insert_into_history (0, 1, ip); 8051 break; 8052 8053 case APPEND_ADD_WITH_NOP: 8054 { 8055 struct mips_cl_insn *nop; 8056 8057 insert_into_history (0, 1, ip); 8058 nop = get_delay_slot_nop (ip); 8059 add_fixed_insn (nop); 8060 insert_into_history (0, 1, nop); 8061 if (mips_relax.sequence) 8062 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); 8063 } 8064 break; 8065 8066 case APPEND_ADD_COMPACT: 8067 /* Convert MIPS16 jr/jalr into a "compact" jump. */ 8068 if (mips_opts.mips16) 8069 { 8070 ip->insn_opcode |= 0x0080; 8071 find_altered_mips16_opcode (ip); 8072 } 8073 /* Convert microMIPS instructions. */ 8074 else if (mips_opts.micromips) 8075 { 8076 /* jr16->jrc */ 8077 if ((ip->insn_opcode & 0xffe0) == 0x4580) 8078 ip->insn_opcode |= 0x0020; 8079 /* b16->bc */ 8080 else if ((ip->insn_opcode & 0xfc00) == 0xcc00) 8081 ip->insn_opcode = 0x40e00000; 8082 /* beqz16->beqzc, bnez16->bnezc */ 8083 else if ((ip->insn_opcode & 0xdc00) == 0x8c00) 8084 { 8085 unsigned long regno; 8086 8087 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; 8088 regno &= MICROMIPSOP_MASK_MD; 8089 regno = micromips_to_32_reg_d_map[regno]; 8090 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) 8091 | (regno << MICROMIPSOP_SH_RS) 8092 | 0x40a00000) ^ 0x00400000; 8093 } 8094 /* beqz->beqzc, bnez->bnezc */ 8095 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) 8096 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) 8097 | ((ip->insn_opcode >> 7) & 0x00400000) 8098 | 0x40a00000) ^ 0x00400000; 8099 /* beq $0->beqzc, bne $0->bnezc */ 8100 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) 8101 ip->insn_opcode = (((ip->insn_opcode >> 8102 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) 8103 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) 8104 | ((ip->insn_opcode >> 7) & 0x00400000) 8105 | 0x40a00000) ^ 0x00400000; 8106 else 8107 abort (); 8108 find_altered_micromips_opcode (ip); 8109 } 8110 else 8111 abort (); 8112 install_insn (ip); 8113 insert_into_history (0, 1, ip); 8114 break; 8115 8116 case APPEND_SWAP: 8117 { 8118 struct mips_cl_insn delay = history[0]; 8119 8120 if (relaxed_branch || delay.frag != ip->frag) 8121 { 8122 /* Add the delay slot instruction to the end of the 8123 current frag and shrink the fixed part of the 8124 original frag. If the branch occupies the tail of 8125 the latter, move it backwards to cover the gap. */ 8126 delay.frag->fr_fix -= branch_disp; 8127 if (delay.frag == ip->frag) 8128 move_insn (ip, ip->frag, ip->where - branch_disp); 8129 add_fixed_insn (&delay); 8130 } 8131 else 8132 { 8133 /* If this is not a relaxed branch and we are in the 8134 same frag, then just swap the instructions. */ 8135 move_insn (ip, delay.frag, delay.where); 8136 move_insn (&delay, ip->frag, ip->where + insn_length (ip)); 8137 } 8138 history[0] = *ip; 8139 delay.fixed_p = 1; 8140 insert_into_history (0, 1, &delay); 8141 } 8142 break; 8143 } 8144 8145 /* If we have just completed an unconditional branch, clear the history. */ 8146 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) 8147 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) 8148 { 8149 unsigned int i; 8150 8151 mips_no_prev_insn (); 8152 8153 for (i = 0; i < ARRAY_SIZE (history); i++) 8154 history[i].cleared_p = 1; 8155 } 8156 8157 /* We need to emit a label at the end of branch-likely macros. */ 8158 if (emit_branch_likely_macro) 8159 { 8160 emit_branch_likely_macro = FALSE; 8161 micromips_add_label (); 8162 } 8163 8164 /* We just output an insn, so the next one doesn't have a label. */ 8165 mips_clear_insn_labels (); 8166} 8167 8168/* Forget that there was any previous instruction or label. 8169 When BRANCH is true, the branch history is also flushed. */ 8170 8171static void 8172mips_no_prev_insn (void) 8173{ 8174 prev_nop_frag = NULL; 8175 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); 8176 mips_clear_insn_labels (); 8177} 8178 8179/* This function must be called before we emit something other than 8180 instructions. It is like mips_no_prev_insn except that it inserts 8181 any NOPS that might be needed by previous instructions. */ 8182 8183void 8184mips_emit_delays (void) 8185{ 8186 if (! mips_opts.noreorder) 8187 { 8188 int nops = nops_for_insn (0, history, NULL); 8189 if (nops > 0) 8190 { 8191 while (nops-- > 0) 8192 add_fixed_insn (NOP_INSN); 8193 mips_move_text_labels (); 8194 } 8195 } 8196 mips_no_prev_insn (); 8197} 8198 8199/* Start a (possibly nested) noreorder block. */ 8200 8201static void 8202start_noreorder (void) 8203{ 8204 if (mips_opts.noreorder == 0) 8205 { 8206 unsigned int i; 8207 int nops; 8208 8209 /* None of the instructions before the .set noreorder can be moved. */ 8210 for (i = 0; i < ARRAY_SIZE (history); i++) 8211 history[i].fixed_p = 1; 8212 8213 /* Insert any nops that might be needed between the .set noreorder 8214 block and the previous instructions. We will later remove any 8215 nops that turn out not to be needed. */ 8216 nops = nops_for_insn (0, history, NULL); 8217 if (nops > 0) 8218 { 8219 if (mips_optimize != 0) 8220 { 8221 /* Record the frag which holds the nop instructions, so 8222 that we can remove them if we don't need them. */ 8223 frag_grow (nops * NOP_INSN_SIZE); 8224 prev_nop_frag = frag_now; 8225 prev_nop_frag_holds = nops; 8226 prev_nop_frag_required = 0; 8227 prev_nop_frag_since = 0; 8228 } 8229 8230 for (; nops > 0; --nops) 8231 add_fixed_insn (NOP_INSN); 8232 8233 /* Move on to a new frag, so that it is safe to simply 8234 decrease the size of prev_nop_frag. */ 8235 frag_wane (frag_now); 8236 frag_new (0); 8237 mips_move_text_labels (); 8238 } 8239 mips_mark_labels (); 8240 mips_clear_insn_labels (); 8241 } 8242 mips_opts.noreorder++; 8243 mips_any_noreorder = 1; 8244} 8245 8246/* End a nested noreorder block. */ 8247 8248static void 8249end_noreorder (void) 8250{ 8251 mips_opts.noreorder--; 8252 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) 8253 { 8254 /* Commit to inserting prev_nop_frag_required nops and go back to 8255 handling nop insertion the .set reorder way. */ 8256 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) 8257 * NOP_INSN_SIZE); 8258 insert_into_history (prev_nop_frag_since, 8259 prev_nop_frag_required, NOP_INSN); 8260 prev_nop_frag = NULL; 8261 } 8262} 8263 8264/* Sign-extend 32-bit mode constants that have bit 31 set and all 8265 higher bits unset. */ 8266 8267static void 8268normalize_constant_expr (expressionS *ex) 8269{ 8270 if (ex->X_op == O_constant 8271 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 8272 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 8273 - 0x80000000); 8274} 8275 8276/* Sign-extend 32-bit mode address offsets that have bit 31 set and 8277 all higher bits unset. */ 8278 8279static void 8280normalize_address_expr (expressionS *ex) 8281{ 8282 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) 8283 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) 8284 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 8285 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 8286 - 0x80000000); 8287} 8288 8289/* Try to match TOKENS against OPCODE, storing the result in INSN. 8290 Return true if the match was successful. 8291 8292 OPCODE_EXTRA is a value that should be ORed into the opcode 8293 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if 8294 there are more alternatives after OPCODE and SOFT_MATCH is 8295 as for mips_arg_info. */ 8296 8297static bfd_boolean 8298match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 8299 struct mips_operand_token *tokens, unsigned int opcode_extra, 8300 bfd_boolean lax_match, bfd_boolean complete_p) 8301{ 8302 const char *args; 8303 struct mips_arg_info arg; 8304 const struct mips_operand *operand; 8305 char c; 8306 8307 imm_expr.X_op = O_absent; 8308 offset_expr.X_op = O_absent; 8309 offset_reloc[0] = BFD_RELOC_UNUSED; 8310 offset_reloc[1] = BFD_RELOC_UNUSED; 8311 offset_reloc[2] = BFD_RELOC_UNUSED; 8312 8313 create_insn (insn, opcode); 8314 /* When no opcode suffix is specified, assume ".xyzw". */ 8315 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) 8316 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; 8317 else 8318 insn->insn_opcode |= opcode_extra; 8319 memset (&arg, 0, sizeof (arg)); 8320 arg.insn = insn; 8321 arg.token = tokens; 8322 arg.argnum = 1; 8323 arg.last_regno = ILLEGAL_REG; 8324 arg.dest_regno = ILLEGAL_REG; 8325 arg.lax_match = lax_match; 8326 for (args = opcode->args;; ++args) 8327 { 8328 if (arg.token->type == OT_END) 8329 { 8330 /* Handle unary instructions in which only one operand is given. 8331 The source is then the same as the destination. */ 8332 if (arg.opnum == 1 && *args == ',') 8333 { 8334 operand = (mips_opts.micromips 8335 ? decode_micromips_operand (args + 1) 8336 : decode_mips_operand (args + 1)); 8337 if (operand && mips_optional_operand_p (operand)) 8338 { 8339 arg.token = tokens; 8340 arg.argnum = 1; 8341 continue; 8342 } 8343 } 8344 8345 /* Treat elided base registers as $0. */ 8346 if (strcmp (args, "(b)") == 0) 8347 args += 3; 8348 8349 if (args[0] == '+') 8350 switch (args[1]) 8351 { 8352 case 'K': 8353 case 'N': 8354 /* The register suffix is optional. */ 8355 args += 2; 8356 break; 8357 } 8358 8359 /* Fail the match if there were too few operands. */ 8360 if (*args) 8361 return FALSE; 8362 8363 /* Successful match. */ 8364 if (!complete_p) 8365 return TRUE; 8366 clear_insn_error (); 8367 if (arg.dest_regno == arg.last_regno 8368 && strncmp (insn->insn_mo->name, "jalr", 4) == 0) 8369 { 8370 if (arg.opnum == 2) 8371 set_insn_error 8372 (0, _("source and destination must be different")); 8373 else if (arg.last_regno == 31) 8374 set_insn_error 8375 (0, _("a destination register must be supplied")); 8376 } 8377 else if (arg.last_regno == 31 8378 && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 8379 || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) 8380 set_insn_error (0, _("the source register must not be $31")); 8381 check_completed_insn (&arg); 8382 return TRUE; 8383 } 8384 8385 /* Fail the match if the line has too many operands. */ 8386 if (*args == 0) 8387 return FALSE; 8388 8389 /* Handle characters that need to match exactly. */ 8390 if (*args == '(' || *args == ')' || *args == ',') 8391 { 8392 if (match_char (&arg, *args)) 8393 continue; 8394 return FALSE; 8395 } 8396 if (*args == '#') 8397 { 8398 ++args; 8399 if (arg.token->type == OT_DOUBLE_CHAR 8400 && arg.token->u.ch == *args) 8401 { 8402 ++arg.token; 8403 continue; 8404 } 8405 return FALSE; 8406 } 8407 8408 /* Handle special macro operands. Work out the properties of 8409 other operands. */ 8410 arg.opnum += 1; 8411 switch (*args) 8412 { 8413 case '-': 8414 switch (args[1]) 8415 { 8416 case 'A': 8417 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; 8418 break; 8419 8420 case 'B': 8421 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; 8422 break; 8423 } 8424 break; 8425 8426 case '+': 8427 switch (args[1]) 8428 { 8429 case 'i': 8430 *offset_reloc = BFD_RELOC_MIPS_JMP; 8431 break; 8432 8433 case '\'': 8434 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; 8435 break; 8436 8437 case '\"': 8438 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; 8439 break; 8440 } 8441 break; 8442 8443 case 'I': 8444 if (!match_const_int (&arg, &imm_expr.X_add_number)) 8445 return FALSE; 8446 imm_expr.X_op = O_constant; 8447 if (GPR_SIZE == 32) 8448 normalize_constant_expr (&imm_expr); 8449 continue; 8450 8451 case 'A': 8452 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 8453 { 8454 /* Assume that the offset has been elided and that what 8455 we saw was a base register. The match will fail later 8456 if that assumption turns out to be wrong. */ 8457 offset_expr.X_op = O_constant; 8458 offset_expr.X_add_number = 0; 8459 } 8460 else 8461 { 8462 if (!match_expression (&arg, &offset_expr, offset_reloc)) 8463 return FALSE; 8464 normalize_address_expr (&offset_expr); 8465 } 8466 continue; 8467 8468 case 'F': 8469 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8470 8, TRUE)) 8471 return FALSE; 8472 continue; 8473 8474 case 'L': 8475 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8476 8, FALSE)) 8477 return FALSE; 8478 continue; 8479 8480 case 'f': 8481 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8482 4, TRUE)) 8483 return FALSE; 8484 continue; 8485 8486 case 'l': 8487 if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8488 4, FALSE)) 8489 return FALSE; 8490 continue; 8491 8492 case 'p': 8493 *offset_reloc = BFD_RELOC_16_PCREL_S2; 8494 break; 8495 8496 case 'a': 8497 *offset_reloc = BFD_RELOC_MIPS_JMP; 8498 break; 8499 8500 case 'm': 8501 gas_assert (mips_opts.micromips); 8502 c = args[1]; 8503 switch (c) 8504 { 8505 case 'D': 8506 case 'E': 8507 if (!forced_insn_length) 8508 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 8509 else if (c == 'D') 8510 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; 8511 else 8512 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; 8513 break; 8514 } 8515 break; 8516 } 8517 8518 operand = (mips_opts.micromips 8519 ? decode_micromips_operand (args) 8520 : decode_mips_operand (args)); 8521 if (!operand) 8522 abort (); 8523 8524 /* Skip prefixes. */ 8525 if (*args == '+' || *args == 'm' || *args == '-') 8526 args++; 8527 8528 if (mips_optional_operand_p (operand) 8529 && args[1] == ',' 8530 && (arg.token[0].type != OT_REG 8531 || arg.token[1].type == OT_END)) 8532 { 8533 /* Assume that the register has been elided and is the 8534 same as the first operand. */ 8535 arg.token = tokens; 8536 arg.argnum = 1; 8537 } 8538 8539 if (!match_operand (&arg, operand)) 8540 return FALSE; 8541 } 8542} 8543 8544/* Like match_insn, but for MIPS16. */ 8545 8546static bfd_boolean 8547match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, 8548 struct mips_operand_token *tokens) 8549{ 8550 const char *args; 8551 const struct mips_operand *operand; 8552 const struct mips_operand *ext_operand; 8553 bfd_boolean pcrel = FALSE; 8554 int required_insn_length; 8555 struct mips_arg_info arg; 8556 int relax_char; 8557 8558 if (forced_insn_length) 8559 required_insn_length = forced_insn_length; 8560 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) 8561 required_insn_length = 2; 8562 else 8563 required_insn_length = 0; 8564 8565 create_insn (insn, opcode); 8566 imm_expr.X_op = O_absent; 8567 offset_expr.X_op = O_absent; 8568 offset_reloc[0] = BFD_RELOC_UNUSED; 8569 offset_reloc[1] = BFD_RELOC_UNUSED; 8570 offset_reloc[2] = BFD_RELOC_UNUSED; 8571 relax_char = 0; 8572 8573 memset (&arg, 0, sizeof (arg)); 8574 arg.insn = insn; 8575 arg.token = tokens; 8576 arg.argnum = 1; 8577 arg.last_regno = ILLEGAL_REG; 8578 arg.dest_regno = ILLEGAL_REG; 8579 relax_char = 0; 8580 for (args = opcode->args;; ++args) 8581 { 8582 int c; 8583 8584 if (arg.token->type == OT_END) 8585 { 8586 offsetT value; 8587 8588 /* Handle unary instructions in which only one operand is given. 8589 The source is then the same as the destination. */ 8590 if (arg.opnum == 1 && *args == ',') 8591 { 8592 operand = decode_mips16_operand (args[1], FALSE); 8593 if (operand && mips_optional_operand_p (operand)) 8594 { 8595 arg.token = tokens; 8596 arg.argnum = 1; 8597 continue; 8598 } 8599 } 8600 8601 /* Fail the match if there were too few operands. */ 8602 if (*args) 8603 return FALSE; 8604 8605 /* Successful match. Stuff the immediate value in now, if 8606 we can. */ 8607 clear_insn_error (); 8608 if (opcode->pinfo == INSN_MACRO) 8609 { 8610 gas_assert (relax_char == 0 || relax_char == 'p'); 8611 gas_assert (*offset_reloc == BFD_RELOC_UNUSED); 8612 } 8613 else if (relax_char 8614 && offset_expr.X_op == O_constant 8615 && !pcrel 8616 && calculate_reloc (*offset_reloc, 8617 offset_expr.X_add_number, 8618 &value)) 8619 { 8620 mips16_immed (NULL, 0, relax_char, *offset_reloc, value, 8621 required_insn_length, &insn->insn_opcode); 8622 offset_expr.X_op = O_absent; 8623 *offset_reloc = BFD_RELOC_UNUSED; 8624 } 8625 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) 8626 { 8627 if (required_insn_length == 2) 8628 set_insn_error (0, _("invalid unextended operand value")); 8629 else if (!mips_opcode_32bit_p (opcode)) 8630 { 8631 forced_insn_length = 4; 8632 insn->insn_opcode |= MIPS16_EXTEND; 8633 } 8634 } 8635 else if (relax_char) 8636 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; 8637 8638 check_completed_insn (&arg); 8639 return TRUE; 8640 } 8641 8642 /* Fail the match if the line has too many operands. */ 8643 if (*args == 0) 8644 return FALSE; 8645 8646 /* Handle characters that need to match exactly. */ 8647 if (*args == '(' || *args == ')' || *args == ',') 8648 { 8649 if (match_char (&arg, *args)) 8650 continue; 8651 return FALSE; 8652 } 8653 8654 arg.opnum += 1; 8655 c = *args; 8656 switch (c) 8657 { 8658 case 'p': 8659 case 'q': 8660 case 'A': 8661 case 'B': 8662 case 'E': 8663 case 'V': 8664 case 'u': 8665 relax_char = c; 8666 break; 8667 8668 case 'I': 8669 if (!match_const_int (&arg, &imm_expr.X_add_number)) 8670 return FALSE; 8671 imm_expr.X_op = O_constant; 8672 if (GPR_SIZE == 32) 8673 normalize_constant_expr (&imm_expr); 8674 continue; 8675 8676 case 'a': 8677 case 'i': 8678 *offset_reloc = BFD_RELOC_MIPS16_JMP; 8679 break; 8680 } 8681 8682 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); 8683 if (!operand) 8684 abort (); 8685 8686 if (operand->type == OP_PCREL) 8687 pcrel = TRUE; 8688 else 8689 { 8690 ext_operand = decode_mips16_operand (c, TRUE); 8691 if (operand != ext_operand) 8692 { 8693 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') 8694 { 8695 offset_expr.X_op = O_constant; 8696 offset_expr.X_add_number = 0; 8697 relax_char = c; 8698 continue; 8699 } 8700 8701 if (!match_expression (&arg, &offset_expr, offset_reloc)) 8702 return FALSE; 8703 8704 /* '8' is used for SLTI(U) and has traditionally not 8705 been allowed to take relocation operators. */ 8706 if (offset_reloc[0] != BFD_RELOC_UNUSED 8707 && (ext_operand->size != 16 || c == '8')) 8708 { 8709 match_not_constant (&arg); 8710 return FALSE; 8711 } 8712 8713 if (offset_expr.X_op == O_big) 8714 { 8715 match_out_of_range (&arg); 8716 return FALSE; 8717 } 8718 8719 relax_char = c; 8720 continue; 8721 } 8722 } 8723 8724 if (mips_optional_operand_p (operand) 8725 && args[1] == ',' 8726 && (arg.token[0].type != OT_REG 8727 || arg.token[1].type == OT_END)) 8728 { 8729 /* Assume that the register has been elided and is the 8730 same as the first operand. */ 8731 arg.token = tokens; 8732 arg.argnum = 1; 8733 } 8734 8735 if (!match_operand (&arg, operand)) 8736 return FALSE; 8737 } 8738} 8739 8740/* Record that the current instruction is invalid for the current ISA. */ 8741 8742static void 8743match_invalid_for_isa (void) 8744{ 8745 set_insn_error_ss 8746 (0, _("opcode not supported on this processor: %s (%s)"), 8747 mips_cpu_info_from_arch (mips_opts.arch)->name, 8748 mips_cpu_info_from_isa (mips_opts.isa)->name); 8749} 8750 8751/* Try to match TOKENS against a series of opcode entries, starting at FIRST. 8752 Return true if a definite match or failure was found, storing any match 8753 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode 8754 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already 8755 tried and failed to match under normal conditions and now want to try a 8756 more relaxed match. */ 8757 8758static bfd_boolean 8759match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8760 const struct mips_opcode *past, struct mips_operand_token *tokens, 8761 int opcode_extra, bfd_boolean lax_match) 8762{ 8763 const struct mips_opcode *opcode; 8764 const struct mips_opcode *invalid_delay_slot; 8765 bfd_boolean seen_valid_for_isa, seen_valid_for_size; 8766 8767 /* Search for a match, ignoring alternatives that don't satisfy the 8768 current ISA or forced_length. */ 8769 invalid_delay_slot = 0; 8770 seen_valid_for_isa = FALSE; 8771 seen_valid_for_size = FALSE; 8772 opcode = first; 8773 do 8774 { 8775 gas_assert (strcmp (opcode->name, first->name) == 0); 8776 if (is_opcode_valid (opcode)) 8777 { 8778 seen_valid_for_isa = TRUE; 8779 if (is_size_valid (opcode)) 8780 { 8781 bfd_boolean delay_slot_ok; 8782 8783 seen_valid_for_size = TRUE; 8784 delay_slot_ok = is_delay_slot_valid (opcode); 8785 if (match_insn (insn, opcode, tokens, opcode_extra, 8786 lax_match, delay_slot_ok)) 8787 { 8788 if (!delay_slot_ok) 8789 { 8790 if (!invalid_delay_slot) 8791 invalid_delay_slot = opcode; 8792 } 8793 else 8794 return TRUE; 8795 } 8796 } 8797 } 8798 ++opcode; 8799 } 8800 while (opcode < past && strcmp (opcode->name, first->name) == 0); 8801 8802 /* If the only matches we found had the wrong length for the delay slot, 8803 pick the first such match. We'll issue an appropriate warning later. */ 8804 if (invalid_delay_slot) 8805 { 8806 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, 8807 lax_match, TRUE)) 8808 return TRUE; 8809 abort (); 8810 } 8811 8812 /* Handle the case where we didn't try to match an instruction because 8813 all the alternatives were incompatible with the current ISA. */ 8814 if (!seen_valid_for_isa) 8815 { 8816 match_invalid_for_isa (); 8817 return TRUE; 8818 } 8819 8820 /* Handle the case where we didn't try to match an instruction because 8821 all the alternatives were of the wrong size. */ 8822 if (!seen_valid_for_size) 8823 { 8824 if (mips_opts.insn32) 8825 set_insn_error (0, _("opcode not supported in the `insn32' mode")); 8826 else 8827 set_insn_error_i 8828 (0, _("unrecognized %d-bit version of microMIPS opcode"), 8829 8 * forced_insn_length); 8830 return TRUE; 8831 } 8832 8833 return FALSE; 8834} 8835 8836/* Like match_insns, but for MIPS16. */ 8837 8838static bfd_boolean 8839match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, 8840 struct mips_operand_token *tokens) 8841{ 8842 const struct mips_opcode *opcode; 8843 bfd_boolean seen_valid_for_isa; 8844 bfd_boolean seen_valid_for_size; 8845 8846 /* Search for a match, ignoring alternatives that don't satisfy the 8847 current ISA. There are no separate entries for extended forms so 8848 we deal with forced_length later. */ 8849 seen_valid_for_isa = FALSE; 8850 seen_valid_for_size = FALSE; 8851 opcode = first; 8852 do 8853 { 8854 gas_assert (strcmp (opcode->name, first->name) == 0); 8855 if (is_opcode_valid_16 (opcode)) 8856 { 8857 seen_valid_for_isa = TRUE; 8858 if (is_size_valid_16 (opcode)) 8859 { 8860 seen_valid_for_size = TRUE; 8861 if (match_mips16_insn (insn, opcode, tokens)) 8862 return TRUE; 8863 } 8864 } 8865 ++opcode; 8866 } 8867 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] 8868 && strcmp (opcode->name, first->name) == 0); 8869 8870 /* Handle the case where we didn't try to match an instruction because 8871 all the alternatives were incompatible with the current ISA. */ 8872 if (!seen_valid_for_isa) 8873 { 8874 match_invalid_for_isa (); 8875 return TRUE; 8876 } 8877 8878 /* Handle the case where we didn't try to match an instruction because 8879 all the alternatives were of the wrong size. */ 8880 if (!seen_valid_for_size) 8881 { 8882 if (forced_insn_length == 2) 8883 set_insn_error 8884 (0, _("unrecognized unextended version of MIPS16 opcode")); 8885 else 8886 set_insn_error 8887 (0, _("unrecognized extended version of MIPS16 opcode")); 8888 return TRUE; 8889 } 8890 8891 return FALSE; 8892} 8893 8894/* Set up global variables for the start of a new macro. */ 8895 8896static void 8897macro_start (void) 8898{ 8899 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 8900 memset (&mips_macro_warning.first_insn_sizes, 0, 8901 sizeof (mips_macro_warning.first_insn_sizes)); 8902 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); 8903 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 8904 && delayed_branch_p (&history[0])); 8905 if (history[0].frag 8906 && history[0].frag->fr_type == rs_machine_dependent 8907 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) 8908 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) 8909 mips_macro_warning.delay_slot_length = 0; 8910 else 8911 switch (history[0].insn_mo->pinfo2 8912 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) 8913 { 8914 case INSN2_BRANCH_DELAY_32BIT: 8915 mips_macro_warning.delay_slot_length = 4; 8916 break; 8917 case INSN2_BRANCH_DELAY_16BIT: 8918 mips_macro_warning.delay_slot_length = 2; 8919 break; 8920 default: 8921 mips_macro_warning.delay_slot_length = 0; 8922 break; 8923 } 8924 mips_macro_warning.first_frag = NULL; 8925} 8926 8927/* Given that a macro is longer than one instruction or of the wrong size, 8928 return the appropriate warning for it. Return null if no warning is 8929 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, 8930 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, 8931 and RELAX_NOMACRO. */ 8932 8933static const char * 8934macro_warning (relax_substateT subtype) 8935{ 8936 if (subtype & RELAX_DELAY_SLOT) 8937 return _("macro instruction expanded into multiple instructions" 8938 " in a branch delay slot"); 8939 else if (subtype & RELAX_NOMACRO) 8940 return _("macro instruction expanded into multiple instructions"); 8941 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST 8942 | RELAX_DELAY_SLOT_SIZE_SECOND)) 8943 return ((subtype & RELAX_DELAY_SLOT_16BIT) 8944 ? _("macro instruction expanded into a wrong size instruction" 8945 " in a 16-bit branch delay slot") 8946 : _("macro instruction expanded into a wrong size instruction" 8947 " in a 32-bit branch delay slot")); 8948 else 8949 return 0; 8950} 8951 8952/* Finish up a macro. Emit warnings as appropriate. */ 8953 8954static void 8955macro_end (void) 8956{ 8957 /* Relaxation warning flags. */ 8958 relax_substateT subtype = 0; 8959 8960 /* Check delay slot size requirements. */ 8961 if (mips_macro_warning.delay_slot_length == 2) 8962 subtype |= RELAX_DELAY_SLOT_16BIT; 8963 if (mips_macro_warning.delay_slot_length != 0) 8964 { 8965 if (mips_macro_warning.delay_slot_length 8966 != mips_macro_warning.first_insn_sizes[0]) 8967 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; 8968 if (mips_macro_warning.delay_slot_length 8969 != mips_macro_warning.first_insn_sizes[1]) 8970 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; 8971 } 8972 8973 /* Check instruction count requirements. */ 8974 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) 8975 { 8976 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) 8977 subtype |= RELAX_SECOND_LONGER; 8978 if (mips_opts.warn_about_macros) 8979 subtype |= RELAX_NOMACRO; 8980 if (mips_macro_warning.delay_slot_p) 8981 subtype |= RELAX_DELAY_SLOT; 8982 } 8983 8984 /* If both alternatives fail to fill a delay slot correctly, 8985 emit the warning now. */ 8986 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 8987 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) 8988 { 8989 relax_substateT s; 8990 const char *msg; 8991 8992 s = subtype & (RELAX_DELAY_SLOT_16BIT 8993 | RELAX_DELAY_SLOT_SIZE_FIRST 8994 | RELAX_DELAY_SLOT_SIZE_SECOND); 8995 msg = macro_warning (s); 8996 if (msg != NULL) 8997 as_warn ("%s", msg); 8998 subtype &= ~s; 8999 } 9000 9001 /* If both implementations are longer than 1 instruction, then emit the 9002 warning now. */ 9003 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) 9004 { 9005 relax_substateT s; 9006 const char *msg; 9007 9008 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); 9009 msg = macro_warning (s); 9010 if (msg != NULL) 9011 as_warn ("%s", msg); 9012 subtype &= ~s; 9013 } 9014 9015 /* If any flags still set, then one implementation might need a warning 9016 and the other either will need one of a different kind or none at all. 9017 Pass any remaining flags over to relaxation. */ 9018 if (mips_macro_warning.first_frag != NULL) 9019 mips_macro_warning.first_frag->fr_subtype |= subtype; 9020} 9021 9022/* Instruction operand formats used in macros that vary between 9023 standard MIPS and microMIPS code. */ 9024 9025static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; 9026static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; 9027static const char * const jalr_fmt[2] = { "d,s", "t,s" }; 9028static const char * const lui_fmt[2] = { "t,u", "s,u" }; 9029static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; 9030static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; 9031static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; 9032static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; 9033 9034#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) 9035#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ 9036 : cop12_fmt[mips_opts.micromips]) 9037#define JALR_FMT (jalr_fmt[mips_opts.micromips]) 9038#define LUI_FMT (lui_fmt[mips_opts.micromips]) 9039#define MEM12_FMT (mem12_fmt[mips_opts.micromips]) 9040#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ 9041 : mem12_fmt[mips_opts.micromips]) 9042#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) 9043#define SHFT_FMT (shft_fmt[mips_opts.micromips]) 9044#define TRAP_FMT (trap_fmt[mips_opts.micromips]) 9045 9046/* Read a macro's relocation codes from *ARGS and store them in *R. 9047 The first argument in *ARGS will be either the code for a single 9048 relocation or -1 followed by the three codes that make up a 9049 composite relocation. */ 9050 9051static void 9052macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) 9053{ 9054 int i, next; 9055 9056 next = va_arg (*args, int); 9057 if (next >= 0) 9058 r[0] = (bfd_reloc_code_real_type) next; 9059 else 9060 { 9061 for (i = 0; i < 3; i++) 9062 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); 9063 /* This function is only used for 16-bit relocation fields. 9064 To make the macro code simpler, treat an unrelocated value 9065 in the same way as BFD_RELOC_LO16. */ 9066 if (r[0] == BFD_RELOC_UNUSED) 9067 r[0] = BFD_RELOC_LO16; 9068 } 9069} 9070 9071/* Build an instruction created by a macro expansion. This is passed 9072 a pointer to the count of instructions created so far, an 9073 expression, the name of the instruction to build, an operand format 9074 string, and corresponding arguments. */ 9075 9076static void 9077macro_build (expressionS *ep, const char *name, const char *fmt, ...) 9078{ 9079 const struct mips_opcode *mo = NULL; 9080 bfd_reloc_code_real_type r[3]; 9081 const struct mips_opcode *amo; 9082 const struct mips_operand *operand; 9083 struct hash_control *hash; 9084 struct mips_cl_insn insn; 9085 va_list args; 9086 unsigned int uval; 9087 9088 va_start (args, fmt); 9089 9090 if (mips_opts.mips16) 9091 { 9092 mips16_macro_build (ep, name, fmt, &args); 9093 va_end (args); 9094 return; 9095 } 9096 9097 r[0] = BFD_RELOC_UNUSED; 9098 r[1] = BFD_RELOC_UNUSED; 9099 r[2] = BFD_RELOC_UNUSED; 9100 hash = mips_opts.micromips ? micromips_op_hash : op_hash; 9101 amo = (struct mips_opcode *) hash_find (hash, name); 9102 gas_assert (amo); 9103 gas_assert (strcmp (name, amo->name) == 0); 9104 9105 do 9106 { 9107 /* Search until we get a match for NAME. It is assumed here that 9108 macros will never generate MDMX, MIPS-3D, or MT instructions. 9109 We try to match an instruction that fulfills the branch delay 9110 slot instruction length requirement (if any) of the previous 9111 instruction. While doing this we record the first instruction 9112 seen that matches all the other conditions and use it anyway 9113 if the requirement cannot be met; we will issue an appropriate 9114 warning later on. */ 9115 if (strcmp (fmt, amo->args) == 0 9116 && amo->pinfo != INSN_MACRO 9117 && is_opcode_valid (amo) 9118 && is_size_valid (amo)) 9119 { 9120 if (is_delay_slot_valid (amo)) 9121 { 9122 mo = amo; 9123 break; 9124 } 9125 else if (!mo) 9126 mo = amo; 9127 } 9128 9129 ++amo; 9130 gas_assert (amo->name); 9131 } 9132 while (strcmp (name, amo->name) == 0); 9133 9134 gas_assert (mo); 9135 create_insn (&insn, mo); 9136 for (; *fmt; ++fmt) 9137 { 9138 switch (*fmt) 9139 { 9140 case ',': 9141 case '(': 9142 case ')': 9143 case 'z': 9144 break; 9145 9146 case 'i': 9147 case 'j': 9148 macro_read_relocs (&args, r); 9149 gas_assert (*r == BFD_RELOC_GPREL16 9150 || *r == BFD_RELOC_MIPS_HIGHER 9151 || *r == BFD_RELOC_HI16_S 9152 || *r == BFD_RELOC_LO16 9153 || *r == BFD_RELOC_MIPS_GOT_OFST 9154 || (mips_opts.micromips 9155 && (*r == BFD_RELOC_16 9156 || *r == BFD_RELOC_MIPS_GOT16 9157 || *r == BFD_RELOC_MIPS_CALL16 9158 || *r == BFD_RELOC_MIPS_GOT_HI16 9159 || *r == BFD_RELOC_MIPS_GOT_LO16 9160 || *r == BFD_RELOC_MIPS_CALL_HI16 9161 || *r == BFD_RELOC_MIPS_CALL_LO16 9162 || *r == BFD_RELOC_MIPS_SUB 9163 || *r == BFD_RELOC_MIPS_GOT_PAGE 9164 || *r == BFD_RELOC_MIPS_HIGHEST 9165 || *r == BFD_RELOC_MIPS_GOT_DISP 9166 || *r == BFD_RELOC_MIPS_TLS_GD 9167 || *r == BFD_RELOC_MIPS_TLS_LDM 9168 || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 9169 || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 9170 || *r == BFD_RELOC_MIPS_TLS_GOTTPREL 9171 || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 9172 || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); 9173 break; 9174 9175 case 'o': 9176 macro_read_relocs (&args, r); 9177 break; 9178 9179 case 'u': 9180 macro_read_relocs (&args, r); 9181 gas_assert (ep != NULL 9182 && (ep->X_op == O_constant 9183 || (ep->X_op == O_symbol 9184 && (*r == BFD_RELOC_MIPS_HIGHEST 9185 || *r == BFD_RELOC_HI16_S 9186 || *r == BFD_RELOC_HI16 9187 || *r == BFD_RELOC_GPREL16 9188 || *r == BFD_RELOC_MIPS_GOT_HI16 9189 || *r == BFD_RELOC_MIPS_CALL_HI16)))); 9190 break; 9191 9192 case 'p': 9193 gas_assert (ep != NULL); 9194 9195 /* 9196 * This allows macro() to pass an immediate expression for 9197 * creating short branches without creating a symbol. 9198 * 9199 * We don't allow branch relaxation for these branches, as 9200 * they should only appear in ".set nomacro" anyway. 9201 */ 9202 if (ep->X_op == O_constant) 9203 { 9204 /* For microMIPS we always use relocations for branches. 9205 So we should not resolve immediate values. */ 9206 gas_assert (!mips_opts.micromips); 9207 9208 if ((ep->X_add_number & 3) != 0) 9209 as_bad (_("branch to misaligned address (0x%lx)"), 9210 (unsigned long) ep->X_add_number); 9211 if ((ep->X_add_number + 0x20000) & ~0x3ffff) 9212 as_bad (_("branch address range overflow (0x%lx)"), 9213 (unsigned long) ep->X_add_number); 9214 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 9215 ep = NULL; 9216 } 9217 else 9218 *r = BFD_RELOC_16_PCREL_S2; 9219 break; 9220 9221 case 'a': 9222 gas_assert (ep != NULL); 9223 *r = BFD_RELOC_MIPS_JMP; 9224 break; 9225 9226 default: 9227 operand = (mips_opts.micromips 9228 ? decode_micromips_operand (fmt) 9229 : decode_mips_operand (fmt)); 9230 if (!operand) 9231 abort (); 9232 9233 uval = va_arg (args, int); 9234 if (operand->type == OP_CLO_CLZ_DEST) 9235 uval |= (uval << 5); 9236 insn_insert_operand (&insn, operand, uval); 9237 9238 if (*fmt == '+' || *fmt == 'm' || *fmt == '-') 9239 ++fmt; 9240 break; 9241 } 9242 } 9243 va_end (args); 9244 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 9245 9246 append_insn (&insn, ep, r, TRUE); 9247} 9248 9249static void 9250mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 9251 va_list *args) 9252{ 9253 struct mips_opcode *mo; 9254 struct mips_cl_insn insn; 9255 const struct mips_operand *operand; 9256 bfd_reloc_code_real_type r[3] 9257 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 9258 9259 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 9260 gas_assert (mo); 9261 gas_assert (strcmp (name, mo->name) == 0); 9262 9263 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) 9264 { 9265 ++mo; 9266 gas_assert (mo->name); 9267 gas_assert (strcmp (name, mo->name) == 0); 9268 } 9269 9270 create_insn (&insn, mo); 9271 for (; *fmt; ++fmt) 9272 { 9273 int c; 9274 9275 c = *fmt; 9276 switch (c) 9277 { 9278 case ',': 9279 case '(': 9280 case ')': 9281 break; 9282 9283 case '.': 9284 case 'S': 9285 case 'P': 9286 case 'R': 9287 break; 9288 9289 case '<': 9290 case '5': 9291 case 'F': 9292 case 'H': 9293 case 'W': 9294 case 'D': 9295 case 'j': 9296 case '8': 9297 case 'V': 9298 case 'C': 9299 case 'U': 9300 case 'k': 9301 case 'K': 9302 case 'p': 9303 case 'q': 9304 { 9305 offsetT value; 9306 9307 gas_assert (ep != NULL); 9308 9309 if (ep->X_op != O_constant) 9310 *r = (int) BFD_RELOC_UNUSED + c; 9311 else if (calculate_reloc (*r, ep->X_add_number, &value)) 9312 { 9313 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); 9314 ep = NULL; 9315 *r = BFD_RELOC_UNUSED; 9316 } 9317 } 9318 break; 9319 9320 default: 9321 operand = decode_mips16_operand (c, FALSE); 9322 if (!operand) 9323 abort (); 9324 9325 insn_insert_operand (&insn, operand, va_arg (*args, int)); 9326 break; 9327 } 9328 } 9329 9330 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 9331 9332 append_insn (&insn, ep, r, TRUE); 9333} 9334 9335/* 9336 * Generate a "jalr" instruction with a relocation hint to the called 9337 * function. This occurs in NewABI PIC code. 9338 */ 9339static void 9340macro_build_jalr (expressionS *ep, int cprestore) 9341{ 9342 static const bfd_reloc_code_real_type jalr_relocs[2] 9343 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; 9344 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; 9345 const char *jalr; 9346 char *f = NULL; 9347 9348 if (MIPS_JALR_HINT_P (ep)) 9349 { 9350 frag_grow (8); 9351 f = frag_more (0); 9352 } 9353 if (mips_opts.micromips) 9354 { 9355 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 9356 ? "jalr" : "jalrs"); 9357 if (MIPS_JALR_HINT_P (ep) 9358 || mips_opts.insn32 9359 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 9360 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); 9361 else 9362 macro_build (NULL, jalr, "mj", PIC_CALL_REG); 9363 } 9364 else 9365 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 9366 if (MIPS_JALR_HINT_P (ep)) 9367 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); 9368} 9369 9370/* 9371 * Generate a "lui" instruction. 9372 */ 9373static void 9374macro_build_lui (expressionS *ep, int regnum) 9375{ 9376 gas_assert (! mips_opts.mips16); 9377 9378 if (ep->X_op != O_constant) 9379 { 9380 gas_assert (ep->X_op == O_symbol); 9381 /* _gp_disp is a special case, used from s_cpload. 9382 __gnu_local_gp is used if mips_no_shared. */ 9383 gas_assert (mips_pic == NO_PIC 9384 || (! HAVE_NEWABI 9385 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) 9386 || (! mips_in_shared 9387 && strcmp (S_GET_NAME (ep->X_add_symbol), 9388 "__gnu_local_gp") == 0)); 9389 } 9390 9391 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); 9392} 9393 9394/* Generate a sequence of instructions to do a load or store from a constant 9395 offset off of a base register (breg) into/from a target register (treg), 9396 using AT if necessary. */ 9397static void 9398macro_build_ldst_constoffset (expressionS *ep, const char *op, 9399 int treg, int breg, int dbl) 9400{ 9401 gas_assert (ep->X_op == O_constant); 9402 9403 /* Sign-extending 32-bit constants makes their handling easier. */ 9404 if (!dbl) 9405 normalize_constant_expr (ep); 9406 9407 /* Right now, this routine can only handle signed 32-bit constants. */ 9408 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 9409 as_warn (_("operand overflow")); 9410 9411 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 9412 { 9413 /* Signed 16-bit offset will fit in the op. Easy! */ 9414 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 9415 } 9416 else 9417 { 9418 /* 32-bit offset, need multiple instructions and AT, like: 9419 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 9420 addu $tempreg,$tempreg,$breg 9421 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 9422 to handle the complete offset. */ 9423 macro_build_lui (ep, AT); 9424 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 9425 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 9426 9427 if (!mips_opts.at) 9428 as_bad (_("macro used $at after \".set noat\"")); 9429 } 9430} 9431 9432/* set_at() 9433 * Generates code to set the $at register to true (one) 9434 * if reg is less than the immediate expression. 9435 */ 9436static void 9437set_at (int reg, int unsignedp) 9438{ 9439 if (imm_expr.X_add_number >= -0x8000 9440 && imm_expr.X_add_number < 0x8000) 9441 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 9442 AT, reg, BFD_RELOC_LO16); 9443 else 9444 { 9445 load_register (AT, &imm_expr, GPR_SIZE == 64); 9446 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 9447 } 9448} 9449 9450/* Count the leading zeroes by performing a binary chop. This is a 9451 bulky bit of source, but performance is a LOT better for the 9452 majority of values than a simple loop to count the bits: 9453 for (lcnt = 0; (lcnt < 32); lcnt++) 9454 if ((v) & (1 << (31 - lcnt))) 9455 break; 9456 However it is not code size friendly, and the gain will drop a bit 9457 on certain cached systems. 9458*/ 9459#define COUNT_TOP_ZEROES(v) \ 9460 (((v) & ~0xffff) == 0 \ 9461 ? ((v) & ~0xff) == 0 \ 9462 ? ((v) & ~0xf) == 0 \ 9463 ? ((v) & ~0x3) == 0 \ 9464 ? ((v) & ~0x1) == 0 \ 9465 ? !(v) \ 9466 ? 32 \ 9467 : 31 \ 9468 : 30 \ 9469 : ((v) & ~0x7) == 0 \ 9470 ? 29 \ 9471 : 28 \ 9472 : ((v) & ~0x3f) == 0 \ 9473 ? ((v) & ~0x1f) == 0 \ 9474 ? 27 \ 9475 : 26 \ 9476 : ((v) & ~0x7f) == 0 \ 9477 ? 25 \ 9478 : 24 \ 9479 : ((v) & ~0xfff) == 0 \ 9480 ? ((v) & ~0x3ff) == 0 \ 9481 ? ((v) & ~0x1ff) == 0 \ 9482 ? 23 \ 9483 : 22 \ 9484 : ((v) & ~0x7ff) == 0 \ 9485 ? 21 \ 9486 : 20 \ 9487 : ((v) & ~0x3fff) == 0 \ 9488 ? ((v) & ~0x1fff) == 0 \ 9489 ? 19 \ 9490 : 18 \ 9491 : ((v) & ~0x7fff) == 0 \ 9492 ? 17 \ 9493 : 16 \ 9494 : ((v) & ~0xffffff) == 0 \ 9495 ? ((v) & ~0xfffff) == 0 \ 9496 ? ((v) & ~0x3ffff) == 0 \ 9497 ? ((v) & ~0x1ffff) == 0 \ 9498 ? 15 \ 9499 : 14 \ 9500 : ((v) & ~0x7ffff) == 0 \ 9501 ? 13 \ 9502 : 12 \ 9503 : ((v) & ~0x3fffff) == 0 \ 9504 ? ((v) & ~0x1fffff) == 0 \ 9505 ? 11 \ 9506 : 10 \ 9507 : ((v) & ~0x7fffff) == 0 \ 9508 ? 9 \ 9509 : 8 \ 9510 : ((v) & ~0xfffffff) == 0 \ 9511 ? ((v) & ~0x3ffffff) == 0 \ 9512 ? ((v) & ~0x1ffffff) == 0 \ 9513 ? 7 \ 9514 : 6 \ 9515 : ((v) & ~0x7ffffff) == 0 \ 9516 ? 5 \ 9517 : 4 \ 9518 : ((v) & ~0x3fffffff) == 0 \ 9519 ? ((v) & ~0x1fffffff) == 0 \ 9520 ? 3 \ 9521 : 2 \ 9522 : ((v) & ~0x7fffffff) == 0 \ 9523 ? 1 \ 9524 : 0) 9525 9526/* load_register() 9527 * This routine generates the least number of instructions necessary to load 9528 * an absolute expression value into a register. 9529 */ 9530static void 9531load_register (int reg, expressionS *ep, int dbl) 9532{ 9533 int freg; 9534 expressionS hi32, lo32; 9535 9536 if (ep->X_op != O_big) 9537 { 9538 gas_assert (ep->X_op == O_constant); 9539 9540 /* Sign-extending 32-bit constants makes their handling easier. */ 9541 if (!dbl) 9542 normalize_constant_expr (ep); 9543 9544 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 9545 { 9546 /* We can handle 16 bit signed values with an addiu to 9547 $zero. No need to ever use daddiu here, since $zero and 9548 the result are always correct in 32 bit mode. */ 9549 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9550 return; 9551 } 9552 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 9553 { 9554 /* We can handle 16 bit unsigned values with an ori to 9555 $zero. */ 9556 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9557 return; 9558 } 9559 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 9560 { 9561 /* 32 bit values require an lui. */ 9562 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9563 if ((ep->X_add_number & 0xffff) != 0) 9564 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9565 return; 9566 } 9567 } 9568 9569 /* The value is larger than 32 bits. */ 9570 9571 if (!dbl || GPR_SIZE == 32) 9572 { 9573 char value[32]; 9574 9575 sprintf_vma (value, ep->X_add_number); 9576 as_bad (_("number (0x%s) larger than 32 bits"), value); 9577 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9578 return; 9579 } 9580 9581 if (ep->X_op != O_big) 9582 { 9583 hi32 = *ep; 9584 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9585 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 9586 hi32.X_add_number &= 0xffffffff; 9587 lo32 = *ep; 9588 lo32.X_add_number &= 0xffffffff; 9589 } 9590 else 9591 { 9592 gas_assert (ep->X_add_number > 2); 9593 if (ep->X_add_number == 3) 9594 generic_bignum[3] = 0; 9595 else if (ep->X_add_number > 4) 9596 as_bad (_("number larger than 64 bits")); 9597 lo32.X_op = O_constant; 9598 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 9599 hi32.X_op = O_constant; 9600 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 9601 } 9602 9603 if (hi32.X_add_number == 0) 9604 freg = 0; 9605 else 9606 { 9607 int shift, bit; 9608 unsigned long hi, lo; 9609 9610 if (hi32.X_add_number == (offsetT) 0xffffffff) 9611 { 9612 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 9613 { 9614 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9615 return; 9616 } 9617 if (lo32.X_add_number & 0x80000000) 9618 { 9619 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9620 if (lo32.X_add_number & 0xffff) 9621 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 9622 return; 9623 } 9624 } 9625 9626 /* Check for 16bit shifted constant. We know that hi32 is 9627 non-zero, so start the mask on the first bit of the hi32 9628 value. */ 9629 shift = 17; 9630 do 9631 { 9632 unsigned long himask, lomask; 9633 9634 if (shift < 32) 9635 { 9636 himask = 0xffff >> (32 - shift); 9637 lomask = (0xffff << shift) & 0xffffffff; 9638 } 9639 else 9640 { 9641 himask = 0xffff << (shift - 32); 9642 lomask = 0; 9643 } 9644 if ((hi32.X_add_number & ~(offsetT) himask) == 0 9645 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 9646 { 9647 expressionS tmp; 9648 9649 tmp.X_op = O_constant; 9650 if (shift < 32) 9651 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 9652 | (lo32.X_add_number >> shift)); 9653 else 9654 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 9655 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 9656 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9657 reg, reg, (shift >= 32) ? shift - 32 : shift); 9658 return; 9659 } 9660 ++shift; 9661 } 9662 while (shift <= (64 - 16)); 9663 9664 /* Find the bit number of the lowest one bit, and store the 9665 shifted value in hi/lo. */ 9666 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 9667 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 9668 if (lo != 0) 9669 { 9670 bit = 0; 9671 while ((lo & 1) == 0) 9672 { 9673 lo >>= 1; 9674 ++bit; 9675 } 9676 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 9677 hi >>= bit; 9678 } 9679 else 9680 { 9681 bit = 32; 9682 while ((hi & 1) == 0) 9683 { 9684 hi >>= 1; 9685 ++bit; 9686 } 9687 lo = hi; 9688 hi = 0; 9689 } 9690 9691 /* Optimize if the shifted value is a (power of 2) - 1. */ 9692 if ((hi == 0 && ((lo + 1) & lo) == 0) 9693 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 9694 { 9695 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 9696 if (shift != 0) 9697 { 9698 expressionS tmp; 9699 9700 /* This instruction will set the register to be all 9701 ones. */ 9702 tmp.X_op = O_constant; 9703 tmp.X_add_number = (offsetT) -1; 9704 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 9705 if (bit != 0) 9706 { 9707 bit += shift; 9708 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, 9709 reg, reg, (bit >= 32) ? bit - 32 : bit); 9710 } 9711 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, 9712 reg, reg, (shift >= 32) ? shift - 32 : shift); 9713 return; 9714 } 9715 } 9716 9717 /* Sign extend hi32 before calling load_register, because we can 9718 generally get better code when we load a sign extended value. */ 9719 if ((hi32.X_add_number & 0x80000000) != 0) 9720 hi32.X_add_number |= ~(offsetT) 0xffffffff; 9721 load_register (reg, &hi32, 0); 9722 freg = reg; 9723 } 9724 if ((lo32.X_add_number & 0xffff0000) == 0) 9725 { 9726 if (freg != 0) 9727 { 9728 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); 9729 freg = reg; 9730 } 9731 } 9732 else 9733 { 9734 expressionS mid16; 9735 9736 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 9737 { 9738 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); 9739 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); 9740 return; 9741 } 9742 9743 if (freg != 0) 9744 { 9745 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); 9746 freg = reg; 9747 } 9748 mid16 = lo32; 9749 mid16.X_add_number >>= 16; 9750 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9751 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9752 freg = reg; 9753 } 9754 if ((lo32.X_add_number & 0xffff) != 0) 9755 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 9756} 9757 9758static inline void 9759load_delay_nop (void) 9760{ 9761 if (!gpr_interlocks) 9762 macro_build (NULL, "nop", ""); 9763} 9764 9765/* Load an address into a register. */ 9766 9767static void 9768load_address (int reg, expressionS *ep, int *used_at) 9769{ 9770 if (ep->X_op != O_constant 9771 && ep->X_op != O_symbol) 9772 { 9773 as_bad (_("expression too complex")); 9774 ep->X_op = O_constant; 9775 } 9776 9777 if (ep->X_op == O_constant) 9778 { 9779 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 9780 return; 9781 } 9782 9783 if (mips_pic == NO_PIC) 9784 { 9785 /* If this is a reference to a GP relative symbol, we want 9786 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 9787 Otherwise we want 9788 lui $reg,<sym> (BFD_RELOC_HI16_S) 9789 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9790 If we have an addend, we always use the latter form. 9791 9792 With 64bit address space and a usable $at we want 9793 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9794 lui $at,<sym> (BFD_RELOC_HI16_S) 9795 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9796 daddiu $at,<sym> (BFD_RELOC_LO16) 9797 dsll32 $reg,0 9798 daddu $reg,$reg,$at 9799 9800 If $at is already in use, we use a path which is suboptimal 9801 on superscalar processors. 9802 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 9803 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 9804 dsll $reg,16 9805 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 9806 dsll $reg,16 9807 daddiu $reg,<sym> (BFD_RELOC_LO16) 9808 9809 For GP relative symbols in 64bit address space we can use 9810 the same sequence as in 32bit address space. */ 9811 if (HAVE_64BIT_SYMBOLS) 9812 { 9813 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9814 && !nopic_need_relax (ep->X_add_symbol, 1)) 9815 { 9816 relax_start (ep->X_add_symbol); 9817 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9818 mips_gp_register, BFD_RELOC_GPREL16); 9819 relax_switch (); 9820 } 9821 9822 if (*used_at == 0 && mips_opts.at) 9823 { 9824 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9825 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); 9826 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9827 BFD_RELOC_MIPS_HIGHER); 9828 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 9829 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); 9830 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 9831 *used_at = 1; 9832 } 9833 else 9834 { 9835 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); 9836 macro_build (ep, "daddiu", "t,r,j", reg, reg, 9837 BFD_RELOC_MIPS_HIGHER); 9838 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9839 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 9840 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); 9841 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 9842 } 9843 9844 if (mips_relax.sequence) 9845 relax_end (); 9846 } 9847 else 9848 { 9849 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 9850 && !nopic_need_relax (ep->X_add_symbol, 1)) 9851 { 9852 relax_start (ep->X_add_symbol); 9853 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 9854 mips_gp_register, BFD_RELOC_GPREL16); 9855 relax_switch (); 9856 } 9857 macro_build_lui (ep, reg); 9858 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 9859 reg, reg, BFD_RELOC_LO16); 9860 if (mips_relax.sequence) 9861 relax_end (); 9862 } 9863 } 9864 else if (!mips_big_got) 9865 { 9866 expressionS ex; 9867 9868 /* If this is a reference to an external symbol, we want 9869 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9870 Otherwise we want 9871 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9872 nop 9873 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9874 If there is a constant, it must be added in after. 9875 9876 If we have NewABI, we want 9877 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 9878 unless we're referencing a global symbol with a non-zero 9879 offset, in which case cst must be added separately. */ 9880 if (HAVE_NEWABI) 9881 { 9882 if (ep->X_add_number) 9883 { 9884 ex.X_add_number = ep->X_add_number; 9885 ep->X_add_number = 0; 9886 relax_start (ep->X_add_symbol); 9887 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9888 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9889 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9890 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9891 ex.X_op = O_constant; 9892 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9893 reg, reg, BFD_RELOC_LO16); 9894 ep->X_add_number = ex.X_add_number; 9895 relax_switch (); 9896 } 9897 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9898 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 9899 if (mips_relax.sequence) 9900 relax_end (); 9901 } 9902 else 9903 { 9904 ex.X_add_number = ep->X_add_number; 9905 ep->X_add_number = 0; 9906 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9907 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9908 load_delay_nop (); 9909 relax_start (ep->X_add_symbol); 9910 relax_switch (); 9911 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9912 BFD_RELOC_LO16); 9913 relax_end (); 9914 9915 if (ex.X_add_number != 0) 9916 { 9917 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9918 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9919 ex.X_op = O_constant; 9920 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 9921 reg, reg, BFD_RELOC_LO16); 9922 } 9923 } 9924 } 9925 else if (mips_big_got) 9926 { 9927 expressionS ex; 9928 9929 /* This is the large GOT case. If this is a reference to an 9930 external symbol, we want 9931 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 9932 addu $reg,$reg,$gp 9933 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 9934 9935 Otherwise, for a reference to a local symbol in old ABI, we want 9936 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 9937 nop 9938 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 9939 If there is a constant, it must be added in after. 9940 9941 In the NewABI, for local symbols, with or without offsets, we want: 9942 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 9943 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 9944 */ 9945 if (HAVE_NEWABI) 9946 { 9947 ex.X_add_number = ep->X_add_number; 9948 ep->X_add_number = 0; 9949 relax_start (ep->X_add_symbol); 9950 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9951 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9952 reg, reg, mips_gp_register); 9953 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9954 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9955 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 9956 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 9957 else if (ex.X_add_number) 9958 { 9959 ex.X_op = O_constant; 9960 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9961 BFD_RELOC_LO16); 9962 } 9963 9964 ep->X_add_number = ex.X_add_number; 9965 relax_switch (); 9966 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9967 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 9968 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9969 BFD_RELOC_MIPS_GOT_OFST); 9970 relax_end (); 9971 } 9972 else 9973 { 9974 ex.X_add_number = ep->X_add_number; 9975 ep->X_add_number = 0; 9976 relax_start (ep->X_add_symbol); 9977 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); 9978 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 9979 reg, reg, mips_gp_register); 9980 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 9981 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 9982 relax_switch (); 9983 if (reg_needs_delay (mips_gp_register)) 9984 { 9985 /* We need a nop before loading from $gp. This special 9986 check is required because the lui which starts the main 9987 instruction stream does not refer to $gp, and so will not 9988 insert the nop which may be required. */ 9989 macro_build (NULL, "nop", ""); 9990 } 9991 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 9992 BFD_RELOC_MIPS_GOT16, mips_gp_register); 9993 load_delay_nop (); 9994 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 9995 BFD_RELOC_LO16); 9996 relax_end (); 9997 9998 if (ex.X_add_number != 0) 9999 { 10000 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 10001 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 10002 ex.X_op = O_constant; 10003 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 10004 BFD_RELOC_LO16); 10005 } 10006 } 10007 } 10008 else 10009 abort (); 10010 10011 if (!mips_opts.at && *used_at == 1) 10012 as_bad (_("macro used $at after \".set noat\"")); 10013} 10014 10015/* Move the contents of register SOURCE into register DEST. */ 10016 10017static void 10018move_register (int dest, int source) 10019{ 10020 /* Prefer to use a 16-bit microMIPS instruction unless the previous 10021 instruction specifically requires a 32-bit one. */ 10022 if (mips_opts.micromips 10023 && !mips_opts.insn32 10024 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 10025 macro_build (NULL, "move", "mp,mj", dest, source); 10026 else 10027 macro_build (NULL, "or", "d,v,t", dest, source, 0); 10028} 10029 10030/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 10031 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 10032 The two alternatives are: 10033 10034 Global symbol Local symbol 10035 ------------- ------------ 10036 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 10037 ... ... 10038 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 10039 10040 load_got_offset emits the first instruction and add_got_offset 10041 emits the second for a 16-bit offset or add_got_offset_hilo emits 10042 a sequence to add a 32-bit offset using a scratch register. */ 10043 10044static void 10045load_got_offset (int dest, expressionS *local) 10046{ 10047 expressionS global; 10048 10049 global = *local; 10050 global.X_add_number = 0; 10051 10052 relax_start (local->X_add_symbol); 10053 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 10054 BFD_RELOC_MIPS_GOT16, mips_gp_register); 10055 relax_switch (); 10056 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 10057 BFD_RELOC_MIPS_GOT16, mips_gp_register); 10058 relax_end (); 10059} 10060 10061static void 10062add_got_offset (int dest, expressionS *local) 10063{ 10064 expressionS global; 10065 10066 global.X_op = O_constant; 10067 global.X_op_symbol = NULL; 10068 global.X_add_symbol = NULL; 10069 global.X_add_number = local->X_add_number; 10070 10071 relax_start (local->X_add_symbol); 10072 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 10073 dest, dest, BFD_RELOC_LO16); 10074 relax_switch (); 10075 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 10076 relax_end (); 10077} 10078 10079static void 10080add_got_offset_hilo (int dest, expressionS *local, int tmp) 10081{ 10082 expressionS global; 10083 int hold_mips_optimize; 10084 10085 global.X_op = O_constant; 10086 global.X_op_symbol = NULL; 10087 global.X_add_symbol = NULL; 10088 global.X_add_number = local->X_add_number; 10089 10090 relax_start (local->X_add_symbol); 10091 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 10092 relax_switch (); 10093 /* Set mips_optimize around the lui instruction to avoid 10094 inserting an unnecessary nop after the lw. */ 10095 hold_mips_optimize = mips_optimize; 10096 mips_optimize = 2; 10097 macro_build_lui (&global, tmp); 10098 mips_optimize = hold_mips_optimize; 10099 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 10100 relax_end (); 10101 10102 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 10103} 10104 10105/* Emit a sequence of instructions to emulate a branch likely operation. 10106 BR is an ordinary branch corresponding to one to be emulated. BRNEG 10107 is its complementing branch with the original condition negated. 10108 CALL is set if the original branch specified the link operation. 10109 EP, FMT, SREG and TREG specify the usual macro_build() parameters. 10110 10111 Code like this is produced in the noreorder mode: 10112 10113 BRNEG <args>, 1f 10114 nop 10115 b <sym> 10116 delay slot (executed only if branch taken) 10117 1: 10118 10119 or, if CALL is set: 10120 10121 BRNEG <args>, 1f 10122 nop 10123 bal <sym> 10124 delay slot (executed only if branch taken) 10125 1: 10126 10127 In the reorder mode the delay slot would be filled with a nop anyway, 10128 so code produced is simply: 10129 10130 BR <args>, <sym> 10131 nop 10132 10133 This function is used when producing code for the microMIPS ASE that 10134 does not implement branch likely instructions in hardware. */ 10135 10136static void 10137macro_build_branch_likely (const char *br, const char *brneg, 10138 int call, expressionS *ep, const char *fmt, 10139 unsigned int sreg, unsigned int treg) 10140{ 10141 int noreorder = mips_opts.noreorder; 10142 expressionS expr1; 10143 10144 gas_assert (mips_opts.micromips); 10145 start_noreorder (); 10146 if (noreorder) 10147 { 10148 micromips_label_expr (&expr1); 10149 macro_build (&expr1, brneg, fmt, sreg, treg); 10150 macro_build (NULL, "nop", ""); 10151 macro_build (ep, call ? "bal" : "b", "p"); 10152 10153 /* Set to true so that append_insn adds a label. */ 10154 emit_branch_likely_macro = TRUE; 10155 } 10156 else 10157 { 10158 macro_build (ep, br, fmt, sreg, treg); 10159 macro_build (NULL, "nop", ""); 10160 } 10161 end_noreorder (); 10162} 10163 10164/* Emit a coprocessor branch-likely macro specified by TYPE, using CC as 10165 the condition code tested. EP specifies the branch target. */ 10166 10167static void 10168macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) 10169{ 10170 const int call = 0; 10171 const char *brneg; 10172 const char *br; 10173 10174 switch (type) 10175 { 10176 case M_BC1FL: 10177 br = "bc1f"; 10178 brneg = "bc1t"; 10179 break; 10180 case M_BC1TL: 10181 br = "bc1t"; 10182 brneg = "bc1f"; 10183 break; 10184 case M_BC2FL: 10185 br = "bc2f"; 10186 brneg = "bc2t"; 10187 break; 10188 case M_BC2TL: 10189 br = "bc2t"; 10190 brneg = "bc2f"; 10191 break; 10192 default: 10193 abort (); 10194 } 10195 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); 10196} 10197 10198/* Emit a two-argument branch macro specified by TYPE, using SREG as 10199 the register tested. EP specifies the branch target. */ 10200 10201static void 10202macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) 10203{ 10204 const char *brneg = NULL; 10205 const char *br; 10206 int call = 0; 10207 10208 switch (type) 10209 { 10210 case M_BGEZ: 10211 br = "bgez"; 10212 break; 10213 case M_BGEZL: 10214 br = mips_opts.micromips ? "bgez" : "bgezl"; 10215 brneg = "bltz"; 10216 break; 10217 case M_BGEZALL: 10218 gas_assert (mips_opts.micromips); 10219 br = mips_opts.insn32 ? "bgezal" : "bgezals"; 10220 brneg = "bltz"; 10221 call = 1; 10222 break; 10223 case M_BGTZ: 10224 br = "bgtz"; 10225 break; 10226 case M_BGTZL: 10227 br = mips_opts.micromips ? "bgtz" : "bgtzl"; 10228 brneg = "blez"; 10229 break; 10230 case M_BLEZ: 10231 br = "blez"; 10232 break; 10233 case M_BLEZL: 10234 br = mips_opts.micromips ? "blez" : "blezl"; 10235 brneg = "bgtz"; 10236 break; 10237 case M_BLTZ: 10238 br = "bltz"; 10239 break; 10240 case M_BLTZL: 10241 br = mips_opts.micromips ? "bltz" : "bltzl"; 10242 brneg = "bgez"; 10243 break; 10244 case M_BLTZALL: 10245 gas_assert (mips_opts.micromips); 10246 br = mips_opts.insn32 ? "bltzal" : "bltzals"; 10247 brneg = "bgez"; 10248 call = 1; 10249 break; 10250 default: 10251 abort (); 10252 } 10253 if (mips_opts.micromips && brneg) 10254 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); 10255 else 10256 macro_build (ep, br, "s,p", sreg); 10257} 10258 10259/* Emit a three-argument branch macro specified by TYPE, using SREG and 10260 TREG as the registers tested. EP specifies the branch target. */ 10261 10262static void 10263macro_build_branch_rsrt (int type, expressionS *ep, 10264 unsigned int sreg, unsigned int treg) 10265{ 10266 const char *brneg = NULL; 10267 const int call = 0; 10268 const char *br; 10269 10270 switch (type) 10271 { 10272 case M_BEQ: 10273 case M_BEQ_I: 10274 br = "beq"; 10275 break; 10276 case M_BEQL: 10277 case M_BEQL_I: 10278 br = mips_opts.micromips ? "beq" : "beql"; 10279 brneg = "bne"; 10280 break; 10281 case M_BNE: 10282 case M_BNE_I: 10283 br = "bne"; 10284 break; 10285 case M_BNEL: 10286 case M_BNEL_I: 10287 br = mips_opts.micromips ? "bne" : "bnel"; 10288 brneg = "beq"; 10289 break; 10290 default: 10291 abort (); 10292 } 10293 if (mips_opts.micromips && brneg) 10294 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); 10295 else 10296 macro_build (ep, br, "s,t,p", sreg, treg); 10297} 10298 10299/* Return the high part that should be loaded in order to make the low 10300 part of VALUE accessible using an offset of OFFBITS bits. */ 10301 10302static offsetT 10303offset_high_part (offsetT value, unsigned int offbits) 10304{ 10305 offsetT bias; 10306 addressT low_mask; 10307 10308 if (offbits == 0) 10309 return value; 10310 bias = 1 << (offbits - 1); 10311 low_mask = bias * 2 - 1; 10312 return (value + bias) & ~low_mask; 10313} 10314 10315/* Return true if the value stored in offset_expr and offset_reloc 10316 fits into a signed offset of OFFBITS bits. RANGE is the maximum 10317 amount that the caller wants to add without inducing overflow 10318 and ALIGN is the known alignment of the value in bytes. */ 10319 10320static bfd_boolean 10321small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) 10322{ 10323 if (offbits == 16) 10324 { 10325 /* Accept any relocation operator if overflow isn't a concern. */ 10326 if (range < align && *offset_reloc != BFD_RELOC_UNUSED) 10327 return TRUE; 10328 10329 /* These relocations are guaranteed not to overflow in correct links. */ 10330 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL 10331 || gprel16_reloc_p (*offset_reloc)) 10332 return TRUE; 10333 } 10334 if (offset_expr.X_op == O_constant 10335 && offset_high_part (offset_expr.X_add_number, offbits) == 0 10336 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) 10337 return TRUE; 10338 return FALSE; 10339} 10340 10341/* 10342 * Build macros 10343 * This routine implements the seemingly endless macro or synthesized 10344 * instructions and addressing modes in the mips assembly language. Many 10345 * of these macros are simple and are similar to each other. These could 10346 * probably be handled by some kind of table or grammar approach instead of 10347 * this verbose method. Others are not simple macros but are more like 10348 * optimizing code generation. 10349 * One interesting optimization is when several store macros appear 10350 * consecutively that would load AT with the upper half of the same address. 10351 * The ensuing load upper instructions are omitted. This implies some kind 10352 * of global optimization. We currently only optimize within a single macro. 10353 * For many of the load and store macros if the address is specified as a 10354 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 10355 * first load register 'at' with zero and use it as the base register. The 10356 * mips assembler simply uses register $zero. Just one tiny optimization 10357 * we're missing. 10358 */ 10359static void 10360macro (struct mips_cl_insn *ip, char *str) 10361{ 10362 const struct mips_operand_array *operands; 10363 unsigned int breg, i; 10364 unsigned int tempreg; 10365 int mask; 10366 int used_at = 0; 10367 expressionS label_expr; 10368 expressionS expr1; 10369 expressionS *ep; 10370 const char *s; 10371 const char *s2; 10372 const char *fmt; 10373 int likely = 0; 10374 int coproc = 0; 10375 int offbits = 16; 10376 int call = 0; 10377 int jals = 0; 10378 int dbl = 0; 10379 int imm = 0; 10380 int ust = 0; 10381 int lp = 0; 10382 int ll_sc_paired = 0; 10383 bfd_boolean large_offset; 10384 int off; 10385 int hold_mips_optimize; 10386 unsigned int align; 10387 unsigned int op[MAX_OPERANDS]; 10388 10389 gas_assert (! mips_opts.mips16); 10390 10391 operands = insn_operands (ip); 10392 for (i = 0; i < MAX_OPERANDS; i++) 10393 if (operands->operand[i]) 10394 op[i] = insn_extract_operand (ip, operands->operand[i]); 10395 else 10396 op[i] = -1; 10397 10398 mask = ip->insn_mo->mask; 10399 10400 label_expr.X_op = O_constant; 10401 label_expr.X_op_symbol = NULL; 10402 label_expr.X_add_symbol = NULL; 10403 label_expr.X_add_number = 0; 10404 10405 expr1.X_op = O_constant; 10406 expr1.X_op_symbol = NULL; 10407 expr1.X_add_symbol = NULL; 10408 expr1.X_add_number = 1; 10409 align = 1; 10410 10411 switch (mask) 10412 { 10413 case M_DABS: 10414 dbl = 1; 10415 /* Fall through. */ 10416 case M_ABS: 10417 /* bgez $a0,1f 10418 move v0,$a0 10419 sub v0,$zero,$a0 10420 1: 10421 */ 10422 10423 start_noreorder (); 10424 10425 if (mips_opts.micromips) 10426 micromips_label_expr (&label_expr); 10427 else 10428 label_expr.X_add_number = 8; 10429 macro_build (&label_expr, "bgez", "s,p", op[1]); 10430 if (op[0] == op[1]) 10431 macro_build (NULL, "nop", ""); 10432 else 10433 move_register (op[0], op[1]); 10434 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); 10435 if (mips_opts.micromips) 10436 micromips_add_label (); 10437 10438 end_noreorder (); 10439 break; 10440 10441 case M_ADD_I: 10442 s = "addi"; 10443 s2 = "add"; 10444 if (ISA_IS_R6 (mips_opts.isa)) 10445 goto do_addi_i; 10446 else 10447 goto do_addi; 10448 case M_ADDU_I: 10449 s = "addiu"; 10450 s2 = "addu"; 10451 goto do_addi; 10452 case M_DADD_I: 10453 dbl = 1; 10454 s = "daddi"; 10455 s2 = "dadd"; 10456 if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) 10457 goto do_addi; 10458 if (imm_expr.X_add_number >= -0x200 10459 && imm_expr.X_add_number < 0x200 10460 && !ISA_IS_R6 (mips_opts.isa)) 10461 { 10462 macro_build (NULL, s, "t,r,.", op[0], op[1], 10463 (int) imm_expr.X_add_number); 10464 break; 10465 } 10466 goto do_addi_i; 10467 case M_DADDU_I: 10468 dbl = 1; 10469 s = "daddiu"; 10470 s2 = "daddu"; 10471 do_addi: 10472 if (imm_expr.X_add_number >= -0x8000 10473 && imm_expr.X_add_number < 0x8000) 10474 { 10475 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 10476 break; 10477 } 10478 do_addi_i: 10479 used_at = 1; 10480 load_register (AT, &imm_expr, dbl); 10481 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 10482 break; 10483 10484 case M_AND_I: 10485 s = "andi"; 10486 s2 = "and"; 10487 goto do_bit; 10488 case M_OR_I: 10489 s = "ori"; 10490 s2 = "or"; 10491 goto do_bit; 10492 case M_NOR_I: 10493 s = ""; 10494 s2 = "nor"; 10495 goto do_bit; 10496 case M_XOR_I: 10497 s = "xori"; 10498 s2 = "xor"; 10499 do_bit: 10500 if (imm_expr.X_add_number >= 0 10501 && imm_expr.X_add_number < 0x10000) 10502 { 10503 if (mask != M_NOR_I) 10504 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); 10505 else 10506 { 10507 macro_build (&imm_expr, "ori", "t,r,i", 10508 op[0], op[1], BFD_RELOC_LO16); 10509 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); 10510 } 10511 break; 10512 } 10513 10514 used_at = 1; 10515 load_register (AT, &imm_expr, GPR_SIZE == 64); 10516 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 10517 break; 10518 10519 case M_BALIGN: 10520 switch (imm_expr.X_add_number) 10521 { 10522 case 0: 10523 macro_build (NULL, "nop", ""); 10524 break; 10525 case 2: 10526 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); 10527 break; 10528 case 1: 10529 case 3: 10530 macro_build (NULL, "balign", "t,s,2", op[0], op[1], 10531 (int) imm_expr.X_add_number); 10532 break; 10533 default: 10534 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), 10535 (unsigned long) imm_expr.X_add_number); 10536 break; 10537 } 10538 break; 10539 10540 case M_BC1FL: 10541 case M_BC1TL: 10542 case M_BC2FL: 10543 case M_BC2TL: 10544 gas_assert (mips_opts.micromips); 10545 macro_build_branch_ccl (mask, &offset_expr, 10546 EXTRACT_OPERAND (1, BCC, *ip)); 10547 break; 10548 10549 case M_BEQ_I: 10550 case M_BEQL_I: 10551 case M_BNE_I: 10552 case M_BNEL_I: 10553 if (imm_expr.X_add_number == 0) 10554 op[1] = 0; 10555 else 10556 { 10557 op[1] = AT; 10558 used_at = 1; 10559 load_register (op[1], &imm_expr, GPR_SIZE == 64); 10560 } 10561 /* Fall through. */ 10562 case M_BEQL: 10563 case M_BNEL: 10564 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); 10565 break; 10566 10567 case M_BGEL: 10568 likely = 1; 10569 /* Fall through. */ 10570 case M_BGE: 10571 if (op[1] == 0) 10572 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); 10573 else if (op[0] == 0) 10574 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); 10575 else 10576 { 10577 used_at = 1; 10578 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10579 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10580 &offset_expr, AT, ZERO); 10581 } 10582 break; 10583 10584 case M_BGEZL: 10585 case M_BGEZALL: 10586 case M_BGTZL: 10587 case M_BLEZL: 10588 case M_BLTZL: 10589 case M_BLTZALL: 10590 macro_build_branch_rs (mask, &offset_expr, op[0]); 10591 break; 10592 10593 case M_BGTL_I: 10594 likely = 1; 10595 /* Fall through. */ 10596 case M_BGT_I: 10597 /* Check for > max integer. */ 10598 if (imm_expr.X_add_number >= GPR_SMAX) 10599 { 10600 do_false: 10601 /* Result is always false. */ 10602 if (! likely) 10603 macro_build (NULL, "nop", ""); 10604 else 10605 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); 10606 break; 10607 } 10608 ++imm_expr.X_add_number; 10609 /* Fall through. */ 10610 case M_BGE_I: 10611 case M_BGEL_I: 10612 if (mask == M_BGEL_I) 10613 likely = 1; 10614 if (imm_expr.X_add_number == 0) 10615 { 10616 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, 10617 &offset_expr, op[0]); 10618 break; 10619 } 10620 if (imm_expr.X_add_number == 1) 10621 { 10622 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, 10623 &offset_expr, op[0]); 10624 break; 10625 } 10626 if (imm_expr.X_add_number <= GPR_SMIN) 10627 { 10628 do_true: 10629 /* Result is always true. */ 10630 as_warn (_("branch %s is always true"), ip->insn_mo->name); 10631 macro_build (&offset_expr, "b", "p"); 10632 break; 10633 } 10634 used_at = 1; 10635 set_at (op[0], 0); 10636 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10637 &offset_expr, AT, ZERO); 10638 break; 10639 10640 case M_BGEUL: 10641 likely = 1; 10642 /* Fall through. */ 10643 case M_BGEU: 10644 if (op[1] == 0) 10645 goto do_true; 10646 else if (op[0] == 0) 10647 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10648 &offset_expr, ZERO, op[1]); 10649 else 10650 { 10651 used_at = 1; 10652 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10653 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10654 &offset_expr, AT, ZERO); 10655 } 10656 break; 10657 10658 case M_BGTUL_I: 10659 likely = 1; 10660 /* Fall through. */ 10661 case M_BGTU_I: 10662 if (op[0] == 0 10663 || (GPR_SIZE == 32 10664 && imm_expr.X_add_number == -1)) 10665 goto do_false; 10666 ++imm_expr.X_add_number; 10667 /* Fall through. */ 10668 case M_BGEU_I: 10669 case M_BGEUL_I: 10670 if (mask == M_BGEUL_I) 10671 likely = 1; 10672 if (imm_expr.X_add_number == 0) 10673 goto do_true; 10674 else if (imm_expr.X_add_number == 1) 10675 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10676 &offset_expr, op[0], ZERO); 10677 else 10678 { 10679 used_at = 1; 10680 set_at (op[0], 1); 10681 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10682 &offset_expr, AT, ZERO); 10683 } 10684 break; 10685 10686 case M_BGTL: 10687 likely = 1; 10688 /* Fall through. */ 10689 case M_BGT: 10690 if (op[1] == 0) 10691 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); 10692 else if (op[0] == 0) 10693 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); 10694 else 10695 { 10696 used_at = 1; 10697 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10698 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10699 &offset_expr, AT, ZERO); 10700 } 10701 break; 10702 10703 case M_BGTUL: 10704 likely = 1; 10705 /* Fall through. */ 10706 case M_BGTU: 10707 if (op[1] == 0) 10708 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10709 &offset_expr, op[0], ZERO); 10710 else if (op[0] == 0) 10711 goto do_false; 10712 else 10713 { 10714 used_at = 1; 10715 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10716 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10717 &offset_expr, AT, ZERO); 10718 } 10719 break; 10720 10721 case M_BLEL: 10722 likely = 1; 10723 /* Fall through. */ 10724 case M_BLE: 10725 if (op[1] == 0) 10726 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10727 else if (op[0] == 0) 10728 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); 10729 else 10730 { 10731 used_at = 1; 10732 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); 10733 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10734 &offset_expr, AT, ZERO); 10735 } 10736 break; 10737 10738 case M_BLEL_I: 10739 likely = 1; 10740 /* Fall through. */ 10741 case M_BLE_I: 10742 if (imm_expr.X_add_number >= GPR_SMAX) 10743 goto do_true; 10744 ++imm_expr.X_add_number; 10745 /* Fall through. */ 10746 case M_BLT_I: 10747 case M_BLTL_I: 10748 if (mask == M_BLTL_I) 10749 likely = 1; 10750 if (imm_expr.X_add_number == 0) 10751 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10752 else if (imm_expr.X_add_number == 1) 10753 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); 10754 else 10755 { 10756 used_at = 1; 10757 set_at (op[0], 0); 10758 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10759 &offset_expr, AT, ZERO); 10760 } 10761 break; 10762 10763 case M_BLEUL: 10764 likely = 1; 10765 /* Fall through. */ 10766 case M_BLEU: 10767 if (op[1] == 0) 10768 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10769 &offset_expr, op[0], ZERO); 10770 else if (op[0] == 0) 10771 goto do_true; 10772 else 10773 { 10774 used_at = 1; 10775 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); 10776 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10777 &offset_expr, AT, ZERO); 10778 } 10779 break; 10780 10781 case M_BLEUL_I: 10782 likely = 1; 10783 /* Fall through. */ 10784 case M_BLEU_I: 10785 if (op[0] == 0 10786 || (GPR_SIZE == 32 10787 && imm_expr.X_add_number == -1)) 10788 goto do_true; 10789 ++imm_expr.X_add_number; 10790 /* Fall through. */ 10791 case M_BLTU_I: 10792 case M_BLTUL_I: 10793 if (mask == M_BLTUL_I) 10794 likely = 1; 10795 if (imm_expr.X_add_number == 0) 10796 goto do_false; 10797 else if (imm_expr.X_add_number == 1) 10798 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, 10799 &offset_expr, op[0], ZERO); 10800 else 10801 { 10802 used_at = 1; 10803 set_at (op[0], 1); 10804 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10805 &offset_expr, AT, ZERO); 10806 } 10807 break; 10808 10809 case M_BLTL: 10810 likely = 1; 10811 /* Fall through. */ 10812 case M_BLT: 10813 if (op[1] == 0) 10814 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); 10815 else if (op[0] == 0) 10816 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); 10817 else 10818 { 10819 used_at = 1; 10820 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); 10821 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10822 &offset_expr, AT, ZERO); 10823 } 10824 break; 10825 10826 case M_BLTUL: 10827 likely = 1; 10828 /* Fall through. */ 10829 case M_BLTU: 10830 if (op[1] == 0) 10831 goto do_false; 10832 else if (op[0] == 0) 10833 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10834 &offset_expr, ZERO, op[1]); 10835 else 10836 { 10837 used_at = 1; 10838 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); 10839 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, 10840 &offset_expr, AT, ZERO); 10841 } 10842 break; 10843 10844 case M_DDIV_3: 10845 dbl = 1; 10846 /* Fall through. */ 10847 case M_DIV_3: 10848 s = "mflo"; 10849 goto do_div3; 10850 case M_DREM_3: 10851 dbl = 1; 10852 /* Fall through. */ 10853 case M_REM_3: 10854 s = "mfhi"; 10855 do_div3: 10856 if (op[2] == 0) 10857 { 10858 as_warn (_("divide by zero")); 10859 if (mips_trap) 10860 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10861 else 10862 macro_build (NULL, "break", BRK_FMT, 7); 10863 break; 10864 } 10865 10866 start_noreorder (); 10867 if (mips_trap) 10868 { 10869 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 10870 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10871 } 10872 else 10873 { 10874 if (mips_opts.micromips) 10875 micromips_label_expr (&label_expr); 10876 else 10877 label_expr.X_add_number = 8; 10878 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 10879 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); 10880 macro_build (NULL, "break", BRK_FMT, 7); 10881 if (mips_opts.micromips) 10882 micromips_add_label (); 10883 } 10884 expr1.X_add_number = -1; 10885 used_at = 1; 10886 load_register (AT, &expr1, dbl); 10887 if (mips_opts.micromips) 10888 micromips_label_expr (&label_expr); 10889 else 10890 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 10891 macro_build (&label_expr, "bne", "s,t,p", op[2], AT); 10892 if (dbl) 10893 { 10894 expr1.X_add_number = 1; 10895 load_register (AT, &expr1, dbl); 10896 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); 10897 } 10898 else 10899 { 10900 expr1.X_add_number = 0x80000000; 10901 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); 10902 } 10903 if (mips_trap) 10904 { 10905 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); 10906 /* We want to close the noreorder block as soon as possible, so 10907 that later insns are available for delay slot filling. */ 10908 end_noreorder (); 10909 } 10910 else 10911 { 10912 if (mips_opts.micromips) 10913 micromips_label_expr (&label_expr); 10914 else 10915 label_expr.X_add_number = 8; 10916 macro_build (&label_expr, "bne", "s,t,p", op[1], AT); 10917 macro_build (NULL, "nop", ""); 10918 10919 /* We want to close the noreorder block as soon as possible, so 10920 that later insns are available for delay slot filling. */ 10921 end_noreorder (); 10922 10923 macro_build (NULL, "break", BRK_FMT, 6); 10924 } 10925 if (mips_opts.micromips) 10926 micromips_add_label (); 10927 macro_build (NULL, s, MFHL_FMT, op[0]); 10928 break; 10929 10930 case M_DIV_3I: 10931 s = "div"; 10932 s2 = "mflo"; 10933 goto do_divi; 10934 case M_DIVU_3I: 10935 s = "divu"; 10936 s2 = "mflo"; 10937 goto do_divi; 10938 case M_REM_3I: 10939 s = "div"; 10940 s2 = "mfhi"; 10941 goto do_divi; 10942 case M_REMU_3I: 10943 s = "divu"; 10944 s2 = "mfhi"; 10945 goto do_divi; 10946 case M_DDIV_3I: 10947 dbl = 1; 10948 s = "ddiv"; 10949 s2 = "mflo"; 10950 goto do_divi; 10951 case M_DDIVU_3I: 10952 dbl = 1; 10953 s = "ddivu"; 10954 s2 = "mflo"; 10955 goto do_divi; 10956 case M_DREM_3I: 10957 dbl = 1; 10958 s = "ddiv"; 10959 s2 = "mfhi"; 10960 goto do_divi; 10961 case M_DREMU_3I: 10962 dbl = 1; 10963 s = "ddivu"; 10964 s2 = "mfhi"; 10965 do_divi: 10966 if (imm_expr.X_add_number == 0) 10967 { 10968 as_warn (_("divide by zero")); 10969 if (mips_trap) 10970 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); 10971 else 10972 macro_build (NULL, "break", BRK_FMT, 7); 10973 break; 10974 } 10975 if (imm_expr.X_add_number == 1) 10976 { 10977 if (strcmp (s2, "mflo") == 0) 10978 move_register (op[0], op[1]); 10979 else 10980 move_register (op[0], ZERO); 10981 break; 10982 } 10983 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') 10984 { 10985 if (strcmp (s2, "mflo") == 0) 10986 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); 10987 else 10988 move_register (op[0], ZERO); 10989 break; 10990 } 10991 10992 used_at = 1; 10993 load_register (AT, &imm_expr, dbl); 10994 macro_build (NULL, s, "z,s,t", op[1], AT); 10995 macro_build (NULL, s2, MFHL_FMT, op[0]); 10996 break; 10997 10998 case M_DIVU_3: 10999 s = "divu"; 11000 s2 = "mflo"; 11001 goto do_divu3; 11002 case M_REMU_3: 11003 s = "divu"; 11004 s2 = "mfhi"; 11005 goto do_divu3; 11006 case M_DDIVU_3: 11007 s = "ddivu"; 11008 s2 = "mflo"; 11009 goto do_divu3; 11010 case M_DREMU_3: 11011 s = "ddivu"; 11012 s2 = "mfhi"; 11013 do_divu3: 11014 start_noreorder (); 11015 if (mips_trap) 11016 { 11017 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); 11018 macro_build (NULL, s, "z,s,t", op[1], op[2]); 11019 /* We want to close the noreorder block as soon as possible, so 11020 that later insns are available for delay slot filling. */ 11021 end_noreorder (); 11022 } 11023 else 11024 { 11025 if (mips_opts.micromips) 11026 micromips_label_expr (&label_expr); 11027 else 11028 label_expr.X_add_number = 8; 11029 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); 11030 macro_build (NULL, s, "z,s,t", op[1], op[2]); 11031 11032 /* We want to close the noreorder block as soon as possible, so 11033 that later insns are available for delay slot filling. */ 11034 end_noreorder (); 11035 macro_build (NULL, "break", BRK_FMT, 7); 11036 if (mips_opts.micromips) 11037 micromips_add_label (); 11038 } 11039 macro_build (NULL, s2, MFHL_FMT, op[0]); 11040 break; 11041 11042 case M_DLCA_AB: 11043 dbl = 1; 11044 /* Fall through. */ 11045 case M_LCA_AB: 11046 call = 1; 11047 goto do_la; 11048 case M_DLA_AB: 11049 dbl = 1; 11050 /* Fall through. */ 11051 case M_LA_AB: 11052 do_la: 11053 /* Load the address of a symbol into a register. If breg is not 11054 zero, we then add a base register to it. */ 11055 11056 breg = op[2]; 11057 if (dbl && GPR_SIZE == 32) 11058 as_warn (_("dla used to load 32-bit register; recommend using la " 11059 "instead")); 11060 11061 if (!dbl && HAVE_64BIT_OBJECTS) 11062 as_warn (_("la used to load 64-bit address; recommend using dla " 11063 "instead")); 11064 11065 if (small_offset_p (0, align, 16)) 11066 { 11067 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, 11068 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); 11069 break; 11070 } 11071 11072 if (mips_opts.at && (op[0] == breg)) 11073 { 11074 tempreg = AT; 11075 used_at = 1; 11076 } 11077 else 11078 tempreg = op[0]; 11079 11080 if (offset_expr.X_op != O_symbol 11081 && offset_expr.X_op != O_constant) 11082 { 11083 as_bad (_("expression too complex")); 11084 offset_expr.X_op = O_constant; 11085 } 11086 11087 if (offset_expr.X_op == O_constant) 11088 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); 11089 else if (mips_pic == NO_PIC) 11090 { 11091 /* If this is a reference to a GP relative symbol, we want 11092 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 11093 Otherwise we want 11094 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 11095 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11096 If we have a constant, we need two instructions anyhow, 11097 so we may as well always use the latter form. 11098 11099 With 64bit address space and a usable $at we want 11100 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11101 lui $at,<sym> (BFD_RELOC_HI16_S) 11102 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11103 daddiu $at,<sym> (BFD_RELOC_LO16) 11104 dsll32 $tempreg,0 11105 daddu $tempreg,$tempreg,$at 11106 11107 If $at is already in use, we use a path which is suboptimal 11108 on superscalar processors. 11109 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 11110 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 11111 dsll $tempreg,16 11112 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 11113 dsll $tempreg,16 11114 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 11115 11116 For GP relative symbols in 64bit address space we can use 11117 the same sequence as in 32bit address space. */ 11118 if (HAVE_64BIT_SYMBOLS) 11119 { 11120 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11121 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11122 { 11123 relax_start (offset_expr.X_add_symbol); 11124 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11125 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 11126 relax_switch (); 11127 } 11128 11129 if (used_at == 0 && mips_opts.at) 11130 { 11131 macro_build (&offset_expr, "lui", LUI_FMT, 11132 tempreg, BFD_RELOC_MIPS_HIGHEST); 11133 macro_build (&offset_expr, "lui", LUI_FMT, 11134 AT, BFD_RELOC_HI16_S); 11135 macro_build (&offset_expr, "daddiu", "t,r,j", 11136 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 11137 macro_build (&offset_expr, "daddiu", "t,r,j", 11138 AT, AT, BFD_RELOC_LO16); 11139 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 11140 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 11141 used_at = 1; 11142 } 11143 else 11144 { 11145 macro_build (&offset_expr, "lui", LUI_FMT, 11146 tempreg, BFD_RELOC_MIPS_HIGHEST); 11147 macro_build (&offset_expr, "daddiu", "t,r,j", 11148 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 11149 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11150 macro_build (&offset_expr, "daddiu", "t,r,j", 11151 tempreg, tempreg, BFD_RELOC_HI16_S); 11152 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 11153 macro_build (&offset_expr, "daddiu", "t,r,j", 11154 tempreg, tempreg, BFD_RELOC_LO16); 11155 } 11156 11157 if (mips_relax.sequence) 11158 relax_end (); 11159 } 11160 else 11161 { 11162 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 11163 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 11164 { 11165 relax_start (offset_expr.X_add_symbol); 11166 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11167 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 11168 relax_switch (); 11169 } 11170 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 11171 as_bad (_("offset too large")); 11172 macro_build_lui (&offset_expr, tempreg); 11173 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11174 tempreg, tempreg, BFD_RELOC_LO16); 11175 if (mips_relax.sequence) 11176 relax_end (); 11177 } 11178 } 11179 else if (!mips_big_got && !HAVE_NEWABI) 11180 { 11181 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 11182 11183 /* If this is a reference to an external symbol, and there 11184 is no constant, we want 11185 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11186 or for lca or if tempreg is PIC_CALL_REG 11187 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11188 For a local symbol, we want 11189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11190 nop 11191 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11192 11193 If we have a small constant, and this is a reference to 11194 an external symbol, we want 11195 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11196 nop 11197 addiu $tempreg,$tempreg,<constant> 11198 For a local symbol, we want the same instruction 11199 sequence, but we output a BFD_RELOC_LO16 reloc on the 11200 addiu instruction. 11201 11202 If we have a large constant, and this is a reference to 11203 an external symbol, we want 11204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11205 lui $at,<hiconstant> 11206 addiu $at,$at,<loconstant> 11207 addu $tempreg,$tempreg,$at 11208 For a local symbol, we want the same instruction 11209 sequence, but we output a BFD_RELOC_LO16 reloc on the 11210 addiu instruction. 11211 */ 11212 11213 if (offset_expr.X_add_number == 0) 11214 { 11215 if (mips_pic == SVR4_PIC 11216 && breg == 0 11217 && (call || tempreg == PIC_CALL_REG)) 11218 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 11219 11220 relax_start (offset_expr.X_add_symbol); 11221 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11222 lw_reloc_type, mips_gp_register); 11223 if (breg != 0) 11224 { 11225 /* We're going to put in an addu instruction using 11226 tempreg, so we may as well insert the nop right 11227 now. */ 11228 load_delay_nop (); 11229 } 11230 relax_switch (); 11231 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11232 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 11233 load_delay_nop (); 11234 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11235 tempreg, tempreg, BFD_RELOC_LO16); 11236 relax_end (); 11237 /* FIXME: If breg == 0, and the next instruction uses 11238 $tempreg, then if this variant case is used an extra 11239 nop will be generated. */ 11240 } 11241 else if (offset_expr.X_add_number >= -0x8000 11242 && offset_expr.X_add_number < 0x8000) 11243 { 11244 load_got_offset (tempreg, &offset_expr); 11245 load_delay_nop (); 11246 add_got_offset (tempreg, &offset_expr); 11247 } 11248 else 11249 { 11250 expr1.X_add_number = offset_expr.X_add_number; 11251 offset_expr.X_add_number = 11252 SEXT_16BIT (offset_expr.X_add_number); 11253 load_got_offset (tempreg, &offset_expr); 11254 offset_expr.X_add_number = expr1.X_add_number; 11255 /* If we are going to add in a base register, and the 11256 target register and the base register are the same, 11257 then we are using AT as a temporary register. Since 11258 we want to load the constant into AT, we add our 11259 current AT (from the global offset table) and the 11260 register into the register now, and pretend we were 11261 not using a base register. */ 11262 if (breg == op[0]) 11263 { 11264 load_delay_nop (); 11265 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11266 op[0], AT, breg); 11267 breg = 0; 11268 tempreg = op[0]; 11269 } 11270 add_got_offset_hilo (tempreg, &offset_expr, AT); 11271 used_at = 1; 11272 } 11273 } 11274 else if (!mips_big_got && HAVE_NEWABI) 11275 { 11276 int add_breg_early = 0; 11277 11278 /* If this is a reference to an external, and there is no 11279 constant, or local symbol (*), with or without a 11280 constant, we want 11281 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 11282 or for lca or if tempreg is PIC_CALL_REG 11283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11284 11285 If we have a small constant, and this is a reference to 11286 an external symbol, we want 11287 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 11288 addiu $tempreg,$tempreg,<constant> 11289 11290 If we have a large constant, and this is a reference to 11291 an external symbol, we want 11292 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 11293 lui $at,<hiconstant> 11294 addiu $at,$at,<loconstant> 11295 addu $tempreg,$tempreg,$at 11296 11297 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 11298 local symbols, even though it introduces an additional 11299 instruction. */ 11300 11301 if (offset_expr.X_add_number) 11302 { 11303 expr1.X_add_number = offset_expr.X_add_number; 11304 offset_expr.X_add_number = 0; 11305 11306 relax_start (offset_expr.X_add_symbol); 11307 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11308 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 11309 11310 if (expr1.X_add_number >= -0x8000 11311 && expr1.X_add_number < 0x8000) 11312 { 11313 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 11314 tempreg, tempreg, BFD_RELOC_LO16); 11315 } 11316 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 11317 { 11318 unsigned int dreg; 11319 11320 /* If we are going to add in a base register, and the 11321 target register and the base register are the same, 11322 then we are using AT as a temporary register. Since 11323 we want to load the constant into AT, we add our 11324 current AT (from the global offset table) and the 11325 register into the register now, and pretend we were 11326 not using a base register. */ 11327 if (breg != op[0]) 11328 dreg = tempreg; 11329 else 11330 { 11331 gas_assert (tempreg == AT); 11332 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11333 op[0], AT, breg); 11334 dreg = op[0]; 11335 add_breg_early = 1; 11336 } 11337 11338 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 11339 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11340 dreg, dreg, AT); 11341 11342 used_at = 1; 11343 } 11344 else 11345 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 11346 11347 relax_switch (); 11348 offset_expr.X_add_number = expr1.X_add_number; 11349 11350 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11351 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 11352 if (add_breg_early) 11353 { 11354 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11355 op[0], tempreg, breg); 11356 breg = 0; 11357 tempreg = op[0]; 11358 } 11359 relax_end (); 11360 } 11361 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 11362 { 11363 relax_start (offset_expr.X_add_symbol); 11364 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11365 BFD_RELOC_MIPS_CALL16, mips_gp_register); 11366 relax_switch (); 11367 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11368 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 11369 relax_end (); 11370 } 11371 else 11372 { 11373 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11374 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 11375 } 11376 } 11377 else if (mips_big_got && !HAVE_NEWABI) 11378 { 11379 int gpdelay; 11380 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 11381 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 11382 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 11383 11384 /* This is the large GOT case. If this is a reference to an 11385 external symbol, and there is no constant, we want 11386 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11387 addu $tempreg,$tempreg,$gp 11388 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11389 or for lca or if tempreg is PIC_CALL_REG 11390 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11391 addu $tempreg,$tempreg,$gp 11392 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 11393 For a local symbol, we want 11394 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11395 nop 11396 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 11397 11398 If we have a small constant, and this is a reference to 11399 an external symbol, we want 11400 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11401 addu $tempreg,$tempreg,$gp 11402 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11403 nop 11404 addiu $tempreg,$tempreg,<constant> 11405 For a local symbol, we want 11406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11407 nop 11408 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 11409 11410 If we have a large constant, and this is a reference to 11411 an external symbol, we want 11412 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11413 addu $tempreg,$tempreg,$gp 11414 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11415 lui $at,<hiconstant> 11416 addiu $at,$at,<loconstant> 11417 addu $tempreg,$tempreg,$at 11418 For a local symbol, we want 11419 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11420 lui $at,<hiconstant> 11421 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 11422 addu $tempreg,$tempreg,$at 11423 */ 11424 11425 expr1.X_add_number = offset_expr.X_add_number; 11426 offset_expr.X_add_number = 0; 11427 relax_start (offset_expr.X_add_symbol); 11428 gpdelay = reg_needs_delay (mips_gp_register); 11429 if (expr1.X_add_number == 0 && breg == 0 11430 && (call || tempreg == PIC_CALL_REG)) 11431 { 11432 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 11433 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 11434 } 11435 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 11436 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11437 tempreg, tempreg, mips_gp_register); 11438 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11439 tempreg, lw_reloc_type, tempreg); 11440 if (expr1.X_add_number == 0) 11441 { 11442 if (breg != 0) 11443 { 11444 /* We're going to put in an addu instruction using 11445 tempreg, so we may as well insert the nop right 11446 now. */ 11447 load_delay_nop (); 11448 } 11449 } 11450 else if (expr1.X_add_number >= -0x8000 11451 && expr1.X_add_number < 0x8000) 11452 { 11453 load_delay_nop (); 11454 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 11455 tempreg, tempreg, BFD_RELOC_LO16); 11456 } 11457 else 11458 { 11459 unsigned int dreg; 11460 11461 /* If we are going to add in a base register, and the 11462 target register and the base register are the same, 11463 then we are using AT as a temporary register. Since 11464 we want to load the constant into AT, we add our 11465 current AT (from the global offset table) and the 11466 register into the register now, and pretend we were 11467 not using a base register. */ 11468 if (breg != op[0]) 11469 dreg = tempreg; 11470 else 11471 { 11472 gas_assert (tempreg == AT); 11473 load_delay_nop (); 11474 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11475 op[0], AT, breg); 11476 dreg = op[0]; 11477 } 11478 11479 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 11480 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 11481 11482 used_at = 1; 11483 } 11484 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); 11485 relax_switch (); 11486 11487 if (gpdelay) 11488 { 11489 /* This is needed because this instruction uses $gp, but 11490 the first instruction on the main stream does not. */ 11491 macro_build (NULL, "nop", ""); 11492 } 11493 11494 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11495 local_reloc_type, mips_gp_register); 11496 if (expr1.X_add_number >= -0x8000 11497 && expr1.X_add_number < 0x8000) 11498 { 11499 load_delay_nop (); 11500 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11501 tempreg, tempreg, BFD_RELOC_LO16); 11502 /* FIXME: If add_number is 0, and there was no base 11503 register, the external symbol case ended with a load, 11504 so if the symbol turns out to not be external, and 11505 the next instruction uses tempreg, an unnecessary nop 11506 will be inserted. */ 11507 } 11508 else 11509 { 11510 if (breg == op[0]) 11511 { 11512 /* We must add in the base register now, as in the 11513 external symbol case. */ 11514 gas_assert (tempreg == AT); 11515 load_delay_nop (); 11516 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11517 op[0], AT, breg); 11518 tempreg = op[0]; 11519 /* We set breg to 0 because we have arranged to add 11520 it in in both cases. */ 11521 breg = 0; 11522 } 11523 11524 macro_build_lui (&expr1, AT); 11525 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11526 AT, AT, BFD_RELOC_LO16); 11527 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11528 tempreg, tempreg, AT); 11529 used_at = 1; 11530 } 11531 relax_end (); 11532 } 11533 else if (mips_big_got && HAVE_NEWABI) 11534 { 11535 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 11536 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 11537 int add_breg_early = 0; 11538 11539 /* This is the large GOT case. If this is a reference to an 11540 external symbol, and there is no constant, we want 11541 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11542 add $tempreg,$tempreg,$gp 11543 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11544 or for lca or if tempreg is PIC_CALL_REG 11545 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11546 add $tempreg,$tempreg,$gp 11547 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 11548 11549 If we have a small constant, and this is a reference to 11550 an external symbol, we want 11551 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11552 add $tempreg,$tempreg,$gp 11553 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11554 addi $tempreg,$tempreg,<constant> 11555 11556 If we have a large constant, and this is a reference to 11557 an external symbol, we want 11558 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 11559 addu $tempreg,$tempreg,$gp 11560 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 11561 lui $at,<hiconstant> 11562 addi $at,$at,<loconstant> 11563 add $tempreg,$tempreg,$at 11564 11565 If we have NewABI, and we know it's a local symbol, we want 11566 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 11567 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 11568 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 11569 11570 relax_start (offset_expr.X_add_symbol); 11571 11572 expr1.X_add_number = offset_expr.X_add_number; 11573 offset_expr.X_add_number = 0; 11574 11575 if (expr1.X_add_number == 0 && breg == 0 11576 && (call || tempreg == PIC_CALL_REG)) 11577 { 11578 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 11579 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 11580 } 11581 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); 11582 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11583 tempreg, tempreg, mips_gp_register); 11584 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11585 tempreg, lw_reloc_type, tempreg); 11586 11587 if (expr1.X_add_number == 0) 11588 ; 11589 else if (expr1.X_add_number >= -0x8000 11590 && expr1.X_add_number < 0x8000) 11591 { 11592 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 11593 tempreg, tempreg, BFD_RELOC_LO16); 11594 } 11595 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 11596 { 11597 unsigned int dreg; 11598 11599 /* If we are going to add in a base register, and the 11600 target register and the base register are the same, 11601 then we are using AT as a temporary register. Since 11602 we want to load the constant into AT, we add our 11603 current AT (from the global offset table) and the 11604 register into the register now, and pretend we were 11605 not using a base register. */ 11606 if (breg != op[0]) 11607 dreg = tempreg; 11608 else 11609 { 11610 gas_assert (tempreg == AT); 11611 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11612 op[0], AT, breg); 11613 dreg = op[0]; 11614 add_breg_early = 1; 11615 } 11616 11617 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 11618 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 11619 11620 used_at = 1; 11621 } 11622 else 11623 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 11624 11625 relax_switch (); 11626 offset_expr.X_add_number = expr1.X_add_number; 11627 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 11628 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 11629 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 11630 tempreg, BFD_RELOC_MIPS_GOT_OFST); 11631 if (add_breg_early) 11632 { 11633 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 11634 op[0], tempreg, breg); 11635 breg = 0; 11636 tempreg = op[0]; 11637 } 11638 relax_end (); 11639 } 11640 else 11641 abort (); 11642 11643 if (breg != 0) 11644 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); 11645 break; 11646 11647 case M_JR_S: 11648 macro_build_jrpatch (&expr1, op[2]); 11649 macro_build (NULL, "jr", "s", op[2]); 11650 return; /* didn't modify $at */ 11651 11652 case M_J_S: 11653 macro_build_jrpatch (&expr1, op[2]); 11654 macro_build (NULL, "j", "s", op[2]); 11655 return; /* didn't modify $at */ 11656 11657 case M_JALR_S: 11658 macro_build_jrpatch (&expr1, op[2]); 11659 macro_build (NULL, "jalr", "s", op[2]); 11660 return; /* didn't modify $at */ 11661 11662 case M_JALR_DS: 11663 macro_build_jrpatch (&expr1, op[2]); 11664 macro_build (NULL, "jalr", "d,s", op[0], op[2]); 11665 return; /* didn't modify $at */ 11666 11667 case M_MSGSND: 11668 gas_assert (!mips_opts.micromips); 11669 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); 11670 break; 11671 11672 case M_MSGLD: 11673 gas_assert (!mips_opts.micromips); 11674 macro_build (NULL, "c2", "C", 0x02); 11675 break; 11676 11677 case M_MSGLD_T: 11678 gas_assert (!mips_opts.micromips); 11679 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); 11680 break; 11681 11682 case M_MSGWAIT: 11683 gas_assert (!mips_opts.micromips); 11684 macro_build (NULL, "c2", "C", 3); 11685 break; 11686 11687 case M_MSGWAIT_T: 11688 gas_assert (!mips_opts.micromips); 11689 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); 11690 break; 11691 11692 case M_J_A: 11693 /* The j instruction may not be used in PIC code, since it 11694 requires an absolute address. We convert it to a b 11695 instruction. */ 11696 if (mips_pic == NO_PIC) 11697 macro_build (&offset_expr, "j", "a"); 11698 else 11699 macro_build (&offset_expr, "b", "p"); 11700 break; 11701 11702 /* The jal instructions must be handled as macros because when 11703 generating PIC code they expand to multi-instruction 11704 sequences. Normally they are simple instructions. */ 11705 case M_JALS_1: 11706 op[1] = op[0]; 11707 op[0] = RA; 11708 /* Fall through. */ 11709 case M_JALS_2: 11710 gas_assert (mips_opts.micromips); 11711 if (mips_opts.insn32) 11712 { 11713 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11714 break; 11715 } 11716 jals = 1; 11717 goto jal; 11718 case M_JAL_1: 11719 op[1] = op[0]; 11720 op[0] = RA; 11721 /* Fall through. */ 11722 case M_JAL_2: 11723 jal: 11724 if (mips_pic == NO_PIC) 11725 { 11726 s = jals ? "jalrs" : "jalr"; 11727 if (mips_opts.micromips 11728 && !mips_opts.insn32 11729 && op[0] == RA 11730 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11731 macro_build (NULL, s, "mj", op[1]); 11732 else 11733 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11734 } 11735 else 11736 { 11737 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI 11738 && mips_cprestore_offset >= 0); 11739 11740 if (op[1] != PIC_CALL_REG) 11741 as_warn (_("MIPS PIC call to register other than $25")); 11742 11743 s = ((mips_opts.micromips 11744 && !mips_opts.insn32 11745 && (!mips_opts.noreorder || cprestore)) 11746 ? "jalrs" : "jalr"); 11747 if (mips_opts.micromips 11748 && !mips_opts.insn32 11749 && op[0] == RA 11750 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) 11751 macro_build (NULL, s, "mj", op[1]); 11752 else 11753 macro_build (NULL, s, JALR_FMT, op[0], op[1]); 11754 if (mips_pic == SVR4_PIC && !HAVE_NEWABI) 11755 { 11756 if (mips_cprestore_offset < 0) 11757 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11758 else 11759 { 11760 if (!mips_frame_reg_valid) 11761 { 11762 as_warn (_("no .frame pseudo-op used in PIC code")); 11763 /* Quiet this warning. */ 11764 mips_frame_reg_valid = 1; 11765 } 11766 if (!mips_cprestore_valid) 11767 { 11768 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11769 /* Quiet this warning. */ 11770 mips_cprestore_valid = 1; 11771 } 11772 if (mips_opts.noreorder) 11773 macro_build (NULL, "nop", ""); 11774 expr1.X_add_number = mips_cprestore_offset; 11775 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11776 mips_gp_register, 11777 mips_frame_reg, 11778 HAVE_64BIT_ADDRESSES); 11779 } 11780 } 11781 } 11782 11783 break; 11784 11785 case M_JALS_A: 11786 gas_assert (mips_opts.micromips); 11787 if (mips_opts.insn32) 11788 { 11789 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); 11790 break; 11791 } 11792 jals = 1; 11793 /* Fall through. */ 11794 case M_JAL_A: 11795 if (mips_pic == NO_PIC) 11796 macro_build (&offset_expr, jals ? "jals" : "jal", "a"); 11797 else if (mips_pic == SVR4_PIC) 11798 { 11799 /* If this is a reference to an external symbol, and we are 11800 using a small GOT, we want 11801 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 11802 nop 11803 jalr $ra,$25 11804 nop 11805 lw $gp,cprestore($sp) 11806 The cprestore value is set using the .cprestore 11807 pseudo-op. If we are using a big GOT, we want 11808 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 11809 addu $25,$25,$gp 11810 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 11811 nop 11812 jalr $ra,$25 11813 nop 11814 lw $gp,cprestore($sp) 11815 If the symbol is not external, we want 11816 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 11817 nop 11818 addiu $25,$25,<sym> (BFD_RELOC_LO16) 11819 jalr $ra,$25 11820 nop 11821 lw $gp,cprestore($sp) 11822 11823 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 11824 sequences above, minus nops, unless the symbol is local, 11825 which enables us to use GOT_PAGE/GOT_OFST (big got) or 11826 GOT_DISP. */ 11827 if (HAVE_NEWABI) 11828 { 11829 if (!mips_big_got) 11830 { 11831 relax_start (offset_expr.X_add_symbol); 11832 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11833 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11834 mips_gp_register); 11835 relax_switch (); 11836 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11837 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 11838 mips_gp_register); 11839 relax_end (); 11840 } 11841 else 11842 { 11843 relax_start (offset_expr.X_add_symbol); 11844 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11845 BFD_RELOC_MIPS_CALL_HI16); 11846 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11847 PIC_CALL_REG, mips_gp_register); 11848 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11849 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11850 PIC_CALL_REG); 11851 relax_switch (); 11852 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11853 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 11854 mips_gp_register); 11855 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11856 PIC_CALL_REG, PIC_CALL_REG, 11857 BFD_RELOC_MIPS_GOT_OFST); 11858 relax_end (); 11859 } 11860 11861 macro_build_jalr (&offset_expr, 0); 11862 } 11863 else 11864 { 11865 relax_start (offset_expr.X_add_symbol); 11866 if (!mips_big_got) 11867 { 11868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11869 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 11870 mips_gp_register); 11871 load_delay_nop (); 11872 relax_switch (); 11873 } 11874 else 11875 { 11876 int gpdelay; 11877 11878 gpdelay = reg_needs_delay (mips_gp_register); 11879 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, 11880 BFD_RELOC_MIPS_CALL_HI16); 11881 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 11882 PIC_CALL_REG, mips_gp_register); 11883 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11884 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 11885 PIC_CALL_REG); 11886 load_delay_nop (); 11887 relax_switch (); 11888 if (gpdelay) 11889 macro_build (NULL, "nop", ""); 11890 } 11891 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 11892 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 11893 mips_gp_register); 11894 load_delay_nop (); 11895 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 11896 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 11897 relax_end (); 11898 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); 11899 11900 if (mips_cprestore_offset < 0) 11901 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11902 else 11903 { 11904 if (!mips_frame_reg_valid) 11905 { 11906 as_warn (_("no .frame pseudo-op used in PIC code")); 11907 /* Quiet this warning. */ 11908 mips_frame_reg_valid = 1; 11909 } 11910 if (!mips_cprestore_valid) 11911 { 11912 as_warn (_("no .cprestore pseudo-op used in PIC code")); 11913 /* Quiet this warning. */ 11914 mips_cprestore_valid = 1; 11915 } 11916 if (mips_opts.noreorder) 11917 macro_build (NULL, "nop", ""); 11918 expr1.X_add_number = mips_cprestore_offset; 11919 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 11920 mips_gp_register, 11921 mips_frame_reg, 11922 HAVE_64BIT_ADDRESSES); 11923 } 11924 } 11925 } 11926 else if (mips_pic == VXWORKS_PIC) 11927 as_bad (_("non-PIC jump used in PIC library")); 11928 else 11929 abort (); 11930 11931 break; 11932 11933 case M_LBUE_AB: 11934 s = "lbue"; 11935 fmt = "t,+j(b)"; 11936 offbits = 9; 11937 goto ld_st; 11938 case M_LHUE_AB: 11939 s = "lhue"; 11940 fmt = "t,+j(b)"; 11941 offbits = 9; 11942 goto ld_st; 11943 case M_LBE_AB: 11944 s = "lbe"; 11945 fmt = "t,+j(b)"; 11946 offbits = 9; 11947 goto ld_st; 11948 case M_LHE_AB: 11949 s = "lhe"; 11950 fmt = "t,+j(b)"; 11951 offbits = 9; 11952 goto ld_st; 11953 case M_LLE_AB: 11954 s = "lle"; 11955 fmt = "t,+j(b)"; 11956 offbits = 9; 11957 goto ld_st; 11958 case M_LWE_AB: 11959 s = "lwe"; 11960 fmt = "t,+j(b)"; 11961 offbits = 9; 11962 goto ld_st; 11963 case M_LWLE_AB: 11964 s = "lwle"; 11965 fmt = "t,+j(b)"; 11966 offbits = 9; 11967 goto ld_st; 11968 case M_LWRE_AB: 11969 s = "lwre"; 11970 fmt = "t,+j(b)"; 11971 offbits = 9; 11972 goto ld_st; 11973 case M_SBE_AB: 11974 s = "sbe"; 11975 fmt = "t,+j(b)"; 11976 offbits = 9; 11977 goto ld_st; 11978 case M_SCE_AB: 11979 s = "sce"; 11980 fmt = "t,+j(b)"; 11981 offbits = 9; 11982 goto ld_st; 11983 case M_SHE_AB: 11984 s = "she"; 11985 fmt = "t,+j(b)"; 11986 offbits = 9; 11987 goto ld_st; 11988 case M_SWE_AB: 11989 s = "swe"; 11990 fmt = "t,+j(b)"; 11991 offbits = 9; 11992 goto ld_st; 11993 case M_SWLE_AB: 11994 s = "swle"; 11995 fmt = "t,+j(b)"; 11996 offbits = 9; 11997 goto ld_st; 11998 case M_SWRE_AB: 11999 s = "swre"; 12000 fmt = "t,+j(b)"; 12001 offbits = 9; 12002 goto ld_st; 12003 case M_ACLR_AB: 12004 s = "aclr"; 12005 fmt = "\\,~(b)"; 12006 offbits = 12; 12007 goto ld_st; 12008 case M_ASET_AB: 12009 s = "aset"; 12010 fmt = "\\,~(b)"; 12011 offbits = 12; 12012 goto ld_st; 12013 case M_LB_AB: 12014 s = "lb"; 12015 fmt = "t,o(b)"; 12016 goto ld; 12017 case M_LBU_AB: 12018 s = "lbu"; 12019 fmt = "t,o(b)"; 12020 goto ld; 12021 case M_LH_AB: 12022 s = "lh"; 12023 fmt = "t,o(b)"; 12024 goto ld; 12025 case M_LHU_AB: 12026 s = "lhu"; 12027 fmt = "t,o(b)"; 12028 goto ld; 12029 case M_LW_AB: 12030 s = "lw"; 12031 fmt = "t,o(b)"; 12032 goto ld; 12033 case M_LWC0_AB: 12034 gas_assert (!mips_opts.micromips); 12035 s = "lwc0"; 12036 fmt = "E,o(b)"; 12037 /* Itbl support may require additional care here. */ 12038 coproc = 1; 12039 goto ld_st; 12040 case M_LWC1_AB: 12041 s = "lwc1"; 12042 fmt = "T,o(b)"; 12043 /* Itbl support may require additional care here. */ 12044 coproc = 1; 12045 goto ld_st; 12046 case M_LWC2_AB: 12047 s = "lwc2"; 12048 fmt = COP12_FMT; 12049 offbits = (mips_opts.micromips ? 12 12050 : ISA_IS_R6 (mips_opts.isa) ? 11 12051 : 16); 12052 /* Itbl support may require additional care here. */ 12053 coproc = 1; 12054 goto ld_st; 12055 case M_LWC3_AB: 12056 gas_assert (!mips_opts.micromips); 12057 s = "lwc3"; 12058 fmt = "E,o(b)"; 12059 /* Itbl support may require additional care here. */ 12060 coproc = 1; 12061 goto ld_st; 12062 case M_LWL_AB: 12063 s = "lwl"; 12064 fmt = MEM12_FMT; 12065 offbits = (mips_opts.micromips ? 12 : 16); 12066 goto ld_st; 12067 case M_LWR_AB: 12068 s = "lwr"; 12069 fmt = MEM12_FMT; 12070 offbits = (mips_opts.micromips ? 12 : 16); 12071 goto ld_st; 12072 case M_LDC1_AB: 12073 s = "ldc1"; 12074 fmt = "T,o(b)"; 12075 /* Itbl support may require additional care here. */ 12076 coproc = 1; 12077 goto ld_st; 12078 case M_LDC2_AB: 12079 s = "ldc2"; 12080 fmt = COP12_FMT; 12081 offbits = (mips_opts.micromips ? 12 12082 : ISA_IS_R6 (mips_opts.isa) ? 11 12083 : 16); 12084 /* Itbl support may require additional care here. */ 12085 coproc = 1; 12086 goto ld_st; 12087 case M_LQC2_AB: 12088 s = "lqc2"; 12089 fmt = "+7,o(b)"; 12090 /* Itbl support may require additional care here. */ 12091 coproc = 1; 12092 goto ld_st; 12093 case M_LDC3_AB: 12094 s = "ldc3"; 12095 fmt = "E,o(b)"; 12096 /* Itbl support may require additional care here. */ 12097 coproc = 1; 12098 goto ld_st; 12099 case M_LDL_AB: 12100 s = "ldl"; 12101 fmt = MEM12_FMT; 12102 offbits = (mips_opts.micromips ? 12 : 16); 12103 goto ld_st; 12104 case M_LDR_AB: 12105 s = "ldr"; 12106 fmt = MEM12_FMT; 12107 offbits = (mips_opts.micromips ? 12 : 16); 12108 goto ld_st; 12109 case M_LL_AB: 12110 s = "ll"; 12111 fmt = LL_SC_FMT; 12112 offbits = (mips_opts.micromips ? 12 12113 : ISA_IS_R6 (mips_opts.isa) ? 9 12114 : 16); 12115 goto ld; 12116 case M_LLD_AB: 12117 s = "lld"; 12118 fmt = LL_SC_FMT; 12119 offbits = (mips_opts.micromips ? 12 12120 : ISA_IS_R6 (mips_opts.isa) ? 9 12121 : 16); 12122 goto ld; 12123 case M_LWU_AB: 12124 s = "lwu"; 12125 fmt = MEM12_FMT; 12126 offbits = (mips_opts.micromips ? 12 : 16); 12127 goto ld; 12128 case M_LWP_AB: 12129 gas_assert (mips_opts.micromips); 12130 s = "lwp"; 12131 fmt = "t,~(b)"; 12132 offbits = 12; 12133 lp = 1; 12134 goto ld; 12135 case M_LDP_AB: 12136 gas_assert (mips_opts.micromips); 12137 s = "ldp"; 12138 fmt = "t,~(b)"; 12139 offbits = 12; 12140 lp = 1; 12141 goto ld; 12142 case M_LLDP_AB: 12143 case M_LLWP_AB: 12144 case M_LLWPE_AB: 12145 s = ip->insn_mo->name; 12146 fmt = "t,d,s"; 12147 ll_sc_paired = 1; 12148 offbits = 0; 12149 goto ld; 12150 case M_LWM_AB: 12151 gas_assert (mips_opts.micromips); 12152 s = "lwm"; 12153 fmt = "n,~(b)"; 12154 offbits = 12; 12155 goto ld_st; 12156 case M_LDM_AB: 12157 gas_assert (mips_opts.micromips); 12158 s = "ldm"; 12159 fmt = "n,~(b)"; 12160 offbits = 12; 12161 goto ld_st; 12162 12163 ld: 12164 /* Try to use one the the load registers to compute the base address. 12165 We don't want to use $0 as tempreg. */ 12166 if (ll_sc_paired) 12167 { 12168 if ((op[0] == ZERO && op[3] == op[1]) 12169 || (op[1] == ZERO && op[3] == op[0]) 12170 || (op[0] == ZERO && op[1] == ZERO)) 12171 goto ld_st; 12172 else if (op[0] != op[3] && op[0] != ZERO) 12173 tempreg = op[0]; 12174 else 12175 tempreg = op[1]; 12176 } 12177 else 12178 { 12179 if (op[2] == op[0] + lp || op[0] + lp == ZERO) 12180 goto ld_st; 12181 else 12182 tempreg = op[0] + lp; 12183 } 12184 goto ld_noat; 12185 12186 case M_SB_AB: 12187 s = "sb"; 12188 fmt = "t,o(b)"; 12189 goto ld_st; 12190 case M_SH_AB: 12191 s = "sh"; 12192 fmt = "t,o(b)"; 12193 goto ld_st; 12194 case M_SW_AB: 12195 s = "sw"; 12196 fmt = "t,o(b)"; 12197 goto ld_st; 12198 case M_SWC0_AB: 12199 gas_assert (!mips_opts.micromips); 12200 s = "swc0"; 12201 fmt = "E,o(b)"; 12202 /* Itbl support may require additional care here. */ 12203 coproc = 1; 12204 goto ld_st; 12205 case M_SWC1_AB: 12206 s = "swc1"; 12207 fmt = "T,o(b)"; 12208 /* Itbl support may require additional care here. */ 12209 coproc = 1; 12210 goto ld_st; 12211 case M_SWC2_AB: 12212 s = "swc2"; 12213 fmt = COP12_FMT; 12214 offbits = (mips_opts.micromips ? 12 12215 : ISA_IS_R6 (mips_opts.isa) ? 11 12216 : 16); 12217 /* Itbl support may require additional care here. */ 12218 coproc = 1; 12219 goto ld_st; 12220 case M_SWC3_AB: 12221 gas_assert (!mips_opts.micromips); 12222 s = "swc3"; 12223 fmt = "E,o(b)"; 12224 /* Itbl support may require additional care here. */ 12225 coproc = 1; 12226 goto ld_st; 12227 case M_SWL_AB: 12228 s = "swl"; 12229 fmt = MEM12_FMT; 12230 offbits = (mips_opts.micromips ? 12 : 16); 12231 goto ld_st; 12232 case M_SWR_AB: 12233 s = "swr"; 12234 fmt = MEM12_FMT; 12235 offbits = (mips_opts.micromips ? 12 : 16); 12236 goto ld_st; 12237 case M_SC_AB: 12238 s = "sc"; 12239 fmt = LL_SC_FMT; 12240 offbits = (mips_opts.micromips ? 12 12241 : ISA_IS_R6 (mips_opts.isa) ? 9 12242 : 16); 12243 goto ld_st; 12244 case M_SCD_AB: 12245 s = "scd"; 12246 fmt = LL_SC_FMT; 12247 offbits = (mips_opts.micromips ? 12 12248 : ISA_IS_R6 (mips_opts.isa) ? 9 12249 : 16); 12250 goto ld_st; 12251 case M_SCDP_AB: 12252 case M_SCWP_AB: 12253 case M_SCWPE_AB: 12254 s = ip->insn_mo->name; 12255 fmt = "t,d,s"; 12256 ll_sc_paired = 1; 12257 offbits = 0; 12258 goto ld_st; 12259 case M_CACHE_AB: 12260 s = "cache"; 12261 fmt = (mips_opts.micromips ? "k,~(b)" 12262 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 12263 : "k,o(b)"); 12264 offbits = (mips_opts.micromips ? 12 12265 : ISA_IS_R6 (mips_opts.isa) ? 9 12266 : 16); 12267 goto ld_st; 12268 case M_CACHEE_AB: 12269 s = "cachee"; 12270 fmt = "k,+j(b)"; 12271 offbits = 9; 12272 goto ld_st; 12273 case M_PREF_AB: 12274 s = "pref"; 12275 fmt = (mips_opts.micromips ? "k,~(b)" 12276 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" 12277 : "k,o(b)"); 12278 offbits = (mips_opts.micromips ? 12 12279 : ISA_IS_R6 (mips_opts.isa) ? 9 12280 : 16); 12281 goto ld_st; 12282 case M_PREFE_AB: 12283 s = "prefe"; 12284 fmt = "k,+j(b)"; 12285 offbits = 9; 12286 goto ld_st; 12287 case M_SDC1_AB: 12288 s = "sdc1"; 12289 fmt = "T,o(b)"; 12290 coproc = 1; 12291 /* Itbl support may require additional care here. */ 12292 goto ld_st; 12293 case M_SDC2_AB: 12294 s = "sdc2"; 12295 fmt = COP12_FMT; 12296 offbits = (mips_opts.micromips ? 12 12297 : ISA_IS_R6 (mips_opts.isa) ? 11 12298 : 16); 12299 /* Itbl support may require additional care here. */ 12300 coproc = 1; 12301 goto ld_st; 12302 case M_SQC2_AB: 12303 s = "sqc2"; 12304 fmt = "+7,o(b)"; 12305 /* Itbl support may require additional care here. */ 12306 coproc = 1; 12307 goto ld_st; 12308 case M_SDC3_AB: 12309 gas_assert (!mips_opts.micromips); 12310 s = "sdc3"; 12311 fmt = "E,o(b)"; 12312 /* Itbl support may require additional care here. */ 12313 coproc = 1; 12314 goto ld_st; 12315 case M_SDL_AB: 12316 s = "sdl"; 12317 fmt = MEM12_FMT; 12318 offbits = (mips_opts.micromips ? 12 : 16); 12319 goto ld_st; 12320 case M_SDR_AB: 12321 s = "sdr"; 12322 fmt = MEM12_FMT; 12323 offbits = (mips_opts.micromips ? 12 : 16); 12324 goto ld_st; 12325 case M_SWP_AB: 12326 gas_assert (mips_opts.micromips); 12327 s = "swp"; 12328 fmt = "t,~(b)"; 12329 offbits = 12; 12330 goto ld_st; 12331 case M_SDP_AB: 12332 gas_assert (mips_opts.micromips); 12333 s = "sdp"; 12334 fmt = "t,~(b)"; 12335 offbits = 12; 12336 goto ld_st; 12337 case M_SWM_AB: 12338 gas_assert (mips_opts.micromips); 12339 s = "swm"; 12340 fmt = "n,~(b)"; 12341 offbits = 12; 12342 goto ld_st; 12343 case M_SDM_AB: 12344 gas_assert (mips_opts.micromips); 12345 s = "sdm"; 12346 fmt = "n,~(b)"; 12347 offbits = 12; 12348 12349 ld_st: 12350 tempreg = AT; 12351 ld_noat: 12352 breg = ll_sc_paired ? op[3] : op[2]; 12353 if (small_offset_p (0, align, 16)) 12354 { 12355 /* The first case exists for M_LD_AB and M_SD_AB, which are 12356 macros for o32 but which should act like normal instructions 12357 otherwise. */ 12358 if (offbits == 16) 12359 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], 12360 offset_reloc[1], offset_reloc[2], breg); 12361 else if (small_offset_p (0, align, offbits)) 12362 { 12363 if (offbits == 0) 12364 { 12365 if (ll_sc_paired) 12366 macro_build (NULL, s, fmt, op[0], op[1], breg); 12367 else 12368 macro_build (NULL, s, fmt, op[0], breg); 12369 } 12370 else 12371 macro_build (NULL, s, fmt, op[0], 12372 (int) offset_expr.X_add_number, breg); 12373 } 12374 else 12375 { 12376 if (tempreg == AT) 12377 used_at = 1; 12378 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 12379 tempreg, breg, -1, offset_reloc[0], 12380 offset_reloc[1], offset_reloc[2]); 12381 if (offbits == 0) 12382 { 12383 if (ll_sc_paired) 12384 macro_build (NULL, s, fmt, op[0], op[1], tempreg); 12385 else 12386 macro_build (NULL, s, fmt, op[0], tempreg); 12387 } 12388 else 12389 macro_build (NULL, s, fmt, op[0], 0, tempreg); 12390 } 12391 break; 12392 } 12393 12394 if (tempreg == AT) 12395 used_at = 1; 12396 12397 if (offset_expr.X_op != O_constant 12398 && offset_expr.X_op != O_symbol) 12399 { 12400 as_bad (_("expression too complex")); 12401 offset_expr.X_op = O_constant; 12402 } 12403 12404 if (HAVE_32BIT_ADDRESSES 12405 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 12406 { 12407 char value [32]; 12408 12409 sprintf_vma (value, offset_expr.X_add_number); 12410 as_bad (_("number (0x%s) larger than 32 bits"), value); 12411 } 12412 12413 /* A constant expression in PIC code can be handled just as it 12414 is in non PIC code. */ 12415 if (offset_expr.X_op == O_constant) 12416 { 12417 expr1.X_add_number = offset_high_part (offset_expr.X_add_number, 12418 offbits == 0 ? 16 : offbits); 12419 offset_expr.X_add_number -= expr1.X_add_number; 12420 12421 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); 12422 if (breg != 0) 12423 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12424 tempreg, tempreg, breg); 12425 if (offbits == 0) 12426 { 12427 if (offset_expr.X_add_number != 0) 12428 macro_build (&offset_expr, ADDRESS_ADDI_INSN, 12429 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); 12430 if (ll_sc_paired) 12431 macro_build (NULL, s, fmt, op[0], op[1], tempreg); 12432 else 12433 macro_build (NULL, s, fmt, op[0], tempreg); 12434 } 12435 else if (offbits == 16) 12436 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12437 else 12438 macro_build (NULL, s, fmt, op[0], 12439 (int) offset_expr.X_add_number, tempreg); 12440 } 12441 else if (offbits != 16) 12442 { 12443 /* The offset field is too narrow to be used for a low-part 12444 relocation, so load the whole address into the auxiliary 12445 register. */ 12446 load_address (tempreg, &offset_expr, &used_at); 12447 if (breg != 0) 12448 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12449 tempreg, tempreg, breg); 12450 if (offbits == 0) 12451 { 12452 if (ll_sc_paired) 12453 macro_build (NULL, s, fmt, op[0], op[1], tempreg); 12454 else 12455 macro_build (NULL, s, fmt, op[0], tempreg); 12456 } 12457 else 12458 macro_build (NULL, s, fmt, op[0], 0, tempreg); 12459 } 12460 else if (mips_pic == NO_PIC) 12461 { 12462 /* If this is a reference to a GP relative symbol, and there 12463 is no base register, we want 12464 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 12465 Otherwise, if there is no base register, we want 12466 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 12467 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12468 If we have a constant, we need two instructions anyhow, 12469 so we always use the latter form. 12470 12471 If we have a base register, and this is a reference to a 12472 GP relative symbol, we want 12473 addu $tempreg,$breg,$gp 12474 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) 12475 Otherwise we want 12476 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 12477 addu $tempreg,$tempreg,$breg 12478 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12479 With a constant we always use the latter case. 12480 12481 With 64bit address space and no base register and $at usable, 12482 we want 12483 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 12484 lui $at,<sym> (BFD_RELOC_HI16_S) 12485 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 12486 dsll32 $tempreg,0 12487 daddu $tempreg,$at 12488 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12489 If we have a base register, we want 12490 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 12491 lui $at,<sym> (BFD_RELOC_HI16_S) 12492 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 12493 daddu $at,$breg 12494 dsll32 $tempreg,0 12495 daddu $tempreg,$at 12496 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12497 12498 Without $at we can't generate the optimal path for superscalar 12499 processors here since this would require two temporary registers. 12500 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 12501 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 12502 dsll $tempreg,16 12503 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 12504 dsll $tempreg,16 12505 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12506 If we have a base register, we want 12507 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 12508 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 12509 dsll $tempreg,16 12510 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 12511 dsll $tempreg,16 12512 daddu $tempreg,$tempreg,$breg 12513 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) 12514 12515 For GP relative symbols in 64bit address space we can use 12516 the same sequence as in 32bit address space. */ 12517 if (HAVE_64BIT_SYMBOLS) 12518 { 12519 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12520 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12521 { 12522 relax_start (offset_expr.X_add_symbol); 12523 if (breg == 0) 12524 { 12525 macro_build (&offset_expr, s, fmt, op[0], 12526 BFD_RELOC_GPREL16, mips_gp_register); 12527 } 12528 else 12529 { 12530 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12531 tempreg, breg, mips_gp_register); 12532 macro_build (&offset_expr, s, fmt, op[0], 12533 BFD_RELOC_GPREL16, tempreg); 12534 } 12535 relax_switch (); 12536 } 12537 12538 if (used_at == 0 && mips_opts.at) 12539 { 12540 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12541 BFD_RELOC_MIPS_HIGHEST); 12542 macro_build (&offset_expr, "lui", LUI_FMT, AT, 12543 BFD_RELOC_HI16_S); 12544 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 12545 tempreg, BFD_RELOC_MIPS_HIGHER); 12546 if (breg != 0) 12547 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 12548 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); 12549 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 12550 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, 12551 tempreg); 12552 used_at = 1; 12553 } 12554 else 12555 { 12556 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12557 BFD_RELOC_MIPS_HIGHEST); 12558 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 12559 tempreg, BFD_RELOC_MIPS_HIGHER); 12560 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 12561 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 12562 tempreg, BFD_RELOC_HI16_S); 12563 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); 12564 if (breg != 0) 12565 macro_build (NULL, "daddu", "d,v,t", 12566 tempreg, tempreg, breg); 12567 macro_build (&offset_expr, s, fmt, op[0], 12568 BFD_RELOC_LO16, tempreg); 12569 } 12570 12571 if (mips_relax.sequence) 12572 relax_end (); 12573 break; 12574 } 12575 12576 if (breg == 0) 12577 { 12578 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12579 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12580 { 12581 relax_start (offset_expr.X_add_symbol); 12582 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, 12583 mips_gp_register); 12584 relax_switch (); 12585 } 12586 macro_build_lui (&offset_expr, tempreg); 12587 macro_build (&offset_expr, s, fmt, op[0], 12588 BFD_RELOC_LO16, tempreg); 12589 if (mips_relax.sequence) 12590 relax_end (); 12591 } 12592 else 12593 { 12594 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 12595 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 12596 { 12597 relax_start (offset_expr.X_add_symbol); 12598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12599 tempreg, breg, mips_gp_register); 12600 macro_build (&offset_expr, s, fmt, op[0], 12601 BFD_RELOC_GPREL16, tempreg); 12602 relax_switch (); 12603 } 12604 macro_build_lui (&offset_expr, tempreg); 12605 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12606 tempreg, tempreg, breg); 12607 macro_build (&offset_expr, s, fmt, op[0], 12608 BFD_RELOC_LO16, tempreg); 12609 if (mips_relax.sequence) 12610 relax_end (); 12611 } 12612 } 12613 else if (!mips_big_got) 12614 { 12615 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 12616 12617 /* If this is a reference to an external symbol, we want 12618 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12619 nop 12620 <op> op[0],0($tempreg) 12621 Otherwise we want 12622 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12623 nop 12624 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 12625 <op> op[0],0($tempreg) 12626 12627 For NewABI, we want 12628 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 12629 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 12630 12631 If there is a base register, we add it to $tempreg before 12632 the <op>. If there is a constant, we stick it in the 12633 <op> instruction. We don't handle constants larger than 12634 16 bits, because we have no way to load the upper 16 bits 12635 (actually, we could handle them for the subset of cases 12636 in which we are not using $at). */ 12637 gas_assert (offset_expr.X_op == O_symbol); 12638 if (HAVE_NEWABI) 12639 { 12640 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12641 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12642 if (breg != 0) 12643 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12644 tempreg, tempreg, breg); 12645 macro_build (&offset_expr, s, fmt, op[0], 12646 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12647 break; 12648 } 12649 expr1.X_add_number = offset_expr.X_add_number; 12650 offset_expr.X_add_number = 0; 12651 if (expr1.X_add_number < -0x8000 12652 || expr1.X_add_number >= 0x8000) 12653 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12654 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12655 lw_reloc_type, mips_gp_register); 12656 load_delay_nop (); 12657 relax_start (offset_expr.X_add_symbol); 12658 relax_switch (); 12659 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12660 tempreg, BFD_RELOC_LO16); 12661 relax_end (); 12662 if (breg != 0) 12663 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12664 tempreg, tempreg, breg); 12665 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12666 } 12667 else if (mips_big_got && !HAVE_NEWABI) 12668 { 12669 int gpdelay; 12670 12671 /* If this is a reference to an external symbol, we want 12672 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12673 addu $tempreg,$tempreg,$gp 12674 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12675 <op> op[0],0($tempreg) 12676 Otherwise we want 12677 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 12678 nop 12679 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 12680 <op> op[0],0($tempreg) 12681 If there is a base register, we add it to $tempreg before 12682 the <op>. If there is a constant, we stick it in the 12683 <op> instruction. We don't handle constants larger than 12684 16 bits, because we have no way to load the upper 16 bits 12685 (actually, we could handle them for the subset of cases 12686 in which we are not using $at). */ 12687 gas_assert (offset_expr.X_op == O_symbol); 12688 expr1.X_add_number = offset_expr.X_add_number; 12689 offset_expr.X_add_number = 0; 12690 if (expr1.X_add_number < -0x8000 12691 || expr1.X_add_number >= 0x8000) 12692 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12693 gpdelay = reg_needs_delay (mips_gp_register); 12694 relax_start (offset_expr.X_add_symbol); 12695 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12696 BFD_RELOC_MIPS_GOT_HI16); 12697 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12698 mips_gp_register); 12699 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12700 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12701 relax_switch (); 12702 if (gpdelay) 12703 macro_build (NULL, "nop", ""); 12704 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12705 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12706 load_delay_nop (); 12707 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 12708 tempreg, BFD_RELOC_LO16); 12709 relax_end (); 12710 12711 if (breg != 0) 12712 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12713 tempreg, tempreg, breg); 12714 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12715 } 12716 else if (mips_big_got && HAVE_NEWABI) 12717 { 12718 /* If this is a reference to an external symbol, we want 12719 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 12720 add $tempreg,$tempreg,$gp 12721 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 12722 <op> op[0],<ofst>($tempreg) 12723 Otherwise, for local symbols, we want: 12724 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 12725 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 12726 gas_assert (offset_expr.X_op == O_symbol); 12727 expr1.X_add_number = offset_expr.X_add_number; 12728 offset_expr.X_add_number = 0; 12729 if (expr1.X_add_number < -0x8000 12730 || expr1.X_add_number >= 0x8000) 12731 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 12732 relax_start (offset_expr.X_add_symbol); 12733 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, 12734 BFD_RELOC_MIPS_GOT_HI16); 12735 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 12736 mips_gp_register); 12737 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12738 BFD_RELOC_MIPS_GOT_LO16, tempreg); 12739 if (breg != 0) 12740 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12741 tempreg, tempreg, breg); 12742 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); 12743 12744 relax_switch (); 12745 offset_expr.X_add_number = expr1.X_add_number; 12746 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 12747 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 12748 if (breg != 0) 12749 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 12750 tempreg, tempreg, breg); 12751 macro_build (&offset_expr, s, fmt, op[0], 12752 BFD_RELOC_MIPS_GOT_OFST, tempreg); 12753 relax_end (); 12754 } 12755 else 12756 abort (); 12757 12758 break; 12759 12760 case M_JRADDIUSP: 12761 gas_assert (mips_opts.micromips); 12762 gas_assert (mips_opts.insn32); 12763 start_noreorder (); 12764 macro_build (NULL, "jr", "s", RA); 12765 expr1.X_add_number = op[0] << 2; 12766 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); 12767 end_noreorder (); 12768 break; 12769 12770 case M_JRC: 12771 gas_assert (mips_opts.micromips); 12772 gas_assert (mips_opts.insn32); 12773 macro_build (NULL, "jr", "s", op[0]); 12774 if (mips_opts.noreorder) 12775 macro_build (NULL, "nop", ""); 12776 break; 12777 12778 case M_LI: 12779 case M_LI_S: 12780 load_register (op[0], &imm_expr, 0); 12781 break; 12782 12783 case M_DLI: 12784 load_register (op[0], &imm_expr, 1); 12785 break; 12786 12787 case M_LI_SS: 12788 if (imm_expr.X_op == O_constant) 12789 { 12790 used_at = 1; 12791 load_register (AT, &imm_expr, 0); 12792 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12793 break; 12794 } 12795 else 12796 { 12797 gas_assert (imm_expr.X_op == O_absent 12798 && offset_expr.X_op == O_symbol 12799 && strcmp (segment_name (S_GET_SEGMENT 12800 (offset_expr.X_add_symbol)), 12801 ".lit4") == 0 12802 && offset_expr.X_add_number == 0); 12803 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], 12804 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 12805 break; 12806 } 12807 12808 case M_LI_D: 12809 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 12810 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 12811 order 32 bits of the value and the low order 32 bits are either 12812 zero or in OFFSET_EXPR. */ 12813 if (imm_expr.X_op == O_constant) 12814 { 12815 if (GPR_SIZE == 64) 12816 load_register (op[0], &imm_expr, 1); 12817 else 12818 { 12819 int hreg, lreg; 12820 12821 if (target_big_endian) 12822 { 12823 hreg = op[0]; 12824 lreg = op[0] + 1; 12825 } 12826 else 12827 { 12828 hreg = op[0] + 1; 12829 lreg = op[0]; 12830 } 12831 12832 if (hreg <= 31) 12833 load_register (hreg, &imm_expr, 0); 12834 if (lreg <= 31) 12835 { 12836 if (offset_expr.X_op == O_absent) 12837 move_register (lreg, 0); 12838 else 12839 { 12840 gas_assert (offset_expr.X_op == O_constant); 12841 load_register (lreg, &offset_expr, 0); 12842 } 12843 } 12844 } 12845 break; 12846 } 12847 gas_assert (imm_expr.X_op == O_absent); 12848 12849 /* We know that sym is in the .rdata section. First we get the 12850 upper 16 bits of the address. */ 12851 if (mips_pic == NO_PIC) 12852 { 12853 macro_build_lui (&offset_expr, AT); 12854 used_at = 1; 12855 } 12856 else 12857 { 12858 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12859 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12860 used_at = 1; 12861 } 12862 12863 /* Now we load the register(s). */ 12864 if (GPR_SIZE == 64) 12865 { 12866 used_at = 1; 12867 macro_build (&offset_expr, "ld", "t,o(b)", op[0], 12868 BFD_RELOC_LO16, AT); 12869 } 12870 else 12871 { 12872 used_at = 1; 12873 macro_build (&offset_expr, "lw", "t,o(b)", op[0], 12874 BFD_RELOC_LO16, AT); 12875 if (op[0] != RA) 12876 { 12877 /* FIXME: How in the world do we deal with the possible 12878 overflow here? */ 12879 offset_expr.X_add_number += 4; 12880 macro_build (&offset_expr, "lw", "t,o(b)", 12881 op[0] + 1, BFD_RELOC_LO16, AT); 12882 } 12883 } 12884 break; 12885 12886 case M_LI_DD: 12887 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 12888 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 12889 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 12890 the value and the low order 32 bits are either zero or in 12891 OFFSET_EXPR. */ 12892 if (imm_expr.X_op == O_constant) 12893 { 12894 tempreg = ZERO; 12895 if (((FPR_SIZE == 64 && GPR_SIZE == 64) 12896 || !ISA_HAS_MXHC1 (mips_opts.isa)) 12897 && imm_expr.X_add_number != 0) 12898 { 12899 used_at = 1; 12900 tempreg = AT; 12901 load_register (AT, &imm_expr, FPR_SIZE == 64); 12902 } 12903 if (FPR_SIZE == 64 && GPR_SIZE == 64) 12904 macro_build (NULL, "dmtc1", "t,S", tempreg, op[0]); 12905 else 12906 { 12907 if (!ISA_HAS_MXHC1 (mips_opts.isa)) 12908 { 12909 if (FPR_SIZE != 32) 12910 as_bad (_("Unable to generate `%s' compliant code " 12911 "without mthc1"), 12912 (FPR_SIZE == 64) ? "fp64" : "fpxx"); 12913 else 12914 macro_build (NULL, "mtc1", "t,G", tempreg, op[0] + 1); 12915 } 12916 if (offset_expr.X_op == O_absent) 12917 macro_build (NULL, "mtc1", "t,G", 0, op[0]); 12918 else 12919 { 12920 gas_assert (offset_expr.X_op == O_constant); 12921 load_register (AT, &offset_expr, 0); 12922 macro_build (NULL, "mtc1", "t,G", AT, op[0]); 12923 } 12924 if (ISA_HAS_MXHC1 (mips_opts.isa)) 12925 { 12926 if (imm_expr.X_add_number != 0) 12927 { 12928 used_at = 1; 12929 tempreg = AT; 12930 load_register (AT, &imm_expr, 0); 12931 } 12932 macro_build (NULL, "mthc1", "t,G", tempreg, op[0]); 12933 } 12934 } 12935 break; 12936 } 12937 12938 gas_assert (imm_expr.X_op == O_absent 12939 && offset_expr.X_op == O_symbol 12940 && offset_expr.X_add_number == 0); 12941 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 12942 if (strcmp (s, ".lit8") == 0) 12943 { 12944 op[2] = mips_gp_register; 12945 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; 12946 offset_reloc[1] = BFD_RELOC_UNUSED; 12947 offset_reloc[2] = BFD_RELOC_UNUSED; 12948 } 12949 else 12950 { 12951 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); 12952 used_at = 1; 12953 if (mips_pic != NO_PIC) 12954 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 12955 BFD_RELOC_MIPS_GOT16, mips_gp_register); 12956 else 12957 { 12958 /* FIXME: This won't work for a 64 bit address. */ 12959 macro_build_lui (&offset_expr, AT); 12960 } 12961 12962 op[2] = AT; 12963 offset_reloc[0] = BFD_RELOC_LO16; 12964 offset_reloc[1] = BFD_RELOC_UNUSED; 12965 offset_reloc[2] = BFD_RELOC_UNUSED; 12966 } 12967 align = 8; 12968 /* Fall through. */ 12969 12970 case M_L_DAB: 12971 /* The MIPS assembler seems to check for X_add_number not 12972 being double aligned and generating: 12973 lui at,%hi(foo+1) 12974 addu at,at,v1 12975 addiu at,at,%lo(foo+1) 12976 lwc1 f2,0(at) 12977 lwc1 f3,4(at) 12978 But, the resulting address is the same after relocation so why 12979 generate the extra instruction? */ 12980 /* Itbl support may require additional care here. */ 12981 coproc = 1; 12982 fmt = "T,o(b)"; 12983 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12984 { 12985 s = "ldc1"; 12986 goto ld_st; 12987 } 12988 s = "lwc1"; 12989 goto ldd_std; 12990 12991 case M_S_DAB: 12992 gas_assert (!mips_opts.micromips); 12993 /* Itbl support may require additional care here. */ 12994 coproc = 1; 12995 fmt = "T,o(b)"; 12996 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) 12997 { 12998 s = "sdc1"; 12999 goto ld_st; 13000 } 13001 s = "swc1"; 13002 goto ldd_std; 13003 13004 case M_LQ_AB: 13005 fmt = "t,o(b)"; 13006 s = "lq"; 13007 goto ld; 13008 13009 case M_SQ_AB: 13010 fmt = "t,o(b)"; 13011 s = "sq"; 13012 goto ld_st; 13013 13014 case M_LD_AB: 13015 fmt = "t,o(b)"; 13016 if (GPR_SIZE == 64) 13017 { 13018 s = "ld"; 13019 goto ld; 13020 } 13021 s = "lw"; 13022 goto ldd_std; 13023 13024 case M_SD_AB: 13025 fmt = "t,o(b)"; 13026 if (GPR_SIZE == 64) 13027 { 13028 s = "sd"; 13029 goto ld_st; 13030 } 13031 s = "sw"; 13032 13033 ldd_std: 13034 /* Even on a big endian machine $fn comes before $fn+1. We have 13035 to adjust when loading from memory. We set coproc if we must 13036 load $fn+1 first. */ 13037 /* Itbl support may require additional care here. */ 13038 if (!target_big_endian) 13039 coproc = 0; 13040 13041 breg = op[2]; 13042 if (small_offset_p (0, align, 16)) 13043 { 13044 ep = &offset_expr; 13045 if (!small_offset_p (4, align, 16)) 13046 { 13047 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, 13048 -1, offset_reloc[0], offset_reloc[1], 13049 offset_reloc[2]); 13050 expr1.X_add_number = 0; 13051 ep = &expr1; 13052 breg = AT; 13053 used_at = 1; 13054 offset_reloc[0] = BFD_RELOC_LO16; 13055 offset_reloc[1] = BFD_RELOC_UNUSED; 13056 offset_reloc[2] = BFD_RELOC_UNUSED; 13057 } 13058 if (strcmp (s, "lw") == 0 && op[0] == breg) 13059 { 13060 ep->X_add_number += 4; 13061 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], 13062 offset_reloc[1], offset_reloc[2], breg); 13063 ep->X_add_number -= 4; 13064 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], 13065 offset_reloc[1], offset_reloc[2], breg); 13066 } 13067 else 13068 { 13069 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, 13070 offset_reloc[0], offset_reloc[1], offset_reloc[2], 13071 breg); 13072 ep->X_add_number += 4; 13073 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, 13074 offset_reloc[0], offset_reloc[1], offset_reloc[2], 13075 breg); 13076 } 13077 break; 13078 } 13079 13080 if (offset_expr.X_op != O_symbol 13081 && offset_expr.X_op != O_constant) 13082 { 13083 as_bad (_("expression too complex")); 13084 offset_expr.X_op = O_constant; 13085 } 13086 13087 if (HAVE_32BIT_ADDRESSES 13088 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) 13089 { 13090 char value [32]; 13091 13092 sprintf_vma (value, offset_expr.X_add_number); 13093 as_bad (_("number (0x%s) larger than 32 bits"), value); 13094 } 13095 13096 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) 13097 { 13098 /* If this is a reference to a GP relative symbol, we want 13099 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) 13100 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 13101 If we have a base register, we use this 13102 addu $at,$breg,$gp 13103 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) 13104 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) 13105 If this is not a GP relative symbol, we want 13106 lui $at,<sym> (BFD_RELOC_HI16_S) 13107 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 13108 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 13109 If there is a base register, we add it to $at after the 13110 lui instruction. If there is a constant, we always use 13111 the last case. */ 13112 if (offset_expr.X_op == O_symbol 13113 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 13114 && !nopic_need_relax (offset_expr.X_add_symbol, 1)) 13115 { 13116 relax_start (offset_expr.X_add_symbol); 13117 if (breg == 0) 13118 { 13119 tempreg = mips_gp_register; 13120 } 13121 else 13122 { 13123 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 13124 AT, breg, mips_gp_register); 13125 tempreg = AT; 13126 used_at = 1; 13127 } 13128 13129 /* Itbl support may require additional care here. */ 13130 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 13131 BFD_RELOC_GPREL16, tempreg); 13132 offset_expr.X_add_number += 4; 13133 13134 /* Set mips_optimize to 2 to avoid inserting an 13135 undesired nop. */ 13136 hold_mips_optimize = mips_optimize; 13137 mips_optimize = 2; 13138 /* Itbl support may require additional care here. */ 13139 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 13140 BFD_RELOC_GPREL16, tempreg); 13141 mips_optimize = hold_mips_optimize; 13142 13143 relax_switch (); 13144 13145 offset_expr.X_add_number -= 4; 13146 } 13147 used_at = 1; 13148 if (offset_high_part (offset_expr.X_add_number, 16) 13149 != offset_high_part (offset_expr.X_add_number + 4, 16)) 13150 { 13151 load_address (AT, &offset_expr, &used_at); 13152 offset_expr.X_op = O_constant; 13153 offset_expr.X_add_number = 0; 13154 } 13155 else 13156 macro_build_lui (&offset_expr, AT); 13157 if (breg != 0) 13158 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 13159 /* Itbl support may require additional care here. */ 13160 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 13161 BFD_RELOC_LO16, AT); 13162 /* FIXME: How do we handle overflow here? */ 13163 offset_expr.X_add_number += 4; 13164 /* Itbl support may require additional care here. */ 13165 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 13166 BFD_RELOC_LO16, AT); 13167 if (mips_relax.sequence) 13168 relax_end (); 13169 } 13170 else if (!mips_big_got) 13171 { 13172 /* If this is a reference to an external symbol, we want 13173 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 13174 nop 13175 <op> op[0],0($at) 13176 <op> op[0]+1,4($at) 13177 Otherwise we want 13178 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 13179 nop 13180 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 13181 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 13182 If there is a base register we add it to $at before the 13183 lwc1 instructions. If there is a constant we include it 13184 in the lwc1 instructions. */ 13185 used_at = 1; 13186 expr1.X_add_number = offset_expr.X_add_number; 13187 if (expr1.X_add_number < -0x8000 13188 || expr1.X_add_number >= 0x8000 - 4) 13189 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 13190 load_got_offset (AT, &offset_expr); 13191 load_delay_nop (); 13192 if (breg != 0) 13193 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 13194 13195 /* Set mips_optimize to 2 to avoid inserting an undesired 13196 nop. */ 13197 hold_mips_optimize = mips_optimize; 13198 mips_optimize = 2; 13199 13200 /* Itbl support may require additional care here. */ 13201 relax_start (offset_expr.X_add_symbol); 13202 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 13203 BFD_RELOC_LO16, AT); 13204 expr1.X_add_number += 4; 13205 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 13206 BFD_RELOC_LO16, AT); 13207 relax_switch (); 13208 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 13209 BFD_RELOC_LO16, AT); 13210 offset_expr.X_add_number += 4; 13211 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 13212 BFD_RELOC_LO16, AT); 13213 relax_end (); 13214 13215 mips_optimize = hold_mips_optimize; 13216 } 13217 else if (mips_big_got) 13218 { 13219 int gpdelay; 13220 13221 /* If this is a reference to an external symbol, we want 13222 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 13223 addu $at,$at,$gp 13224 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 13225 nop 13226 <op> op[0],0($at) 13227 <op> op[0]+1,4($at) 13228 Otherwise we want 13229 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 13230 nop 13231 <op> op[0],<sym>($at) (BFD_RELOC_LO16) 13232 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) 13233 If there is a base register we add it to $at before the 13234 lwc1 instructions. If there is a constant we include it 13235 in the lwc1 instructions. */ 13236 used_at = 1; 13237 expr1.X_add_number = offset_expr.X_add_number; 13238 offset_expr.X_add_number = 0; 13239 if (expr1.X_add_number < -0x8000 13240 || expr1.X_add_number >= 0x8000 - 4) 13241 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 13242 gpdelay = reg_needs_delay (mips_gp_register); 13243 relax_start (offset_expr.X_add_symbol); 13244 macro_build (&offset_expr, "lui", LUI_FMT, 13245 AT, BFD_RELOC_MIPS_GOT_HI16); 13246 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 13247 AT, AT, mips_gp_register); 13248 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 13249 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 13250 load_delay_nop (); 13251 if (breg != 0) 13252 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 13253 /* Itbl support may require additional care here. */ 13254 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], 13255 BFD_RELOC_LO16, AT); 13256 expr1.X_add_number += 4; 13257 13258 /* Set mips_optimize to 2 to avoid inserting an undesired 13259 nop. */ 13260 hold_mips_optimize = mips_optimize; 13261 mips_optimize = 2; 13262 /* Itbl support may require additional care here. */ 13263 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, 13264 BFD_RELOC_LO16, AT); 13265 mips_optimize = hold_mips_optimize; 13266 expr1.X_add_number -= 4; 13267 13268 relax_switch (); 13269 offset_expr.X_add_number = expr1.X_add_number; 13270 if (gpdelay) 13271 macro_build (NULL, "nop", ""); 13272 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 13273 BFD_RELOC_MIPS_GOT16, mips_gp_register); 13274 load_delay_nop (); 13275 if (breg != 0) 13276 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 13277 /* Itbl support may require additional care here. */ 13278 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], 13279 BFD_RELOC_LO16, AT); 13280 offset_expr.X_add_number += 4; 13281 13282 /* Set mips_optimize to 2 to avoid inserting an undesired 13283 nop. */ 13284 hold_mips_optimize = mips_optimize; 13285 mips_optimize = 2; 13286 /* Itbl support may require additional care here. */ 13287 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, 13288 BFD_RELOC_LO16, AT); 13289 mips_optimize = hold_mips_optimize; 13290 relax_end (); 13291 } 13292 else 13293 abort (); 13294 13295 break; 13296 13297 case M_SAA_AB: 13298 s = "saa"; 13299 goto saa_saad; 13300 case M_SAAD_AB: 13301 s = "saad"; 13302 saa_saad: 13303 gas_assert (!mips_opts.micromips); 13304 offbits = 0; 13305 fmt = "t,(b)"; 13306 goto ld_st; 13307 13308 /* New code added to support COPZ instructions. 13309 This code builds table entries out of the macros in mip_opcodes. 13310 R4000 uses interlocks to handle coproc delays. 13311 Other chips (like the R3000) require nops to be inserted for delays. 13312 13313 FIXME: Currently, we require that the user handle delays. 13314 In order to fill delay slots for non-interlocked chips, 13315 we must have a way to specify delays based on the coprocessor. 13316 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 13317 What are the side-effects of the cop instruction? 13318 What cache support might we have and what are its effects? 13319 Both coprocessor & memory require delays. how long??? 13320 What registers are read/set/modified? 13321 13322 If an itbl is provided to interpret cop instructions, 13323 this knowledge can be encoded in the itbl spec. */ 13324 13325 case M_COP0: 13326 s = "c0"; 13327 goto copz; 13328 case M_COP1: 13329 s = "c1"; 13330 goto copz; 13331 case M_COP2: 13332 s = "c2"; 13333 goto copz; 13334 case M_COP3: 13335 s = "c3"; 13336 copz: 13337 gas_assert (!mips_opts.micromips); 13338 /* For now we just do C (same as Cz). The parameter will be 13339 stored in insn_opcode by mips_ip. */ 13340 macro_build (NULL, s, "C", (int) ip->insn_opcode); 13341 break; 13342 13343 case M_MOVE: 13344 move_register (op[0], op[1]); 13345 break; 13346 13347 case M_MOVEP: 13348 gas_assert (mips_opts.micromips); 13349 gas_assert (mips_opts.insn32); 13350 move_register (micromips_to_32_reg_h_map1[op[0]], 13351 micromips_to_32_reg_m_map[op[1]]); 13352 move_register (micromips_to_32_reg_h_map2[op[0]], 13353 micromips_to_32_reg_n_map[op[2]]); 13354 break; 13355 13356 case M_DMUL: 13357 dbl = 1; 13358 /* Fall through. */ 13359 case M_MUL: 13360 if (mips_opts.arch == CPU_R5900) 13361 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], 13362 op[2]); 13363 else 13364 { 13365 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); 13366 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 13367 } 13368 break; 13369 13370 case M_DMUL_I: 13371 dbl = 1; 13372 /* Fall through. */ 13373 case M_MUL_I: 13374 /* The MIPS assembler some times generates shifts and adds. I'm 13375 not trying to be that fancy. GCC should do this for us 13376 anyway. */ 13377 used_at = 1; 13378 load_register (AT, &imm_expr, dbl); 13379 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); 13380 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 13381 break; 13382 13383 case M_DMULO_I: 13384 dbl = 1; 13385 /* Fall through. */ 13386 case M_MULO_I: 13387 imm = 1; 13388 goto do_mulo; 13389 13390 case M_DMULO: 13391 dbl = 1; 13392 /* Fall through. */ 13393 case M_MULO: 13394 do_mulo: 13395 start_noreorder (); 13396 used_at = 1; 13397 if (imm) 13398 load_register (AT, &imm_expr, dbl); 13399 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", 13400 op[1], imm ? AT : op[2]); 13401 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 13402 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); 13403 macro_build (NULL, "mfhi", MFHL_FMT, AT); 13404 if (mips_trap) 13405 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); 13406 else 13407 { 13408 if (mips_opts.micromips) 13409 micromips_label_expr (&label_expr); 13410 else 13411 label_expr.X_add_number = 8; 13412 macro_build (&label_expr, "beq", "s,t,p", op[0], AT); 13413 macro_build (NULL, "nop", ""); 13414 macro_build (NULL, "break", BRK_FMT, 6); 13415 if (mips_opts.micromips) 13416 micromips_add_label (); 13417 } 13418 end_noreorder (); 13419 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 13420 break; 13421 13422 case M_DMULOU_I: 13423 dbl = 1; 13424 /* Fall through. */ 13425 case M_MULOU_I: 13426 imm = 1; 13427 goto do_mulou; 13428 13429 case M_DMULOU: 13430 dbl = 1; 13431 /* Fall through. */ 13432 case M_MULOU: 13433 do_mulou: 13434 start_noreorder (); 13435 used_at = 1; 13436 if (imm) 13437 load_register (AT, &imm_expr, dbl); 13438 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 13439 op[1], imm ? AT : op[2]); 13440 macro_build (NULL, "mfhi", MFHL_FMT, AT); 13441 macro_build (NULL, "mflo", MFHL_FMT, op[0]); 13442 if (mips_trap) 13443 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); 13444 else 13445 { 13446 if (mips_opts.micromips) 13447 micromips_label_expr (&label_expr); 13448 else 13449 label_expr.X_add_number = 8; 13450 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); 13451 macro_build (NULL, "nop", ""); 13452 macro_build (NULL, "break", BRK_FMT, 6); 13453 if (mips_opts.micromips) 13454 micromips_add_label (); 13455 } 13456 end_noreorder (); 13457 break; 13458 13459 case M_DROL: 13460 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 13461 { 13462 if (op[0] == op[1]) 13463 { 13464 tempreg = AT; 13465 used_at = 1; 13466 } 13467 else 13468 tempreg = op[0]; 13469 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); 13470 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); 13471 break; 13472 } 13473 used_at = 1; 13474 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 13475 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); 13476 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); 13477 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13478 break; 13479 13480 case M_ROL: 13481 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 13482 { 13483 if (op[0] == op[1]) 13484 { 13485 tempreg = AT; 13486 used_at = 1; 13487 } 13488 else 13489 tempreg = op[0]; 13490 macro_build (NULL, "negu", "d,w", tempreg, op[2]); 13491 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); 13492 break; 13493 } 13494 used_at = 1; 13495 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 13496 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); 13497 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); 13498 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13499 break; 13500 13501 case M_DROL_I: 13502 { 13503 unsigned int rot; 13504 const char *l; 13505 const char *rr; 13506 13507 rot = imm_expr.X_add_number & 0x3f; 13508 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 13509 { 13510 rot = (64 - rot) & 0x3f; 13511 if (rot >= 32) 13512 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 13513 else 13514 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 13515 break; 13516 } 13517 if (rot == 0) 13518 { 13519 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 13520 break; 13521 } 13522 l = (rot < 0x20) ? "dsll" : "dsll32"; 13523 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 13524 rot &= 0x1f; 13525 used_at = 1; 13526 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); 13527 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13528 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13529 } 13530 break; 13531 13532 case M_ROL_I: 13533 { 13534 unsigned int rot; 13535 13536 rot = imm_expr.X_add_number & 0x1f; 13537 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 13538 { 13539 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], 13540 (32 - rot) & 0x1f); 13541 break; 13542 } 13543 if (rot == 0) 13544 { 13545 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 13546 break; 13547 } 13548 used_at = 1; 13549 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); 13550 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13551 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13552 } 13553 break; 13554 13555 case M_DROR: 13556 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 13557 { 13558 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); 13559 break; 13560 } 13561 used_at = 1; 13562 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); 13563 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); 13564 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); 13565 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13566 break; 13567 13568 case M_ROR: 13569 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 13570 { 13571 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); 13572 break; 13573 } 13574 used_at = 1; 13575 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); 13576 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); 13577 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); 13578 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13579 break; 13580 13581 case M_DROR_I: 13582 { 13583 unsigned int rot; 13584 const char *l; 13585 const char *rr; 13586 13587 rot = imm_expr.X_add_number & 0x3f; 13588 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 13589 { 13590 if (rot >= 32) 13591 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); 13592 else 13593 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); 13594 break; 13595 } 13596 if (rot == 0) 13597 { 13598 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); 13599 break; 13600 } 13601 rr = (rot < 0x20) ? "dsrl" : "dsrl32"; 13602 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 13603 rot &= 0x1f; 13604 used_at = 1; 13605 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); 13606 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13607 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13608 } 13609 break; 13610 13611 case M_ROR_I: 13612 { 13613 unsigned int rot; 13614 13615 rot = imm_expr.X_add_number & 0x1f; 13616 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 13617 { 13618 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); 13619 break; 13620 } 13621 if (rot == 0) 13622 { 13623 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); 13624 break; 13625 } 13626 used_at = 1; 13627 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); 13628 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); 13629 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 13630 } 13631 break; 13632 13633 case M_SEQ: 13634 if (op[1] == 0) 13635 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); 13636 else if (op[2] == 0) 13637 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13638 else 13639 { 13640 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13641 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 13642 } 13643 break; 13644 13645 case M_SEQ_I: 13646 if (imm_expr.X_add_number == 0) 13647 { 13648 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13649 break; 13650 } 13651 if (op[1] == 0) 13652 { 13653 as_warn (_("instruction %s: result is always false"), 13654 ip->insn_mo->name); 13655 move_register (op[0], 0); 13656 break; 13657 } 13658 if (CPU_HAS_SEQ (mips_opts.arch) 13659 && -512 <= imm_expr.X_add_number 13660 && imm_expr.X_add_number < 512) 13661 { 13662 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], 13663 (int) imm_expr.X_add_number); 13664 break; 13665 } 13666 if (imm_expr.X_add_number >= 0 13667 && imm_expr.X_add_number < 0x10000) 13668 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); 13669 else if (imm_expr.X_add_number > -0x8000 13670 && imm_expr.X_add_number < 0) 13671 { 13672 imm_expr.X_add_number = -imm_expr.X_add_number; 13673 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13674 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13675 } 13676 else if (CPU_HAS_SEQ (mips_opts.arch)) 13677 { 13678 used_at = 1; 13679 load_register (AT, &imm_expr, GPR_SIZE == 64); 13680 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); 13681 break; 13682 } 13683 else 13684 { 13685 load_register (AT, &imm_expr, GPR_SIZE == 64); 13686 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13687 used_at = 1; 13688 } 13689 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); 13690 break; 13691 13692 case M_SGE: /* X >= Y <==> not (X < Y) */ 13693 s = "slt"; 13694 goto sge; 13695 case M_SGEU: 13696 s = "sltu"; 13697 sge: 13698 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); 13699 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13700 break; 13701 13702 case M_SGE_I: /* X >= I <==> not (X < I). */ 13703 case M_SGEU_I: 13704 if (imm_expr.X_add_number >= -0x8000 13705 && imm_expr.X_add_number < 0x8000) 13706 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 13707 op[0], op[1], BFD_RELOC_LO16); 13708 else 13709 { 13710 load_register (AT, &imm_expr, GPR_SIZE == 64); 13711 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 13712 op[0], op[1], AT); 13713 used_at = 1; 13714 } 13715 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13716 break; 13717 13718 case M_SGT: /* X > Y <==> Y < X. */ 13719 s = "slt"; 13720 goto sgt; 13721 case M_SGTU: 13722 s = "sltu"; 13723 sgt: 13724 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13725 break; 13726 13727 case M_SGT_I: /* X > I <==> I < X. */ 13728 s = "slt"; 13729 goto sgti; 13730 case M_SGTU_I: 13731 s = "sltu"; 13732 sgti: 13733 used_at = 1; 13734 load_register (AT, &imm_expr, GPR_SIZE == 64); 13735 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13736 break; 13737 13738 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */ 13739 s = "slt"; 13740 goto sle; 13741 case M_SLEU: 13742 s = "sltu"; 13743 sle: 13744 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); 13745 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13746 break; 13747 13748 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ 13749 s = "slt"; 13750 goto slei; 13751 case M_SLEU_I: 13752 s = "sltu"; 13753 slei: 13754 used_at = 1; 13755 load_register (AT, &imm_expr, GPR_SIZE == 64); 13756 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); 13757 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); 13758 break; 13759 13760 case M_SLT_I: 13761 if (imm_expr.X_add_number >= -0x8000 13762 && imm_expr.X_add_number < 0x8000) 13763 { 13764 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], 13765 BFD_RELOC_LO16); 13766 break; 13767 } 13768 used_at = 1; 13769 load_register (AT, &imm_expr, GPR_SIZE == 64); 13770 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); 13771 break; 13772 13773 case M_SLTU_I: 13774 if (imm_expr.X_add_number >= -0x8000 13775 && imm_expr.X_add_number < 0x8000) 13776 { 13777 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], 13778 BFD_RELOC_LO16); 13779 break; 13780 } 13781 used_at = 1; 13782 load_register (AT, &imm_expr, GPR_SIZE == 64); 13783 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); 13784 break; 13785 13786 case M_SNE: 13787 if (op[1] == 0) 13788 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); 13789 else if (op[2] == 0) 13790 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13791 else 13792 { 13793 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); 13794 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13795 } 13796 break; 13797 13798 case M_SNE_I: 13799 if (imm_expr.X_add_number == 0) 13800 { 13801 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); 13802 break; 13803 } 13804 if (op[1] == 0) 13805 { 13806 as_warn (_("instruction %s: result is always true"), 13807 ip->insn_mo->name); 13808 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", 13809 op[0], 0, BFD_RELOC_LO16); 13810 break; 13811 } 13812 if (CPU_HAS_SEQ (mips_opts.arch) 13813 && -512 <= imm_expr.X_add_number 13814 && imm_expr.X_add_number < 512) 13815 { 13816 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], 13817 (int) imm_expr.X_add_number); 13818 break; 13819 } 13820 if (imm_expr.X_add_number >= 0 13821 && imm_expr.X_add_number < 0x10000) 13822 { 13823 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], 13824 BFD_RELOC_LO16); 13825 } 13826 else if (imm_expr.X_add_number > -0x8000 13827 && imm_expr.X_add_number < 0) 13828 { 13829 imm_expr.X_add_number = -imm_expr.X_add_number; 13830 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", 13831 "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13832 } 13833 else if (CPU_HAS_SEQ (mips_opts.arch)) 13834 { 13835 used_at = 1; 13836 load_register (AT, &imm_expr, GPR_SIZE == 64); 13837 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); 13838 break; 13839 } 13840 else 13841 { 13842 load_register (AT, &imm_expr, GPR_SIZE == 64); 13843 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); 13844 used_at = 1; 13845 } 13846 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); 13847 break; 13848 13849 case M_SUB_I: 13850 s = "addi"; 13851 s2 = "sub"; 13852 if (ISA_IS_R6 (mips_opts.isa)) 13853 goto do_subi_i; 13854 else 13855 goto do_subi; 13856 case M_SUBU_I: 13857 s = "addiu"; 13858 s2 = "subu"; 13859 goto do_subi; 13860 case M_DSUB_I: 13861 dbl = 1; 13862 s = "daddi"; 13863 s2 = "dsub"; 13864 if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa)) 13865 goto do_subi; 13866 if (imm_expr.X_add_number > -0x200 13867 && imm_expr.X_add_number <= 0x200 13868 && !ISA_IS_R6 (mips_opts.isa)) 13869 { 13870 macro_build (NULL, s, "t,r,.", op[0], op[1], 13871 (int) -imm_expr.X_add_number); 13872 break; 13873 } 13874 goto do_subi_i; 13875 case M_DSUBU_I: 13876 dbl = 1; 13877 s = "daddiu"; 13878 s2 = "dsubu"; 13879 do_subi: 13880 if (imm_expr.X_add_number > -0x8000 13881 && imm_expr.X_add_number <= 0x8000) 13882 { 13883 imm_expr.X_add_number = -imm_expr.X_add_number; 13884 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); 13885 break; 13886 } 13887 do_subi_i: 13888 used_at = 1; 13889 load_register (AT, &imm_expr, dbl); 13890 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); 13891 break; 13892 13893 case M_TEQ_I: 13894 s = "teq"; 13895 goto trap; 13896 case M_TGE_I: 13897 s = "tge"; 13898 goto trap; 13899 case M_TGEU_I: 13900 s = "tgeu"; 13901 goto trap; 13902 case M_TLT_I: 13903 s = "tlt"; 13904 goto trap; 13905 case M_TLTU_I: 13906 s = "tltu"; 13907 goto trap; 13908 case M_TNE_I: 13909 s = "tne"; 13910 trap: 13911 used_at = 1; 13912 load_register (AT, &imm_expr, GPR_SIZE == 64); 13913 macro_build (NULL, s, "s,t", op[0], AT); 13914 break; 13915 13916 case M_TRUNCWS: 13917 case M_TRUNCWD: 13918 gas_assert (!mips_opts.micromips); 13919 gas_assert (mips_opts.isa == ISA_MIPS1); 13920 used_at = 1; 13921 13922 /* 13923 * Is the double cfc1 instruction a bug in the mips assembler; 13924 * or is there a reason for it? 13925 */ 13926 start_noreorder (); 13927 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13928 macro_build (NULL, "cfc1", "t,G", op[2], RA); 13929 macro_build (NULL, "nop", ""); 13930 expr1.X_add_number = 3; 13931 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); 13932 expr1.X_add_number = 2; 13933 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 13934 macro_build (NULL, "ctc1", "t,G", AT, RA); 13935 macro_build (NULL, "nop", ""); 13936 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 13937 op[0], op[1]); 13938 macro_build (NULL, "ctc1", "t,G", op[2], RA); 13939 macro_build (NULL, "nop", ""); 13940 end_noreorder (); 13941 break; 13942 13943 case M_ULH_AB: 13944 s = "lb"; 13945 s2 = "lbu"; 13946 off = 1; 13947 goto uld_st; 13948 case M_ULHU_AB: 13949 s = "lbu"; 13950 s2 = "lbu"; 13951 off = 1; 13952 goto uld_st; 13953 case M_ULW_AB: 13954 s = "lwl"; 13955 s2 = "lwr"; 13956 offbits = (mips_opts.micromips ? 12 : 16); 13957 off = 3; 13958 goto uld_st; 13959 case M_ULD_AB: 13960 s = "ldl"; 13961 s2 = "ldr"; 13962 offbits = (mips_opts.micromips ? 12 : 16); 13963 off = 7; 13964 goto uld_st; 13965 case M_USH_AB: 13966 s = "sb"; 13967 s2 = "sb"; 13968 off = 1; 13969 ust = 1; 13970 goto uld_st; 13971 case M_USW_AB: 13972 s = "swl"; 13973 s2 = "swr"; 13974 offbits = (mips_opts.micromips ? 12 : 16); 13975 off = 3; 13976 ust = 1; 13977 goto uld_st; 13978 case M_USD_AB: 13979 s = "sdl"; 13980 s2 = "sdr"; 13981 offbits = (mips_opts.micromips ? 12 : 16); 13982 off = 7; 13983 ust = 1; 13984 13985 uld_st: 13986 breg = op[2]; 13987 large_offset = !small_offset_p (off, align, offbits); 13988 ep = &offset_expr; 13989 expr1.X_add_number = 0; 13990 if (large_offset) 13991 { 13992 used_at = 1; 13993 tempreg = AT; 13994 if (small_offset_p (0, align, 16)) 13995 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, 13996 offset_reloc[0], offset_reloc[1], offset_reloc[2]); 13997 else 13998 { 13999 load_address (tempreg, ep, &used_at); 14000 if (breg != 0) 14001 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 14002 tempreg, tempreg, breg); 14003 } 14004 offset_reloc[0] = BFD_RELOC_LO16; 14005 offset_reloc[1] = BFD_RELOC_UNUSED; 14006 offset_reloc[2] = BFD_RELOC_UNUSED; 14007 breg = tempreg; 14008 tempreg = op[0]; 14009 ep = &expr1; 14010 } 14011 else if (!ust && op[0] == breg) 14012 { 14013 used_at = 1; 14014 tempreg = AT; 14015 } 14016 else 14017 tempreg = op[0]; 14018 14019 if (off == 1) 14020 goto ulh_sh; 14021 14022 if (!target_big_endian) 14023 ep->X_add_number += off; 14024 if (offbits == 12) 14025 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); 14026 else 14027 macro_build (ep, s, "t,o(b)", tempreg, -1, 14028 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 14029 14030 if (!target_big_endian) 14031 ep->X_add_number -= off; 14032 else 14033 ep->X_add_number += off; 14034 if (offbits == 12) 14035 macro_build (NULL, s2, "t,~(b)", 14036 tempreg, (int) ep->X_add_number, breg); 14037 else 14038 macro_build (ep, s2, "t,o(b)", tempreg, -1, 14039 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 14040 14041 /* If necessary, move the result in tempreg to the final destination. */ 14042 if (!ust && op[0] != tempreg) 14043 { 14044 /* Protect second load's delay slot. */ 14045 load_delay_nop (); 14046 move_register (op[0], tempreg); 14047 } 14048 break; 14049 14050 ulh_sh: 14051 used_at = 1; 14052 if (target_big_endian == ust) 14053 ep->X_add_number += off; 14054 tempreg = ust || large_offset ? op[0] : AT; 14055 macro_build (ep, s, "t,o(b)", tempreg, -1, 14056 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 14057 14058 /* For halfword transfers we need a temporary register to shuffle 14059 bytes. Unfortunately for M_USH_A we have none available before 14060 the next store as AT holds the base address. We deal with this 14061 case by clobbering TREG and then restoring it as with ULH. */ 14062 tempreg = ust == large_offset ? op[0] : AT; 14063 if (ust) 14064 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); 14065 14066 if (target_big_endian == ust) 14067 ep->X_add_number -= off; 14068 else 14069 ep->X_add_number += off; 14070 macro_build (ep, s2, "t,o(b)", tempreg, -1, 14071 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); 14072 14073 /* For M_USH_A re-retrieve the LSB. */ 14074 if (ust && large_offset) 14075 { 14076 if (target_big_endian) 14077 ep->X_add_number += off; 14078 else 14079 ep->X_add_number -= off; 14080 macro_build (&expr1, "lbu", "t,o(b)", AT, -1, 14081 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); 14082 } 14083 /* For ULH and M_USH_A OR the LSB in. */ 14084 if (!ust || large_offset) 14085 { 14086 tempreg = !large_offset ? AT : op[0]; 14087 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); 14088 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); 14089 } 14090 break; 14091 14092 default: 14093 /* FIXME: Check if this is one of the itbl macros, since they 14094 are added dynamically. */ 14095 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); 14096 break; 14097 } 14098 if (!mips_opts.at && used_at) 14099 as_bad (_("macro used $at after \".set noat\"")); 14100} 14101 14102/* Implement macros in mips16 mode. */ 14103 14104static void 14105mips16_macro (struct mips_cl_insn *ip) 14106{ 14107 const struct mips_operand_array *operands; 14108 int mask; 14109 int tmp; 14110 expressionS expr1; 14111 int dbl; 14112 const char *s, *s2, *s3; 14113 unsigned int op[MAX_OPERANDS]; 14114 unsigned int i; 14115 14116 mask = ip->insn_mo->mask; 14117 14118 operands = insn_operands (ip); 14119 for (i = 0; i < MAX_OPERANDS; i++) 14120 if (operands->operand[i]) 14121 op[i] = insn_extract_operand (ip, operands->operand[i]); 14122 else 14123 op[i] = -1; 14124 14125 expr1.X_op = O_constant; 14126 expr1.X_op_symbol = NULL; 14127 expr1.X_add_symbol = NULL; 14128 expr1.X_add_number = 1; 14129 14130 dbl = 0; 14131 14132 switch (mask) 14133 { 14134 default: 14135 abort (); 14136 14137 case M_DDIV_3: 14138 dbl = 1; 14139 /* Fall through. */ 14140 case M_DIV_3: 14141 s = "mflo"; 14142 goto do_div3; 14143 case M_DREM_3: 14144 dbl = 1; 14145 /* Fall through. */ 14146 case M_REM_3: 14147 s = "mfhi"; 14148 do_div3: 14149 start_noreorder (); 14150 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); 14151 expr1.X_add_number = 2; 14152 macro_build (&expr1, "bnez", "x,p", op[2]); 14153 macro_build (NULL, "break", "6", 7); 14154 14155 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 14156 since that causes an overflow. We should do that as well, 14157 but I don't see how to do the comparisons without a temporary 14158 register. */ 14159 end_noreorder (); 14160 macro_build (NULL, s, "x", op[0]); 14161 break; 14162 14163 case M_DIVU_3: 14164 s = "divu"; 14165 s2 = "mflo"; 14166 goto do_divu3; 14167 case M_REMU_3: 14168 s = "divu"; 14169 s2 = "mfhi"; 14170 goto do_divu3; 14171 case M_DDIVU_3: 14172 s = "ddivu"; 14173 s2 = "mflo"; 14174 goto do_divu3; 14175 case M_DREMU_3: 14176 s = "ddivu"; 14177 s2 = "mfhi"; 14178 do_divu3: 14179 start_noreorder (); 14180 macro_build (NULL, s, ".,x,y", op[1], op[2]); 14181 expr1.X_add_number = 2; 14182 macro_build (&expr1, "bnez", "x,p", op[2]); 14183 macro_build (NULL, "break", "6", 7); 14184 end_noreorder (); 14185 macro_build (NULL, s2, "x", op[0]); 14186 break; 14187 14188 case M_DMUL: 14189 dbl = 1; 14190 /* Fall through. */ 14191 case M_MUL: 14192 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); 14193 macro_build (NULL, "mflo", "x", op[0]); 14194 break; 14195 14196 case M_DSUBU_I: 14197 dbl = 1; 14198 goto do_subu; 14199 case M_SUBU_I: 14200 do_subu: 14201 imm_expr.X_add_number = -imm_expr.X_add_number; 14202 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); 14203 break; 14204 14205 case M_SUBU_I_2: 14206 imm_expr.X_add_number = -imm_expr.X_add_number; 14207 macro_build (&imm_expr, "addiu", "x,k", op[0]); 14208 break; 14209 14210 case M_DSUBU_I_2: 14211 imm_expr.X_add_number = -imm_expr.X_add_number; 14212 macro_build (&imm_expr, "daddiu", "y,j", op[0]); 14213 break; 14214 14215 case M_BEQ: 14216 s = "cmp"; 14217 s2 = "bteqz"; 14218 goto do_branch; 14219 case M_BNE: 14220 s = "cmp"; 14221 s2 = "btnez"; 14222 goto do_branch; 14223 case M_BLT: 14224 s = "slt"; 14225 s2 = "btnez"; 14226 goto do_branch; 14227 case M_BLTU: 14228 s = "sltu"; 14229 s2 = "btnez"; 14230 goto do_branch; 14231 case M_BLE: 14232 s = "slt"; 14233 s2 = "bteqz"; 14234 goto do_reverse_branch; 14235 case M_BLEU: 14236 s = "sltu"; 14237 s2 = "bteqz"; 14238 goto do_reverse_branch; 14239 case M_BGE: 14240 s = "slt"; 14241 s2 = "bteqz"; 14242 goto do_branch; 14243 case M_BGEU: 14244 s = "sltu"; 14245 s2 = "bteqz"; 14246 goto do_branch; 14247 case M_BGT: 14248 s = "slt"; 14249 s2 = "btnez"; 14250 goto do_reverse_branch; 14251 case M_BGTU: 14252 s = "sltu"; 14253 s2 = "btnez"; 14254 14255 do_reverse_branch: 14256 tmp = op[1]; 14257 op[1] = op[0]; 14258 op[0] = tmp; 14259 14260 do_branch: 14261 macro_build (NULL, s, "x,y", op[0], op[1]); 14262 macro_build (&offset_expr, s2, "p"); 14263 break; 14264 14265 case M_BEQ_I: 14266 s = "cmpi"; 14267 s2 = "bteqz"; 14268 s3 = "x,U"; 14269 goto do_branch_i; 14270 case M_BNE_I: 14271 s = "cmpi"; 14272 s2 = "btnez"; 14273 s3 = "x,U"; 14274 goto do_branch_i; 14275 case M_BLT_I: 14276 s = "slti"; 14277 s2 = "btnez"; 14278 s3 = "x,8"; 14279 goto do_branch_i; 14280 case M_BLTU_I: 14281 s = "sltiu"; 14282 s2 = "btnez"; 14283 s3 = "x,8"; 14284 goto do_branch_i; 14285 case M_BLE_I: 14286 s = "slti"; 14287 s2 = "btnez"; 14288 s3 = "x,8"; 14289 goto do_addone_branch_i; 14290 case M_BLEU_I: 14291 s = "sltiu"; 14292 s2 = "btnez"; 14293 s3 = "x,8"; 14294 goto do_addone_branch_i; 14295 case M_BGE_I: 14296 s = "slti"; 14297 s2 = "bteqz"; 14298 s3 = "x,8"; 14299 goto do_branch_i; 14300 case M_BGEU_I: 14301 s = "sltiu"; 14302 s2 = "bteqz"; 14303 s3 = "x,8"; 14304 goto do_branch_i; 14305 case M_BGT_I: 14306 s = "slti"; 14307 s2 = "bteqz"; 14308 s3 = "x,8"; 14309 goto do_addone_branch_i; 14310 case M_BGTU_I: 14311 s = "sltiu"; 14312 s2 = "bteqz"; 14313 s3 = "x,8"; 14314 14315 do_addone_branch_i: 14316 ++imm_expr.X_add_number; 14317 14318 do_branch_i: 14319 macro_build (&imm_expr, s, s3, op[0]); 14320 macro_build (&offset_expr, s2, "p"); 14321 break; 14322 14323 case M_ABS: 14324 expr1.X_add_number = 0; 14325 macro_build (&expr1, "slti", "x,8", op[1]); 14326 if (op[0] != op[1]) 14327 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); 14328 expr1.X_add_number = 2; 14329 macro_build (&expr1, "bteqz", "p"); 14330 macro_build (NULL, "neg", "x,w", op[0], op[0]); 14331 break; 14332 } 14333} 14334 14335/* Look up instruction [START, START + LENGTH) in HASH. Record any extra 14336 opcode bits in *OPCODE_EXTRA. */ 14337 14338static struct mips_opcode * 14339mips_lookup_insn (struct hash_control *hash, const char *start, 14340 ssize_t length, unsigned int *opcode_extra) 14341{ 14342 char *name, *dot, *p; 14343 unsigned int mask, suffix; 14344 ssize_t opend; 14345 struct mips_opcode *insn; 14346 14347 /* Make a copy of the instruction so that we can fiddle with it. */ 14348 name = xstrndup (start, length); 14349 14350 /* Look up the instruction as-is. */ 14351 insn = (struct mips_opcode *) hash_find (hash, name); 14352 if (insn) 14353 goto end; 14354 14355 dot = strchr (name, '.'); 14356 if (dot && dot[1]) 14357 { 14358 /* Try to interpret the text after the dot as a VU0 channel suffix. */ 14359 p = mips_parse_vu0_channels (dot + 1, &mask); 14360 if (*p == 0 && mask != 0) 14361 { 14362 *dot = 0; 14363 insn = (struct mips_opcode *) hash_find (hash, name); 14364 *dot = '.'; 14365 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) 14366 { 14367 *opcode_extra |= mask << mips_vu0_channel_mask.lsb; 14368 goto end; 14369 } 14370 } 14371 } 14372 14373 if (mips_opts.micromips) 14374 { 14375 /* See if there's an instruction size override suffix, 14376 either `16' or `32', at the end of the mnemonic proper, 14377 that defines the operation, i.e. before the first `.' 14378 character if any. Strip it and retry. */ 14379 opend = dot != NULL ? dot - name : length; 14380 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') 14381 suffix = 2; 14382 else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2') 14383 suffix = 4; 14384 else 14385 suffix = 0; 14386 if (suffix) 14387 { 14388 memmove (name + opend - 2, name + opend, length - opend + 1); 14389 insn = (struct mips_opcode *) hash_find (hash, name); 14390 if (insn) 14391 { 14392 forced_insn_length = suffix; 14393 goto end; 14394 } 14395 } 14396 } 14397 14398 insn = NULL; 14399 end: 14400 free (name); 14401 return insn; 14402} 14403 14404/* Assemble an instruction into its binary format. If the instruction 14405 is a macro, set imm_expr and offset_expr to the values associated 14406 with "I" and "A" operands respectively. Otherwise store the value 14407 of the relocatable field (if any) in offset_expr. In both cases 14408 set offset_reloc to the relocation operators applied to offset_expr. */ 14409 14410static void 14411mips_ip (char *str, struct mips_cl_insn *insn) 14412{ 14413 const struct mips_opcode *first, *past; 14414 struct hash_control *hash; 14415 char format; 14416 size_t end; 14417 struct mips_operand_token *tokens; 14418 unsigned int opcode_extra; 14419 14420 if (mips_opts.micromips) 14421 { 14422 hash = micromips_op_hash; 14423 past = µmips_opcodes[bfd_micromips_num_opcodes]; 14424 } 14425 else 14426 { 14427 hash = op_hash; 14428 past = &mips_opcodes[NUMOPCODES]; 14429 } 14430 forced_insn_length = 0; 14431 opcode_extra = 0; 14432 14433 /* We first try to match an instruction up to a space or to the end. */ 14434 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) 14435 continue; 14436 14437 first = mips_lookup_insn (hash, str, end, &opcode_extra); 14438 if (first == NULL) 14439 { 14440 set_insn_error (0, _("unrecognized opcode")); 14441 return; 14442 } 14443 14444 if (strcmp (first->name, "li.s") == 0) 14445 format = 'f'; 14446 else if (strcmp (first->name, "li.d") == 0) 14447 format = 'd'; 14448 else 14449 format = 0; 14450 tokens = mips_parse_arguments (str + end, format); 14451 if (!tokens) 14452 return; 14453 14454 if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) 14455 && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) 14456 set_insn_error (0, _("invalid operands")); 14457 14458 obstack_free (&mips_operand_tokens, tokens); 14459} 14460 14461/* As for mips_ip, but used when assembling MIPS16 code. 14462 Also set forced_insn_length to the resulting instruction size in 14463 bytes if the user explicitly requested a small or extended instruction. */ 14464 14465static void 14466mips16_ip (char *str, struct mips_cl_insn *insn) 14467{ 14468 char *end, *s, c; 14469 struct mips_opcode *first; 14470 struct mips_operand_token *tokens; 14471 unsigned int l; 14472 14473 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) 14474 ; 14475 end = s; 14476 c = *end; 14477 14478 l = 0; 14479 switch (c) 14480 { 14481 case '\0': 14482 break; 14483 14484 case ' ': 14485 s++; 14486 break; 14487 14488 case '.': 14489 s++; 14490 if (*s == 't') 14491 { 14492 l = 2; 14493 s++; 14494 } 14495 else if (*s == 'e') 14496 { 14497 l = 4; 14498 s++; 14499 } 14500 if (*s == '\0') 14501 break; 14502 else if (*s++ == ' ') 14503 break; 14504 set_insn_error (0, _("unrecognized opcode")); 14505 return; 14506 } 14507 forced_insn_length = l; 14508 14509 *end = 0; 14510 first = (struct mips_opcode *) hash_find (mips16_op_hash, str); 14511 *end = c; 14512 14513 if (!first) 14514 { 14515 set_insn_error (0, _("unrecognized opcode")); 14516 return; 14517 } 14518 14519 tokens = mips_parse_arguments (s, 0); 14520 if (!tokens) 14521 return; 14522 14523 if (!match_mips16_insns (insn, first, tokens)) 14524 set_insn_error (0, _("invalid operands")); 14525 14526 obstack_free (&mips_operand_tokens, tokens); 14527} 14528 14529/* Marshal immediate value VAL for an extended MIPS16 instruction. 14530 NBITS is the number of significant bits in VAL. */ 14531 14532static unsigned long 14533mips16_immed_extend (offsetT val, unsigned int nbits) 14534{ 14535 int extval; 14536 14537 extval = 0; 14538 val &= (1U << nbits) - 1; 14539 if (nbits == 16 || nbits == 9) 14540 { 14541 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 14542 val &= 0x1f; 14543 } 14544 else if (nbits == 15) 14545 { 14546 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 14547 val &= 0xf; 14548 } 14549 else if (nbits == 6) 14550 { 14551 extval = ((val & 0x1f) << 6) | (val & 0x20); 14552 val = 0; 14553 } 14554 return (extval << 16) | val; 14555} 14556 14557/* Like decode_mips16_operand, but require the operand to be defined and 14558 require it to be an integer. */ 14559 14560static const struct mips_int_operand * 14561mips16_immed_operand (int type, bfd_boolean extended_p) 14562{ 14563 const struct mips_operand *operand; 14564 14565 operand = decode_mips16_operand (type, extended_p); 14566 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) 14567 abort (); 14568 return (const struct mips_int_operand *) operand; 14569} 14570 14571/* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ 14572 14573static bfd_boolean 14574mips16_immed_in_range_p (const struct mips_int_operand *operand, 14575 bfd_reloc_code_real_type reloc, offsetT sval) 14576{ 14577 int min_val, max_val; 14578 14579 min_val = mips_int_operand_min (operand); 14580 max_val = mips_int_operand_max (operand); 14581 if (reloc != BFD_RELOC_UNUSED) 14582 { 14583 if (min_val < 0) 14584 sval = SEXT_16BIT (sval); 14585 else 14586 sval &= 0xffff; 14587 } 14588 14589 return (sval >= min_val 14590 && sval <= max_val 14591 && (sval & ((1 << operand->shift) - 1)) == 0); 14592} 14593 14594/* Install immediate value VAL into MIPS16 instruction *INSN, 14595 extending it if necessary. The instruction in *INSN may 14596 already be extended. 14597 14598 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED 14599 if none. In the former case, VAL is a 16-bit number with no 14600 defined signedness. 14601 14602 TYPE is the type of the immediate field. USER_INSN_LENGTH 14603 is the length that the user requested, or 0 if none. */ 14604 14605static void 14606mips16_immed (const char *file, unsigned int line, int type, 14607 bfd_reloc_code_real_type reloc, offsetT val, 14608 unsigned int user_insn_length, unsigned long *insn) 14609{ 14610 const struct mips_int_operand *operand; 14611 unsigned int uval, length; 14612 14613 operand = mips16_immed_operand (type, FALSE); 14614 if (!mips16_immed_in_range_p (operand, reloc, val)) 14615 { 14616 /* We need an extended instruction. */ 14617 if (user_insn_length == 2) 14618 as_bad_where (file, line, _("invalid unextended operand value")); 14619 else 14620 *insn |= MIPS16_EXTEND; 14621 } 14622 else if (user_insn_length == 4) 14623 { 14624 /* The operand doesn't force an unextended instruction to be extended. 14625 Warn if the user wanted an extended instruction anyway. */ 14626 *insn |= MIPS16_EXTEND; 14627 as_warn_where (file, line, 14628 _("extended operand requested but not required")); 14629 } 14630 14631 length = mips16_opcode_length (*insn); 14632 if (length == 4) 14633 { 14634 operand = mips16_immed_operand (type, TRUE); 14635 if (!mips16_immed_in_range_p (operand, reloc, val)) 14636 as_bad_where (file, line, 14637 _("operand value out of range for instruction")); 14638 } 14639 uval = ((unsigned int) val >> operand->shift) - operand->bias; 14640 if (length == 2 || operand->root.lsb != 0) 14641 *insn = mips_insert_operand (&operand->root, *insn, uval); 14642 else 14643 *insn |= mips16_immed_extend (uval, operand->root.size); 14644} 14645 14646struct percent_op_match 14647{ 14648 const char *str; 14649 bfd_reloc_code_real_type reloc; 14650}; 14651 14652static const struct percent_op_match mips_percent_op[] = 14653{ 14654 {"%lo", BFD_RELOC_LO16}, 14655 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 14656 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 14657 {"%call16", BFD_RELOC_MIPS_CALL16}, 14658 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 14659 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 14660 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 14661 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 14662 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 14663 {"%got", BFD_RELOC_MIPS_GOT16}, 14664 {"%gp_rel", BFD_RELOC_GPREL16}, 14665 {"%gprel", BFD_RELOC_GPREL16}, 14666 {"%half", BFD_RELOC_16}, 14667 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 14668 {"%higher", BFD_RELOC_MIPS_HIGHER}, 14669 {"%neg", BFD_RELOC_MIPS_SUB}, 14670 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, 14671 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, 14672 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, 14673 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, 14674 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, 14675 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, 14676 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, 14677 {"%hi", BFD_RELOC_HI16_S}, 14678 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, 14679 {"%pcrel_lo", BFD_RELOC_LO16_PCREL} 14680}; 14681 14682static const struct percent_op_match mips16_percent_op[] = 14683{ 14684 {"%lo", BFD_RELOC_MIPS16_LO16}, 14685 {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, 14686 {"%gprel", BFD_RELOC_MIPS16_GPREL}, 14687 {"%got", BFD_RELOC_MIPS16_GOT16}, 14688 {"%call16", BFD_RELOC_MIPS16_CALL16}, 14689 {"%hi", BFD_RELOC_MIPS16_HI16_S}, 14690 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, 14691 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, 14692 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, 14693 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, 14694 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, 14695 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, 14696 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} 14697}; 14698 14699 14700/* Return true if *STR points to a relocation operator. When returning true, 14701 move *STR over the operator and store its relocation code in *RELOC. 14702 Leave both *STR and *RELOC alone when returning false. */ 14703 14704static bfd_boolean 14705parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 14706{ 14707 const struct percent_op_match *percent_op; 14708 size_t limit, i; 14709 14710 if (mips_opts.mips16) 14711 { 14712 percent_op = mips16_percent_op; 14713 limit = ARRAY_SIZE (mips16_percent_op); 14714 } 14715 else 14716 { 14717 percent_op = mips_percent_op; 14718 limit = ARRAY_SIZE (mips_percent_op); 14719 } 14720 14721 for (i = 0; i < limit; i++) 14722 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 14723 { 14724 int len = strlen (percent_op[i].str); 14725 14726 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 14727 continue; 14728 14729 *str += strlen (percent_op[i].str); 14730 *reloc = percent_op[i].reloc; 14731 14732 /* Check whether the output BFD supports this relocation. 14733 If not, issue an error and fall back on something safe. */ 14734 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 14735 { 14736 as_bad (_("relocation %s isn't supported by the current ABI"), 14737 percent_op[i].str); 14738 *reloc = BFD_RELOC_UNUSED; 14739 } 14740 return TRUE; 14741 } 14742 return FALSE; 14743} 14744 14745 14746/* Parse string STR as a 16-bit relocatable operand. Store the 14747 expression in *EP and the relocations in the array starting 14748 at RELOC. Return the number of relocation operators used. 14749 14750 On exit, EXPR_END points to the first character after the expression. */ 14751 14752static size_t 14753my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 14754 char *str) 14755{ 14756 bfd_reloc_code_real_type reversed_reloc[3]; 14757 size_t reloc_index, i; 14758 int crux_depth, str_depth; 14759 char *crux; 14760 14761 /* Search for the start of the main expression, recoding relocations 14762 in REVERSED_RELOC. End the loop with CRUX pointing to the start 14763 of the main expression and with CRUX_DEPTH containing the number 14764 of open brackets at that point. */ 14765 reloc_index = -1; 14766 str_depth = 0; 14767 do 14768 { 14769 reloc_index++; 14770 crux = str; 14771 crux_depth = str_depth; 14772 14773 /* Skip over whitespace and brackets, keeping count of the number 14774 of brackets. */ 14775 while (*str == ' ' || *str == '\t' || *str == '(') 14776 if (*str++ == '(') 14777 str_depth++; 14778 } 14779 while (*str == '%' 14780 && reloc_index < (HAVE_NEWABI ? 3 : 1) 14781 && parse_relocation (&str, &reversed_reloc[reloc_index])); 14782 14783 my_getExpression (ep, crux); 14784 str = expr_end; 14785 14786 /* Match every open bracket. */ 14787 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 14788 if (*str++ == ')') 14789 crux_depth--; 14790 14791 if (crux_depth > 0) 14792 as_bad (_("unclosed '('")); 14793 14794 expr_end = str; 14795 14796 if (reloc_index != 0) 14797 { 14798 prev_reloc_op_frag = frag_now; 14799 for (i = 0; i < reloc_index; i++) 14800 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 14801 } 14802 14803 return reloc_index; 14804} 14805 14806static void 14807my_getExpression (expressionS *ep, char *str) 14808{ 14809 char *save_in; 14810 14811 save_in = input_line_pointer; 14812 input_line_pointer = str; 14813 expression (ep); 14814 expr_end = input_line_pointer; 14815 input_line_pointer = save_in; 14816} 14817 14818const char * 14819md_atof (int type, char *litP, int *sizeP) 14820{ 14821 return ieee_md_atof (type, litP, sizeP, target_big_endian); 14822} 14823 14824void 14825md_number_to_chars (char *buf, valueT val, int n) 14826{ 14827 if (target_big_endian) 14828 number_to_chars_bigendian (buf, val, n); 14829 else 14830 number_to_chars_littleendian (buf, val, n); 14831} 14832 14833static int support_64bit_objects(void) 14834{ 14835 const char **list, **l; 14836 int yes; 14837 14838 list = bfd_target_list (); 14839 for (l = list; *l != NULL; l++) 14840 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 14841 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) 14842 break; 14843 yes = (*l != NULL); 14844 free (list); 14845 return yes; 14846} 14847 14848/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 14849 NEW_VALUE. Warn if another value was already specified. Note: 14850 we have to defer parsing the -march and -mtune arguments in order 14851 to handle 'from-abi' correctly, since the ABI might be specified 14852 in a later argument. */ 14853 14854static void 14855mips_set_option_string (const char **string_ptr, const char *new_value) 14856{ 14857 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 14858 as_warn (_("a different %s was already specified, is now %s"), 14859 string_ptr == &mips_arch_string ? "-march" : "-mtune", 14860 new_value); 14861 14862 *string_ptr = new_value; 14863} 14864 14865int 14866md_parse_option (int c, const char *arg) 14867{ 14868 unsigned int i; 14869 14870 for (i = 0; i < ARRAY_SIZE (mips_ases); i++) 14871 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) 14872 { 14873 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, 14874 c == mips_ases[i].option_on); 14875 return 1; 14876 } 14877 14878 switch (c) 14879 { 14880 case OPTION_CONSTRUCT_FLOATS: 14881 mips_disable_float_construction = 0; 14882 break; 14883 14884 case OPTION_NO_CONSTRUCT_FLOATS: 14885 mips_disable_float_construction = 1; 14886 break; 14887 14888 case OPTION_TRAP: 14889 mips_trap = 1; 14890 break; 14891 14892 case OPTION_BREAK: 14893 mips_trap = 0; 14894 break; 14895 14896 case OPTION_EB: 14897 target_big_endian = 1; 14898 break; 14899 14900 case OPTION_EL: 14901 target_big_endian = 0; 14902 break; 14903 14904 case 'O': 14905 if (arg == NULL) 14906 mips_optimize = 1; 14907 else if (arg[0] == '0') 14908 mips_optimize = 0; 14909 else if (arg[0] == '1') 14910 mips_optimize = 1; 14911 else 14912 mips_optimize = 2; 14913 break; 14914 14915 case 'g': 14916 if (arg == NULL) 14917 mips_debug = 2; 14918 else 14919 mips_debug = atoi (arg); 14920 break; 14921 14922 case OPTION_MIPS1: 14923 file_mips_opts.isa = ISA_MIPS1; 14924 break; 14925 14926 case OPTION_MIPS2: 14927 file_mips_opts.isa = ISA_MIPS2; 14928 break; 14929 14930 case OPTION_MIPS3: 14931 file_mips_opts.isa = ISA_MIPS3; 14932 break; 14933 14934 case OPTION_MIPS4: 14935 file_mips_opts.isa = ISA_MIPS4; 14936 break; 14937 14938 case OPTION_MIPS5: 14939 file_mips_opts.isa = ISA_MIPS5; 14940 break; 14941 14942 case OPTION_MIPS32: 14943 file_mips_opts.isa = ISA_MIPS32; 14944 break; 14945 14946 case OPTION_MIPS32R2: 14947 file_mips_opts.isa = ISA_MIPS32R2; 14948 break; 14949 14950 case OPTION_MIPS32R3: 14951 file_mips_opts.isa = ISA_MIPS32R3; 14952 break; 14953 14954 case OPTION_MIPS32R5: 14955 file_mips_opts.isa = ISA_MIPS32R5; 14956 break; 14957 14958 case OPTION_MIPS32R6: 14959 file_mips_opts.isa = ISA_MIPS32R6; 14960 break; 14961 14962 case OPTION_MIPS64R2: 14963 file_mips_opts.isa = ISA_MIPS64R2; 14964 break; 14965 14966 case OPTION_MIPS64R3: 14967 file_mips_opts.isa = ISA_MIPS64R3; 14968 break; 14969 14970 case OPTION_MIPS64R5: 14971 file_mips_opts.isa = ISA_MIPS64R5; 14972 break; 14973 14974 case OPTION_MIPS64R6: 14975 file_mips_opts.isa = ISA_MIPS64R6; 14976 break; 14977 14978 case OPTION_MIPS64: 14979 file_mips_opts.isa = ISA_MIPS64; 14980 break; 14981 14982 case OPTION_MTUNE: 14983 mips_set_option_string (&mips_tune_string, arg); 14984 break; 14985 14986 case OPTION_MARCH: 14987 mips_set_option_string (&mips_arch_string, arg); 14988 break; 14989 14990 case OPTION_M4650: 14991 mips_set_option_string (&mips_arch_string, "4650"); 14992 mips_set_option_string (&mips_tune_string, "4650"); 14993 break; 14994 14995 case OPTION_NO_M4650: 14996 break; 14997 14998 case OPTION_M4010: 14999 mips_set_option_string (&mips_arch_string, "4010"); 15000 mips_set_option_string (&mips_tune_string, "4010"); 15001 break; 15002 15003 case OPTION_NO_M4010: 15004 break; 15005 15006 case OPTION_M4100: 15007 mips_set_option_string (&mips_arch_string, "4100"); 15008 mips_set_option_string (&mips_tune_string, "4100"); 15009 break; 15010 15011 case OPTION_NO_M4100: 15012 break; 15013 15014 case OPTION_M3900: 15015 mips_set_option_string (&mips_arch_string, "3900"); 15016 mips_set_option_string (&mips_tune_string, "3900"); 15017 break; 15018 15019 case OPTION_NO_M3900: 15020 break; 15021 15022 case OPTION_MICROMIPS: 15023 if (file_mips_opts.mips16 == 1) 15024 { 15025 as_bad (_("-mmicromips cannot be used with -mips16")); 15026 return 0; 15027 } 15028 file_mips_opts.micromips = 1; 15029 mips_no_prev_insn (); 15030 break; 15031 15032 case OPTION_NO_MICROMIPS: 15033 file_mips_opts.micromips = 0; 15034 mips_no_prev_insn (); 15035 break; 15036 15037 case OPTION_MIPS16: 15038 if (file_mips_opts.micromips == 1) 15039 { 15040 as_bad (_("-mips16 cannot be used with -micromips")); 15041 return 0; 15042 } 15043 file_mips_opts.mips16 = 1; 15044 mips_no_prev_insn (); 15045 break; 15046 15047 case OPTION_NO_MIPS16: 15048 file_mips_opts.mips16 = 0; 15049 mips_no_prev_insn (); 15050 break; 15051 15052 case OPTION_FIX_24K: 15053 mips_fix_24k = 1; 15054 break; 15055 15056 case OPTION_NO_FIX_24K: 15057 mips_fix_24k = 0; 15058 break; 15059 15060 case OPTION_FIX_RM7000: 15061 mips_fix_rm7000 = 1; 15062 break; 15063 15064 case OPTION_NO_FIX_RM7000: 15065 mips_fix_rm7000 = 0; 15066 break; 15067 15068 case OPTION_FIX_LOONGSON3_LLSC: 15069 mips_fix_loongson3_llsc = TRUE; 15070 break; 15071 15072 case OPTION_NO_FIX_LOONGSON3_LLSC: 15073 mips_fix_loongson3_llsc = FALSE; 15074 break; 15075 15076 case OPTION_FIX_LOONGSON2F_JUMP: 15077 mips_fix_loongson2f_jump = TRUE; 15078 break; 15079 15080 case OPTION_NO_FIX_LOONGSON2F_JUMP: 15081 mips_fix_loongson2f_jump = FALSE; 15082 break; 15083 15084 case OPTION_FIX_LOONGSON2F_NOP: 15085 mips_fix_loongson2f_nop = TRUE; 15086 break; 15087 15088 case OPTION_NO_FIX_LOONGSON2F_NOP: 15089 mips_fix_loongson2f_nop = FALSE; 15090 break; 15091 15092 case OPTION_FIX_VR4120: 15093 mips_fix_vr4120 = 1; 15094 break; 15095 15096 case OPTION_NO_FIX_VR4120: 15097 mips_fix_vr4120 = 0; 15098 break; 15099 15100 case OPTION_FIX_VR4130: 15101 mips_fix_vr4130 = 1; 15102 break; 15103 15104 case OPTION_NO_FIX_VR4130: 15105 mips_fix_vr4130 = 0; 15106 break; 15107 15108 case OPTION_FIX_LOONGSON2F_BTB: 15109 mips_fix_loongson2f_btb = 1; 15110 break; 15111 15112 case OPTION_NO_FIX_LOONGSON2F_BTB: 15113 mips_fix_loongson2f_btb = 0; 15114 break; 15115 15116 case OPTION_FIX_CN63XXP1: 15117 mips_fix_cn63xxp1 = TRUE; 15118 break; 15119 15120 case OPTION_NO_FIX_CN63XXP1: 15121 mips_fix_cn63xxp1 = FALSE; 15122 break; 15123 15124 case OPTION_FIX_R5900: 15125 mips_fix_r5900 = TRUE; 15126 mips_fix_r5900_explicit = TRUE; 15127 break; 15128 15129 case OPTION_NO_FIX_R5900: 15130 mips_fix_r5900 = FALSE; 15131 mips_fix_r5900_explicit = TRUE; 15132 break; 15133 15134 case OPTION_RELAX_BRANCH: 15135 mips_relax_branch = 1; 15136 break; 15137 15138 case OPTION_NO_RELAX_BRANCH: 15139 mips_relax_branch = 0; 15140 break; 15141 15142 case OPTION_IGNORE_BRANCH_ISA: 15143 mips_ignore_branch_isa = TRUE; 15144 break; 15145 15146 case OPTION_NO_IGNORE_BRANCH_ISA: 15147 mips_ignore_branch_isa = FALSE; 15148 break; 15149 15150 case OPTION_INSN32: 15151 file_mips_opts.insn32 = TRUE; 15152 break; 15153 15154 case OPTION_NO_INSN32: 15155 file_mips_opts.insn32 = FALSE; 15156 break; 15157 15158 case OPTION_MSHARED: 15159 mips_in_shared = TRUE; 15160 break; 15161 15162 case OPTION_MNO_SHARED: 15163 mips_in_shared = FALSE; 15164 break; 15165 15166 case OPTION_MSYM32: 15167 file_mips_opts.sym32 = TRUE; 15168 break; 15169 15170 case OPTION_MNO_SYM32: 15171 file_mips_opts.sym32 = FALSE; 15172 break; 15173 15174 /* When generating ELF code, we permit -KPIC and -call_shared to 15175 select SVR4_PIC, and -non_shared to select no PIC. This is 15176 intended to be compatible with Irix 5. */ 15177 case OPTION_CALL_SHARED: 15178 mips_pic = SVR4_PIC; 15179 mips_abicalls = TRUE; 15180 break; 15181 15182 case OPTION_CALL_NONPIC: 15183 mips_pic = NO_PIC; 15184 mips_abicalls = TRUE; 15185 break; 15186 15187 case OPTION_NON_SHARED: 15188 mips_pic = NO_PIC; 15189 mips_abicalls = FALSE; 15190 break; 15191 15192 /* The -xgot option tells the assembler to use 32 bit offsets 15193 when accessing the got in SVR4_PIC mode. It is for Irix 15194 compatibility. */ 15195 case OPTION_XGOT: 15196 mips_big_got = 1; 15197 break; 15198 15199 case 'G': 15200 g_switch_value = atoi (arg); 15201 g_switch_seen = 1; 15202 break; 15203 15204 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 15205 and -mabi=64. */ 15206 case OPTION_32: 15207 mips_abi = O32_ABI; 15208 break; 15209 15210 case OPTION_N32: 15211 mips_abi = N32_ABI; 15212 break; 15213 15214 case OPTION_64: 15215 mips_abi = N64_ABI; 15216 if (!support_64bit_objects()) 15217 as_fatal (_("no compiled in support for 64 bit object file format")); 15218 break; 15219 15220 case OPTION_GP32: 15221 file_mips_opts.gp = 32; 15222 break; 15223 15224 case OPTION_GP64: 15225 file_mips_opts.gp = 64; 15226 break; 15227 15228 case OPTION_FP32: 15229 file_mips_opts.fp = 32; 15230 break; 15231 15232 case OPTION_FPXX: 15233 file_mips_opts.fp = 0; 15234 break; 15235 15236 case OPTION_FP64: 15237 file_mips_opts.fp = 64; 15238 break; 15239 15240 case OPTION_ODD_SPREG: 15241 file_mips_opts.oddspreg = 1; 15242 break; 15243 15244 case OPTION_NO_ODD_SPREG: 15245 file_mips_opts.oddspreg = 0; 15246 break; 15247 15248 case OPTION_SINGLE_FLOAT: 15249 file_mips_opts.single_float = 1; 15250 break; 15251 15252 case OPTION_DOUBLE_FLOAT: 15253 file_mips_opts.single_float = 0; 15254 break; 15255 15256 case OPTION_SOFT_FLOAT: 15257 file_mips_opts.soft_float = 1; 15258 break; 15259 15260 case OPTION_HARD_FLOAT: 15261 file_mips_opts.soft_float = 0; 15262 break; 15263 15264 case OPTION_MABI: 15265 if (strcmp (arg, "32") == 0) 15266 mips_abi = O32_ABI; 15267 else if (strcmp (arg, "o64") == 0) 15268 mips_abi = O64_ABI; 15269 else if (strcmp (arg, "n32") == 0) 15270 mips_abi = N32_ABI; 15271 else if (strcmp (arg, "64") == 0) 15272 { 15273 mips_abi = N64_ABI; 15274 if (! support_64bit_objects()) 15275 as_fatal (_("no compiled in support for 64 bit object file " 15276 "format")); 15277 } 15278 else if (strcmp (arg, "eabi") == 0) 15279 mips_abi = EABI_ABI; 15280 else 15281 { 15282 as_fatal (_("invalid abi -mabi=%s"), arg); 15283 return 0; 15284 } 15285 break; 15286 15287 case OPTION_M7000_HILO_FIX: 15288 mips_7000_hilo_fix = TRUE; 15289 break; 15290 15291 case OPTION_MNO_7000_HILO_FIX: 15292 mips_7000_hilo_fix = FALSE; 15293 break; 15294 15295 case OPTION_MDEBUG: 15296 mips_flag_mdebug = TRUE; 15297 break; 15298 15299 case OPTION_NO_MDEBUG: 15300 mips_flag_mdebug = FALSE; 15301 break; 15302 15303 case OPTION_PDR: 15304 mips_flag_pdr = TRUE; 15305 break; 15306 15307 case OPTION_NO_PDR: 15308 mips_flag_pdr = FALSE; 15309 break; 15310 15311 case OPTION_MVXWORKS_PIC: 15312 mips_pic = VXWORKS_PIC; 15313 break; 15314 15315 case OPTION_NAN: 15316 if (strcmp (arg, "2008") == 0) 15317 mips_nan2008 = 1; 15318 else if (strcmp (arg, "legacy") == 0) 15319 mips_nan2008 = 0; 15320 else 15321 { 15322 as_fatal (_("invalid NaN setting -mnan=%s"), arg); 15323 return 0; 15324 } 15325 break; 15326 15327 default: 15328 return 0; 15329 } 15330 15331 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; 15332 15333 return 1; 15334} 15335 15336/* Set up globals to tune for the ISA or processor described by INFO. */ 15337 15338static void 15339mips_set_tune (const struct mips_cpu_info *info) 15340{ 15341 if (info != 0) 15342 mips_tune = info->cpu; 15343} 15344 15345 15346void 15347mips_after_parse_args (void) 15348{ 15349 const struct mips_cpu_info *arch_info = 0; 15350 const struct mips_cpu_info *tune_info = 0; 15351 15352 /* GP relative stuff not working for PE. */ 15353 if (strncmp (TARGET_OS, "pe", 2) == 0) 15354 { 15355 if (g_switch_seen && g_switch_value != 0) 15356 as_bad (_("-G not supported in this configuration")); 15357 g_switch_value = 0; 15358 } 15359 15360 if (mips_abi == NO_ABI) 15361 mips_abi = MIPS_DEFAULT_ABI; 15362 15363 /* The following code determines the architecture. 15364 Similar code was added to GCC 3.3 (see override_options() in 15365 config/mips/mips.c). The GAS and GCC code should be kept in sync 15366 as much as possible. */ 15367 15368 if (mips_arch_string != 0) 15369 arch_info = mips_parse_cpu ("-march", mips_arch_string); 15370 15371 if (file_mips_opts.isa != ISA_UNKNOWN) 15372 { 15373 /* Handle -mipsN. At this point, file_mips_opts.isa contains the 15374 ISA level specified by -mipsN, while arch_info->isa contains 15375 the -march selection (if any). */ 15376 if (arch_info != 0) 15377 { 15378 /* -march takes precedence over -mipsN, since it is more descriptive. 15379 There's no harm in specifying both as long as the ISA levels 15380 are the same. */ 15381 if (file_mips_opts.isa != arch_info->isa) 15382 as_bad (_("-%s conflicts with the other architecture options," 15383 " which imply -%s"), 15384 mips_cpu_info_from_isa (file_mips_opts.isa)->name, 15385 mips_cpu_info_from_isa (arch_info->isa)->name); 15386 } 15387 else 15388 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); 15389 } 15390 15391 if (arch_info == 0) 15392 { 15393 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 15394 gas_assert (arch_info); 15395 } 15396 15397 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 15398 as_bad (_("-march=%s is not compatible with the selected ABI"), 15399 arch_info->name); 15400 15401 file_mips_opts.arch = arch_info->cpu; 15402 file_mips_opts.isa = arch_info->isa; 15403 file_mips_opts.init_ase = arch_info->ase; 15404 15405 /* The EVA Extension has instructions which are only valid when the R6 ISA 15406 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are 15407 present. */ 15408 if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa)) 15409 file_mips_opts.ase |= ASE_EVA_R6; 15410 15411 /* Set up initial mips_opts state. */ 15412 mips_opts = file_mips_opts; 15413 15414 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ 15415 if (!mips_fix_r5900_explicit) 15416 mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; 15417 15418 /* The register size inference code is now placed in 15419 file_mips_check_options. */ 15420 15421 /* Optimize for file_mips_opts.arch, unless -mtune selects a different 15422 processor. */ 15423 if (mips_tune_string != 0) 15424 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 15425 15426 if (tune_info == 0) 15427 mips_set_tune (arch_info); 15428 else 15429 mips_set_tune (tune_info); 15430 15431 if (mips_flag_mdebug < 0) 15432 mips_flag_mdebug = 0; 15433} 15434 15435void 15436mips_init_after_args (void) 15437{ 15438 /* Initialize opcodes. */ 15439 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 15440 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 15441} 15442 15443long 15444md_pcrel_from (fixS *fixP) 15445{ 15446 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 15447 15448 switch (fixP->fx_r_type) 15449 { 15450 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15451 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15452 /* Return the address of the delay slot. */ 15453 return addr + 2; 15454 15455 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15456 case BFD_RELOC_MICROMIPS_JMP: 15457 case BFD_RELOC_MIPS16_16_PCREL_S1: 15458 case BFD_RELOC_16_PCREL_S2: 15459 case BFD_RELOC_MIPS_21_PCREL_S2: 15460 case BFD_RELOC_MIPS_26_PCREL_S2: 15461 case BFD_RELOC_MIPS_JMP: 15462 /* Return the address of the delay slot. */ 15463 return addr + 4; 15464 15465 case BFD_RELOC_MIPS_18_PCREL_S3: 15466 /* Return the aligned address of the doubleword containing 15467 the instruction. */ 15468 return addr & ~7; 15469 15470 default: 15471 return addr; 15472 } 15473} 15474 15475/* This is called before the symbol table is processed. In order to 15476 work with gcc when using mips-tfile, we must keep all local labels. 15477 However, in other cases, we want to discard them. If we were 15478 called with -g, but we didn't see any debugging information, it may 15479 mean that gcc is smuggling debugging information through to 15480 mips-tfile, in which case we must generate all local labels. */ 15481 15482void 15483mips_frob_file_before_adjust (void) 15484{ 15485#ifndef NO_ECOFF_DEBUGGING 15486 if (ECOFF_DEBUGGING 15487 && mips_debug != 0 15488 && ! ecoff_debugging_seen) 15489 flag_keep_locals = 1; 15490#endif 15491} 15492 15493/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede 15494 the corresponding LO16 reloc. This is called before md_apply_fix and 15495 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit 15496 relocation operators. 15497 15498 For our purposes, a %lo() expression matches a %got() or %hi() 15499 expression if: 15500 15501 (a) it refers to the same symbol; and 15502 (b) the offset applied in the %lo() expression is no lower than 15503 the offset applied in the %got() or %hi(). 15504 15505 (b) allows us to cope with code like: 15506 15507 lui $4,%hi(foo) 15508 lh $4,%lo(foo+2)($4) 15509 15510 ...which is legal on RELA targets, and has a well-defined behaviour 15511 if the user knows that adding 2 to "foo" will not induce a carry to 15512 the high 16 bits. 15513 15514 When several %lo()s match a particular %got() or %hi(), we use the 15515 following rules to distinguish them: 15516 15517 (1) %lo()s with smaller offsets are a better match than %lo()s with 15518 higher offsets. 15519 15520 (2) %lo()s with no matching %got() or %hi() are better than those 15521 that already have a matching %got() or %hi(). 15522 15523 (3) later %lo()s are better than earlier %lo()s. 15524 15525 These rules are applied in order. 15526 15527 (1) means, among other things, that %lo()s with identical offsets are 15528 chosen if they exist. 15529 15530 (2) means that we won't associate several high-part relocations with 15531 the same low-part relocation unless there's no alternative. Having 15532 several high parts for the same low part is a GNU extension; this rule 15533 allows careful users to avoid it. 15534 15535 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, 15536 with the last high-part relocation being at the front of the list. 15537 It therefore makes sense to choose the last matching low-part 15538 relocation, all other things being equal. It's also easier 15539 to code that way. */ 15540 15541void 15542mips_frob_file (void) 15543{ 15544 struct mips_hi_fixup *l; 15545 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; 15546 15547 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 15548 { 15549 segment_info_type *seginfo; 15550 bfd_boolean matched_lo_p; 15551 fixS **hi_pos, **lo_pos, **pos; 15552 15553 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 15554 15555 /* If a GOT16 relocation turns out to be against a global symbol, 15556 there isn't supposed to be a matching LO. Ignore %gots against 15557 constants; we'll report an error for those later. */ 15558 if (got16_reloc_p (l->fixp->fx_r_type) 15559 && !(l->fixp->fx_addsy 15560 && pic_need_relax (l->fixp->fx_addsy))) 15561 continue; 15562 15563 /* Check quickly whether the next fixup happens to be a matching %lo. */ 15564 if (fixup_has_matching_lo_p (l->fixp)) 15565 continue; 15566 15567 seginfo = seg_info (l->seg); 15568 15569 /* Set HI_POS to the position of this relocation in the chain. 15570 Set LO_POS to the position of the chosen low-part relocation. 15571 MATCHED_LO_P is true on entry to the loop if *POS is a low-part 15572 relocation that matches an immediately-preceding high-part 15573 relocation. */ 15574 hi_pos = NULL; 15575 lo_pos = NULL; 15576 matched_lo_p = FALSE; 15577 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); 15578 15579 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) 15580 { 15581 if (*pos == l->fixp) 15582 hi_pos = pos; 15583 15584 if ((*pos)->fx_r_type == looking_for_rtype 15585 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) 15586 && (*pos)->fx_offset >= l->fixp->fx_offset 15587 && (lo_pos == NULL 15588 || (*pos)->fx_offset < (*lo_pos)->fx_offset 15589 || (!matched_lo_p 15590 && (*pos)->fx_offset == (*lo_pos)->fx_offset))) 15591 lo_pos = pos; 15592 15593 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) 15594 && fixup_has_matching_lo_p (*pos)); 15595 } 15596 15597 /* If we found a match, remove the high-part relocation from its 15598 current position and insert it before the low-part relocation. 15599 Make the offsets match so that fixup_has_matching_lo_p() 15600 will return true. 15601 15602 We don't warn about unmatched high-part relocations since some 15603 versions of gcc have been known to emit dead "lui ...%hi(...)" 15604 instructions. */ 15605 if (lo_pos != NULL) 15606 { 15607 l->fixp->fx_offset = (*lo_pos)->fx_offset; 15608 if (l->fixp->fx_next != *lo_pos) 15609 { 15610 *hi_pos = l->fixp->fx_next; 15611 l->fixp->fx_next = *lo_pos; 15612 *lo_pos = l->fixp; 15613 } 15614 } 15615 } 15616} 15617 15618int 15619mips_force_relocation (fixS *fixp) 15620{ 15621 if (generic_force_reloc (fixp)) 15622 return 1; 15623 15624 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, 15625 so that the linker relaxation can update targets. */ 15626 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 15627 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 15628 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) 15629 return 1; 15630 15631 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 15632 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and 15633 microMIPS symbols so that we can do cross-mode branch diagnostics 15634 and BAL to JALX conversion by the linker. */ 15635 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 15636 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 15637 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) 15638 && fixp->fx_addsy 15639 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) 15640 return 1; 15641 15642 /* We want all PC-relative relocations to be kept for R6 relaxation. */ 15643 if (ISA_IS_R6 (file_mips_opts.isa) 15644 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 15645 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 15646 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 15647 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 15648 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 15649 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 15650 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) 15651 return 1; 15652 15653 return 0; 15654} 15655 15656/* Implement TC_FORCE_RELOCATION_ABS. */ 15657 15658bfd_boolean 15659mips_force_relocation_abs (fixS *fixp) 15660{ 15661 if (generic_force_reloc (fixp)) 15662 return TRUE; 15663 15664 /* These relocations do not have enough bits in the in-place addend 15665 to hold an arbitrary absolute section's offset. */ 15666 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) 15667 return TRUE; 15668 15669 return FALSE; 15670} 15671 15672/* Read the instruction associated with RELOC from BUF. */ 15673 15674static unsigned int 15675read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) 15676{ 15677 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 15678 return read_compressed_insn (buf, 4); 15679 else 15680 return read_insn (buf); 15681} 15682 15683/* Write instruction INSN to BUF, given that it has been relocated 15684 by RELOC. */ 15685 15686static void 15687write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, 15688 unsigned long insn) 15689{ 15690 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) 15691 write_compressed_insn (buf, insn, 4); 15692 else 15693 write_insn (buf, insn); 15694} 15695 15696/* Return TRUE if the instruction pointed to by FIXP is an invalid jump 15697 to a symbol in another ISA mode, which cannot be converted to JALX. */ 15698 15699static bfd_boolean 15700fix_bad_cross_mode_jump_p (fixS *fixP) 15701{ 15702 unsigned long opcode; 15703 int other; 15704 char *buf; 15705 15706 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15707 return FALSE; 15708 15709 other = S_GET_OTHER (fixP->fx_addsy); 15710 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15711 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; 15712 switch (fixP->fx_r_type) 15713 { 15714 case BFD_RELOC_MIPS_JMP: 15715 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); 15716 case BFD_RELOC_MICROMIPS_JMP: 15717 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); 15718 default: 15719 return FALSE; 15720 } 15721} 15722 15723/* Return TRUE if the instruction pointed to by FIXP is an invalid JALX 15724 jump to a symbol in the same ISA mode. */ 15725 15726static bfd_boolean 15727fix_bad_same_mode_jalx_p (fixS *fixP) 15728{ 15729 unsigned long opcode; 15730 int other; 15731 char *buf; 15732 15733 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15734 return FALSE; 15735 15736 other = S_GET_OTHER (fixP->fx_addsy); 15737 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15738 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; 15739 switch (fixP->fx_r_type) 15740 { 15741 case BFD_RELOC_MIPS_JMP: 15742 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); 15743 case BFD_RELOC_MIPS16_JMP: 15744 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); 15745 case BFD_RELOC_MICROMIPS_JMP: 15746 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); 15747 default: 15748 return FALSE; 15749 } 15750} 15751 15752/* Return TRUE if the instruction pointed to by FIXP is an invalid jump 15753 to a symbol whose value plus addend is not aligned according to the 15754 ultimate (after linker relaxation) jump instruction's immediate field 15755 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to 15756 regular MIPS code, to (1 << 2). */ 15757 15758static bfd_boolean 15759fix_bad_misaligned_jump_p (fixS *fixP, int shift) 15760{ 15761 bfd_boolean micro_to_mips_p; 15762 valueT val; 15763 int other; 15764 15765 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15766 return FALSE; 15767 15768 other = S_GET_OTHER (fixP->fx_addsy); 15769 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); 15770 val += fixP->fx_offset; 15771 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP 15772 && !ELF_ST_IS_MICROMIPS (other)); 15773 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) 15774 != ELF_ST_IS_COMPRESSED (other)); 15775} 15776 15777/* Return TRUE if the instruction pointed to by FIXP is an invalid branch 15778 to a symbol whose annotation indicates another ISA mode. For absolute 15779 symbols check the ISA bit instead. 15780 15781 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS 15782 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular 15783 MIPS symbols and associated with BAL instructions as these instructions 15784 may be converted to JALX by the linker. */ 15785 15786static bfd_boolean 15787fix_bad_cross_mode_branch_p (fixS *fixP) 15788{ 15789 bfd_boolean absolute_p; 15790 unsigned long opcode; 15791 asection *symsec; 15792 valueT val; 15793 int other; 15794 char *buf; 15795 15796 if (mips_ignore_branch_isa) 15797 return FALSE; 15798 15799 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15800 return FALSE; 15801 15802 symsec = S_GET_SEGMENT (fixP->fx_addsy); 15803 absolute_p = bfd_is_abs_section (symsec); 15804 15805 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; 15806 other = S_GET_OTHER (fixP->fx_addsy); 15807 15808 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15809 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; 15810 switch (fixP->fx_r_type) 15811 { 15812 case BFD_RELOC_16_PCREL_S2: 15813 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) 15814 && opcode != 0x0411); 15815 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15816 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) 15817 && opcode != 0x4060); 15818 case BFD_RELOC_MIPS_21_PCREL_S2: 15819 case BFD_RELOC_MIPS_26_PCREL_S2: 15820 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); 15821 case BFD_RELOC_MIPS16_16_PCREL_S1: 15822 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); 15823 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15824 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15825 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); 15826 default: 15827 abort (); 15828 } 15829} 15830 15831/* Return TRUE if the symbol plus addend associated with a regular MIPS 15832 branch instruction pointed to by FIXP is not aligned according to the 15833 branch instruction's immediate field requirement. We need the addend 15834 to preserve the ISA bit and also the sum must not have bit 2 set. We 15835 must explicitly OR in the ISA bit from symbol annotation as the bit 15836 won't be set in the symbol's value then. */ 15837 15838static bfd_boolean 15839fix_bad_misaligned_branch_p (fixS *fixP) 15840{ 15841 bfd_boolean absolute_p; 15842 asection *symsec; 15843 valueT isa_bit; 15844 valueT val; 15845 valueT off; 15846 int other; 15847 15848 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) 15849 return FALSE; 15850 15851 symsec = S_GET_SEGMENT (fixP->fx_addsy); 15852 absolute_p = bfd_is_abs_section (symsec); 15853 15854 val = S_GET_VALUE (fixP->fx_addsy); 15855 other = S_GET_OTHER (fixP->fx_addsy); 15856 off = fixP->fx_offset; 15857 15858 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); 15859 val |= ELF_ST_IS_COMPRESSED (other); 15860 val += off; 15861 return (val & 0x3) != isa_bit; 15862} 15863 15864/* Calculate the relocation target by masking off ISA mode bit before 15865 combining symbol and addend. */ 15866 15867static valueT 15868fix_bad_misaligned_address (fixS *fixP) 15869{ 15870 valueT val; 15871 valueT off; 15872 unsigned isa_mode; 15873 gas_assert (fixP != NULL && fixP->fx_addsy != NULL); 15874 val = S_GET_VALUE (fixP->fx_addsy); 15875 off = fixP->fx_offset; 15876 isa_mode = (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP->fx_addsy)) 15877 ? 1 : 0); 15878 15879 return ((val & ~isa_mode) + off); 15880} 15881 15882/* Make the necessary checks on a regular MIPS branch pointed to by FIXP 15883 and its calculated value VAL. */ 15884 15885static void 15886fix_validate_branch (fixS *fixP, valueT val) 15887{ 15888 if (fixP->fx_done && (val & 0x3) != 0) 15889 as_bad_where (fixP->fx_file, fixP->fx_line, 15890 _("branch to misaligned address (0x%lx)"), 15891 (long) (val + md_pcrel_from (fixP))); 15892 else if (fix_bad_cross_mode_branch_p (fixP)) 15893 as_bad_where (fixP->fx_file, fixP->fx_line, 15894 _("branch to a symbol in another ISA mode")); 15895 else if (fix_bad_misaligned_branch_p (fixP)) 15896 as_bad_where (fixP->fx_file, fixP->fx_line, 15897 _("branch to misaligned address (0x%lx)"), 15898 (long) fix_bad_misaligned_address (fixP)); 15899 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) 15900 as_bad_where (fixP->fx_file, fixP->fx_line, 15901 _("cannot encode misaligned addend " 15902 "in the relocatable field (0x%lx)"), 15903 (long) fixP->fx_offset); 15904} 15905 15906/* Apply a fixup to the object file. */ 15907 15908void 15909md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 15910{ 15911 char *buf; 15912 unsigned long insn; 15913 reloc_howto_type *howto; 15914 15915 if (fixP->fx_pcrel) 15916 switch (fixP->fx_r_type) 15917 { 15918 case BFD_RELOC_16_PCREL_S2: 15919 case BFD_RELOC_MIPS16_16_PCREL_S1: 15920 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 15921 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 15922 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 15923 case BFD_RELOC_32_PCREL: 15924 case BFD_RELOC_MIPS_21_PCREL_S2: 15925 case BFD_RELOC_MIPS_26_PCREL_S2: 15926 case BFD_RELOC_MIPS_18_PCREL_S3: 15927 case BFD_RELOC_MIPS_19_PCREL_S2: 15928 case BFD_RELOC_HI16_S_PCREL: 15929 case BFD_RELOC_LO16_PCREL: 15930 break; 15931 15932 case BFD_RELOC_32: 15933 fixP->fx_r_type = BFD_RELOC_32_PCREL; 15934 break; 15935 15936 default: 15937 as_bad_where (fixP->fx_file, fixP->fx_line, 15938 _("PC-relative reference to a different section")); 15939 break; 15940 } 15941 15942 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations 15943 that have no MIPS ELF equivalent. */ 15944 if (fixP->fx_r_type != BFD_RELOC_8) 15945 { 15946 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 15947 if (!howto) 15948 return; 15949 } 15950 15951 gas_assert (fixP->fx_size == 2 15952 || fixP->fx_size == 4 15953 || fixP->fx_r_type == BFD_RELOC_8 15954 || fixP->fx_r_type == BFD_RELOC_16 15955 || fixP->fx_r_type == BFD_RELOC_64 15956 || fixP->fx_r_type == BFD_RELOC_CTOR 15957 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 15958 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB 15959 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 15960 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 15961 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 15962 || fixP->fx_r_type == BFD_RELOC_NONE); 15963 15964 buf = fixP->fx_frag->fr_literal + fixP->fx_where; 15965 15966 /* Don't treat parts of a composite relocation as done. There are two 15967 reasons for this: 15968 15969 (1) The second and third parts will be against 0 (RSS_UNDEF) but 15970 should nevertheless be emitted if the first part is. 15971 15972 (2) In normal usage, composite relocations are never assembly-time 15973 constants. The easiest way of dealing with the pathological 15974 exceptions is to generate a relocation against STN_UNDEF and 15975 leave everything up to the linker. */ 15976 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) 15977 fixP->fx_done = 1; 15978 15979 switch (fixP->fx_r_type) 15980 { 15981 case BFD_RELOC_MIPS_TLS_GD: 15982 case BFD_RELOC_MIPS_TLS_LDM: 15983 case BFD_RELOC_MIPS_TLS_DTPREL32: 15984 case BFD_RELOC_MIPS_TLS_DTPREL64: 15985 case BFD_RELOC_MIPS_TLS_DTPREL_HI16: 15986 case BFD_RELOC_MIPS_TLS_DTPREL_LO16: 15987 case BFD_RELOC_MIPS_TLS_GOTTPREL: 15988 case BFD_RELOC_MIPS_TLS_TPREL32: 15989 case BFD_RELOC_MIPS_TLS_TPREL64: 15990 case BFD_RELOC_MIPS_TLS_TPREL_HI16: 15991 case BFD_RELOC_MIPS_TLS_TPREL_LO16: 15992 case BFD_RELOC_MICROMIPS_TLS_GD: 15993 case BFD_RELOC_MICROMIPS_TLS_LDM: 15994 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: 15995 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: 15996 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: 15997 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: 15998 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: 15999 case BFD_RELOC_MIPS16_TLS_GD: 16000 case BFD_RELOC_MIPS16_TLS_LDM: 16001 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: 16002 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: 16003 case BFD_RELOC_MIPS16_TLS_GOTTPREL: 16004 case BFD_RELOC_MIPS16_TLS_TPREL_HI16: 16005 case BFD_RELOC_MIPS16_TLS_TPREL_LO16: 16006 if (fixP->fx_addsy) 16007 S_SET_THREAD_LOCAL (fixP->fx_addsy); 16008 else 16009 as_bad_where (fixP->fx_file, fixP->fx_line, 16010 _("TLS relocation against a constant")); 16011 break; 16012 16013 case BFD_RELOC_MIPS_JMP: 16014 case BFD_RELOC_MIPS16_JMP: 16015 case BFD_RELOC_MICROMIPS_JMP: 16016 { 16017 int shift; 16018 16019 gas_assert (!fixP->fx_done); 16020 16021 /* Shift is 2, unusually, for microMIPS JALX. */ 16022 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP 16023 && (read_compressed_insn (buf, 4) >> 26) != 0x3c) 16024 shift = 1; 16025 else 16026 shift = 2; 16027 16028 if (fix_bad_cross_mode_jump_p (fixP)) 16029 as_bad_where (fixP->fx_file, fixP->fx_line, 16030 _("jump to a symbol in another ISA mode")); 16031 else if (fix_bad_same_mode_jalx_p (fixP)) 16032 as_bad_where (fixP->fx_file, fixP->fx_line, 16033 _("JALX to a symbol in the same ISA mode")); 16034 else if (fix_bad_misaligned_jump_p (fixP, shift)) 16035 as_bad_where (fixP->fx_file, fixP->fx_line, 16036 _("jump to misaligned address (0x%lx)"), 16037 (long) fix_bad_misaligned_address (fixP)); 16038 else if (HAVE_IN_PLACE_ADDENDS 16039 && (fixP->fx_offset & ((1 << shift) - 1)) != 0) 16040 as_bad_where (fixP->fx_file, fixP->fx_line, 16041 _("cannot encode misaligned addend " 16042 "in the relocatable field (0x%lx)"), 16043 (long) fixP->fx_offset); 16044 } 16045 /* Fall through. */ 16046 16047 case BFD_RELOC_MIPS_SHIFT5: 16048 case BFD_RELOC_MIPS_SHIFT6: 16049 case BFD_RELOC_MIPS_GOT_DISP: 16050 case BFD_RELOC_MIPS_GOT_PAGE: 16051 case BFD_RELOC_MIPS_GOT_OFST: 16052 case BFD_RELOC_MIPS_SUB: 16053 case BFD_RELOC_MIPS_INSERT_A: 16054 case BFD_RELOC_MIPS_INSERT_B: 16055 case BFD_RELOC_MIPS_DELETE: 16056 case BFD_RELOC_MIPS_HIGHEST: 16057 case BFD_RELOC_MIPS_HIGHER: 16058 case BFD_RELOC_MIPS_SCN_DISP: 16059 case BFD_RELOC_MIPS_REL16: 16060 case BFD_RELOC_MIPS_RELGOT: 16061 case BFD_RELOC_MIPS_JALR: 16062 case BFD_RELOC_HI16: 16063 case BFD_RELOC_HI16_S: 16064 case BFD_RELOC_LO16: 16065 case BFD_RELOC_GPREL16: 16066 case BFD_RELOC_MIPS_LITERAL: 16067 case BFD_RELOC_MIPS_CALL16: 16068 case BFD_RELOC_MIPS_GOT16: 16069 case BFD_RELOC_GPREL32: 16070 case BFD_RELOC_MIPS_GOT_HI16: 16071 case BFD_RELOC_MIPS_GOT_LO16: 16072 case BFD_RELOC_MIPS_CALL_HI16: 16073 case BFD_RELOC_MIPS_CALL_LO16: 16074 case BFD_RELOC_HI16_S_PCREL: 16075 case BFD_RELOC_LO16_PCREL: 16076 case BFD_RELOC_MIPS16_GPREL: 16077 case BFD_RELOC_MIPS16_GOT16: 16078 case BFD_RELOC_MIPS16_CALL16: 16079 case BFD_RELOC_MIPS16_HI16: 16080 case BFD_RELOC_MIPS16_HI16_S: 16081 case BFD_RELOC_MIPS16_LO16: 16082 case BFD_RELOC_MICROMIPS_GOT_DISP: 16083 case BFD_RELOC_MICROMIPS_GOT_PAGE: 16084 case BFD_RELOC_MICROMIPS_GOT_OFST: 16085 case BFD_RELOC_MICROMIPS_SUB: 16086 case BFD_RELOC_MICROMIPS_HIGHEST: 16087 case BFD_RELOC_MICROMIPS_HIGHER: 16088 case BFD_RELOC_MICROMIPS_SCN_DISP: 16089 case BFD_RELOC_MICROMIPS_JALR: 16090 case BFD_RELOC_MICROMIPS_HI16: 16091 case BFD_RELOC_MICROMIPS_HI16_S: 16092 case BFD_RELOC_MICROMIPS_LO16: 16093 case BFD_RELOC_MICROMIPS_GPREL16: 16094 case BFD_RELOC_MICROMIPS_LITERAL: 16095 case BFD_RELOC_MICROMIPS_CALL16: 16096 case BFD_RELOC_MICROMIPS_GOT16: 16097 case BFD_RELOC_MICROMIPS_GOT_HI16: 16098 case BFD_RELOC_MICROMIPS_GOT_LO16: 16099 case BFD_RELOC_MICROMIPS_CALL_HI16: 16100 case BFD_RELOC_MICROMIPS_CALL_LO16: 16101 case BFD_RELOC_MIPS_EH: 16102 if (fixP->fx_done) 16103 { 16104 offsetT value; 16105 16106 if (calculate_reloc (fixP->fx_r_type, *valP, &value)) 16107 { 16108 insn = read_reloc_insn (buf, fixP->fx_r_type); 16109 if (mips16_reloc_p (fixP->fx_r_type)) 16110 insn |= mips16_immed_extend (value, 16); 16111 else 16112 insn |= (value & 0xffff); 16113 write_reloc_insn (buf, fixP->fx_r_type, insn); 16114 } 16115 else 16116 as_bad_where (fixP->fx_file, fixP->fx_line, 16117 _("unsupported constant in relocation")); 16118 } 16119 break; 16120 16121 case BFD_RELOC_64: 16122 /* This is handled like BFD_RELOC_32, but we output a sign 16123 extended value if we are only 32 bits. */ 16124 if (fixP->fx_done) 16125 { 16126 if (8 <= sizeof (valueT)) 16127 md_number_to_chars (buf, *valP, 8); 16128 else 16129 { 16130 valueT hiv; 16131 16132 if ((*valP & 0x80000000) != 0) 16133 hiv = 0xffffffff; 16134 else 16135 hiv = 0; 16136 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); 16137 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); 16138 } 16139 } 16140 break; 16141 16142 case BFD_RELOC_RVA: 16143 case BFD_RELOC_32: 16144 case BFD_RELOC_32_PCREL: 16145 case BFD_RELOC_16: 16146 case BFD_RELOC_8: 16147 /* If we are deleting this reloc entry, we must fill in the 16148 value now. This can happen if we have a .word which is not 16149 resolved when it appears but is later defined. */ 16150 if (fixP->fx_done) 16151 md_number_to_chars (buf, *valP, fixP->fx_size); 16152 break; 16153 16154 case BFD_RELOC_MIPS_21_PCREL_S2: 16155 fix_validate_branch (fixP, *valP); 16156 if (!fixP->fx_done) 16157 break; 16158 16159 if (*valP + 0x400000 <= 0x7fffff) 16160 { 16161 insn = read_insn (buf); 16162 insn |= (*valP >> 2) & 0x1fffff; 16163 write_insn (buf, insn); 16164 } 16165 else 16166 as_bad_where (fixP->fx_file, fixP->fx_line, 16167 _("branch out of range")); 16168 break; 16169 16170 case BFD_RELOC_MIPS_26_PCREL_S2: 16171 fix_validate_branch (fixP, *valP); 16172 if (!fixP->fx_done) 16173 break; 16174 16175 if (*valP + 0x8000000 <= 0xfffffff) 16176 { 16177 insn = read_insn (buf); 16178 insn |= (*valP >> 2) & 0x3ffffff; 16179 write_insn (buf, insn); 16180 } 16181 else 16182 as_bad_where (fixP->fx_file, fixP->fx_line, 16183 _("branch out of range")); 16184 break; 16185 16186 case BFD_RELOC_MIPS_18_PCREL_S3: 16187 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) 16188 as_bad_where (fixP->fx_file, fixP->fx_line, 16189 _("PC-relative access using misaligned symbol (%lx)"), 16190 (long) S_GET_VALUE (fixP->fx_addsy)); 16191 if ((fixP->fx_offset & 0x7) != 0) 16192 as_bad_where (fixP->fx_file, fixP->fx_line, 16193 _("PC-relative access using misaligned offset (%lx)"), 16194 (long) fixP->fx_offset); 16195 if (!fixP->fx_done) 16196 break; 16197 16198 if (*valP + 0x100000 <= 0x1fffff) 16199 { 16200 insn = read_insn (buf); 16201 insn |= (*valP >> 3) & 0x3ffff; 16202 write_insn (buf, insn); 16203 } 16204 else 16205 as_bad_where (fixP->fx_file, fixP->fx_line, 16206 _("PC-relative access out of range")); 16207 break; 16208 16209 case BFD_RELOC_MIPS_19_PCREL_S2: 16210 if ((*valP & 0x3) != 0) 16211 as_bad_where (fixP->fx_file, fixP->fx_line, 16212 _("PC-relative access to misaligned address (%lx)"), 16213 (long) *valP); 16214 if (!fixP->fx_done) 16215 break; 16216 16217 if (*valP + 0x100000 <= 0x1fffff) 16218 { 16219 insn = read_insn (buf); 16220 insn |= (*valP >> 2) & 0x7ffff; 16221 write_insn (buf, insn); 16222 } 16223 else 16224 as_bad_where (fixP->fx_file, fixP->fx_line, 16225 _("PC-relative access out of range")); 16226 break; 16227 16228 case BFD_RELOC_16_PCREL_S2: 16229 fix_validate_branch (fixP, *valP); 16230 16231 /* We need to save the bits in the instruction since fixup_segment() 16232 might be deleting the relocation entry (i.e., a branch within 16233 the current segment). */ 16234 if (! fixP->fx_done) 16235 break; 16236 16237 /* Update old instruction data. */ 16238 insn = read_insn (buf); 16239 16240 if (*valP + 0x20000 <= 0x3ffff) 16241 { 16242 insn |= (*valP >> 2) & 0xffff; 16243 write_insn (buf, insn); 16244 } 16245 else if (fixP->fx_tcbit2 16246 && fixP->fx_done 16247 && fixP->fx_frag->fr_address >= text_section->vma 16248 && (fixP->fx_frag->fr_address 16249 < text_section->vma + bfd_section_size (text_section)) 16250 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 16251 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 16252 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 16253 { 16254 /* The branch offset is too large. If this is an 16255 unconditional branch, and we are not generating PIC code, 16256 we can convert it to an absolute jump instruction. */ 16257 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 16258 insn = 0x0c000000; /* jal */ 16259 else 16260 insn = 0x08000000; /* j */ 16261 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 16262 fixP->fx_done = 0; 16263 fixP->fx_addsy = section_symbol (text_section); 16264 *valP += md_pcrel_from (fixP); 16265 write_insn (buf, insn); 16266 } 16267 else 16268 { 16269 /* If we got here, we have branch-relaxation disabled, 16270 and there's nothing we can do to fix this instruction 16271 without turning it into a longer sequence. */ 16272 as_bad_where (fixP->fx_file, fixP->fx_line, 16273 _("branch out of range")); 16274 } 16275 break; 16276 16277 case BFD_RELOC_MIPS16_16_PCREL_S1: 16278 case BFD_RELOC_MICROMIPS_7_PCREL_S1: 16279 case BFD_RELOC_MICROMIPS_10_PCREL_S1: 16280 case BFD_RELOC_MICROMIPS_16_PCREL_S1: 16281 gas_assert (!fixP->fx_done); 16282 if (fix_bad_cross_mode_branch_p (fixP)) 16283 as_bad_where (fixP->fx_file, fixP->fx_line, 16284 _("branch to a symbol in another ISA mode")); 16285 else if (fixP->fx_addsy 16286 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) 16287 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) 16288 && (fixP->fx_offset & 0x1) != 0) 16289 as_bad_where (fixP->fx_file, fixP->fx_line, 16290 _("branch to misaligned address (0x%lx)"), 16291 (long) fix_bad_misaligned_address (fixP)); 16292 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) 16293 as_bad_where (fixP->fx_file, fixP->fx_line, 16294 _("cannot encode misaligned addend " 16295 "in the relocatable field (0x%lx)"), 16296 (long) fixP->fx_offset); 16297 break; 16298 16299 case BFD_RELOC_VTABLE_INHERIT: 16300 fixP->fx_done = 0; 16301 if (fixP->fx_addsy 16302 && !S_IS_DEFINED (fixP->fx_addsy) 16303 && !S_IS_WEAK (fixP->fx_addsy)) 16304 S_SET_WEAK (fixP->fx_addsy); 16305 break; 16306 16307 case BFD_RELOC_NONE: 16308 case BFD_RELOC_VTABLE_ENTRY: 16309 fixP->fx_done = 0; 16310 break; 16311 16312 default: 16313 abort (); 16314 } 16315 16316 /* Remember value for tc_gen_reloc. */ 16317 fixP->fx_addnumber = *valP; 16318} 16319 16320static symbolS * 16321get_symbol (void) 16322{ 16323 int c; 16324 char *name; 16325 symbolS *p; 16326 16327 c = get_symbol_name (&name); 16328 p = (symbolS *) symbol_find_or_make (name); 16329 (void) restore_line_pointer (c); 16330 return p; 16331} 16332 16333/* Align the current frag to a given power of two. If a particular 16334 fill byte should be used, FILL points to an integer that contains 16335 that byte, otherwise FILL is null. 16336 16337 This function used to have the comment: 16338 16339 The MIPS assembler also automatically adjusts any preceding label. 16340 16341 The implementation therefore applied the adjustment to a maximum of 16342 one label. However, other label adjustments are applied to batches 16343 of labels, and adjusting just one caused problems when new labels 16344 were added for the sake of debugging or unwind information. 16345 We therefore adjust all preceding labels (given as LABELS) instead. */ 16346 16347static void 16348mips_align (int to, int *fill, struct insn_label_list *labels) 16349{ 16350 mips_emit_delays (); 16351 mips_record_compressed_mode (); 16352 if (fill == NULL && subseg_text_p (now_seg)) 16353 frag_align_code (to, 0); 16354 else 16355 frag_align (to, fill ? *fill : 0, 0); 16356 record_alignment (now_seg, to); 16357 mips_move_labels (labels, subseg_text_p (now_seg)); 16358} 16359 16360/* Align to a given power of two. .align 0 turns off the automatic 16361 alignment used by the data creating pseudo-ops. */ 16362 16363static void 16364s_align (int x ATTRIBUTE_UNUSED) 16365{ 16366 int temp, fill_value, *fill_ptr; 16367 long max_alignment = 28; 16368 16369 /* o Note that the assembler pulls down any immediately preceding label 16370 to the aligned address. 16371 o It's not documented but auto alignment is reinstated by 16372 a .align pseudo instruction. 16373 o Note also that after auto alignment is turned off the mips assembler 16374 issues an error on attempt to assemble an improperly aligned data item. 16375 We don't. */ 16376 16377 temp = get_absolute_expression (); 16378 if (temp > max_alignment) 16379 as_bad (_("alignment too large, %d assumed"), temp = max_alignment); 16380 else if (temp < 0) 16381 { 16382 as_warn (_("alignment negative, 0 assumed")); 16383 temp = 0; 16384 } 16385 if (*input_line_pointer == ',') 16386 { 16387 ++input_line_pointer; 16388 fill_value = get_absolute_expression (); 16389 fill_ptr = &fill_value; 16390 } 16391 else 16392 fill_ptr = 0; 16393 if (temp) 16394 { 16395 segment_info_type *si = seg_info (now_seg); 16396 struct insn_label_list *l = si->label_list; 16397 /* Auto alignment should be switched on by next section change. */ 16398 auto_align = 1; 16399 mips_align (temp, fill_ptr, l); 16400 } 16401 else 16402 { 16403 auto_align = 0; 16404 } 16405 16406 demand_empty_rest_of_line (); 16407} 16408 16409static void 16410s_change_sec (int sec) 16411{ 16412 segT seg; 16413 16414 /* The ELF backend needs to know that we are changing sections, so 16415 that .previous works correctly. We could do something like check 16416 for an obj_section_change_hook macro, but that might be confusing 16417 as it would not be appropriate to use it in the section changing 16418 functions in read.c, since obj-elf.c intercepts those. FIXME: 16419 This should be cleaner, somehow. */ 16420 obj_elf_section_change_hook (); 16421 16422 mips_emit_delays (); 16423 16424 switch (sec) 16425 { 16426 case 't': 16427 s_text (0); 16428 break; 16429 case 'd': 16430 s_data (0); 16431 break; 16432 case 'b': 16433 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 16434 demand_empty_rest_of_line (); 16435 break; 16436 16437 case 'r': 16438 seg = subseg_new (RDATA_SECTION_NAME, 16439 (subsegT) get_absolute_expression ()); 16440 bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY 16441 | SEC_RELOC | SEC_DATA)); 16442 if (strncmp (TARGET_OS, "elf", 3) != 0) 16443 record_alignment (seg, 4); 16444 demand_empty_rest_of_line (); 16445 break; 16446 16447 case 's': 16448 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 16449 bfd_set_section_flags (seg, 16450 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); 16451 if (strncmp (TARGET_OS, "elf", 3) != 0) 16452 record_alignment (seg, 4); 16453 demand_empty_rest_of_line (); 16454 break; 16455 16456 case 'B': 16457 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); 16458 bfd_set_section_flags (seg, SEC_ALLOC); 16459 if (strncmp (TARGET_OS, "elf", 3) != 0) 16460 record_alignment (seg, 4); 16461 demand_empty_rest_of_line (); 16462 break; 16463 } 16464 16465 auto_align = 1; 16466} 16467 16468void 16469s_change_section (int ignore ATTRIBUTE_UNUSED) 16470{ 16471 char *saved_ilp; 16472 char *section_name; 16473 char c, endc; 16474 char next_c = 0; 16475 int section_type; 16476 int section_flag; 16477 int section_entry_size; 16478 int section_alignment; 16479 16480 saved_ilp = input_line_pointer; 16481 endc = get_symbol_name (§ion_name); 16482 c = (endc == '"' ? input_line_pointer[1] : endc); 16483 if (c) 16484 next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; 16485 16486 /* Do we have .section Name<,"flags">? */ 16487 if (c != ',' || (c == ',' && next_c == '"')) 16488 { 16489 /* Just after name is now '\0'. */ 16490 (void) restore_line_pointer (endc); 16491 input_line_pointer = saved_ilp; 16492 obj_elf_section (ignore); 16493 return; 16494 } 16495 16496 section_name = xstrdup (section_name); 16497 c = restore_line_pointer (endc); 16498 16499 input_line_pointer++; 16500 16501 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 16502 if (c == ',') 16503 section_type = get_absolute_expression (); 16504 else 16505 section_type = 0; 16506 16507 if (*input_line_pointer++ == ',') 16508 section_flag = get_absolute_expression (); 16509 else 16510 section_flag = 0; 16511 16512 if (*input_line_pointer++ == ',') 16513 section_entry_size = get_absolute_expression (); 16514 else 16515 section_entry_size = 0; 16516 16517 if (*input_line_pointer++ == ',') 16518 section_alignment = get_absolute_expression (); 16519 else 16520 section_alignment = 0; 16521 16522 /* FIXME: really ignore? */ 16523 (void) section_alignment; 16524 16525 /* When using the generic form of .section (as implemented by obj-elf.c), 16526 there's no way to set the section type to SHT_MIPS_DWARF. Users have 16527 traditionally had to fall back on the more common @progbits instead. 16528 16529 There's nothing really harmful in this, since bfd will correct 16530 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 16531 means that, for backwards compatibility, the special_section entries 16532 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 16533 16534 Even so, we shouldn't force users of the MIPS .section syntax to 16535 incorrectly label the sections as SHT_PROGBITS. The best compromise 16536 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 16537 generic type-checking code. */ 16538 if (section_type == SHT_MIPS_DWARF) 16539 section_type = SHT_PROGBITS; 16540 16541 obj_elf_change_section (section_name, section_type, 0, section_flag, 16542 section_entry_size, 0, 0, 0); 16543 16544 if (now_seg->name != section_name) 16545 free (section_name); 16546} 16547 16548void 16549mips_enable_auto_align (void) 16550{ 16551 auto_align = 1; 16552} 16553 16554static void 16555s_cons (int log_size) 16556{ 16557 segment_info_type *si = seg_info (now_seg); 16558 struct insn_label_list *l = si->label_list; 16559 16560 mips_emit_delays (); 16561 if (log_size > 0 && auto_align) 16562 mips_align (log_size, 0, l); 16563 cons (1 << log_size); 16564 mips_clear_insn_labels (); 16565} 16566 16567static void 16568s_float_cons (int type) 16569{ 16570 segment_info_type *si = seg_info (now_seg); 16571 struct insn_label_list *l = si->label_list; 16572 16573 mips_emit_delays (); 16574 16575 if (auto_align) 16576 { 16577 if (type == 'd') 16578 mips_align (3, 0, l); 16579 else 16580 mips_align (2, 0, l); 16581 } 16582 16583 float_cons (type); 16584 mips_clear_insn_labels (); 16585} 16586 16587/* Handle .globl. We need to override it because on Irix 5 you are 16588 permitted to say 16589 .globl foo .text 16590 where foo is an undefined symbol, to mean that foo should be 16591 considered to be the address of a function. */ 16592 16593static void 16594s_mips_globl (int x ATTRIBUTE_UNUSED) 16595{ 16596 char *name; 16597 int c; 16598 symbolS *symbolP; 16599 16600 do 16601 { 16602 c = get_symbol_name (&name); 16603 symbolP = symbol_find_or_make (name); 16604 S_SET_EXTERNAL (symbolP); 16605 16606 *input_line_pointer = c; 16607 SKIP_WHITESPACE_AFTER_NAME (); 16608 16609 if (!is_end_of_line[(unsigned char) *input_line_pointer] 16610 && (*input_line_pointer != ',')) 16611 { 16612 char *secname; 16613 asection *sec; 16614 16615 c = get_symbol_name (&secname); 16616 sec = bfd_get_section_by_name (stdoutput, secname); 16617 if (sec == NULL) 16618 as_bad (_("%s: no such section"), secname); 16619 (void) restore_line_pointer (c); 16620 16621 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 16622 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 16623 } 16624 16625 c = *input_line_pointer; 16626 if (c == ',') 16627 { 16628 input_line_pointer++; 16629 SKIP_WHITESPACE (); 16630 if (is_end_of_line[(unsigned char) *input_line_pointer]) 16631 c = '\n'; 16632 } 16633 } 16634 while (c == ','); 16635 16636 demand_empty_rest_of_line (); 16637} 16638 16639#ifdef TE_IRIX 16640/* The Irix 5 and 6 assemblers set the type of any common symbol and 16641 any undefined non-function symbol to STT_OBJECT. We try to be 16642 compatible, since newer Irix 5 and 6 linkers care. */ 16643 16644void 16645mips_frob_symbol (symbolS *symp ATTRIBUTE_UNUSED) 16646{ 16647 /* This late in assembly we can set BSF_OBJECT indiscriminately 16648 and let elf.c:swap_out_syms sort out the symbol type. */ 16649 flagword *flags = &symbol_get_bfdsym (symp)->flags; 16650 if ((*flags & (BSF_GLOBAL | BSF_WEAK)) != 0 16651 || !S_IS_DEFINED (symp)) 16652 *flags |= BSF_OBJECT; 16653} 16654#endif 16655 16656static void 16657s_option (int x ATTRIBUTE_UNUSED) 16658{ 16659 char *opt; 16660 char c; 16661 16662 c = get_symbol_name (&opt); 16663 16664 if (*opt == 'O') 16665 { 16666 /* FIXME: What does this mean? */ 16667 } 16668 else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') 16669 { 16670 int i; 16671 16672 i = atoi (opt + 3); 16673 if (i != 0 && i != 2) 16674 as_bad (_(".option pic%d not supported"), i); 16675 else if (mips_pic == VXWORKS_PIC) 16676 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); 16677 else if (i == 0) 16678 mips_pic = NO_PIC; 16679 else if (i == 2) 16680 { 16681 mips_pic = SVR4_PIC; 16682 mips_abicalls = TRUE; 16683 } 16684 16685 if (mips_pic == SVR4_PIC) 16686 { 16687 if (g_switch_seen && g_switch_value != 0) 16688 as_warn (_("-G may not be used with SVR4 PIC code")); 16689 g_switch_value = 0; 16690 bfd_set_gp_size (stdoutput, 0); 16691 } 16692 } 16693 else 16694 as_warn (_("unrecognized option \"%s\""), opt); 16695 16696 (void) restore_line_pointer (c); 16697 demand_empty_rest_of_line (); 16698} 16699 16700/* This structure is used to hold a stack of .set values. */ 16701 16702struct mips_option_stack 16703{ 16704 struct mips_option_stack *next; 16705 struct mips_set_options options; 16706}; 16707 16708static struct mips_option_stack *mips_opts_stack; 16709 16710/* Return status for .set/.module option handling. */ 16711 16712enum code_option_type 16713{ 16714 /* Unrecognized option. */ 16715 OPTION_TYPE_BAD = -1, 16716 16717 /* Ordinary option. */ 16718 OPTION_TYPE_NORMAL, 16719 16720 /* ISA changing option. */ 16721 OPTION_TYPE_ISA 16722}; 16723 16724/* Handle common .set/.module options. Return status indicating option 16725 type. */ 16726 16727static enum code_option_type 16728parse_code_option (char * name) 16729{ 16730 bfd_boolean isa_set = FALSE; 16731 const struct mips_ase *ase; 16732 16733 if (strncmp (name, "at=", 3) == 0) 16734 { 16735 char *s = name + 3; 16736 16737 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) 16738 as_bad (_("unrecognized register name `%s'"), s); 16739 } 16740 else if (strcmp (name, "at") == 0) 16741 mips_opts.at = ATREG; 16742 else if (strcmp (name, "noat") == 0) 16743 mips_opts.at = ZERO; 16744 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 16745 mips_opts.nomove = 0; 16746 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 16747 mips_opts.nomove = 1; 16748 else if (strcmp (name, "bopt") == 0) 16749 mips_opts.nobopt = 0; 16750 else if (strcmp (name, "nobopt") == 0) 16751 mips_opts.nobopt = 1; 16752 else if (strcmp (name, "gp=32") == 0) 16753 mips_opts.gp = 32; 16754 else if (strcmp (name, "gp=64") == 0) 16755 mips_opts.gp = 64; 16756 else if (strcmp (name, "fp=32") == 0) 16757 mips_opts.fp = 32; 16758 else if (strcmp (name, "fp=xx") == 0) 16759 mips_opts.fp = 0; 16760 else if (strcmp (name, "fp=64") == 0) 16761 mips_opts.fp = 64; 16762 else if (strcmp (name, "softfloat") == 0) 16763 mips_opts.soft_float = 1; 16764 else if (strcmp (name, "hardfloat") == 0) 16765 mips_opts.soft_float = 0; 16766 else if (strcmp (name, "singlefloat") == 0) 16767 mips_opts.single_float = 1; 16768 else if (strcmp (name, "doublefloat") == 0) 16769 mips_opts.single_float = 0; 16770 else if (strcmp (name, "nooddspreg") == 0) 16771 mips_opts.oddspreg = 0; 16772 else if (strcmp (name, "oddspreg") == 0) 16773 mips_opts.oddspreg = 1; 16774 else if (strcmp (name, "mips16") == 0 16775 || strcmp (name, "MIPS-16") == 0) 16776 mips_opts.mips16 = 1; 16777 else if (strcmp (name, "nomips16") == 0 16778 || strcmp (name, "noMIPS-16") == 0) 16779 mips_opts.mips16 = 0; 16780 else if (strcmp (name, "micromips") == 0) 16781 mips_opts.micromips = 1; 16782 else if (strcmp (name, "nomicromips") == 0) 16783 mips_opts.micromips = 0; 16784 else if (name[0] == 'n' 16785 && name[1] == 'o' 16786 && (ase = mips_lookup_ase (name + 2))) 16787 mips_set_ase (ase, &mips_opts, FALSE); 16788 else if ((ase = mips_lookup_ase (name))) 16789 mips_set_ase (ase, &mips_opts, TRUE); 16790 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 16791 { 16792 /* Permit the user to change the ISA and architecture on the fly. 16793 Needless to say, misuse can cause serious problems. */ 16794 if (strncmp (name, "arch=", 5) == 0) 16795 { 16796 const struct mips_cpu_info *p; 16797 16798 p = mips_parse_cpu ("internal use", name + 5); 16799 if (!p) 16800 as_bad (_("unknown architecture %s"), name + 5); 16801 else 16802 { 16803 mips_opts.arch = p->cpu; 16804 mips_opts.isa = p->isa; 16805 isa_set = TRUE; 16806 mips_opts.init_ase = p->ase; 16807 } 16808 } 16809 else if (strncmp (name, "mips", 4) == 0) 16810 { 16811 const struct mips_cpu_info *p; 16812 16813 p = mips_parse_cpu ("internal use", name); 16814 if (!p) 16815 as_bad (_("unknown ISA level %s"), name + 4); 16816 else 16817 { 16818 mips_opts.arch = p->cpu; 16819 mips_opts.isa = p->isa; 16820 isa_set = TRUE; 16821 mips_opts.init_ase = p->ase; 16822 } 16823 } 16824 else 16825 as_bad (_("unknown ISA or architecture %s"), name); 16826 } 16827 else if (strcmp (name, "autoextend") == 0) 16828 mips_opts.noautoextend = 0; 16829 else if (strcmp (name, "noautoextend") == 0) 16830 mips_opts.noautoextend = 1; 16831 else if (strcmp (name, "insn32") == 0) 16832 mips_opts.insn32 = TRUE; 16833 else if (strcmp (name, "noinsn32") == 0) 16834 mips_opts.insn32 = FALSE; 16835 else if (strcmp (name, "sym32") == 0) 16836 mips_opts.sym32 = TRUE; 16837 else if (strcmp (name, "nosym32") == 0) 16838 mips_opts.sym32 = FALSE; 16839 else 16840 return OPTION_TYPE_BAD; 16841 16842 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; 16843} 16844 16845/* Handle the .set pseudo-op. */ 16846 16847static void 16848s_mipsset (int x ATTRIBUTE_UNUSED) 16849{ 16850 enum code_option_type type = OPTION_TYPE_NORMAL; 16851 char *name = input_line_pointer, ch; 16852 16853 file_mips_check_options (); 16854 16855 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 16856 ++input_line_pointer; 16857 ch = *input_line_pointer; 16858 *input_line_pointer = '\0'; 16859 16860 if (strchr (name, ',')) 16861 { 16862 /* Generic ".set" directive; use the generic handler. */ 16863 *input_line_pointer = ch; 16864 input_line_pointer = name; 16865 s_set (0); 16866 return; 16867 } 16868 16869 if (strcmp (name, "reorder") == 0) 16870 { 16871 if (mips_opts.noreorder) 16872 end_noreorder (); 16873 } 16874 else if (strcmp (name, "noreorder") == 0) 16875 { 16876 if (!mips_opts.noreorder) 16877 start_noreorder (); 16878 } 16879 else if (strcmp (name, "macro") == 0) 16880 mips_opts.warn_about_macros = 0; 16881 else if (strcmp (name, "nomacro") == 0) 16882 { 16883 if (mips_opts.noreorder == 0) 16884 as_bad (_("`noreorder' must be set before `nomacro'")); 16885 mips_opts.warn_about_macros = 1; 16886 } 16887 else if (strcmp (name, "gp=default") == 0) 16888 mips_opts.gp = file_mips_opts.gp; 16889 else if (strcmp (name, "fp=default") == 0) 16890 mips_opts.fp = file_mips_opts.fp; 16891 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) 16892 { 16893 mips_opts.isa = file_mips_opts.isa; 16894 mips_opts.arch = file_mips_opts.arch; 16895 mips_opts.init_ase = file_mips_opts.init_ase; 16896 mips_opts.gp = file_mips_opts.gp; 16897 mips_opts.fp = file_mips_opts.fp; 16898 } 16899 else if (strcmp (name, "push") == 0) 16900 { 16901 struct mips_option_stack *s; 16902 16903 s = XNEW (struct mips_option_stack); 16904 s->next = mips_opts_stack; 16905 s->options = mips_opts; 16906 mips_opts_stack = s; 16907 } 16908 else if (strcmp (name, "pop") == 0) 16909 { 16910 struct mips_option_stack *s; 16911 16912 s = mips_opts_stack; 16913 if (s == NULL) 16914 as_bad (_(".set pop with no .set push")); 16915 else 16916 { 16917 /* If we're changing the reorder mode we need to handle 16918 delay slots correctly. */ 16919 if (s->options.noreorder && ! mips_opts.noreorder) 16920 start_noreorder (); 16921 else if (! s->options.noreorder && mips_opts.noreorder) 16922 end_noreorder (); 16923 16924 mips_opts = s->options; 16925 mips_opts_stack = s->next; 16926 free (s); 16927 } 16928 } 16929 else 16930 { 16931 type = parse_code_option (name); 16932 if (type == OPTION_TYPE_BAD) 16933 as_warn (_("tried to set unrecognized symbol: %s\n"), name); 16934 } 16935 16936 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp 16937 registers based on what is supported by the arch/cpu. */ 16938 if (type == OPTION_TYPE_ISA) 16939 { 16940 switch (mips_opts.isa) 16941 { 16942 case 0: 16943 break; 16944 case ISA_MIPS1: 16945 /* MIPS I cannot support FPXX. */ 16946 mips_opts.fp = 32; 16947 /* fall-through. */ 16948 case ISA_MIPS2: 16949 case ISA_MIPS32: 16950 case ISA_MIPS32R2: 16951 case ISA_MIPS32R3: 16952 case ISA_MIPS32R5: 16953 mips_opts.gp = 32; 16954 if (mips_opts.fp != 0) 16955 mips_opts.fp = 32; 16956 break; 16957 case ISA_MIPS32R6: 16958 mips_opts.gp = 32; 16959 mips_opts.fp = 64; 16960 break; 16961 case ISA_MIPS3: 16962 case ISA_MIPS4: 16963 case ISA_MIPS5: 16964 case ISA_MIPS64: 16965 case ISA_MIPS64R2: 16966 case ISA_MIPS64R3: 16967 case ISA_MIPS64R5: 16968 case ISA_MIPS64R6: 16969 mips_opts.gp = 64; 16970 if (mips_opts.fp != 0) 16971 { 16972 if (mips_opts.arch == CPU_R5900) 16973 mips_opts.fp = 32; 16974 else 16975 mips_opts.fp = 64; 16976 } 16977 break; 16978 default: 16979 as_bad (_("unknown ISA level %s"), name + 4); 16980 break; 16981 } 16982 } 16983 16984 mips_check_options (&mips_opts, FALSE); 16985 16986 mips_check_isa_supports_ases (); 16987 *input_line_pointer = ch; 16988 demand_empty_rest_of_line (); 16989} 16990 16991/* Handle the .module pseudo-op. */ 16992 16993static void 16994s_module (int ignore ATTRIBUTE_UNUSED) 16995{ 16996 char *name = input_line_pointer, ch; 16997 16998 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 16999 ++input_line_pointer; 17000 ch = *input_line_pointer; 17001 *input_line_pointer = '\0'; 17002 17003 if (!file_mips_opts_checked) 17004 { 17005 if (parse_code_option (name) == OPTION_TYPE_BAD) 17006 as_bad (_(".module used with unrecognized symbol: %s\n"), name); 17007 17008 /* Update module level settings from mips_opts. */ 17009 file_mips_opts = mips_opts; 17010 } 17011 else 17012 as_bad (_(".module is not permitted after generating code")); 17013 17014 *input_line_pointer = ch; 17015 demand_empty_rest_of_line (); 17016} 17017 17018/* Handle the .abicalls pseudo-op. I believe this is equivalent to 17019 .option pic2. It means to generate SVR4 PIC calls. */ 17020 17021static void 17022s_abicalls (int ignore ATTRIBUTE_UNUSED) 17023{ 17024 mips_pic = SVR4_PIC; 17025 mips_abicalls = TRUE; 17026 17027 if (g_switch_seen && g_switch_value != 0) 17028 as_warn (_("-G may not be used with SVR4 PIC code")); 17029 g_switch_value = 0; 17030 17031 bfd_set_gp_size (stdoutput, 0); 17032 demand_empty_rest_of_line (); 17033} 17034 17035/* Handle the .cpload pseudo-op. This is used when generating SVR4 17036 PIC code. It sets the $gp register for the function based on the 17037 function address, which is in the register named in the argument. 17038 This uses a relocation against _gp_disp, which is handled specially 17039 by the linker. The result is: 17040 lui $gp,%hi(_gp_disp) 17041 addiu $gp,$gp,%lo(_gp_disp) 17042 addu $gp,$gp,.cpload argument 17043 The .cpload argument is normally $25 == $t9. 17044 17045 The -mno-shared option changes this to: 17046 lui $gp,%hi(__gnu_local_gp) 17047 addiu $gp,$gp,%lo(__gnu_local_gp) 17048 and the argument is ignored. This saves an instruction, but the 17049 resulting code is not position independent; it uses an absolute 17050 address for __gnu_local_gp. Thus code assembled with -mno-shared 17051 can go into an ordinary executable, but not into a shared library. */ 17052 17053static void 17054s_cpload (int ignore ATTRIBUTE_UNUSED) 17055{ 17056 expressionS ex; 17057 int reg; 17058 int in_shared; 17059 17060 file_mips_check_options (); 17061 17062 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 17063 .cpload is ignored. */ 17064 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 17065 { 17066 s_ignore (0); 17067 return; 17068 } 17069 17070 if (mips_opts.mips16) 17071 { 17072 as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); 17073 ignore_rest_of_line (); 17074 return; 17075 } 17076 17077 /* .cpload should be in a .set noreorder section. */ 17078 if (mips_opts.noreorder == 0) 17079 as_warn (_(".cpload not in noreorder section")); 17080 17081 reg = tc_get_register (0); 17082 17083 /* If we need to produce a 64-bit address, we are better off using 17084 the default instruction sequence. */ 17085 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; 17086 17087 ex.X_op = O_symbol; 17088 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : 17089 "__gnu_local_gp"); 17090 ex.X_op_symbol = NULL; 17091 ex.X_add_number = 0; 17092 17093 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 17094 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 17095 17096 mips_mark_labels (); 17097 mips_assembling_insn = TRUE; 17098 17099 macro_start (); 17100 macro_build_lui (&ex, mips_gp_register); 17101 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 17102 mips_gp_register, BFD_RELOC_LO16); 17103 if (in_shared) 17104 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 17105 mips_gp_register, reg); 17106 macro_end (); 17107 17108 mips_assembling_insn = FALSE; 17109 demand_empty_rest_of_line (); 17110} 17111 17112/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 17113 .cpsetup $reg1, offset|$reg2, label 17114 17115 If offset is given, this results in: 17116 sd $gp, offset($sp) 17117 lui $gp, %hi(%neg(%gp_rel(label))) 17118 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 17119 daddu $gp, $gp, $reg1 17120 17121 If $reg2 is given, this results in: 17122 or $reg2, $gp, $0 17123 lui $gp, %hi(%neg(%gp_rel(label))) 17124 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 17125 daddu $gp, $gp, $reg1 17126 $reg1 is normally $25 == $t9. 17127 17128 The -mno-shared option replaces the last three instructions with 17129 lui $gp,%hi(_gp) 17130 addiu $gp,$gp,%lo(_gp) */ 17131 17132static void 17133s_cpsetup (int ignore ATTRIBUTE_UNUSED) 17134{ 17135 expressionS ex_off; 17136 expressionS ex_sym; 17137 int reg1; 17138 17139 file_mips_check_options (); 17140 17141 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 17142 We also need NewABI support. */ 17143 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 17144 { 17145 s_ignore (0); 17146 return; 17147 } 17148 17149 if (mips_opts.mips16) 17150 { 17151 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); 17152 ignore_rest_of_line (); 17153 return; 17154 } 17155 17156 reg1 = tc_get_register (0); 17157 SKIP_WHITESPACE (); 17158 if (*input_line_pointer != ',') 17159 { 17160 as_bad (_("missing argument separator ',' for .cpsetup")); 17161 return; 17162 } 17163 else 17164 ++input_line_pointer; 17165 SKIP_WHITESPACE (); 17166 if (*input_line_pointer == '$') 17167 { 17168 mips_cpreturn_register = tc_get_register (0); 17169 mips_cpreturn_offset = -1; 17170 } 17171 else 17172 { 17173 mips_cpreturn_offset = get_absolute_expression (); 17174 mips_cpreturn_register = -1; 17175 } 17176 SKIP_WHITESPACE (); 17177 if (*input_line_pointer != ',') 17178 { 17179 as_bad (_("missing argument separator ',' for .cpsetup")); 17180 return; 17181 } 17182 else 17183 ++input_line_pointer; 17184 SKIP_WHITESPACE (); 17185 expression (&ex_sym); 17186 17187 mips_mark_labels (); 17188 mips_assembling_insn = TRUE; 17189 17190 macro_start (); 17191 if (mips_cpreturn_register == -1) 17192 { 17193 ex_off.X_op = O_constant; 17194 ex_off.X_add_symbol = NULL; 17195 ex_off.X_op_symbol = NULL; 17196 ex_off.X_add_number = mips_cpreturn_offset; 17197 17198 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 17199 BFD_RELOC_LO16, SP); 17200 } 17201 else 17202 move_register (mips_cpreturn_register, mips_gp_register); 17203 17204 if (mips_in_shared || HAVE_64BIT_SYMBOLS) 17205 { 17206 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, 17207 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, 17208 BFD_RELOC_HI16_S); 17209 17210 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 17211 mips_gp_register, -1, BFD_RELOC_GPREL16, 17212 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); 17213 17214 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 17215 mips_gp_register, reg1); 17216 } 17217 else 17218 { 17219 expressionS ex; 17220 17221 ex.X_op = O_symbol; 17222 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); 17223 ex.X_op_symbol = NULL; 17224 ex.X_add_number = 0; 17225 17226 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 17227 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 17228 17229 macro_build_lui (&ex, mips_gp_register); 17230 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 17231 mips_gp_register, BFD_RELOC_LO16); 17232 } 17233 17234 macro_end (); 17235 17236 mips_assembling_insn = FALSE; 17237 demand_empty_rest_of_line (); 17238} 17239 17240static void 17241s_cplocal (int ignore ATTRIBUTE_UNUSED) 17242{ 17243 file_mips_check_options (); 17244 17245 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 17246 .cplocal is ignored. */ 17247 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 17248 { 17249 s_ignore (0); 17250 return; 17251 } 17252 17253 if (mips_opts.mips16) 17254 { 17255 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); 17256 ignore_rest_of_line (); 17257 return; 17258 } 17259 17260 mips_gp_register = tc_get_register (0); 17261 demand_empty_rest_of_line (); 17262} 17263 17264/* Handle the .cprestore pseudo-op. This stores $gp into a given 17265 offset from $sp. The offset is remembered, and after making a PIC 17266 call $gp is restored from that location. */ 17267 17268static void 17269s_cprestore (int ignore ATTRIBUTE_UNUSED) 17270{ 17271 expressionS ex; 17272 17273 file_mips_check_options (); 17274 17275 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 17276 .cprestore is ignored. */ 17277 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 17278 { 17279 s_ignore (0); 17280 return; 17281 } 17282 17283 if (mips_opts.mips16) 17284 { 17285 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); 17286 ignore_rest_of_line (); 17287 return; 17288 } 17289 17290 mips_cprestore_offset = get_absolute_expression (); 17291 mips_cprestore_valid = 1; 17292 17293 ex.X_op = O_constant; 17294 ex.X_add_symbol = NULL; 17295 ex.X_op_symbol = NULL; 17296 ex.X_add_number = mips_cprestore_offset; 17297 17298 mips_mark_labels (); 17299 mips_assembling_insn = TRUE; 17300 17301 macro_start (); 17302 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 17303 SP, HAVE_64BIT_ADDRESSES); 17304 macro_end (); 17305 17306 mips_assembling_insn = FALSE; 17307 demand_empty_rest_of_line (); 17308} 17309 17310/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 17311 was given in the preceding .cpsetup, it results in: 17312 ld $gp, offset($sp) 17313 17314 If a register $reg2 was given there, it results in: 17315 or $gp, $reg2, $0 */ 17316 17317static void 17318s_cpreturn (int ignore ATTRIBUTE_UNUSED) 17319{ 17320 expressionS ex; 17321 17322 file_mips_check_options (); 17323 17324 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 17325 We also need NewABI support. */ 17326 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 17327 { 17328 s_ignore (0); 17329 return; 17330 } 17331 17332 if (mips_opts.mips16) 17333 { 17334 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); 17335 ignore_rest_of_line (); 17336 return; 17337 } 17338 17339 mips_mark_labels (); 17340 mips_assembling_insn = TRUE; 17341 17342 macro_start (); 17343 if (mips_cpreturn_register == -1) 17344 { 17345 ex.X_op = O_constant; 17346 ex.X_add_symbol = NULL; 17347 ex.X_op_symbol = NULL; 17348 ex.X_add_number = mips_cpreturn_offset; 17349 17350 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 17351 } 17352 else 17353 move_register (mips_gp_register, mips_cpreturn_register); 17354 17355 macro_end (); 17356 17357 mips_assembling_insn = FALSE; 17358 demand_empty_rest_of_line (); 17359} 17360 17361/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword 17362 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size 17363 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF 17364 debug information or MIPS16 TLS. */ 17365 17366static void 17367s_tls_rel_directive (const size_t bytes, const char *dirstr, 17368 bfd_reloc_code_real_type rtype) 17369{ 17370 expressionS ex; 17371 char *p; 17372 17373 expression (&ex); 17374 17375 if (ex.X_op != O_symbol) 17376 { 17377 as_bad (_("unsupported use of %s"), dirstr); 17378 ignore_rest_of_line (); 17379 } 17380 17381 p = frag_more (bytes); 17382 md_number_to_chars (p, 0, bytes); 17383 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); 17384 demand_empty_rest_of_line (); 17385 mips_clear_insn_labels (); 17386} 17387 17388/* Handle .dtprelword. */ 17389 17390static void 17391s_dtprelword (int ignore ATTRIBUTE_UNUSED) 17392{ 17393 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); 17394} 17395 17396/* Handle .dtpreldword. */ 17397 17398static void 17399s_dtpreldword (int ignore ATTRIBUTE_UNUSED) 17400{ 17401 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); 17402} 17403 17404/* Handle .tprelword. */ 17405 17406static void 17407s_tprelword (int ignore ATTRIBUTE_UNUSED) 17408{ 17409 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); 17410} 17411 17412/* Handle .tpreldword. */ 17413 17414static void 17415s_tpreldword (int ignore ATTRIBUTE_UNUSED) 17416{ 17417 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); 17418} 17419 17420/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 17421 code. It sets the offset to use in gp_rel relocations. */ 17422 17423static void 17424s_gpvalue (int ignore ATTRIBUTE_UNUSED) 17425{ 17426 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 17427 We also need NewABI support. */ 17428 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 17429 { 17430 s_ignore (0); 17431 return; 17432 } 17433 17434 mips_gprel_offset = get_absolute_expression (); 17435 17436 demand_empty_rest_of_line (); 17437} 17438 17439/* Handle the .gpword pseudo-op. This is used when generating PIC 17440 code. It generates a 32 bit GP relative reloc. */ 17441 17442static void 17443s_gpword (int ignore ATTRIBUTE_UNUSED) 17444{ 17445 segment_info_type *si; 17446 struct insn_label_list *l; 17447 expressionS ex; 17448 char *p; 17449 17450 /* When not generating PIC code, this is treated as .word. */ 17451 if (mips_pic != SVR4_PIC) 17452 { 17453 s_cons (2); 17454 return; 17455 } 17456 17457 si = seg_info (now_seg); 17458 l = si->label_list; 17459 mips_emit_delays (); 17460 if (auto_align) 17461 mips_align (2, 0, l); 17462 17463 expression (&ex); 17464 mips_clear_insn_labels (); 17465 17466 if (ex.X_op != O_symbol || ex.X_add_number != 0) 17467 { 17468 as_bad (_("unsupported use of .gpword")); 17469 ignore_rest_of_line (); 17470 } 17471 17472 p = frag_more (4); 17473 md_number_to_chars (p, 0, 4); 17474 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 17475 BFD_RELOC_GPREL32); 17476 17477 demand_empty_rest_of_line (); 17478} 17479 17480static void 17481s_gpdword (int ignore ATTRIBUTE_UNUSED) 17482{ 17483 segment_info_type *si; 17484 struct insn_label_list *l; 17485 expressionS ex; 17486 char *p; 17487 17488 /* When not generating PIC code, this is treated as .dword. */ 17489 if (mips_pic != SVR4_PIC) 17490 { 17491 s_cons (3); 17492 return; 17493 } 17494 17495 si = seg_info (now_seg); 17496 l = si->label_list; 17497 mips_emit_delays (); 17498 if (auto_align) 17499 mips_align (3, 0, l); 17500 17501 expression (&ex); 17502 mips_clear_insn_labels (); 17503 17504 if (ex.X_op != O_symbol || ex.X_add_number != 0) 17505 { 17506 as_bad (_("unsupported use of .gpdword")); 17507 ignore_rest_of_line (); 17508 } 17509 17510 p = frag_more (8); 17511 md_number_to_chars (p, 0, 8); 17512 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 17513 BFD_RELOC_GPREL32)->fx_tcbit = 1; 17514 17515 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 17516 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, 17517 FALSE, BFD_RELOC_64)->fx_tcbit = 1; 17518 17519 demand_empty_rest_of_line (); 17520} 17521 17522/* Handle the .ehword pseudo-op. This is used when generating unwinding 17523 tables. It generates a R_MIPS_EH reloc. */ 17524 17525static void 17526s_ehword (int ignore ATTRIBUTE_UNUSED) 17527{ 17528 expressionS ex; 17529 char *p; 17530 17531 mips_emit_delays (); 17532 17533 expression (&ex); 17534 mips_clear_insn_labels (); 17535 17536 if (ex.X_op != O_symbol || ex.X_add_number != 0) 17537 { 17538 as_bad (_("unsupported use of .ehword")); 17539 ignore_rest_of_line (); 17540 } 17541 17542 p = frag_more (4); 17543 md_number_to_chars (p, 0, 4); 17544 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 17545 BFD_RELOC_32_PCREL); 17546 17547 demand_empty_rest_of_line (); 17548} 17549 17550/* Handle the .cpadd pseudo-op. This is used when dealing with switch 17551 tables in SVR4 PIC code. */ 17552 17553static void 17554s_cpadd (int ignore ATTRIBUTE_UNUSED) 17555{ 17556 int reg; 17557 17558 file_mips_check_options (); 17559 17560 /* This is ignored when not generating SVR4 PIC code. */ 17561 if (mips_pic != SVR4_PIC) 17562 { 17563 s_ignore (0); 17564 return; 17565 } 17566 17567 mips_mark_labels (); 17568 mips_assembling_insn = TRUE; 17569 17570 /* Add $gp to the register named as an argument. */ 17571 macro_start (); 17572 reg = tc_get_register (0); 17573 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 17574 macro_end (); 17575 17576 mips_assembling_insn = FALSE; 17577 demand_empty_rest_of_line (); 17578} 17579 17580/* Handle the .insn pseudo-op. This marks instruction labels in 17581 mips16/micromips mode. This permits the linker to handle them specially, 17582 such as generating jalx instructions when needed. We also make 17583 them odd for the duration of the assembly, in order to generate the 17584 right sort of code. We will make them even in the adjust_symtab 17585 routine, while leaving them marked. This is convenient for the 17586 debugger and the disassembler. The linker knows to make them odd 17587 again. */ 17588 17589static void 17590s_insn (int ignore ATTRIBUTE_UNUSED) 17591{ 17592 file_mips_check_options (); 17593 file_ase_mips16 |= mips_opts.mips16; 17594 file_ase_micromips |= mips_opts.micromips; 17595 17596 mips_mark_labels (); 17597 17598 demand_empty_rest_of_line (); 17599} 17600 17601/* Handle the .nan pseudo-op. */ 17602 17603static void 17604s_nan (int ignore ATTRIBUTE_UNUSED) 17605{ 17606 static const char str_legacy[] = "legacy"; 17607 static const char str_2008[] = "2008"; 17608 size_t i; 17609 17610 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); 17611 17612 if (i == sizeof (str_2008) - 1 17613 && memcmp (input_line_pointer, str_2008, i) == 0) 17614 mips_nan2008 = 1; 17615 else if (i == sizeof (str_legacy) - 1 17616 && memcmp (input_line_pointer, str_legacy, i) == 0) 17617 { 17618 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) 17619 mips_nan2008 = 0; 17620 else 17621 as_bad (_("`%s' does not support legacy NaN"), 17622 mips_cpu_info_from_isa (file_mips_opts.isa)->name); 17623 } 17624 else 17625 as_bad (_("bad .nan directive")); 17626 17627 input_line_pointer += i; 17628 demand_empty_rest_of_line (); 17629} 17630 17631/* Handle a .stab[snd] directive. Ideally these directives would be 17632 implemented in a transparent way, so that removing them would not 17633 have any effect on the generated instructions. However, s_stab 17634 internally changes the section, so in practice we need to decide 17635 now whether the preceding label marks compressed code. We do not 17636 support changing the compression mode of a label after a .stab* 17637 directive, such as in: 17638 17639 foo: 17640 .stabs ... 17641 .set mips16 17642 17643 so the current mode wins. */ 17644 17645static void 17646s_mips_stab (int type) 17647{ 17648 file_mips_check_options (); 17649 mips_mark_labels (); 17650 s_stab (type); 17651} 17652 17653/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ 17654 17655static void 17656s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 17657{ 17658 char *name; 17659 int c; 17660 symbolS *symbolP; 17661 expressionS exp; 17662 17663 c = get_symbol_name (&name); 17664 symbolP = symbol_find_or_make (name); 17665 S_SET_WEAK (symbolP); 17666 *input_line_pointer = c; 17667 17668 SKIP_WHITESPACE_AFTER_NAME (); 17669 17670 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 17671 { 17672 if (S_IS_DEFINED (symbolP)) 17673 { 17674 as_bad (_("ignoring attempt to redefine symbol %s"), 17675 S_GET_NAME (symbolP)); 17676 ignore_rest_of_line (); 17677 return; 17678 } 17679 17680 if (*input_line_pointer == ',') 17681 { 17682 ++input_line_pointer; 17683 SKIP_WHITESPACE (); 17684 } 17685 17686 expression (&exp); 17687 if (exp.X_op != O_symbol) 17688 { 17689 as_bad (_("bad .weakext directive")); 17690 ignore_rest_of_line (); 17691 return; 17692 } 17693 symbol_set_value_expression (symbolP, &exp); 17694 } 17695 17696 demand_empty_rest_of_line (); 17697} 17698 17699/* Parse a register string into a number. Called from the ECOFF code 17700 to parse .frame. The argument is non-zero if this is the frame 17701 register, so that we can record it in mips_frame_reg. */ 17702 17703int 17704tc_get_register (int frame) 17705{ 17706 unsigned int reg; 17707 17708 SKIP_WHITESPACE (); 17709 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) 17710 reg = 0; 17711 if (frame) 17712 { 17713 mips_frame_reg = reg != 0 ? reg : SP; 17714 mips_frame_reg_valid = 1; 17715 mips_cprestore_valid = 0; 17716 } 17717 return reg; 17718} 17719 17720valueT 17721md_section_align (asection *seg, valueT addr) 17722{ 17723 int align = bfd_section_alignment (seg); 17724 17725 /* We don't need to align ELF sections to the full alignment. 17726 However, Irix 5 may prefer that we align them at least to a 16 17727 byte boundary. We don't bother to align the sections if we 17728 are targeted for an embedded system. */ 17729 if (strncmp (TARGET_OS, "elf", 3) == 0) 17730 return addr; 17731 if (align > 4) 17732 align = 4; 17733 17734 return ((addr + (1 << align) - 1) & -(1 << align)); 17735} 17736 17737/* Utility routine, called from above as well. If called while the 17738 input file is still being read, it's only an approximation. (For 17739 example, a symbol may later become defined which appeared to be 17740 undefined earlier.) */ 17741 17742static int 17743nopic_need_relax (symbolS *sym, int before_relaxing) 17744{ 17745 if (sym == 0) 17746 return 0; 17747 17748 if (g_switch_value > 0) 17749 { 17750 const char *symname; 17751 int change; 17752 17753 /* Find out whether this symbol can be referenced off the $gp 17754 register. It can be if it is smaller than the -G size or if 17755 it is in the .sdata or .sbss section. Certain symbols can 17756 not be referenced off the $gp, although it appears as though 17757 they can. */ 17758 symname = S_GET_NAME (sym); 17759 if (symname != (const char *) NULL 17760 && (strcmp (symname, "eprol") == 0 17761 || strcmp (symname, "etext") == 0 17762 || strcmp (symname, "_gp") == 0 17763 || strcmp (symname, "edata") == 0 17764 || strcmp (symname, "_fbss") == 0 17765 || strcmp (symname, "_fdata") == 0 17766 || strcmp (symname, "_ftext") == 0 17767 || strcmp (symname, "end") == 0 17768 || strcmp (symname, "_gp_disp") == 0)) 17769 change = 1; 17770 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 17771 && (0 17772#ifndef NO_ECOFF_DEBUGGING 17773 || (symbol_get_obj (sym)->ecoff_extern_size != 0 17774 && (symbol_get_obj (sym)->ecoff_extern_size 17775 <= g_switch_value)) 17776#endif 17777 /* We must defer this decision until after the whole 17778 file has been read, since there might be a .extern 17779 after the first use of this symbol. */ 17780 || (before_relaxing 17781#ifndef NO_ECOFF_DEBUGGING 17782 && symbol_get_obj (sym)->ecoff_extern_size == 0 17783#endif 17784 && S_GET_VALUE (sym) == 0) 17785 || (S_GET_VALUE (sym) != 0 17786 && S_GET_VALUE (sym) <= g_switch_value))) 17787 change = 0; 17788 else 17789 { 17790 const char *segname; 17791 17792 segname = segment_name (S_GET_SEGMENT (sym)); 17793 gas_assert (strcmp (segname, ".lit8") != 0 17794 && strcmp (segname, ".lit4") != 0); 17795 change = (strcmp (segname, ".sdata") != 0 17796 && strcmp (segname, ".sbss") != 0 17797 && strncmp (segname, ".sdata.", 7) != 0 17798 && strncmp (segname, ".sbss.", 6) != 0 17799 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 17800 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 17801 } 17802 return change; 17803 } 17804 else 17805 /* We are not optimizing for the $gp register. */ 17806 return 1; 17807} 17808 17809 17810/* Return true if the given symbol should be considered local for SVR4 PIC. */ 17811 17812static bfd_boolean 17813pic_need_relax (symbolS *sym) 17814{ 17815 asection *symsec; 17816 17817 /* Handle the case of a symbol equated to another symbol. */ 17818 while (symbol_equated_reloc_p (sym)) 17819 { 17820 symbolS *n; 17821 17822 /* It's possible to get a loop here in a badly written program. */ 17823 n = symbol_get_value_expression (sym)->X_add_symbol; 17824 if (n == sym) 17825 break; 17826 sym = n; 17827 } 17828 17829 if (symbol_section_p (sym)) 17830 return TRUE; 17831 17832 symsec = S_GET_SEGMENT (sym); 17833 17834 /* This must duplicate the test in adjust_reloc_syms. */ 17835 return (!bfd_is_und_section (symsec) 17836 && !bfd_is_abs_section (symsec) 17837 && !bfd_is_com_section (symsec) 17838 /* A global or weak symbol is treated as external. */ 17839 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); 17840} 17841 17842/* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP 17843 convert a section-relative value VAL to the equivalent PC-relative 17844 value. */ 17845 17846static offsetT 17847mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, 17848 offsetT val, long stretch) 17849{ 17850 fragS *sym_frag; 17851 addressT addr; 17852 17853 gas_assert (pcrel_op->root.root.type == OP_PCREL); 17854 17855 sym_frag = symbol_get_frag (fragp->fr_symbol); 17856 17857 /* If the relax_marker of the symbol fragment differs from the 17858 relax_marker of this fragment, we have not yet adjusted the 17859 symbol fragment fr_address. We want to add in STRETCH in 17860 order to get a better estimate of the address. This 17861 particularly matters because of the shift bits. */ 17862 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) 17863 { 17864 fragS *f; 17865 17866 /* Adjust stretch for any alignment frag. Note that if have 17867 been expanding the earlier code, the symbol may be 17868 defined in what appears to be an earlier frag. FIXME: 17869 This doesn't handle the fr_subtype field, which specifies 17870 a maximum number of bytes to skip when doing an 17871 alignment. */ 17872 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 17873 { 17874 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 17875 { 17876 if (stretch < 0) 17877 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); 17878 else 17879 stretch &= ~((1 << (int) f->fr_offset) - 1); 17880 if (stretch == 0) 17881 break; 17882 } 17883 } 17884 if (f != NULL) 17885 val += stretch; 17886 } 17887 17888 addr = fragp->fr_address + fragp->fr_fix; 17889 17890 /* The base address rules are complicated. The base address of 17891 a branch is the following instruction. The base address of a 17892 PC relative load or add is the instruction itself, but if it 17893 is in a delay slot (in which case it can not be extended) use 17894 the address of the instruction whose delay slot it is in. */ 17895 if (pcrel_op->include_isa_bit) 17896 { 17897 addr += 2; 17898 17899 /* If we are currently assuming that this frag should be 17900 extended, then the current address is two bytes higher. */ 17901 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17902 addr += 2; 17903 17904 /* Ignore the low bit in the target, since it will be set 17905 for a text label. */ 17906 val &= -2; 17907 } 17908 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 17909 addr -= 4; 17910 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 17911 addr -= 2; 17912 17913 val -= addr & -(1 << pcrel_op->align_log2); 17914 17915 return val; 17916} 17917 17918/* Given a mips16 variant frag FRAGP, return non-zero if it needs an 17919 extended opcode. SEC is the section the frag is in. */ 17920 17921static int 17922mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 17923{ 17924 const struct mips_int_operand *operand; 17925 offsetT val; 17926 segT symsec; 17927 int type; 17928 17929 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 17930 return 0; 17931 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 17932 return 1; 17933 17934 symsec = S_GET_SEGMENT (fragp->fr_symbol); 17935 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 17936 operand = mips16_immed_operand (type, FALSE); 17937 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 17938 || (operand->root.type == OP_PCREL 17939 ? sec != symsec 17940 : !bfd_is_abs_section (symsec))) 17941 return 1; 17942 17943 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 17944 17945 if (operand->root.type == OP_PCREL) 17946 { 17947 const struct mips_pcrel_operand *pcrel_op; 17948 offsetT maxtiny; 17949 17950 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) 17951 return 1; 17952 17953 pcrel_op = (const struct mips_pcrel_operand *) operand; 17954 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); 17955 17956 /* If any of the shifted bits are set, we must use an extended 17957 opcode. If the address depends on the size of this 17958 instruction, this can lead to a loop, so we arrange to always 17959 use an extended opcode. */ 17960 if ((val & ((1 << operand->shift) - 1)) != 0) 17961 { 17962 fragp->fr_subtype = 17963 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); 17964 return 1; 17965 } 17966 17967 /* If we are about to mark a frag as extended because the value 17968 is precisely the next value above maxtiny, then there is a 17969 chance of an infinite loop as in the following code: 17970 la $4,foo 17971 .skip 1020 17972 .align 2 17973 foo: 17974 In this case when the la is extended, foo is 0x3fc bytes 17975 away, so the la can be shrunk, but then foo is 0x400 away, so 17976 the la must be extended. To avoid this loop, we mark the 17977 frag as extended if it was small, and is about to become 17978 extended with the next value above maxtiny. */ 17979 maxtiny = mips_int_operand_max (operand); 17980 if (val == maxtiny + (1 << operand->shift) 17981 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 17982 { 17983 fragp->fr_subtype = 17984 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); 17985 return 1; 17986 } 17987 } 17988 17989 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); 17990} 17991 17992/* Given a MIPS16 variant frag FRAGP, return non-zero if it needs 17993 macro expansion. SEC is the section the frag is in. We only 17994 support PC-relative instructions (LA, DLA, LW, LD) here, in 17995 non-PIC code using 32-bit addressing. */ 17996 17997static int 17998mips16_macro_frag (fragS *fragp, asection *sec, long stretch) 17999{ 18000 const struct mips_pcrel_operand *pcrel_op; 18001 const struct mips_int_operand *operand; 18002 offsetT val; 18003 segT symsec; 18004 int type; 18005 18006 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); 18007 18008 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 18009 return 0; 18010 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) 18011 return 0; 18012 18013 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 18014 switch (type) 18015 { 18016 case 'A': 18017 case 'B': 18018 case 'E': 18019 symsec = S_GET_SEGMENT (fragp->fr_symbol); 18020 if (bfd_is_abs_section (symsec)) 18021 return 1; 18022 if (RELAX_MIPS16_PIC (fragp->fr_subtype)) 18023 return 0; 18024 if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) 18025 return 1; 18026 18027 operand = mips16_immed_operand (type, TRUE); 18028 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 18029 pcrel_op = (const struct mips_pcrel_operand *) operand; 18030 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); 18031 18032 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); 18033 18034 default: 18035 return 0; 18036 } 18037} 18038 18039/* Compute the length of a branch sequence, and adjust the 18040 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 18041 worst-case length is computed, with UPDATE being used to indicate 18042 whether an unconditional (-1), branch-likely (+1) or regular (0) 18043 branch is to be computed. */ 18044static int 18045relaxed_branch_length (fragS *fragp, asection *sec, int update) 18046{ 18047 bfd_boolean toofar; 18048 int length; 18049 18050 if (fragp 18051 && S_IS_DEFINED (fragp->fr_symbol) 18052 && !S_IS_WEAK (fragp->fr_symbol) 18053 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 18054 { 18055 addressT addr; 18056 offsetT val; 18057 18058 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 18059 18060 addr = fragp->fr_address + fragp->fr_fix + 4; 18061 18062 val -= addr; 18063 18064 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 18065 } 18066 else 18067 /* If the symbol is not defined or it's in a different segment, 18068 we emit the long sequence. */ 18069 toofar = TRUE; 18070 18071 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 18072 fragp->fr_subtype 18073 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), 18074 RELAX_BRANCH_PIC (fragp->fr_subtype), 18075 RELAX_BRANCH_UNCOND (fragp->fr_subtype), 18076 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 18077 RELAX_BRANCH_LINK (fragp->fr_subtype), 18078 toofar); 18079 18080 length = 4; 18081 if (toofar) 18082 { 18083 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 18084 length += 8; 18085 18086 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) 18087 { 18088 /* Additional space for PIC loading of target address. */ 18089 length += 8; 18090 if (mips_opts.isa == ISA_MIPS1) 18091 /* Additional space for $at-stabilizing nop. */ 18092 length += 4; 18093 } 18094 18095 /* If branch is conditional. */ 18096 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 18097 length += 8; 18098 } 18099 18100 return length; 18101} 18102 18103/* Get a FRAG's branch instruction delay slot size, either from the 18104 short-delay-slot bit of a branch-and-link instruction if AL is TRUE, 18105 or SHORT_INSN_SIZE otherwise. */ 18106 18107static int 18108frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) 18109{ 18110 char *buf = fragp->fr_literal + fragp->fr_fix; 18111 18112 if (al) 18113 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; 18114 else 18115 return short_insn_size; 18116} 18117 18118/* Compute the length of a branch sequence, and adjust the 18119 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the 18120 worst-case length is computed, with UPDATE being used to indicate 18121 whether an unconditional (-1), or regular (0) branch is to be 18122 computed. */ 18123 18124static int 18125relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) 18126{ 18127 bfd_boolean insn32 = TRUE; 18128 bfd_boolean nods = TRUE; 18129 bfd_boolean pic = TRUE; 18130 bfd_boolean al = TRUE; 18131 int short_insn_size; 18132 bfd_boolean toofar; 18133 int length; 18134 18135 if (fragp) 18136 { 18137 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); 18138 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); 18139 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); 18140 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 18141 } 18142 short_insn_size = insn32 ? 4 : 2; 18143 18144 if (fragp 18145 && S_IS_DEFINED (fragp->fr_symbol) 18146 && !S_IS_WEAK (fragp->fr_symbol) 18147 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 18148 { 18149 addressT addr; 18150 offsetT val; 18151 18152 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 18153 /* Ignore the low bit in the target, since it will be set 18154 for a text label. */ 18155 if ((val & 1) != 0) 18156 --val; 18157 18158 addr = fragp->fr_address + fragp->fr_fix + 4; 18159 18160 val -= addr; 18161 18162 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); 18163 } 18164 else 18165 /* If the symbol is not defined or it's in a different segment, 18166 we emit the long sequence. */ 18167 toofar = TRUE; 18168 18169 if (fragp && update 18170 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 18171 fragp->fr_subtype = (toofar 18172 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) 18173 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); 18174 18175 length = 4; 18176 if (toofar) 18177 { 18178 bfd_boolean compact_known = fragp != NULL; 18179 bfd_boolean compact = FALSE; 18180 bfd_boolean uncond; 18181 18182 if (fragp) 18183 { 18184 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 18185 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); 18186 } 18187 else 18188 uncond = update < 0; 18189 18190 /* If label is out of range, we turn branch <br>: 18191 18192 <br> label # 4 bytes 18193 0: 18194 18195 into: 18196 18197 j label # 4 bytes 18198 nop # 2/4 bytes if 18199 # compact && (!PIC || insn32) 18200 0: 18201 */ 18202 if ((!pic || insn32) && (!compact_known || compact)) 18203 length += short_insn_size; 18204 18205 /* If assembling PIC code, we further turn: 18206 18207 j label # 4 bytes 18208 18209 into: 18210 18211 lw/ld at, %got(label)(gp) # 4 bytes 18212 d/addiu at, %lo(label) # 4 bytes 18213 jr/c at # 2/4 bytes 18214 */ 18215 if (pic) 18216 length += 4 + short_insn_size; 18217 18218 /* Add an extra nop if the jump has no compact form and we need 18219 to fill the delay slot. */ 18220 if ((!pic || al) && nods) 18221 length += (fragp 18222 ? frag_branch_delay_slot_size (fragp, al, short_insn_size) 18223 : short_insn_size); 18224 18225 /* If branch <br> is conditional, we prepend negated branch <brneg>: 18226 18227 <brneg> 0f # 4 bytes 18228 nop # 2/4 bytes if !compact 18229 */ 18230 if (!uncond) 18231 length += (compact_known && compact) ? 4 : 4 + short_insn_size; 18232 } 18233 else if (nods) 18234 { 18235 /* Add an extra nop to fill the delay slot. */ 18236 gas_assert (fragp); 18237 length += frag_branch_delay_slot_size (fragp, al, short_insn_size); 18238 } 18239 18240 return length; 18241} 18242 18243/* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 18244 bit accordingly. */ 18245 18246static int 18247relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) 18248{ 18249 bfd_boolean toofar; 18250 18251 if (fragp 18252 && S_IS_DEFINED (fragp->fr_symbol) 18253 && !S_IS_WEAK (fragp->fr_symbol) 18254 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 18255 { 18256 addressT addr; 18257 offsetT val; 18258 int type; 18259 18260 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 18261 /* Ignore the low bit in the target, since it will be set 18262 for a text label. */ 18263 if ((val & 1) != 0) 18264 --val; 18265 18266 /* Assume this is a 2-byte branch. */ 18267 addr = fragp->fr_address + fragp->fr_fix + 2; 18268 18269 /* We try to avoid the infinite loop by not adding 2 more bytes for 18270 long branches. */ 18271 18272 val -= addr; 18273 18274 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 18275 if (type == 'D') 18276 toofar = val < - (0x200 << 1) || val >= (0x200 << 1); 18277 else if (type == 'E') 18278 toofar = val < - (0x40 << 1) || val >= (0x40 << 1); 18279 else 18280 abort (); 18281 } 18282 else 18283 /* If the symbol is not defined or it's in a different segment, 18284 we emit a normal 32-bit branch. */ 18285 toofar = TRUE; 18286 18287 if (fragp && update 18288 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 18289 fragp->fr_subtype 18290 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) 18291 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); 18292 18293 if (toofar) 18294 return 4; 18295 18296 return 2; 18297} 18298 18299/* Estimate the size of a frag before relaxing. Unless this is the 18300 mips16, we are not really relaxing here, and the final size is 18301 encoded in the subtype information. For the mips16, we have to 18302 decide whether we are using an extended opcode or not. */ 18303 18304int 18305md_estimate_size_before_relax (fragS *fragp, asection *segtype) 18306{ 18307 int change; 18308 18309 if (RELAX_BRANCH_P (fragp->fr_subtype)) 18310 { 18311 18312 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 18313 18314 return fragp->fr_var; 18315 } 18316 18317 if (RELAX_MIPS16_P (fragp->fr_subtype)) 18318 { 18319 /* We don't want to modify the EXTENDED bit here; it might get us 18320 into infinite loops. We change it only in mips_relax_frag(). */ 18321 if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) 18322 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; 18323 else 18324 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; 18325 } 18326 18327 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 18328 { 18329 int length = 4; 18330 18331 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 18332 length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); 18333 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 18334 length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); 18335 fragp->fr_var = length; 18336 18337 return length; 18338 } 18339 18340 if (mips_pic == VXWORKS_PIC) 18341 /* For vxworks, GOT16 relocations never have a corresponding LO16. */ 18342 change = 0; 18343 else if (RELAX_PIC (fragp->fr_subtype)) 18344 change = pic_need_relax (fragp->fr_symbol); 18345 else 18346 change = nopic_need_relax (fragp->fr_symbol, 0); 18347 18348 if (change) 18349 { 18350 fragp->fr_subtype |= RELAX_USE_SECOND; 18351 return -RELAX_FIRST (fragp->fr_subtype); 18352 } 18353 else 18354 return -RELAX_SECOND (fragp->fr_subtype); 18355} 18356 18357/* This is called to see whether a reloc against a defined symbol 18358 should be converted into a reloc against a section. */ 18359 18360int 18361mips_fix_adjustable (fixS *fixp) 18362{ 18363 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 18364 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 18365 return 0; 18366 18367 if (fixp->fx_addsy == NULL) 18368 return 1; 18369 18370 /* Allow relocs used for EH tables. */ 18371 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 18372 return 1; 18373 18374 /* If symbol SYM is in a mergeable section, relocations of the form 18375 SYM + 0 can usually be made section-relative. The mergeable data 18376 is then identified by the section offset rather than by the symbol. 18377 18378 However, if we're generating REL LO16 relocations, the offset is split 18379 between the LO16 and partnering high part relocation. The linker will 18380 need to recalculate the complete offset in order to correctly identify 18381 the merge data. 18382 18383 The linker has traditionally not looked for the partnering high part 18384 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 18385 placed anywhere. Rather than break backwards compatibility by changing 18386 this, it seems better not to force the issue, and instead keep the 18387 original symbol. This will work with either linker behavior. */ 18388 if ((lo16_reloc_p (fixp->fx_r_type) 18389 || reloc_needs_lo_p (fixp->fx_r_type)) 18390 && HAVE_IN_PLACE_ADDENDS 18391 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 18392 return 0; 18393 18394 /* There is no place to store an in-place offset for JALR relocations. */ 18395 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) 18396 return 0; 18397 18398 /* Likewise an in-range offset of limited PC-relative relocations may 18399 overflow the in-place relocatable field if recalculated against the 18400 start address of the symbol's containing section. 18401 18402 Also, PC relative relocations for MIPS R6 need to be symbol rather than 18403 section relative to allow linker relaxations to be performed later on. */ 18404 if (limited_pcrel_reloc_p (fixp->fx_r_type) 18405 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) 18406 return 0; 18407 18408 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve 18409 to a floating-point stub. The same is true for non-R_MIPS16_26 18410 relocations against MIPS16 functions; in this case, the stub becomes 18411 the function's canonical address. 18412 18413 Floating-point stubs are stored in unique .mips16.call.* or 18414 .mips16.fn.* sections. If a stub T for function F is in section S, 18415 the first relocation in section S must be against F; this is how the 18416 linker determines the target function. All relocations that might 18417 resolve to T must also be against F. We therefore have the following 18418 restrictions, which are given in an intentionally-redundant way: 18419 18420 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 18421 symbols. 18422 18423 2. We cannot reduce a stub's relocations against non-MIPS16 symbols 18424 if that stub might be used. 18425 18426 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 18427 symbols. 18428 18429 4. We cannot reduce a stub's relocations against MIPS16 symbols if 18430 that stub might be used. 18431 18432 There is a further restriction: 18433 18434 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or 18435 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, 18436 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, 18437 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) 18438 against MIPS16 or microMIPS symbols because we need to keep the 18439 MIPS16 or microMIPS symbol for the purpose of mode mismatch 18440 detection and JAL or BAL to JALX instruction conversion in the 18441 linker. 18442 18443 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation 18444 against a MIPS16 symbol. We deal with (5) by additionally leaving 18445 alone any jump and branch relocations against a microMIPS symbol. 18446 18447 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 18448 relocation against some symbol R, no relocation against R may be 18449 reduced. (Note that this deals with (2) as well as (1) because 18450 relocations against global symbols will never be reduced on ELF 18451 targets.) This approach is a little simpler than trying to detect 18452 stub sections, and gives the "all or nothing" per-symbol consistency 18453 that we have for MIPS16 symbols. */ 18454 if (fixp->fx_subsy == NULL 18455 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) 18456 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) 18457 && (jmp_reloc_p (fixp->fx_r_type) 18458 || b_reloc_p (fixp->fx_r_type))) 18459 || *symbol_get_tc (fixp->fx_addsy))) 18460 return 0; 18461 18462 return 1; 18463} 18464 18465/* Translate internal representation of relocation info to BFD target 18466 format. */ 18467 18468arelent ** 18469tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 18470{ 18471 static arelent *retval[4]; 18472 arelent *reloc; 18473 bfd_reloc_code_real_type code; 18474 18475 memset (retval, 0, sizeof(retval)); 18476 reloc = retval[0] = XCNEW (arelent); 18477 reloc->sym_ptr_ptr = XNEW (asymbol *); 18478 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 18479 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 18480 18481 if (fixp->fx_pcrel) 18482 { 18483 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 18484 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 18485 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 18486 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 18487 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 18488 || fixp->fx_r_type == BFD_RELOC_32_PCREL 18489 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 18490 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 18491 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 18492 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 18493 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL 18494 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); 18495 18496 /* At this point, fx_addnumber is "symbol offset - pcrel address". 18497 Relocations want only the symbol offset. */ 18498 switch (fixp->fx_r_type) 18499 { 18500 case BFD_RELOC_MIPS_18_PCREL_S3: 18501 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); 18502 break; 18503 default: 18504 reloc->addend = fixp->fx_addnumber + reloc->address; 18505 break; 18506 } 18507 } 18508 else if (HAVE_IN_PLACE_ADDENDS 18509 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP 18510 && (read_compressed_insn (fixp->fx_frag->fr_literal 18511 + fixp->fx_where, 4) >> 26) == 0x3c) 18512 { 18513 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place 18514 addend accordingly. */ 18515 reloc->addend = fixp->fx_addnumber >> 1; 18516 } 18517 else 18518 reloc->addend = fixp->fx_addnumber; 18519 18520 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 18521 entry to be used in the relocation's section offset. */ 18522 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 18523 { 18524 reloc->address = reloc->addend; 18525 reloc->addend = 0; 18526 } 18527 18528 code = fixp->fx_r_type; 18529 18530 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 18531 if (reloc->howto == NULL) 18532 { 18533 as_bad_where (fixp->fx_file, fixp->fx_line, 18534 _("cannot represent %s relocation in this object file" 18535 " format"), 18536 bfd_get_reloc_code_name (code)); 18537 retval[0] = NULL; 18538 } 18539 18540 return retval; 18541} 18542 18543/* Relax a machine dependent frag. This returns the amount by which 18544 the current size of the frag should change. */ 18545 18546int 18547mips_relax_frag (asection *sec, fragS *fragp, long stretch) 18548{ 18549 if (RELAX_BRANCH_P (fragp->fr_subtype)) 18550 { 18551 offsetT old_var = fragp->fr_var; 18552 18553 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 18554 18555 return fragp->fr_var - old_var; 18556 } 18557 18558 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 18559 { 18560 offsetT old_var = fragp->fr_var; 18561 offsetT new_var = 4; 18562 18563 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) 18564 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); 18565 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) 18566 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); 18567 fragp->fr_var = new_var; 18568 18569 return new_var - old_var; 18570 } 18571 18572 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 18573 return 0; 18574 18575 if (!mips16_extended_frag (fragp, sec, stretch)) 18576 { 18577 if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) 18578 { 18579 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); 18580 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; 18581 } 18582 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 18583 { 18584 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 18585 return -2; 18586 } 18587 else 18588 return 0; 18589 } 18590 else if (!mips16_macro_frag (fragp, sec, stretch)) 18591 { 18592 if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) 18593 { 18594 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); 18595 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 18596 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; 18597 } 18598 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 18599 { 18600 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 18601 return 2; 18602 } 18603 else 18604 return 0; 18605 } 18606 else 18607 { 18608 if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) 18609 return 0; 18610 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 18611 { 18612 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 18613 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); 18614 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; 18615 } 18616 else 18617 { 18618 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); 18619 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; 18620 } 18621 } 18622 18623 return 0; 18624} 18625 18626/* Convert a machine dependent frag. */ 18627 18628void 18629md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 18630{ 18631 if (RELAX_BRANCH_P (fragp->fr_subtype)) 18632 { 18633 char *buf; 18634 unsigned long insn; 18635 fixS *fixp; 18636 18637 buf = fragp->fr_literal + fragp->fr_fix; 18638 insn = read_insn (buf); 18639 18640 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 18641 { 18642 /* We generate a fixup instead of applying it right now 18643 because, if there are linker relaxations, we're going to 18644 need the relocations. */ 18645 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 18646 fragp->fr_symbol, fragp->fr_offset, 18647 TRUE, BFD_RELOC_16_PCREL_S2); 18648 fixp->fx_file = fragp->fr_file; 18649 fixp->fx_line = fragp->fr_line; 18650 18651 buf = write_insn (buf, insn); 18652 } 18653 else 18654 { 18655 int i; 18656 18657 as_warn_where (fragp->fr_file, fragp->fr_line, 18658 _("relaxed out-of-range branch into a jump")); 18659 18660 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 18661 goto uncond; 18662 18663 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 18664 { 18665 /* Reverse the branch. */ 18666 switch ((insn >> 28) & 0xf) 18667 { 18668 case 4: 18669 if ((insn & 0xff000000) == 0x47000000 18670 || (insn & 0xff600000) == 0x45600000) 18671 { 18672 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition 18673 reversed by tweaking bit 23. */ 18674 insn ^= 0x00800000; 18675 } 18676 else 18677 { 18678 /* bc[0-3][tf]l? instructions can have the condition 18679 reversed by tweaking a single TF bit, and their 18680 opcodes all have 0x4???????. */ 18681 gas_assert ((insn & 0xf3e00000) == 0x41000000); 18682 insn ^= 0x00010000; 18683 } 18684 break; 18685 18686 case 0: 18687 /* bltz 0x04000000 bgez 0x04010000 18688 bltzal 0x04100000 bgezal 0x04110000 */ 18689 gas_assert ((insn & 0xfc0e0000) == 0x04000000); 18690 insn ^= 0x00010000; 18691 break; 18692 18693 case 1: 18694 /* beq 0x10000000 bne 0x14000000 18695 blez 0x18000000 bgtz 0x1c000000 */ 18696 insn ^= 0x04000000; 18697 break; 18698 18699 default: 18700 abort (); 18701 } 18702 } 18703 18704 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 18705 { 18706 /* Clear the and-link bit. */ 18707 gas_assert ((insn & 0xfc1c0000) == 0x04100000); 18708 18709 /* bltzal 0x04100000 bgezal 0x04110000 18710 bltzall 0x04120000 bgezall 0x04130000 */ 18711 insn &= ~0x00100000; 18712 } 18713 18714 /* Branch over the branch (if the branch was likely) or the 18715 full jump (not likely case). Compute the offset from the 18716 current instruction to branch to. */ 18717 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 18718 i = 16; 18719 else 18720 { 18721 /* How many bytes in instructions we've already emitted? */ 18722 i = buf - fragp->fr_literal - fragp->fr_fix; 18723 /* How many bytes in instructions from here to the end? */ 18724 i = fragp->fr_var - i; 18725 } 18726 /* Convert to instruction count. */ 18727 i >>= 2; 18728 /* Branch counts from the next instruction. */ 18729 i--; 18730 insn |= i; 18731 /* Branch over the jump. */ 18732 buf = write_insn (buf, insn); 18733 18734 /* nop */ 18735 buf = write_insn (buf, 0); 18736 18737 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 18738 { 18739 /* beql $0, $0, 2f */ 18740 insn = 0x50000000; 18741 /* Compute the PC offset from the current instruction to 18742 the end of the variable frag. */ 18743 /* How many bytes in instructions we've already emitted? */ 18744 i = buf - fragp->fr_literal - fragp->fr_fix; 18745 /* How many bytes in instructions from here to the end? */ 18746 i = fragp->fr_var - i; 18747 /* Convert to instruction count. */ 18748 i >>= 2; 18749 /* Don't decrement i, because we want to branch over the 18750 delay slot. */ 18751 insn |= i; 18752 18753 buf = write_insn (buf, insn); 18754 buf = write_insn (buf, 0); 18755 } 18756 18757 uncond: 18758 if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) 18759 { 18760 /* j or jal. */ 18761 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 18762 ? 0x0c000000 : 0x08000000); 18763 18764 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 18765 fragp->fr_symbol, fragp->fr_offset, 18766 FALSE, BFD_RELOC_MIPS_JMP); 18767 fixp->fx_file = fragp->fr_file; 18768 fixp->fx_line = fragp->fr_line; 18769 18770 buf = write_insn (buf, insn); 18771 } 18772 else 18773 { 18774 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); 18775 18776 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 18777 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; 18778 insn |= at << OP_SH_RT; 18779 18780 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 18781 fragp->fr_symbol, fragp->fr_offset, 18782 FALSE, BFD_RELOC_MIPS_GOT16); 18783 fixp->fx_file = fragp->fr_file; 18784 fixp->fx_line = fragp->fr_line; 18785 18786 buf = write_insn (buf, insn); 18787 18788 if (mips_opts.isa == ISA_MIPS1) 18789 /* nop */ 18790 buf = write_insn (buf, 0); 18791 18792 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 18793 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; 18794 insn |= at << OP_SH_RS | at << OP_SH_RT; 18795 18796 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 18797 fragp->fr_symbol, fragp->fr_offset, 18798 FALSE, BFD_RELOC_LO16); 18799 fixp->fx_file = fragp->fr_file; 18800 fixp->fx_line = fragp->fr_line; 18801 18802 buf = write_insn (buf, insn); 18803 18804 /* j(al)r $at. */ 18805 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 18806 insn = 0x0000f809; 18807 else 18808 insn = 0x00000008; 18809 insn |= at << OP_SH_RS; 18810 18811 buf = write_insn (buf, insn); 18812 } 18813 } 18814 18815 fragp->fr_fix += fragp->fr_var; 18816 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18817 return; 18818 } 18819 18820 /* Relax microMIPS branches. */ 18821 if (RELAX_MICROMIPS_P (fragp->fr_subtype)) 18822 { 18823 char *buf = fragp->fr_literal + fragp->fr_fix; 18824 bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); 18825 bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); 18826 bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); 18827 bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); 18828 bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); 18829 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); 18830 bfd_boolean short_ds; 18831 unsigned long insn; 18832 fixS *fixp; 18833 18834 fragp->fr_fix += fragp->fr_var; 18835 18836 /* Handle 16-bit branches that fit or are forced to fit. */ 18837 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) 18838 { 18839 /* We generate a fixup instead of applying it right now, 18840 because if there is linker relaxation, we're going to 18841 need the relocations. */ 18842 switch (type) 18843 { 18844 case 'D': 18845 fixp = fix_new (fragp, buf - fragp->fr_literal, 2, 18846 fragp->fr_symbol, fragp->fr_offset, 18847 TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); 18848 break; 18849 case 'E': 18850 fixp = fix_new (fragp, buf - fragp->fr_literal, 2, 18851 fragp->fr_symbol, fragp->fr_offset, 18852 TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); 18853 break; 18854 default: 18855 abort (); 18856 } 18857 18858 fixp->fx_file = fragp->fr_file; 18859 fixp->fx_line = fragp->fr_line; 18860 18861 /* These relocations can have an addend that won't fit in 18862 2 octets. */ 18863 fixp->fx_no_overflow = 1; 18864 18865 return; 18866 } 18867 18868 /* Handle 32-bit branches that fit or are forced to fit. */ 18869 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 18870 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 18871 { 18872 /* We generate a fixup instead of applying it right now, 18873 because if there is linker relaxation, we're going to 18874 need the relocations. */ 18875 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 18876 fragp->fr_symbol, fragp->fr_offset, 18877 TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); 18878 fixp->fx_file = fragp->fr_file; 18879 fixp->fx_line = fragp->fr_line; 18880 18881 if (type == 0) 18882 { 18883 insn = read_compressed_insn (buf, 4); 18884 buf += 4; 18885 18886 if (nods) 18887 { 18888 /* Check the short-delay-slot bit. */ 18889 if (!al || (insn & 0x02000000) != 0) 18890 buf = write_compressed_insn (buf, 0x0c00, 2); 18891 else 18892 buf = write_compressed_insn (buf, 0x00000000, 4); 18893 } 18894 18895 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18896 return; 18897 } 18898 } 18899 18900 /* Relax 16-bit branches to 32-bit branches. */ 18901 if (type != 0) 18902 { 18903 insn = read_compressed_insn (buf, 2); 18904 18905 if ((insn & 0xfc00) == 0xcc00) /* b16 */ 18906 insn = 0x94000000; /* beq */ 18907 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ 18908 { 18909 unsigned long regno; 18910 18911 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; 18912 regno = micromips_to_32_reg_d_map [regno]; 18913 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ 18914 insn |= regno << MICROMIPSOP_SH_RS; 18915 } 18916 else 18917 abort (); 18918 18919 /* Nothing else to do, just write it out. */ 18920 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) 18921 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) 18922 { 18923 buf = write_compressed_insn (buf, insn, 4); 18924 if (nods) 18925 buf = write_compressed_insn (buf, 0x0c00, 2); 18926 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 18927 return; 18928 } 18929 } 18930 else 18931 insn = read_compressed_insn (buf, 4); 18932 18933 /* Relax 32-bit branches to a sequence of instructions. */ 18934 as_warn_where (fragp->fr_file, fragp->fr_line, 18935 _("relaxed out-of-range branch into a jump")); 18936 18937 /* Set the short-delay-slot bit. */ 18938 short_ds = !al || (insn & 0x02000000) != 0; 18939 18940 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) 18941 { 18942 symbolS *l; 18943 18944 /* Reverse the branch. */ 18945 if ((insn & 0xfc000000) == 0x94000000 /* beq */ 18946 || (insn & 0xfc000000) == 0xb4000000) /* bne */ 18947 insn ^= 0x20000000; 18948 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ 18949 || (insn & 0xffe00000) == 0x40400000 /* bgez */ 18950 || (insn & 0xffe00000) == 0x40800000 /* blez */ 18951 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ 18952 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ 18953 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ 18954 || (insn & 0xffe00000) == 0x40200000 /* bltzal */ 18955 || (insn & 0xffe00000) == 0x40600000 /* bgezal */ 18956 || (insn & 0xffe00000) == 0x42200000 /* bltzals */ 18957 || (insn & 0xffe00000) == 0x42600000) /* bgezals */ 18958 insn ^= 0x00400000; 18959 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ 18960 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ 18961 || (insn & 0xffe30000) == 0x42800000 /* bc2f */ 18962 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ 18963 insn ^= 0x00200000; 18964 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df 18965 BNZ.df */ 18966 || (insn & 0xff600000) == 0x81600000) /* BZ.V 18967 BNZ.V */ 18968 insn ^= 0x00800000; 18969 else 18970 abort (); 18971 18972 if (al) 18973 { 18974 /* Clear the and-link and short-delay-slot bits. */ 18975 gas_assert ((insn & 0xfda00000) == 0x40200000); 18976 18977 /* bltzal 0x40200000 bgezal 0x40600000 */ 18978 /* bltzals 0x42200000 bgezals 0x42600000 */ 18979 insn &= ~0x02200000; 18980 } 18981 18982 /* Make a label at the end for use with the branch. */ 18983 l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); 18984 micromips_label_inc (); 18985 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); 18986 18987 /* Refer to it. */ 18988 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, 18989 BFD_RELOC_MICROMIPS_16_PCREL_S1); 18990 fixp->fx_file = fragp->fr_file; 18991 fixp->fx_line = fragp->fr_line; 18992 18993 /* Branch over the jump. */ 18994 buf = write_compressed_insn (buf, insn, 4); 18995 18996 if (!compact) 18997 { 18998 /* nop */ 18999 if (insn32) 19000 buf = write_compressed_insn (buf, 0x00000000, 4); 19001 else 19002 buf = write_compressed_insn (buf, 0x0c00, 2); 19003 } 19004 } 19005 19006 if (!pic) 19007 { 19008 unsigned long jal = (short_ds || nods 19009 ? 0x74000000 : 0xf4000000); /* jal/s */ 19010 19011 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ 19012 insn = al ? jal : 0xd4000000; 19013 19014 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 19015 fragp->fr_symbol, fragp->fr_offset, 19016 FALSE, BFD_RELOC_MICROMIPS_JMP); 19017 fixp->fx_file = fragp->fr_file; 19018 fixp->fx_line = fragp->fr_line; 19019 19020 buf = write_compressed_insn (buf, insn, 4); 19021 19022 if (compact || nods) 19023 { 19024 /* nop */ 19025 if (insn32) 19026 buf = write_compressed_insn (buf, 0x00000000, 4); 19027 else 19028 buf = write_compressed_insn (buf, 0x0c00, 2); 19029 } 19030 } 19031 else 19032 { 19033 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); 19034 19035 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ 19036 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; 19037 insn |= at << MICROMIPSOP_SH_RT; 19038 19039 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 19040 fragp->fr_symbol, fragp->fr_offset, 19041 FALSE, BFD_RELOC_MICROMIPS_GOT16); 19042 fixp->fx_file = fragp->fr_file; 19043 fixp->fx_line = fragp->fr_line; 19044 19045 buf = write_compressed_insn (buf, insn, 4); 19046 19047 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ 19048 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; 19049 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; 19050 19051 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 19052 fragp->fr_symbol, fragp->fr_offset, 19053 FALSE, BFD_RELOC_MICROMIPS_LO16); 19054 fixp->fx_file = fragp->fr_file; 19055 fixp->fx_line = fragp->fr_line; 19056 19057 buf = write_compressed_insn (buf, insn, 4); 19058 19059 if (insn32) 19060 { 19061 /* jr/jalr $at */ 19062 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; 19063 insn |= at << MICROMIPSOP_SH_RS; 19064 19065 buf = write_compressed_insn (buf, insn, 4); 19066 19067 if (compact || nods) 19068 /* nop */ 19069 buf = write_compressed_insn (buf, 0x00000000, 4); 19070 } 19071 else 19072 { 19073 /* jr/jrc/jalr/jalrs $at */ 19074 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ 19075 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ 19076 19077 insn = al ? jalr : jr; 19078 insn |= at << MICROMIPSOP_SH_MJ; 19079 19080 buf = write_compressed_insn (buf, insn, 2); 19081 if (al && nods) 19082 { 19083 /* nop */ 19084 if (short_ds) 19085 buf = write_compressed_insn (buf, 0x0c00, 2); 19086 else 19087 buf = write_compressed_insn (buf, 0x00000000, 4); 19088 } 19089 } 19090 } 19091 19092 gas_assert (buf == fragp->fr_literal + fragp->fr_fix); 19093 return; 19094 } 19095 19096 if (RELAX_MIPS16_P (fragp->fr_subtype)) 19097 { 19098 int type; 19099 const struct mips_int_operand *operand; 19100 offsetT val; 19101 char *buf; 19102 unsigned int user_length; 19103 bfd_boolean need_reloc; 19104 unsigned long insn; 19105 bfd_boolean mac; 19106 bfd_boolean ext; 19107 segT symsec; 19108 19109 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 19110 operand = mips16_immed_operand (type, FALSE); 19111 19112 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); 19113 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); 19114 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; 19115 19116 symsec = S_GET_SEGMENT (fragp->fr_symbol); 19117 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) 19118 || (operand->root.type == OP_PCREL && !mac 19119 ? asec != symsec 19120 : !bfd_is_abs_section (symsec))); 19121 19122 if (operand->root.type == OP_PCREL && !mac) 19123 { 19124 const struct mips_pcrel_operand *pcrel_op; 19125 19126 pcrel_op = (const struct mips_pcrel_operand *) operand; 19127 19128 if (pcrel_op->include_isa_bit && !need_reloc) 19129 { 19130 if (!mips_ignore_branch_isa 19131 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) 19132 as_bad_where (fragp->fr_file, fragp->fr_line, 19133 _("branch to a symbol in another ISA mode")); 19134 else if ((fragp->fr_offset & 0x1) != 0) 19135 as_bad_where (fragp->fr_file, fragp->fr_line, 19136 _("branch to misaligned address (0x%lx)"), 19137 (long) (resolve_symbol_value (fragp->fr_symbol) 19138 + (fragp->fr_offset & ~1))); 19139 } 19140 19141 val = mips16_pcrel_val (fragp, pcrel_op, val, 0); 19142 19143 /* Make sure the section winds up with the alignment we have 19144 assumed. */ 19145 if (operand->shift > 0) 19146 record_alignment (asec, operand->shift); 19147 } 19148 19149 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 19150 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 19151 { 19152 if (mac) 19153 as_warn_where (fragp->fr_file, fragp->fr_line, 19154 _("macro instruction expanded into multiple " 19155 "instructions in a branch delay slot")); 19156 else if (ext) 19157 as_warn_where (fragp->fr_file, fragp->fr_line, 19158 _("extended instruction in a branch delay slot")); 19159 } 19160 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) 19161 as_warn_where (fragp->fr_file, fragp->fr_line, 19162 _("macro instruction expanded into multiple " 19163 "instructions")); 19164 19165 buf = fragp->fr_literal + fragp->fr_fix; 19166 19167 insn = read_compressed_insn (buf, 2); 19168 if (ext) 19169 insn |= MIPS16_EXTEND; 19170 19171 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 19172 user_length = 4; 19173 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 19174 user_length = 2; 19175 else 19176 user_length = 0; 19177 19178 if (mac) 19179 { 19180 unsigned long reg; 19181 unsigned long new; 19182 unsigned long op; 19183 bfd_boolean e2; 19184 19185 gas_assert (type == 'A' || type == 'B' || type == 'E'); 19186 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); 19187 19188 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); 19189 19190 if (need_reloc) 19191 { 19192 fixS *fixp; 19193 19194 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); 19195 19196 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 19197 fragp->fr_symbol, fragp->fr_offset, 19198 FALSE, BFD_RELOC_MIPS16_HI16_S); 19199 fixp->fx_file = fragp->fr_file; 19200 fixp->fx_line = fragp->fr_line; 19201 19202 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, 19203 fragp->fr_symbol, fragp->fr_offset, 19204 FALSE, BFD_RELOC_MIPS16_LO16); 19205 fixp->fx_file = fragp->fr_file; 19206 fixp->fx_line = fragp->fr_line; 19207 19208 val = 0; 19209 } 19210 19211 switch (insn & 0xf800) 19212 { 19213 case 0x0800: /* ADDIU */ 19214 reg = (insn >> 8) & 0x7; 19215 op = 0xf0004800 | (reg << 8); 19216 break; 19217 case 0xb000: /* LW */ 19218 reg = (insn >> 8) & 0x7; 19219 op = 0xf0009800 | (reg << 8) | (reg << 5); 19220 break; 19221 case 0xf800: /* I64 */ 19222 reg = (insn >> 5) & 0x7; 19223 switch (insn & 0x0700) 19224 { 19225 case 0x0400: /* LD */ 19226 op = 0xf0003800 | (reg << 8) | (reg << 5); 19227 break; 19228 case 0x0600: /* DADDIU */ 19229 op = 0xf000fd00 | (reg << 5); 19230 break; 19231 default: 19232 abort (); 19233 } 19234 break; 19235 default: 19236 abort (); 19237 } 19238 19239 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ 19240 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); 19241 buf = write_compressed_insn (buf, new, 4); 19242 if (!e2) 19243 { 19244 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ 19245 buf = write_compressed_insn (buf, new, 4); 19246 } 19247 op |= mips16_immed_extend (val, 16); 19248 buf = write_compressed_insn (buf, op, 4); 19249 19250 fragp->fr_fix += e2 ? 8 : 12; 19251 } 19252 else 19253 { 19254 unsigned int length = ext ? 4 : 2; 19255 19256 if (need_reloc) 19257 { 19258 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; 19259 fixS *fixp; 19260 19261 switch (type) 19262 { 19263 case 'p': 19264 case 'q': 19265 reloc = BFD_RELOC_MIPS16_16_PCREL_S1; 19266 break; 19267 default: 19268 break; 19269 } 19270 if (mac || reloc == BFD_RELOC_NONE) 19271 as_bad_where (fragp->fr_file, fragp->fr_line, 19272 _("unsupported relocation")); 19273 else if (ext) 19274 { 19275 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, 19276 fragp->fr_symbol, fragp->fr_offset, 19277 TRUE, reloc); 19278 fixp->fx_file = fragp->fr_file; 19279 fixp->fx_line = fragp->fr_line; 19280 } 19281 else 19282 as_bad_where (fragp->fr_file, fragp->fr_line, 19283 _("invalid unextended operand value")); 19284 } 19285 else 19286 mips16_immed (fragp->fr_file, fragp->fr_line, type, 19287 BFD_RELOC_UNUSED, val, user_length, &insn); 19288 19289 gas_assert (mips16_opcode_length (insn) == length); 19290 write_compressed_insn (buf, insn, length); 19291 fragp->fr_fix += length; 19292 } 19293 } 19294 else 19295 { 19296 relax_substateT subtype = fragp->fr_subtype; 19297 bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; 19298 bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; 19299 unsigned int first, second; 19300 fixS *fixp; 19301 19302 first = RELAX_FIRST (subtype); 19303 second = RELAX_SECOND (subtype); 19304 fixp = (fixS *) fragp->fr_opcode; 19305 19306 /* If the delay slot chosen does not match the size of the instruction, 19307 then emit a warning. */ 19308 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) 19309 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) 19310 { 19311 relax_substateT s; 19312 const char *msg; 19313 19314 s = subtype & (RELAX_DELAY_SLOT_16BIT 19315 | RELAX_DELAY_SLOT_SIZE_FIRST 19316 | RELAX_DELAY_SLOT_SIZE_SECOND); 19317 msg = macro_warning (s); 19318 if (msg != NULL) 19319 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 19320 subtype &= ~s; 19321 } 19322 19323 /* Possibly emit a warning if we've chosen the longer option. */ 19324 if (use_second == second_longer) 19325 { 19326 relax_substateT s; 19327 const char *msg; 19328 19329 s = (subtype 19330 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); 19331 msg = macro_warning (s); 19332 if (msg != NULL) 19333 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); 19334 subtype &= ~s; 19335 } 19336 19337 /* Go through all the fixups for the first sequence. Disable them 19338 (by marking them as done) if we're going to use the second 19339 sequence instead. */ 19340 while (fixp 19341 && fixp->fx_frag == fragp 19342 && fixp->fx_where + second < fragp->fr_fix) 19343 { 19344 if (subtype & RELAX_USE_SECOND) 19345 fixp->fx_done = 1; 19346 fixp = fixp->fx_next; 19347 } 19348 19349 /* Go through the fixups for the second sequence. Disable them if 19350 we're going to use the first sequence, otherwise adjust their 19351 addresses to account for the relaxation. */ 19352 while (fixp && fixp->fx_frag == fragp) 19353 { 19354 if (subtype & RELAX_USE_SECOND) 19355 fixp->fx_where -= first; 19356 else 19357 fixp->fx_done = 1; 19358 fixp = fixp->fx_next; 19359 } 19360 19361 /* Now modify the frag contents. */ 19362 if (subtype & RELAX_USE_SECOND) 19363 { 19364 char *start; 19365 19366 start = fragp->fr_literal + fragp->fr_fix - first - second; 19367 memmove (start, start + first, second); 19368 fragp->fr_fix -= first; 19369 } 19370 else 19371 fragp->fr_fix -= second; 19372 } 19373} 19374 19375/* This function is called after the relocs have been generated. 19376 We've been storing mips16 text labels as odd. Here we convert them 19377 back to even for the convenience of the debugger. */ 19378 19379void 19380mips_frob_file_after_relocs (void) 19381{ 19382 asymbol **syms; 19383 unsigned int count, i; 19384 19385 syms = bfd_get_outsymbols (stdoutput); 19386 count = bfd_get_symcount (stdoutput); 19387 for (i = 0; i < count; i++, syms++) 19388 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) 19389 && ((*syms)->value & 1) != 0) 19390 { 19391 (*syms)->value &= ~1; 19392 /* If the symbol has an odd size, it was probably computed 19393 incorrectly, so adjust that as well. */ 19394 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 19395 ++elf_symbol (*syms)->internal_elf_sym.st_size; 19396 } 19397} 19398 19399/* This function is called whenever a label is defined, including fake 19400 labels instantiated off the dot special symbol. It is used when 19401 handling branch delays; if a branch has a label, we assume we cannot 19402 move it. This also bumps the value of the symbol by 1 in compressed 19403 code. */ 19404 19405static void 19406mips_record_label (symbolS *sym) 19407{ 19408 segment_info_type *si = seg_info (now_seg); 19409 struct insn_label_list *l; 19410 19411 if (free_insn_labels == NULL) 19412 l = XNEW (struct insn_label_list); 19413 else 19414 { 19415 l = free_insn_labels; 19416 free_insn_labels = l->next; 19417 } 19418 19419 l->label = sym; 19420 l->next = si->label_list; 19421 si->label_list = l; 19422} 19423 19424/* This function is called as tc_frob_label() whenever a label is defined 19425 and adds a DWARF-2 record we only want for true labels. */ 19426 19427void 19428mips_define_label (symbolS *sym) 19429{ 19430 mips_record_label (sym); 19431 dwarf2_emit_label (sym); 19432} 19433 19434/* This function is called by tc_new_dot_label whenever a new dot symbol 19435 is defined. */ 19436 19437void 19438mips_add_dot_label (symbolS *sym) 19439{ 19440 mips_record_label (sym); 19441 if (mips_assembling_insn && HAVE_CODE_COMPRESSION) 19442 mips_compressed_mark_label (sym); 19443} 19444 19445/* Converting ASE flags from internal to .MIPS.abiflags values. */ 19446static unsigned int 19447mips_convert_ase_flags (int ase) 19448{ 19449 unsigned int ext_ases = 0; 19450 19451 if (ase & ASE_DSP) 19452 ext_ases |= AFL_ASE_DSP; 19453 if (ase & ASE_DSPR2) 19454 ext_ases |= AFL_ASE_DSPR2; 19455 if (ase & ASE_DSPR3) 19456 ext_ases |= AFL_ASE_DSPR3; 19457 if (ase & ASE_EVA) 19458 ext_ases |= AFL_ASE_EVA; 19459 if (ase & ASE_MCU) 19460 ext_ases |= AFL_ASE_MCU; 19461 if (ase & ASE_MDMX) 19462 ext_ases |= AFL_ASE_MDMX; 19463 if (ase & ASE_MIPS3D) 19464 ext_ases |= AFL_ASE_MIPS3D; 19465 if (ase & ASE_MT) 19466 ext_ases |= AFL_ASE_MT; 19467 if (ase & ASE_SMARTMIPS) 19468 ext_ases |= AFL_ASE_SMARTMIPS; 19469 if (ase & ASE_VIRT) 19470 ext_ases |= AFL_ASE_VIRT; 19471 if (ase & ASE_MSA) 19472 ext_ases |= AFL_ASE_MSA; 19473 if (ase & ASE_XPA) 19474 ext_ases |= AFL_ASE_XPA; 19475 if (ase & ASE_MIPS16E2) 19476 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; 19477 if (ase & ASE_CRC) 19478 ext_ases |= AFL_ASE_CRC; 19479 if (ase & ASE_GINV) 19480 ext_ases |= AFL_ASE_GINV; 19481 if (ase & ASE_LOONGSON_MMI) 19482 ext_ases |= AFL_ASE_LOONGSON_MMI; 19483 if (ase & ASE_LOONGSON_CAM) 19484 ext_ases |= AFL_ASE_LOONGSON_CAM; 19485 if (ase & ASE_LOONGSON_EXT) 19486 ext_ases |= AFL_ASE_LOONGSON_EXT; 19487 if (ase & ASE_LOONGSON_EXT2) 19488 ext_ases |= AFL_ASE_LOONGSON_EXT2; 19489 19490 return ext_ases; 19491} 19492/* Some special processing for a MIPS ELF file. */ 19493 19494void 19495mips_elf_final_processing (void) 19496{ 19497 int fpabi; 19498 Elf_Internal_ABIFlags_v0 flags; 19499 19500 flags.version = 0; 19501 flags.isa_rev = 0; 19502 switch (file_mips_opts.isa) 19503 { 19504 case INSN_ISA1: 19505 flags.isa_level = 1; 19506 break; 19507 case INSN_ISA2: 19508 flags.isa_level = 2; 19509 break; 19510 case INSN_ISA3: 19511 flags.isa_level = 3; 19512 break; 19513 case INSN_ISA4: 19514 flags.isa_level = 4; 19515 break; 19516 case INSN_ISA5: 19517 flags.isa_level = 5; 19518 break; 19519 case INSN_ISA32: 19520 flags.isa_level = 32; 19521 flags.isa_rev = 1; 19522 break; 19523 case INSN_ISA32R2: 19524 flags.isa_level = 32; 19525 flags.isa_rev = 2; 19526 break; 19527 case INSN_ISA32R3: 19528 flags.isa_level = 32; 19529 flags.isa_rev = 3; 19530 break; 19531 case INSN_ISA32R5: 19532 flags.isa_level = 32; 19533 flags.isa_rev = 5; 19534 break; 19535 case INSN_ISA32R6: 19536 flags.isa_level = 32; 19537 flags.isa_rev = 6; 19538 break; 19539 case INSN_ISA64: 19540 flags.isa_level = 64; 19541 flags.isa_rev = 1; 19542 break; 19543 case INSN_ISA64R2: 19544 flags.isa_level = 64; 19545 flags.isa_rev = 2; 19546 break; 19547 case INSN_ISA64R3: 19548 flags.isa_level = 64; 19549 flags.isa_rev = 3; 19550 break; 19551 case INSN_ISA64R5: 19552 flags.isa_level = 64; 19553 flags.isa_rev = 5; 19554 break; 19555 case INSN_ISA64R6: 19556 flags.isa_level = 64; 19557 flags.isa_rev = 6; 19558 break; 19559 } 19560 19561 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; 19562 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE 19563 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 19564 : (file_mips_opts.fp == 64) ? AFL_REG_64 19565 : AFL_REG_32; 19566 flags.cpr2_size = AFL_REG_NONE; 19567 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19568 Tag_GNU_MIPS_ABI_FP); 19569 flags.isa_ext = bfd_mips_isa_ext (stdoutput); 19570 flags.ases = mips_convert_ase_flags (file_mips_opts.ase); 19571 if (file_ase_mips16) 19572 flags.ases |= AFL_ASE_MIPS16; 19573 if (file_ase_micromips) 19574 flags.ases |= AFL_ASE_MICROMIPS; 19575 flags.flags1 = 0; 19576 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) 19577 || file_mips_opts.fp == 64) 19578 && file_mips_opts.oddspreg) 19579 flags.flags1 |= AFL_FLAGS1_ODDSPREG; 19580 flags.flags2 = 0; 19581 19582 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, 19583 ((Elf_External_ABIFlags_v0 *) 19584 mips_flags_frag)); 19585 19586 /* Write out the register information. */ 19587 if (mips_abi != N64_ABI) 19588 { 19589 Elf32_RegInfo s; 19590 19591 s.ri_gprmask = mips_gprmask; 19592 s.ri_cprmask[0] = mips_cprmask[0]; 19593 s.ri_cprmask[1] = mips_cprmask[1]; 19594 s.ri_cprmask[2] = mips_cprmask[2]; 19595 s.ri_cprmask[3] = mips_cprmask[3]; 19596 /* The gp_value field is set by the MIPS ELF backend. */ 19597 19598 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 19599 ((Elf32_External_RegInfo *) 19600 mips_regmask_frag)); 19601 } 19602 else 19603 { 19604 Elf64_Internal_RegInfo s; 19605 19606 s.ri_gprmask = mips_gprmask; 19607 s.ri_pad = 0; 19608 s.ri_cprmask[0] = mips_cprmask[0]; 19609 s.ri_cprmask[1] = mips_cprmask[1]; 19610 s.ri_cprmask[2] = mips_cprmask[2]; 19611 s.ri_cprmask[3] = mips_cprmask[3]; 19612 /* The gp_value field is set by the MIPS ELF backend. */ 19613 19614 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 19615 ((Elf64_External_RegInfo *) 19616 mips_regmask_frag)); 19617 } 19618 19619 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 19620 sort of BFD interface for this. */ 19621 if (mips_any_noreorder) 19622 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 19623 if (mips_pic != NO_PIC) 19624 { 19625 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 19626 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 19627 } 19628 if (mips_abicalls) 19629 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 19630 19631 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags 19632 defined at present; this might need to change in future. */ 19633 if (file_ase_mips16) 19634 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 19635 if (file_ase_micromips) 19636 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; 19637 if (file_mips_opts.ase & ASE_MDMX) 19638 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 19639 19640 /* Set the MIPS ELF ABI flags. */ 19641 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 19642 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 19643 else if (mips_abi == O64_ABI) 19644 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 19645 else if (mips_abi == EABI_ABI) 19646 { 19647 if (file_mips_opts.gp == 64) 19648 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 19649 else 19650 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 19651 } 19652 19653 /* Nothing to do for N32_ABI or N64_ABI. */ 19654 19655 if (mips_32bitmode) 19656 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 19657 19658 if (mips_nan2008 == 1) 19659 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; 19660 19661 /* 32 bit code with 64 bit FP registers. */ 19662 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 19663 Tag_GNU_MIPS_ABI_FP); 19664 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) 19665 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; 19666} 19667 19668typedef struct proc { 19669 symbolS *func_sym; 19670 symbolS *func_end_sym; 19671 unsigned long reg_mask; 19672 unsigned long reg_offset; 19673 unsigned long fpreg_mask; 19674 unsigned long fpreg_offset; 19675 unsigned long frame_offset; 19676 unsigned long frame_reg; 19677 unsigned long pc_reg; 19678} procS; 19679 19680static procS cur_proc; 19681static procS *cur_proc_ptr; 19682static int numprocs; 19683 19684/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop 19685 as "2", and a normal nop as "0". */ 19686 19687#define NOP_OPCODE_MIPS 0 19688#define NOP_OPCODE_MIPS16 1 19689#define NOP_OPCODE_MICROMIPS 2 19690 19691char 19692mips_nop_opcode (void) 19693{ 19694 if (seg_info (now_seg)->tc_segment_info_data.micromips) 19695 return NOP_OPCODE_MICROMIPS; 19696 else if (seg_info (now_seg)->tc_segment_info_data.mips16) 19697 return NOP_OPCODE_MIPS16; 19698 else 19699 return NOP_OPCODE_MIPS; 19700} 19701 19702/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use 19703 32-bit microMIPS NOPs here (if applicable). */ 19704 19705void 19706mips_handle_align (fragS *fragp) 19707{ 19708 char nop_opcode; 19709 char *p; 19710 int bytes, size, excess; 19711 valueT opcode; 19712 19713 if (fragp->fr_type != rs_align_code) 19714 return; 19715 19716 p = fragp->fr_literal + fragp->fr_fix; 19717 nop_opcode = *p; 19718 switch (nop_opcode) 19719 { 19720 case NOP_OPCODE_MICROMIPS: 19721 opcode = micromips_nop32_insn.insn_opcode; 19722 size = 4; 19723 break; 19724 case NOP_OPCODE_MIPS16: 19725 opcode = mips16_nop_insn.insn_opcode; 19726 size = 2; 19727 break; 19728 case NOP_OPCODE_MIPS: 19729 default: 19730 opcode = nop_insn.insn_opcode; 19731 size = 4; 19732 break; 19733 } 19734 19735 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 19736 excess = bytes % size; 19737 19738 /* Handle the leading part if we're not inserting a whole number of 19739 instructions, and make it the end of the fixed part of the frag. 19740 Try to fit in a short microMIPS NOP if applicable and possible, 19741 and use zeroes otherwise. */ 19742 gas_assert (excess < 4); 19743 fragp->fr_fix += excess; 19744 switch (excess) 19745 { 19746 case 3: 19747 *p++ = '\0'; 19748 /* Fall through. */ 19749 case 2: 19750 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) 19751 { 19752 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); 19753 break; 19754 } 19755 *p++ = '\0'; 19756 /* Fall through. */ 19757 case 1: 19758 *p++ = '\0'; 19759 /* Fall through. */ 19760 case 0: 19761 break; 19762 } 19763 19764 md_number_to_chars (p, opcode, size); 19765 fragp->fr_var = size; 19766} 19767 19768static long 19769get_number (void) 19770{ 19771 int negative = 0; 19772 long val = 0; 19773 19774 if (*input_line_pointer == '-') 19775 { 19776 ++input_line_pointer; 19777 negative = 1; 19778 } 19779 if (!ISDIGIT (*input_line_pointer)) 19780 as_bad (_("expected simple number")); 19781 if (input_line_pointer[0] == '0') 19782 { 19783 if (input_line_pointer[1] == 'x') 19784 { 19785 input_line_pointer += 2; 19786 while (ISXDIGIT (*input_line_pointer)) 19787 { 19788 val <<= 4; 19789 val |= hex_value (*input_line_pointer++); 19790 } 19791 return negative ? -val : val; 19792 } 19793 else 19794 { 19795 ++input_line_pointer; 19796 while (ISDIGIT (*input_line_pointer)) 19797 { 19798 val <<= 3; 19799 val |= *input_line_pointer++ - '0'; 19800 } 19801 return negative ? -val : val; 19802 } 19803 } 19804 if (!ISDIGIT (*input_line_pointer)) 19805 { 19806 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 19807 *input_line_pointer, *input_line_pointer); 19808 as_warn (_("invalid number")); 19809 return -1; 19810 } 19811 while (ISDIGIT (*input_line_pointer)) 19812 { 19813 val *= 10; 19814 val += *input_line_pointer++ - '0'; 19815 } 19816 return negative ? -val : val; 19817} 19818 19819/* The .file directive; just like the usual .file directive, but there 19820 is an initial number which is the ECOFF file index. In the non-ECOFF 19821 case .file implies DWARF-2. */ 19822 19823static void 19824s_mips_file (int x ATTRIBUTE_UNUSED) 19825{ 19826 static int first_file_directive = 0; 19827 19828 if (ECOFF_DEBUGGING) 19829 { 19830 get_number (); 19831 s_app_file (0); 19832 } 19833 else 19834 { 19835 char *filename; 19836 19837 filename = dwarf2_directive_filename (); 19838 19839 /* Versions of GCC up to 3.1 start files with a ".file" 19840 directive even for stabs output. Make sure that this 19841 ".file" is handled. Note that you need a version of GCC 19842 after 3.1 in order to support DWARF-2 on MIPS. */ 19843 if (filename != NULL && ! first_file_directive) 19844 { 19845 (void) new_logical_line (filename, -1); 19846 s_app_file_string (filename, 0); 19847 } 19848 first_file_directive = 1; 19849 } 19850} 19851 19852/* The .loc directive, implying DWARF-2. */ 19853 19854static void 19855s_mips_loc (int x ATTRIBUTE_UNUSED) 19856{ 19857 if (!ECOFF_DEBUGGING) 19858 dwarf2_directive_loc (0); 19859} 19860 19861/* The .end directive. */ 19862 19863static void 19864s_mips_end (int x ATTRIBUTE_UNUSED) 19865{ 19866 symbolS *p; 19867 19868 /* Following functions need their own .frame and .cprestore directives. */ 19869 mips_frame_reg_valid = 0; 19870 mips_cprestore_valid = 0; 19871 19872 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 19873 { 19874 p = get_symbol (); 19875 demand_empty_rest_of_line (); 19876 } 19877 else 19878 p = NULL; 19879 19880 if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) 19881 as_warn (_(".end not in text section")); 19882 19883 if (!cur_proc_ptr) 19884 { 19885 as_warn (_(".end directive without a preceding .ent directive")); 19886 demand_empty_rest_of_line (); 19887 return; 19888 } 19889 19890 if (p != NULL) 19891 { 19892 gas_assert (S_GET_NAME (p)); 19893 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) 19894 as_warn (_(".end symbol does not match .ent symbol")); 19895 19896 if (debug_type == DEBUG_STABS) 19897 stabs_generate_asm_endfunc (S_GET_NAME (p), 19898 S_GET_NAME (p)); 19899 } 19900 else 19901 as_warn (_(".end directive missing or unknown symbol")); 19902 19903 /* Create an expression to calculate the size of the function. */ 19904 if (p && cur_proc_ptr) 19905 { 19906 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); 19907 expressionS *exp = XNEW (expressionS); 19908 19909 obj->size = exp; 19910 exp->X_op = O_subtract; 19911 exp->X_add_symbol = symbol_temp_new_now (); 19912 exp->X_op_symbol = p; 19913 exp->X_add_number = 0; 19914 19915 cur_proc_ptr->func_end_sym = exp->X_add_symbol; 19916 } 19917 19918#ifdef md_flush_pending_output 19919 md_flush_pending_output (); 19920#endif 19921 19922 /* Generate a .pdr section. */ 19923 if (!ECOFF_DEBUGGING && mips_flag_pdr) 19924 { 19925 segT saved_seg = now_seg; 19926 subsegT saved_subseg = now_subseg; 19927 expressionS exp; 19928 char *fragp; 19929 19930 gas_assert (pdr_seg); 19931 subseg_set (pdr_seg, 0); 19932 19933 /* Write the symbol. */ 19934 exp.X_op = O_symbol; 19935 exp.X_add_symbol = p; 19936 exp.X_add_number = 0; 19937 emit_expr (&exp, 4); 19938 19939 fragp = frag_more (7 * 4); 19940 19941 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 19942 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 19943 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 19944 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 19945 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 19946 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 19947 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 19948 19949 subseg_set (saved_seg, saved_subseg); 19950 } 19951 19952 cur_proc_ptr = NULL; 19953} 19954 19955/* The .aent and .ent directives. */ 19956 19957static void 19958s_mips_ent (int aent) 19959{ 19960 symbolS *symbolP; 19961 19962 symbolP = get_symbol (); 19963 if (*input_line_pointer == ',') 19964 ++input_line_pointer; 19965 SKIP_WHITESPACE (); 19966 if (ISDIGIT (*input_line_pointer) 19967 || *input_line_pointer == '-') 19968 get_number (); 19969 19970 if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) 19971 as_warn (_(".ent or .aent not in text section")); 19972 19973 if (!aent && cur_proc_ptr) 19974 as_warn (_("missing .end")); 19975 19976 if (!aent) 19977 { 19978 /* This function needs its own .frame and .cprestore directives. */ 19979 mips_frame_reg_valid = 0; 19980 mips_cprestore_valid = 0; 19981 19982 cur_proc_ptr = &cur_proc; 19983 memset (cur_proc_ptr, '\0', sizeof (procS)); 19984 19985 cur_proc_ptr->func_sym = symbolP; 19986 19987 ++numprocs; 19988 19989 if (debug_type == DEBUG_STABS) 19990 stabs_generate_asm_func (S_GET_NAME (symbolP), 19991 S_GET_NAME (symbolP)); 19992 } 19993 19994 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 19995 19996 demand_empty_rest_of_line (); 19997} 19998 19999/* The .frame directive. If the mdebug section is present (IRIX 5 native) 20000 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 20001 s_mips_frame is used so that we can set the PDR information correctly. 20002 We can't use the ecoff routines because they make reference to the ecoff 20003 symbol table (in the mdebug section). */ 20004 20005static void 20006s_mips_frame (int ignore ATTRIBUTE_UNUSED) 20007{ 20008 if (ECOFF_DEBUGGING) 20009 s_ignore (ignore); 20010 else 20011 { 20012 long val; 20013 20014 if (cur_proc_ptr == (procS *) NULL) 20015 { 20016 as_warn (_(".frame outside of .ent")); 20017 demand_empty_rest_of_line (); 20018 return; 20019 } 20020 20021 cur_proc_ptr->frame_reg = tc_get_register (1); 20022 20023 SKIP_WHITESPACE (); 20024 if (*input_line_pointer++ != ',' 20025 || get_absolute_expression_and_terminator (&val) != ',') 20026 { 20027 as_warn (_("bad .frame directive")); 20028 --input_line_pointer; 20029 demand_empty_rest_of_line (); 20030 return; 20031 } 20032 20033 cur_proc_ptr->frame_offset = val; 20034 cur_proc_ptr->pc_reg = tc_get_register (0); 20035 20036 demand_empty_rest_of_line (); 20037 } 20038} 20039 20040/* The .fmask and .mask directives. If the mdebug section is present 20041 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 20042 embedded targets, s_mips_mask is used so that we can set the PDR 20043 information correctly. We can't use the ecoff routines because they 20044 make reference to the ecoff symbol table (in the mdebug section). */ 20045 20046static void 20047s_mips_mask (int reg_type) 20048{ 20049 if (ECOFF_DEBUGGING) 20050 s_ignore (reg_type); 20051 else 20052 { 20053 long mask, off; 20054 20055 if (cur_proc_ptr == (procS *) NULL) 20056 { 20057 as_warn (_(".mask/.fmask outside of .ent")); 20058 demand_empty_rest_of_line (); 20059 return; 20060 } 20061 20062 if (get_absolute_expression_and_terminator (&mask) != ',') 20063 { 20064 as_warn (_("bad .mask/.fmask directive")); 20065 --input_line_pointer; 20066 demand_empty_rest_of_line (); 20067 return; 20068 } 20069 20070 off = get_absolute_expression (); 20071 20072 if (reg_type == 'F') 20073 { 20074 cur_proc_ptr->fpreg_mask = mask; 20075 cur_proc_ptr->fpreg_offset = off; 20076 } 20077 else 20078 { 20079 cur_proc_ptr->reg_mask = mask; 20080 cur_proc_ptr->reg_offset = off; 20081 } 20082 20083 demand_empty_rest_of_line (); 20084 } 20085} 20086 20087/* A table describing all the processors gas knows about. Names are 20088 matched in the order listed. 20089 20090 To ease comparison, please keep this table in the same order as 20091 gcc's mips_cpu_info_table[]. */ 20092static const struct mips_cpu_info mips_cpu_info_table[] = 20093{ 20094 /* Entries for generic ISAs. */ 20095 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, 20096 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, 20097 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, 20098 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, 20099 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, 20100 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, 20101 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20102 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, 20103 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, 20104 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, 20105 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, 20106 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, 20107 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, 20108 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, 20109 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, 20110 20111 /* MIPS I */ 20112 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, 20113 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, 20114 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, 20115 20116 /* MIPS II */ 20117 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, 20118 20119 /* MIPS III */ 20120 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, 20121 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, 20122 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, 20123 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, 20124 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, 20125 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, 20126 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, 20127 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, 20128 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, 20129 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, 20130 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, 20131 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, 20132 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, 20133 /* ST Microelectronics Loongson 2E and 2F cores. */ 20134 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, 20135 { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, 20136 20137 /* MIPS IV */ 20138 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, 20139 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, 20140 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, 20141 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, 20142 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, 20143 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, 20144 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, 20145 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, 20146 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, 20147 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, 20148 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, 20149 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, 20150 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, 20151 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, 20152 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, 20153 20154 /* MIPS 32 */ 20155 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 20156 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 20157 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, 20158 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, 20159 20160 /* MIPS 32 Release 2 */ 20161 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20162 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20163 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20164 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, 20165 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20166 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20167 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 20168 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, 20169 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 20170 ISA_MIPS32R2, CPU_MIPS32R2 }, 20171 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, 20172 ISA_MIPS32R2, CPU_MIPS32R2 }, 20173 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20174 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20175 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20176 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20177 /* Deprecated forms of the above. */ 20178 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20179 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, 20180 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ 20181 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20182 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20183 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20184 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20185 /* Deprecated forms of the above. */ 20186 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20187 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, 20188 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ 20189 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20190 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20191 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20192 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20193 /* Deprecated forms of the above. */ 20194 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20195 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20196 /* 34Kn is a 34kc without DSP. */ 20197 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20198 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ 20199 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20200 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20201 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20202 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20203 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20204 /* Deprecated forms of the above. */ 20205 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20206 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, 20207 /* 1004K cores are multiprocessor versions of the 34K. */ 20208 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20209 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20210 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20211 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20212 /* interaptiv is the new name for 1004kf. */ 20213 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, 20214 { "interaptiv-mr2", 0, 20215 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, 20216 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, 20217 /* M5100 family. */ 20218 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 20219 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, 20220 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ 20221 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, 20222 20223 /* MIPS 64 */ 20224 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 20225 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, 20226 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 20227 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, 20228 20229 /* Broadcom SB-1 CPU core. */ 20230 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 20231 /* Broadcom SB-1A CPU core. */ 20232 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, 20233 20234 /* MIPS 64 Release 2. */ 20235 /* Loongson CPU core. */ 20236 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */ 20237 { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, 20238 ISA_MIPS64R2, CPU_GS464 }, 20239 { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, 20240 ISA_MIPS64R2, CPU_GS464 }, 20241 { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT 20242 | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, 20243 { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT 20244 | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, 20245 20246 /* Cavium Networks Octeon CPU core. */ 20247 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, 20248 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, 20249 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, 20250 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, 20251 20252 /* RMI Xlr */ 20253 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, 20254 20255 /* Broadcom XLP. 20256 XLP is mostly like XLR, with the prominent exception that it is 20257 MIPS64R2 rather than MIPS64. */ 20258 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, 20259 20260 /* MIPS 64 Release 6. */ 20261 { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 20262 { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV, 20263 ISA_MIPS64R6, CPU_MIPS64R6}, 20264 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 20265 20266 /* End marker. */ 20267 { NULL, 0, 0, 0, 0 } 20268}; 20269 20270 20271/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 20272 with a final "000" replaced by "k". Ignore case. 20273 20274 Note: this function is shared between GCC and GAS. */ 20275 20276static bfd_boolean 20277mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 20278{ 20279 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 20280 given++, canonical++; 20281 20282 return ((*given == 0 && *canonical == 0) 20283 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 20284} 20285 20286 20287/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 20288 CPU name. We've traditionally allowed a lot of variation here. 20289 20290 Note: this function is shared between GCC and GAS. */ 20291 20292static bfd_boolean 20293mips_matching_cpu_name_p (const char *canonical, const char *given) 20294{ 20295 /* First see if the name matches exactly, or with a final "000" 20296 turned into "k". */ 20297 if (mips_strict_matching_cpu_name_p (canonical, given)) 20298 return TRUE; 20299 20300 /* If not, try comparing based on numerical designation alone. 20301 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 20302 if (TOLOWER (*given) == 'r') 20303 given++; 20304 if (!ISDIGIT (*given)) 20305 return FALSE; 20306 20307 /* Skip over some well-known prefixes in the canonical name, 20308 hoping to find a number there too. */ 20309 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 20310 canonical += 2; 20311 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 20312 canonical += 2; 20313 else if (TOLOWER (canonical[0]) == 'r') 20314 canonical += 1; 20315 20316 return mips_strict_matching_cpu_name_p (canonical, given); 20317} 20318 20319 20320/* Parse an option that takes the name of a processor as its argument. 20321 OPTION is the name of the option and CPU_STRING is the argument. 20322 Return the corresponding processor enumeration if the CPU_STRING is 20323 recognized, otherwise report an error and return null. 20324 20325 A similar function exists in GCC. */ 20326 20327static const struct mips_cpu_info * 20328mips_parse_cpu (const char *option, const char *cpu_string) 20329{ 20330 const struct mips_cpu_info *p; 20331 20332 /* 'from-abi' selects the most compatible architecture for the given 20333 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 20334 EABIs, we have to decide whether we're using the 32-bit or 64-bit 20335 version. Look first at the -mgp options, if given, otherwise base 20336 the choice on MIPS_DEFAULT_64BIT. 20337 20338 Treat NO_ABI like the EABIs. One reason to do this is that the 20339 plain 'mips' and 'mips64' configs have 'from-abi' as their default 20340 architecture. This code picks MIPS I for 'mips' and MIPS III for 20341 'mips64', just as we did in the days before 'from-abi'. */ 20342 if (strcasecmp (cpu_string, "from-abi") == 0) 20343 { 20344 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 20345 return mips_cpu_info_from_isa (ISA_MIPS1); 20346 20347 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 20348 return mips_cpu_info_from_isa (ISA_MIPS3); 20349 20350 if (file_mips_opts.gp >= 0) 20351 return mips_cpu_info_from_isa (file_mips_opts.gp == 32 20352 ? ISA_MIPS1 : ISA_MIPS3); 20353 20354 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 20355 ? ISA_MIPS3 20356 : ISA_MIPS1); 20357 } 20358 20359 /* 'default' has traditionally been a no-op. Probably not very useful. */ 20360 if (strcasecmp (cpu_string, "default") == 0) 20361 return 0; 20362 20363 for (p = mips_cpu_info_table; p->name != 0; p++) 20364 if (mips_matching_cpu_name_p (p->name, cpu_string)) 20365 return p; 20366 20367 as_bad (_("bad value (%s) for %s"), cpu_string, option); 20368 return 0; 20369} 20370 20371/* Return the canonical processor information for ISA (a member of the 20372 ISA_MIPS* enumeration). */ 20373 20374static const struct mips_cpu_info * 20375mips_cpu_info_from_isa (int isa) 20376{ 20377 int i; 20378 20379 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 20380 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) 20381 && isa == mips_cpu_info_table[i].isa) 20382 return (&mips_cpu_info_table[i]); 20383 20384 return NULL; 20385} 20386 20387static const struct mips_cpu_info * 20388mips_cpu_info_from_arch (int arch) 20389{ 20390 int i; 20391 20392 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 20393 if (arch == mips_cpu_info_table[i].cpu) 20394 return (&mips_cpu_info_table[i]); 20395 20396 return NULL; 20397} 20398 20399static void 20400show (FILE *stream, const char *string, int *col_p, int *first_p) 20401{ 20402 if (*first_p) 20403 { 20404 fprintf (stream, "%24s", ""); 20405 *col_p = 24; 20406 } 20407 else 20408 { 20409 fprintf (stream, ", "); 20410 *col_p += 2; 20411 } 20412 20413 if (*col_p + strlen (string) > 72) 20414 { 20415 fprintf (stream, "\n%24s", ""); 20416 *col_p = 24; 20417 } 20418 20419 fprintf (stream, "%s", string); 20420 *col_p += strlen (string); 20421 20422 *first_p = 0; 20423} 20424 20425void 20426md_show_usage (FILE *stream) 20427{ 20428 int column, first; 20429 size_t i; 20430 20431 fprintf (stream, _("\ 20432MIPS options:\n\ 20433-EB generate big endian output\n\ 20434-EL generate little endian output\n\ 20435-g, -g2 do not remove unneeded NOPs or swap branches\n\ 20436-G NUM allow referencing objects up to NUM bytes\n\ 20437 implicitly with the gp register [default 8]\n")); 20438 fprintf (stream, _("\ 20439-mips1 generate MIPS ISA I instructions\n\ 20440-mips2 generate MIPS ISA II instructions\n\ 20441-mips3 generate MIPS ISA III instructions\n\ 20442-mips4 generate MIPS ISA IV instructions\n\ 20443-mips5 generate MIPS ISA V instructions\n\ 20444-mips32 generate MIPS32 ISA instructions\n\ 20445-mips32r2 generate MIPS32 release 2 ISA instructions\n\ 20446-mips32r3 generate MIPS32 release 3 ISA instructions\n\ 20447-mips32r5 generate MIPS32 release 5 ISA instructions\n\ 20448-mips32r6 generate MIPS32 release 6 ISA instructions\n\ 20449-mips64 generate MIPS64 ISA instructions\n\ 20450-mips64r2 generate MIPS64 release 2 ISA instructions\n\ 20451-mips64r3 generate MIPS64 release 3 ISA instructions\n\ 20452-mips64r5 generate MIPS64 release 5 ISA instructions\n\ 20453-mips64r6 generate MIPS64 release 6 ISA instructions\n\ 20454-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 20455 20456 first = 1; 20457 20458 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 20459 show (stream, mips_cpu_info_table[i].name, &column, &first); 20460 show (stream, "from-abi", &column, &first); 20461 fputc ('\n', stream); 20462 20463 fprintf (stream, _("\ 20464-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 20465-no-mCPU don't generate code specific to CPU.\n\ 20466 For -mCPU and -no-mCPU, CPU must be one of:\n")); 20467 20468 first = 1; 20469 20470 show (stream, "3900", &column, &first); 20471 show (stream, "4010", &column, &first); 20472 show (stream, "4100", &column, &first); 20473 show (stream, "4650", &column, &first); 20474 fputc ('\n', stream); 20475 20476 fprintf (stream, _("\ 20477-mips16 generate mips16 instructions\n\ 20478-no-mips16 do not generate mips16 instructions\n")); 20479 fprintf (stream, _("\ 20480-mmips16e2 generate MIPS16e2 instructions\n\ 20481-mno-mips16e2 do not generate MIPS16e2 instructions\n")); 20482 fprintf (stream, _("\ 20483-mmicromips generate microMIPS instructions\n\ 20484-mno-micromips do not generate microMIPS instructions\n")); 20485 fprintf (stream, _("\ 20486-msmartmips generate smartmips instructions\n\ 20487-mno-smartmips do not generate smartmips instructions\n")); 20488 fprintf (stream, _("\ 20489-mdsp generate DSP instructions\n\ 20490-mno-dsp do not generate DSP instructions\n")); 20491 fprintf (stream, _("\ 20492-mdspr2 generate DSP R2 instructions\n\ 20493-mno-dspr2 do not generate DSP R2 instructions\n")); 20494 fprintf (stream, _("\ 20495-mdspr3 generate DSP R3 instructions\n\ 20496-mno-dspr3 do not generate DSP R3 instructions\n")); 20497 fprintf (stream, _("\ 20498-mmt generate MT instructions\n\ 20499-mno-mt do not generate MT instructions\n")); 20500 fprintf (stream, _("\ 20501-mmcu generate MCU instructions\n\ 20502-mno-mcu do not generate MCU instructions\n")); 20503 fprintf (stream, _("\ 20504-mmsa generate MSA instructions\n\ 20505-mno-msa do not generate MSA instructions\n")); 20506 fprintf (stream, _("\ 20507-mxpa generate eXtended Physical Address (XPA) instructions\n\ 20508-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); 20509 fprintf (stream, _("\ 20510-mvirt generate Virtualization instructions\n\ 20511-mno-virt do not generate Virtualization instructions\n")); 20512 fprintf (stream, _("\ 20513-mcrc generate CRC instructions\n\ 20514-mno-crc do not generate CRC instructions\n")); 20515 fprintf (stream, _("\ 20516-mginv generate Global INValidate (GINV) instructions\n\ 20517-mno-ginv do not generate Global INValidate instructions\n")); 20518 fprintf (stream, _("\ 20519-mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ 20520-mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); 20521 fprintf (stream, _("\ 20522-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ 20523-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); 20524 fprintf (stream, _("\ 20525-mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ 20526-mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); 20527 fprintf (stream, _("\ 20528-mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ 20529-mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); 20530 fprintf (stream, _("\ 20531-minsn32 only generate 32-bit microMIPS instructions\n\ 20532-mno-insn32 generate all microMIPS instructions\n")); 20533#if DEFAULT_MIPS_FIX_LOONGSON3_LLSC 20534 fprintf (stream, _("\ 20535-mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\ 20536-mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n")); 20537#else 20538 fprintf (stream, _("\ 20539-mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ 20540-mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n")); 20541#endif 20542 fprintf (stream, _("\ 20543-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ 20544-mfix-loongson2f-nop work around Loongson2F NOP errata\n\ 20545-mfix-loongson2f-btb work around Loongson2F BTB errata\n\ 20546-mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ 20547-mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\ 20548-mfix-vr4120 work around certain VR4120 errata\n\ 20549-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ 20550-mfix-24k insert a nop after ERET and DERET instructions\n\ 20551-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ 20552-mfix-r5900 work around R5900 short loop errata\n\ 20553-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 20554-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 20555-msym32 assume all symbols have 32-bit values\n\ 20556-O0 do not remove unneeded NOPs, do not swap branches\n\ 20557-O, -O1 remove unneeded NOPs, do not swap branches\n\ 20558-O2 remove unneeded NOPs and swap branches\n\ 20559--trap, --no-break trap exception on div by 0 and mult overflow\n\ 20560--break, --no-trap break exception on div by 0 and mult overflow\n")); 20561 fprintf (stream, _("\ 20562-mhard-float allow floating-point instructions\n\ 20563-msoft-float do not allow floating-point instructions\n\ 20564-msingle-float only allow 32-bit floating-point operations\n\ 20565-mdouble-float allow 32-bit and 64-bit floating-point operations\n\ 20566--[no-]construct-floats [dis]allow floating point values to be constructed\n\ 20567--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ 20568-mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ 20569-mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ 20570-mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); 20571 20572 first = 1; 20573 20574 show (stream, "legacy", &column, &first); 20575 show (stream, "2008", &column, &first); 20576 20577 fputc ('\n', stream); 20578 20579 fprintf (stream, _("\ 20580-KPIC, -call_shared generate SVR4 position independent code\n\ 20581-call_nonpic generate non-PIC code that can operate with DSOs\n\ 20582-mvxworks-pic generate VxWorks position independent code\n\ 20583-non_shared do not generate code that can operate with DSOs\n\ 20584-xgot assume a 32 bit GOT\n\ 20585-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 20586-mshared, -mno-shared disable/enable .cpload optimization for\n\ 20587 position dependent (non shared) code\n\ 20588-mabi=ABI create ABI conformant object file for:\n")); 20589 20590 first = 1; 20591 20592 show (stream, "32", &column, &first); 20593 show (stream, "o64", &column, &first); 20594 show (stream, "n32", &column, &first); 20595 show (stream, "64", &column, &first); 20596 show (stream, "eabi", &column, &first); 20597 20598 fputc ('\n', stream); 20599 20600 fprintf (stream, _("\ 20601-32 create o32 ABI object file%s\n"), 20602 MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); 20603 fprintf (stream, _("\ 20604-n32 create n32 ABI object file%s\n"), 20605 MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); 20606 fprintf (stream, _("\ 20607-64 create 64 ABI object file%s\n"), 20608 MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); 20609} 20610 20611#ifdef TE_IRIX 20612enum dwarf2_format 20613mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) 20614{ 20615 if (HAVE_64BIT_SYMBOLS) 20616 return dwarf2_format_64bit_irix; 20617 else 20618 return dwarf2_format_32bit; 20619} 20620#endif 20621 20622int 20623mips_dwarf2_addr_size (void) 20624{ 20625 if (HAVE_64BIT_OBJECTS) 20626 return 8; 20627 else 20628 return 4; 20629} 20630 20631/* Standard calling conventions leave the CFA at SP on entry. */ 20632void 20633mips_cfi_frame_initial_instructions (void) 20634{ 20635 cfi_add_CFA_def_cfa_register (SP); 20636} 20637 20638int 20639tc_mips_regname_to_dw2regnum (char *regname) 20640{ 20641 unsigned int regnum = -1; 20642 unsigned int reg; 20643 20644 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) 20645 regnum = reg; 20646 20647 return regnum; 20648} 20649 20650/* Implement CONVERT_SYMBOLIC_ATTRIBUTE. 20651 Given a symbolic attribute NAME, return the proper integer value. 20652 Returns -1 if the attribute is not known. */ 20653 20654int 20655mips_convert_symbolic_attribute (const char *name) 20656{ 20657 static const struct 20658 { 20659 const char * name; 20660 const int tag; 20661 } 20662 attribute_table[] = 20663 { 20664#define T(tag) {#tag, tag} 20665 T (Tag_GNU_MIPS_ABI_FP), 20666 T (Tag_GNU_MIPS_ABI_MSA), 20667#undef T 20668 }; 20669 unsigned int i; 20670 20671 if (name == NULL) 20672 return -1; 20673 20674 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 20675 if (streq (name, attribute_table[i].name)) 20676 return attribute_table[i].tag; 20677 20678 return -1; 20679} 20680 20681void 20682md_mips_end (void) 20683{ 20684 int fpabi = Val_GNU_MIPS_ABI_FP_ANY; 20685 20686 mips_emit_delays (); 20687 if (cur_proc_ptr) 20688 as_warn (_("missing .end at end of assembly")); 20689 20690 /* Just in case no code was emitted, do the consistency check. */ 20691 file_mips_check_options (); 20692 20693 /* Set a floating-point ABI if the user did not. */ 20694 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) 20695 { 20696 /* Perform consistency checks on the floating-point ABI. */ 20697 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 20698 Tag_GNU_MIPS_ABI_FP); 20699 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) 20700 check_fpabi (fpabi); 20701 } 20702 else 20703 { 20704 /* Soft-float gets precedence over single-float, the two options should 20705 not be used together so this should not matter. */ 20706 if (file_mips_opts.soft_float == 1) 20707 fpabi = Val_GNU_MIPS_ABI_FP_SOFT; 20708 /* Single-float gets precedence over all double_float cases. */ 20709 else if (file_mips_opts.single_float == 1) 20710 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; 20711 else 20712 { 20713 switch (file_mips_opts.fp) 20714 { 20715 case 32: 20716 if (file_mips_opts.gp == 32) 20717 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 20718 break; 20719 case 0: 20720 fpabi = Val_GNU_MIPS_ABI_FP_XX; 20721 break; 20722 case 64: 20723 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) 20724 fpabi = Val_GNU_MIPS_ABI_FP_64A; 20725 else if (file_mips_opts.gp == 32) 20726 fpabi = Val_GNU_MIPS_ABI_FP_64; 20727 else 20728 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; 20729 break; 20730 } 20731 } 20732 20733 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, 20734 Tag_GNU_MIPS_ABI_FP, fpabi); 20735 } 20736} 20737 20738/* Returns the relocation type required for a particular CFI encoding. */ 20739 20740bfd_reloc_code_real_type 20741mips_cfi_reloc_for_encoding (int encoding) 20742{ 20743 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) 20744 return BFD_RELOC_32_PCREL; 20745 else return BFD_RELOC_NONE; 20746} 20747