reloc.texi revision 1.6
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. Note - the value 2 is used so that it 31 will not be mistaken for the boolean TRUE or FALSE values. */ 32 bfd_reloc_ok = 2, 33 34 /* The relocation was performed, but there was an overflow. */ 35 bfd_reloc_overflow, 36 37 /* The address to relocate was not within the section supplied. */ 38 bfd_reloc_outofrange, 39 40 /* Used by special functions. */ 41 bfd_reloc_continue, 42 43 /* Unsupported relocation size requested. */ 44 bfd_reloc_notsupported, 45 46 /* Unused. */ 47 bfd_reloc_other, 48 49 /* The symbol to relocate against was undefined. */ 50 bfd_reloc_undefined, 51 52 /* The relocation was performed, but may not be ok. If this type is 53 returned, the error_message argument to bfd_perform_relocation 54 will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* The relocation is relative to the field being relocated. */ 285 bfd_boolean pc_relative; 286 287 /* The bit position of the reloc value in the destination. 288 The relocated value is left shifted by this amount. */ 289 unsigned int bitpos; 290 291 /* What type of overflow error should be checked for when 292 relocating. */ 293 enum complain_overflow complain_on_overflow; 294 295 /* If this field is non null, then the supplied function is 296 called rather than the normal function. This allows really 297 strange relocation methods to be accommodated. */ 298 bfd_reloc_status_type (*special_function) 299 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 300 bfd *, char **); 301 302 /* The textual name of the relocation type. */ 303 char *name; 304 305 /* Some formats record a relocation addend in the section contents 306 rather than with the relocation. For ELF formats this is the 307 distinction between USE_REL and USE_RELA (though the code checks 308 for USE_REL == 1/0). The value of this field is TRUE if the 309 addend is recorded with the section contents; when performing a 310 partial link (ld -r) the section contents (the data) will be 311 modified. The value of this field is FALSE if addends are 312 recorded with the relocation (in arelent.addend); when performing 313 a partial link the relocation will be modified. 314 All relocations for all ELF USE_RELA targets should set this field 315 to FALSE (values of TRUE should be looked on with suspicion). 316 However, the converse is not true: not all relocations of all ELF 317 USE_REL targets set this field to TRUE. Why this is so is peculiar 318 to each particular target. For relocs that aren't used in partial 319 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 320 bfd_boolean partial_inplace; 321 322 /* src_mask selects the part of the instruction (or data) to be used 323 in the relocation sum. If the target relocations don't have an 324 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 325 dst_mask to extract the addend from the section contents. If 326 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 327 field should be zero. Non-zero values for ELF USE_RELA targets are 328 bogus as in those cases the value in the dst_mask part of the 329 section contents should be treated as garbage. */ 330 bfd_vma src_mask; 331 332 /* dst_mask selects which parts of the instruction (or data) are 333 replaced with a relocated value. */ 334 bfd_vma dst_mask; 335 336 /* When some formats create PC relative instructions, they leave 337 the value of the pc of the place being relocated in the offset 338 slot of the instruction, so that a PC relative relocation can 339 be made just by adding in an ordinary offset (e.g., sun3 a.out). 340 Some formats leave the displacement part of an instruction 341 empty (e.g., ELF); this flag signals the fact. */ 342 bfd_boolean pcrel_offset; 343@}; 344 345@end example 346@findex The HOWTO Macro 347@subsubsection @code{The HOWTO Macro} 348@strong{Description}@* 349The HOWTO define is horrible and will go away. 350@example 351#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 352 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 353@end example 354 355@strong{Description}@* 356And will be replaced with the totally magic way. But for the 357moment, we are compatible, so do it this way. 358@example 359#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 360 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 361 NAME, FALSE, 0, 0, IN) 362 363@end example 364 365@strong{Description}@* 366This is used to fill in an empty howto entry in an array. 367@example 368#define EMPTY_HOWTO(C) \ 369 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 370 NULL, FALSE, 0, 0, FALSE) 371 372@end example 373 374@strong{Description}@* 375Helper routine to turn a symbol into a relocation value. 376@example 377#define HOWTO_PREPARE(relocation, symbol) \ 378 @{ \ 379 if (symbol != NULL) \ 380 @{ \ 381 if (bfd_is_com_section (symbol->section)) \ 382 @{ \ 383 relocation = 0; \ 384 @} \ 385 else \ 386 @{ \ 387 relocation = symbol->value; \ 388 @} \ 389 @} \ 390 @} 391 392@end example 393 394@findex bfd_get_reloc_size 395@subsubsection @code{bfd_get_reloc_size} 396@strong{Synopsis} 397@example 398unsigned int bfd_get_reloc_size (reloc_howto_type *); 399@end example 400@strong{Description}@* 401For a reloc_howto_type that operates on a fixed number of bytes, 402this returns the number of bytes operated on. 403 404@findex arelent_chain 405@subsubsection @code{arelent_chain} 406@strong{Description}@* 407How relocs are tied together in an @code{asection}: 408@example 409typedef struct relent_chain 410@{ 411 arelent relent; 412 struct relent_chain *next; 413@} 414arelent_chain; 415 416@end example 417 418@findex bfd_check_overflow 419@subsubsection @code{bfd_check_overflow} 420@strong{Synopsis} 421@example 422bfd_reloc_status_type bfd_check_overflow 423 (enum complain_overflow how, 424 unsigned int bitsize, 425 unsigned int rightshift, 426 unsigned int addrsize, 427 bfd_vma relocation); 428@end example 429@strong{Description}@* 430Perform overflow checking on @var{relocation} which has 431@var{bitsize} significant bits and will be shifted right by 432@var{rightshift} bits, on a machine with addresses containing 433@var{addrsize} significant bits. The result is either of 434@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 435 436@findex bfd_reloc_offset_in_range 437@subsubsection @code{bfd_reloc_offset_in_range} 438@strong{Synopsis} 439@example 440bfd_boolean bfd_reloc_offset_in_range 441 (reloc_howto_type *howto, 442 bfd *abfd, 443 asection *section, 444 bfd_size_type offset); 445@end example 446@strong{Description}@* 447Returns TRUE if the reloc described by @var{HOWTO} can be 448applied at @var{OFFSET} octets in @var{SECTION}. 449 450@findex bfd_perform_relocation 451@subsubsection @code{bfd_perform_relocation} 452@strong{Synopsis} 453@example 454bfd_reloc_status_type bfd_perform_relocation 455 (bfd *abfd, 456 arelent *reloc_entry, 457 void *data, 458 asection *input_section, 459 bfd *output_bfd, 460 char **error_message); 461@end example 462@strong{Description}@* 463If @var{output_bfd} is supplied to this function, the 464generated image will be relocatable; the relocations are 465copied to the output file after they have been changed to 466reflect the new state of the world. There are two ways of 467reflecting the results of partial linkage in an output file: 468by modifying the output data in place, and by modifying the 469relocation record. Some native formats (e.g., basic a.out and 470basic coff) have no way of specifying an addend in the 471relocation type, so the addend has to go in the output data. 472This is no big deal since in these formats the output data 473slot will always be big enough for the addend. Complex reloc 474types with addends were invented to solve just this problem. 475The @var{error_message} argument is set to an error message if 476this return @code{bfd_reloc_dangerous}. 477 478@findex bfd_install_relocation 479@subsubsection @code{bfd_install_relocation} 480@strong{Synopsis} 481@example 482bfd_reloc_status_type bfd_install_relocation 483 (bfd *abfd, 484 arelent *reloc_entry, 485 void *data, bfd_vma data_start, 486 asection *input_section, 487 char **error_message); 488@end example 489@strong{Description}@* 490This looks remarkably like @code{bfd_perform_relocation}, except it 491does not expect that the section contents have been filled in. 492I.e., it's suitable for use when creating, rather than applying 493a relocation. 494 495For now, this function should be considered reserved for the 496assembler. 497 498 499@node howto manager, , typedef arelent, Relocations 500@subsection The howto manager 501When an application wants to create a relocation, but doesn't 502know what the target machine might call it, it can find out by 503using this bit of code. 504 505@findex bfd_reloc_code_type 506@subsubsection @code{bfd_reloc_code_type} 507@strong{Description}@* 508The insides of a reloc code. The idea is that, eventually, there 509will be one enumerator for every type of relocation we ever do. 510Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 511return a howto pointer. 512 513This does mean that the application must determine the correct 514enumerator value; you can't get a howto pointer from a random set 515of attributes. 516 517Here are the possible values for @code{enum bfd_reloc_code_real}: 518 519@deffn {} BFD_RELOC_64 520@deffnx {} BFD_RELOC_32 521@deffnx {} BFD_RELOC_26 522@deffnx {} BFD_RELOC_24 523@deffnx {} BFD_RELOC_16 524@deffnx {} BFD_RELOC_14 525@deffnx {} BFD_RELOC_8 526Basic absolute relocations of N bits. 527@end deffn 528@deffn {} BFD_RELOC_64_PCREL 529@deffnx {} BFD_RELOC_32_PCREL 530@deffnx {} BFD_RELOC_24_PCREL 531@deffnx {} BFD_RELOC_16_PCREL 532@deffnx {} BFD_RELOC_12_PCREL 533@deffnx {} BFD_RELOC_8_PCREL 534PC-relative relocations. Sometimes these are relative to the address 535of the relocation itself; sometimes they are relative to the start of 536the section containing the relocation. It depends on the specific target. 537@end deffn 538@deffn {} BFD_RELOC_32_SECREL 539Section relative relocations. Some targets need this for DWARF2. 540@end deffn 541@deffn {} BFD_RELOC_32_GOT_PCREL 542@deffnx {} BFD_RELOC_16_GOT_PCREL 543@deffnx {} BFD_RELOC_8_GOT_PCREL 544@deffnx {} BFD_RELOC_32_GOTOFF 545@deffnx {} BFD_RELOC_16_GOTOFF 546@deffnx {} BFD_RELOC_LO16_GOTOFF 547@deffnx {} BFD_RELOC_HI16_GOTOFF 548@deffnx {} BFD_RELOC_HI16_S_GOTOFF 549@deffnx {} BFD_RELOC_8_GOTOFF 550@deffnx {} BFD_RELOC_64_PLT_PCREL 551@deffnx {} BFD_RELOC_32_PLT_PCREL 552@deffnx {} BFD_RELOC_24_PLT_PCREL 553@deffnx {} BFD_RELOC_16_PLT_PCREL 554@deffnx {} BFD_RELOC_8_PLT_PCREL 555@deffnx {} BFD_RELOC_64_PLTOFF 556@deffnx {} BFD_RELOC_32_PLTOFF 557@deffnx {} BFD_RELOC_16_PLTOFF 558@deffnx {} BFD_RELOC_LO16_PLTOFF 559@deffnx {} BFD_RELOC_HI16_PLTOFF 560@deffnx {} BFD_RELOC_HI16_S_PLTOFF 561@deffnx {} BFD_RELOC_8_PLTOFF 562For ELF. 563@end deffn 564@deffn {} BFD_RELOC_SIZE32 565@deffnx {} BFD_RELOC_SIZE64 566Size relocations. 567@end deffn 568@deffn {} BFD_RELOC_68K_GLOB_DAT 569@deffnx {} BFD_RELOC_68K_JMP_SLOT 570@deffnx {} BFD_RELOC_68K_RELATIVE 571@deffnx {} BFD_RELOC_68K_TLS_GD32 572@deffnx {} BFD_RELOC_68K_TLS_GD16 573@deffnx {} BFD_RELOC_68K_TLS_GD8 574@deffnx {} BFD_RELOC_68K_TLS_LDM32 575@deffnx {} BFD_RELOC_68K_TLS_LDM16 576@deffnx {} BFD_RELOC_68K_TLS_LDM8 577@deffnx {} BFD_RELOC_68K_TLS_LDO32 578@deffnx {} BFD_RELOC_68K_TLS_LDO16 579@deffnx {} BFD_RELOC_68K_TLS_LDO8 580@deffnx {} BFD_RELOC_68K_TLS_IE32 581@deffnx {} BFD_RELOC_68K_TLS_IE16 582@deffnx {} BFD_RELOC_68K_TLS_IE8 583@deffnx {} BFD_RELOC_68K_TLS_LE32 584@deffnx {} BFD_RELOC_68K_TLS_LE16 585@deffnx {} BFD_RELOC_68K_TLS_LE8 586Relocations used by 68K ELF. 587@end deffn 588@deffn {} BFD_RELOC_VAX_GLOB_DAT 589@deffnx {} BFD_RELOC_VAX_GLOB_REF 590@deffnx {} BFD_RELOC_VAX_JMP_SLOT 591@deffnx {} BFD_RELOC_VAX_RELATIVE 592Relocations used by VAX ELF. 593@end deffn 594@deffn {} BFD_RELOC_32_BASEREL 595@deffnx {} BFD_RELOC_16_BASEREL 596@deffnx {} BFD_RELOC_LO16_BASEREL 597@deffnx {} BFD_RELOC_HI16_BASEREL 598@deffnx {} BFD_RELOC_HI16_S_BASEREL 599@deffnx {} BFD_RELOC_8_BASEREL 600@deffnx {} BFD_RELOC_RVA 601Linkage-table relative. 602@end deffn 603@deffn {} BFD_RELOC_8_FFnn 604Absolute 8-bit relocation, but used to form an address like 0xFFnn. 605@end deffn 606@deffn {} BFD_RELOC_32_PCREL_S2 607@deffnx {} BFD_RELOC_16_PCREL_S2 608@deffnx {} BFD_RELOC_23_PCREL_S2 609These PC-relative relocations are stored as word displacements -- 610i.e., byte displacements shifted right two bits. The 30-bit word 611displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 612SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 613signed 16-bit displacement is used on the MIPS, and the 23-bit 614displacement is used on the Alpha. 615@end deffn 616@deffn {} BFD_RELOC_HI22 617@deffnx {} BFD_RELOC_LO10 618High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 619the target word. These are used on the SPARC. 620@end deffn 621@deffn {} BFD_RELOC_GPREL16 622@deffnx {} BFD_RELOC_GPREL32 623For systems that allocate a Global Pointer register, these are 624displacements off that register. These relocation types are 625handled specially, because the value the register will have is 626decided relatively late. 627@end deffn 628@deffn {} BFD_RELOC_NONE 629@deffnx {} BFD_RELOC_SPARC_WDISP22 630@deffnx {} BFD_RELOC_SPARC22 631@deffnx {} BFD_RELOC_SPARC13 632@deffnx {} BFD_RELOC_SPARC_GOT10 633@deffnx {} BFD_RELOC_SPARC_GOT13 634@deffnx {} BFD_RELOC_SPARC_GOT22 635@deffnx {} BFD_RELOC_SPARC_PC10 636@deffnx {} BFD_RELOC_SPARC_PC22 637@deffnx {} BFD_RELOC_SPARC_WPLT30 638@deffnx {} BFD_RELOC_SPARC_COPY 639@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 640@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 641@deffnx {} BFD_RELOC_SPARC_RELATIVE 642@deffnx {} BFD_RELOC_SPARC_UA16 643@deffnx {} BFD_RELOC_SPARC_UA32 644@deffnx {} BFD_RELOC_SPARC_UA64 645@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 646@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 647@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 648@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 649@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 650@deffnx {} BFD_RELOC_SPARC_JMP_IREL 651@deffnx {} BFD_RELOC_SPARC_IRELATIVE 652SPARC ELF relocations. There is probably some overlap with other 653relocation types already defined. 654@end deffn 655@deffn {} BFD_RELOC_SPARC_BASE13 656@deffnx {} BFD_RELOC_SPARC_BASE22 657I think these are specific to SPARC a.out (e.g., Sun 4). 658@end deffn 659@deffn {} BFD_RELOC_SPARC_64 660@deffnx {} BFD_RELOC_SPARC_10 661@deffnx {} BFD_RELOC_SPARC_11 662@deffnx {} BFD_RELOC_SPARC_OLO10 663@deffnx {} BFD_RELOC_SPARC_HH22 664@deffnx {} BFD_RELOC_SPARC_HM10 665@deffnx {} BFD_RELOC_SPARC_LM22 666@deffnx {} BFD_RELOC_SPARC_PC_HH22 667@deffnx {} BFD_RELOC_SPARC_PC_HM10 668@deffnx {} BFD_RELOC_SPARC_PC_LM22 669@deffnx {} BFD_RELOC_SPARC_WDISP16 670@deffnx {} BFD_RELOC_SPARC_WDISP19 671@deffnx {} BFD_RELOC_SPARC_7 672@deffnx {} BFD_RELOC_SPARC_6 673@deffnx {} BFD_RELOC_SPARC_5 674@deffnx {} BFD_RELOC_SPARC_DISP64 675@deffnx {} BFD_RELOC_SPARC_PLT32 676@deffnx {} BFD_RELOC_SPARC_PLT64 677@deffnx {} BFD_RELOC_SPARC_HIX22 678@deffnx {} BFD_RELOC_SPARC_LOX10 679@deffnx {} BFD_RELOC_SPARC_H44 680@deffnx {} BFD_RELOC_SPARC_M44 681@deffnx {} BFD_RELOC_SPARC_L44 682@deffnx {} BFD_RELOC_SPARC_REGISTER 683@deffnx {} BFD_RELOC_SPARC_H34 684@deffnx {} BFD_RELOC_SPARC_SIZE32 685@deffnx {} BFD_RELOC_SPARC_SIZE64 686@deffnx {} BFD_RELOC_SPARC_WDISP10 687SPARC64 relocations 688@end deffn 689@deffn {} BFD_RELOC_SPARC_REV32 690SPARC little endian relocation 691@end deffn 692@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 693@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 694@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 695@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 696@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 697@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 698@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 699@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 700@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 701@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 702@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 703@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 704@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 705@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 706@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 707@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 708@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 709@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 710@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 711@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 712@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 713@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 714@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 715@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 716SPARC TLS relocations 717@end deffn 718@deffn {} BFD_RELOC_SPU_IMM7 719@deffnx {} BFD_RELOC_SPU_IMM8 720@deffnx {} BFD_RELOC_SPU_IMM10 721@deffnx {} BFD_RELOC_SPU_IMM10W 722@deffnx {} BFD_RELOC_SPU_IMM16 723@deffnx {} BFD_RELOC_SPU_IMM16W 724@deffnx {} BFD_RELOC_SPU_IMM18 725@deffnx {} BFD_RELOC_SPU_PCREL9a 726@deffnx {} BFD_RELOC_SPU_PCREL9b 727@deffnx {} BFD_RELOC_SPU_PCREL16 728@deffnx {} BFD_RELOC_SPU_LO16 729@deffnx {} BFD_RELOC_SPU_HI16 730@deffnx {} BFD_RELOC_SPU_PPU32 731@deffnx {} BFD_RELOC_SPU_PPU64 732@deffnx {} BFD_RELOC_SPU_ADD_PIC 733SPU Relocations. 734@end deffn 735@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 736Alpha ECOFF and ELF relocations. Some of these treat the symbol or 737"addend" in some special way. 738For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 739writing; when reading, it will be the absolute section symbol. The 740addend is the displacement in bytes of the "lda" instruction from 741the "ldah" instruction (which is at the address of this reloc). 742@end deffn 743@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 744For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 745with GPDISP_HI16 relocs. The addend is ignored when writing the 746relocations out, and is filled in with the file's GP value on 747reading, for convenience. 748@end deffn 749@deffn {} BFD_RELOC_ALPHA_GPDISP 750The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 751relocation except that there is no accompanying GPDISP_LO16 752relocation. 753@end deffn 754@deffn {} BFD_RELOC_ALPHA_LITERAL 755@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 756@deffnx {} BFD_RELOC_ALPHA_LITUSE 757The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 758the assembler turns it into a LDQ instruction to load the address of 759the symbol, and then fills in a register in the real instruction. 760 761The LITERAL reloc, at the LDQ instruction, refers to the .lita 762section symbol. The addend is ignored when writing, but is filled 763in with the file's GP value on reading, for convenience, as with the 764GPDISP_LO16 reloc. 765 766The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 767It should refer to the symbol to be referenced, as with 16_GOTOFF, 768but it generates output not based on the position within the .got 769section, but relative to the GP value chosen for the file during the 770final link stage. 771 772The LITUSE reloc, on the instruction using the loaded address, gives 773information to the linker that it might be able to use to optimize 774away some literal section references. The symbol is ignored (read 775as the absolute section symbol), and the "addend" indicates the type 776of instruction using the register: 7771 - "memory" fmt insn 7782 - byte-manipulation (byte offset reg) 7793 - jsr (target of branch) 780@end deffn 781@deffn {} BFD_RELOC_ALPHA_HINT 782The HINT relocation indicates a value that should be filled into the 783"hint" field of a jmp/jsr/ret instruction, for possible branch- 784prediction logic which may be provided on some processors. 785@end deffn 786@deffn {} BFD_RELOC_ALPHA_LINKAGE 787The LINKAGE relocation outputs a linkage pair in the object file, 788which is filled by the linker. 789@end deffn 790@deffn {} BFD_RELOC_ALPHA_CODEADDR 791The CODEADDR relocation outputs a STO_CA in the object file, 792which is filled by the linker. 793@end deffn 794@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 795@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 796The GPREL_HI/LO relocations together form a 32-bit offset from the 797GP register. 798@end deffn 799@deffn {} BFD_RELOC_ALPHA_BRSGP 800Like BFD_RELOC_23_PCREL_S2, except that the source and target must 801share a common GP, and the target address is adjusted for 802STO_ALPHA_STD_GPLOAD. 803@end deffn 804@deffn {} BFD_RELOC_ALPHA_NOP 805The NOP relocation outputs a NOP if the longword displacement 806between two procedure entry points is < 2^21. 807@end deffn 808@deffn {} BFD_RELOC_ALPHA_BSR 809The BSR relocation outputs a BSR if the longword displacement 810between two procedure entry points is < 2^21. 811@end deffn 812@deffn {} BFD_RELOC_ALPHA_LDA 813The LDA relocation outputs a LDA if the longword displacement 814between two procedure entry points is < 2^16. 815@end deffn 816@deffn {} BFD_RELOC_ALPHA_BOH 817The BOH relocation outputs a BSR if the longword displacement 818between two procedure entry points is < 2^21, or else a hint. 819@end deffn 820@deffn {} BFD_RELOC_ALPHA_TLSGD 821@deffnx {} BFD_RELOC_ALPHA_TLSLDM 822@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 823@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 824@deffnx {} BFD_RELOC_ALPHA_DTPREL64 825@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 826@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 827@deffnx {} BFD_RELOC_ALPHA_DTPREL16 828@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 829@deffnx {} BFD_RELOC_ALPHA_TPREL64 830@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 831@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 832@deffnx {} BFD_RELOC_ALPHA_TPREL16 833Alpha thread-local storage relocations. 834@end deffn 835@deffn {} BFD_RELOC_MIPS_JMP 836@deffnx {} BFD_RELOC_MICROMIPS_JMP 837The MIPS jump instruction. 838@end deffn 839@deffn {} BFD_RELOC_MIPS16_JMP 840The MIPS16 jump instruction. 841@end deffn 842@deffn {} BFD_RELOC_MIPS16_GPREL 843MIPS16 GP relative reloc. 844@end deffn 845@deffn {} BFD_RELOC_HI16 846High 16 bits of 32-bit value; simple reloc. 847@end deffn 848@deffn {} BFD_RELOC_HI16_S 849High 16 bits of 32-bit value but the low 16 bits will be sign 850extended and added to form the final result. If the low 16 851bits form a negative number, we need to add one to the high value 852to compensate for the borrow when the low bits are added. 853@end deffn 854@deffn {} BFD_RELOC_LO16 855Low 16 bits. 856@end deffn 857@deffn {} BFD_RELOC_HI16_PCREL 858High 16 bits of 32-bit pc-relative value 859@end deffn 860@deffn {} BFD_RELOC_HI16_S_PCREL 861High 16 bits of 32-bit pc-relative value, adjusted 862@end deffn 863@deffn {} BFD_RELOC_LO16_PCREL 864Low 16 bits of pc-relative value 865@end deffn 866@deffn {} BFD_RELOC_MIPS16_GOT16 867@deffnx {} BFD_RELOC_MIPS16_CALL16 868Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 86916-bit immediate fields 870@end deffn 871@deffn {} BFD_RELOC_MIPS16_HI16 872MIPS16 high 16 bits of 32-bit value. 873@end deffn 874@deffn {} BFD_RELOC_MIPS16_HI16_S 875MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 876extended and added to form the final result. If the low 16 877bits form a negative number, we need to add one to the high value 878to compensate for the borrow when the low bits are added. 879@end deffn 880@deffn {} BFD_RELOC_MIPS16_LO16 881MIPS16 low 16 bits. 882@end deffn 883@deffn {} BFD_RELOC_MIPS16_TLS_GD 884@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 885@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 886@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 887@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 888@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 889@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 890MIPS16 TLS relocations 891@end deffn 892@deffn {} BFD_RELOC_MIPS_LITERAL 893@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 894Relocation against a MIPS literal section. 895@end deffn 896@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 897@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 898@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 899microMIPS PC-relative relocations. 900@end deffn 901@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 902MIPS16 PC-relative relocation. 903@end deffn 904@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 905@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 906@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 907@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 908MIPS PC-relative relocations. 909@end deffn 910@deffn {} BFD_RELOC_MICROMIPS_GPREL16 911@deffnx {} BFD_RELOC_MICROMIPS_HI16 912@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 913@deffnx {} BFD_RELOC_MICROMIPS_LO16 914microMIPS versions of generic BFD relocs. 915@end deffn 916@deffn {} BFD_RELOC_MIPS_GOT16 917@deffnx {} BFD_RELOC_MICROMIPS_GOT16 918@deffnx {} BFD_RELOC_MIPS_CALL16 919@deffnx {} BFD_RELOC_MICROMIPS_CALL16 920@deffnx {} BFD_RELOC_MIPS_GOT_HI16 921@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 922@deffnx {} BFD_RELOC_MIPS_GOT_LO16 923@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 924@deffnx {} BFD_RELOC_MIPS_CALL_HI16 925@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 926@deffnx {} BFD_RELOC_MIPS_CALL_LO16 927@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 928@deffnx {} BFD_RELOC_MIPS_SUB 929@deffnx {} BFD_RELOC_MICROMIPS_SUB 930@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 931@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 932@deffnx {} BFD_RELOC_MIPS_GOT_OFST 933@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 934@deffnx {} BFD_RELOC_MIPS_GOT_DISP 935@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 936@deffnx {} BFD_RELOC_MIPS_SHIFT5 937@deffnx {} BFD_RELOC_MIPS_SHIFT6 938@deffnx {} BFD_RELOC_MIPS_INSERT_A 939@deffnx {} BFD_RELOC_MIPS_INSERT_B 940@deffnx {} BFD_RELOC_MIPS_DELETE 941@deffnx {} BFD_RELOC_MIPS_HIGHEST 942@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 943@deffnx {} BFD_RELOC_MIPS_HIGHER 944@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 945@deffnx {} BFD_RELOC_MIPS_SCN_DISP 946@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 947@deffnx {} BFD_RELOC_MIPS_REL16 948@deffnx {} BFD_RELOC_MIPS_RELGOT 949@deffnx {} BFD_RELOC_MIPS_JALR 950@deffnx {} BFD_RELOC_MICROMIPS_JALR 951@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 952@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 953@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 954@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 955@deffnx {} BFD_RELOC_MIPS_TLS_GD 956@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 957@deffnx {} BFD_RELOC_MIPS_TLS_LDM 958@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 959@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 960@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 961@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 962@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 963@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 964@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 965@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 966@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 967@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 968@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 969@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 970@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 971@deffnx {} BFD_RELOC_MIPS_EH 972MIPS ELF relocations. 973@end deffn 974@deffn {} BFD_RELOC_MIPS_COPY 975@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 976MIPS ELF relocations (VxWorks and PLT extensions). 977@end deffn 978@deffn {} BFD_RELOC_MOXIE_10_PCREL 979Moxie ELF relocations. 980@end deffn 981@deffn {} BFD_RELOC_FT32_10 982@deffnx {} BFD_RELOC_FT32_20 983@deffnx {} BFD_RELOC_FT32_17 984@deffnx {} BFD_RELOC_FT32_18 985@deffnx {} BFD_RELOC_FT32_RELAX 986@deffnx {} BFD_RELOC_FT32_SC0 987@deffnx {} BFD_RELOC_FT32_SC1 988@deffnx {} BFD_RELOC_FT32_15 989@deffnx {} BFD_RELOC_FT32_DIFF32 990FT32 ELF relocations. 991@end deffn 992@deffn {} BFD_RELOC_FRV_LABEL16 993@deffnx {} BFD_RELOC_FRV_LABEL24 994@deffnx {} BFD_RELOC_FRV_LO16 995@deffnx {} BFD_RELOC_FRV_HI16 996@deffnx {} BFD_RELOC_FRV_GPREL12 997@deffnx {} BFD_RELOC_FRV_GPRELU12 998@deffnx {} BFD_RELOC_FRV_GPREL32 999@deffnx {} BFD_RELOC_FRV_GPRELHI 1000@deffnx {} BFD_RELOC_FRV_GPRELLO 1001@deffnx {} BFD_RELOC_FRV_GOT12 1002@deffnx {} BFD_RELOC_FRV_GOTHI 1003@deffnx {} BFD_RELOC_FRV_GOTLO 1004@deffnx {} BFD_RELOC_FRV_FUNCDESC 1005@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 1006@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 1007@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 1008@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 1009@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 1010@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 1011@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 1012@deffnx {} BFD_RELOC_FRV_GOTOFF12 1013@deffnx {} BFD_RELOC_FRV_GOTOFFHI 1014@deffnx {} BFD_RELOC_FRV_GOTOFFLO 1015@deffnx {} BFD_RELOC_FRV_GETTLSOFF 1016@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 1017@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 1018@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 1019@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 1020@deffnx {} BFD_RELOC_FRV_TLSMOFF12 1021@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 1022@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 1023@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 1024@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 1025@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 1026@deffnx {} BFD_RELOC_FRV_TLSOFF 1027@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 1028@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 1029@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 1030@deffnx {} BFD_RELOC_FRV_TLSMOFF 1031Fujitsu Frv Relocations. 1032@end deffn 1033@deffn {} BFD_RELOC_MN10300_GOTOFF24 1034This is a 24bit GOT-relative reloc for the mn10300. 1035@end deffn 1036@deffn {} BFD_RELOC_MN10300_GOT32 1037This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1038in the instruction. 1039@end deffn 1040@deffn {} BFD_RELOC_MN10300_GOT24 1041This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1042in the instruction. 1043@end deffn 1044@deffn {} BFD_RELOC_MN10300_GOT16 1045This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1046in the instruction. 1047@end deffn 1048@deffn {} BFD_RELOC_MN10300_COPY 1049Copy symbol at runtime. 1050@end deffn 1051@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1052Create GOT entry. 1053@end deffn 1054@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1055Create PLT entry. 1056@end deffn 1057@deffn {} BFD_RELOC_MN10300_RELATIVE 1058Adjust by program base. 1059@end deffn 1060@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1061Together with another reloc targeted at the same location, 1062allows for a value that is the difference of two symbols 1063in the same section. 1064@end deffn 1065@deffn {} BFD_RELOC_MN10300_ALIGN 1066The addend of this reloc is an alignment power that must 1067be honoured at the offset's location, regardless of linker 1068relaxation. 1069@end deffn 1070@deffn {} BFD_RELOC_MN10300_TLS_GD 1071@deffnx {} BFD_RELOC_MN10300_TLS_LD 1072@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1073@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1074@deffnx {} BFD_RELOC_MN10300_TLS_IE 1075@deffnx {} BFD_RELOC_MN10300_TLS_LE 1076@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1077@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1078@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1079Various TLS-related relocations. 1080@end deffn 1081@deffn {} BFD_RELOC_MN10300_32_PCREL 1082This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1083instruction. 1084@end deffn 1085@deffn {} BFD_RELOC_MN10300_16_PCREL 1086This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1087instruction. 1088@end deffn 1089@deffn {} BFD_RELOC_386_GOT32 1090@deffnx {} BFD_RELOC_386_PLT32 1091@deffnx {} BFD_RELOC_386_COPY 1092@deffnx {} BFD_RELOC_386_GLOB_DAT 1093@deffnx {} BFD_RELOC_386_JUMP_SLOT 1094@deffnx {} BFD_RELOC_386_RELATIVE 1095@deffnx {} BFD_RELOC_386_GOTOFF 1096@deffnx {} BFD_RELOC_386_GOTPC 1097@deffnx {} BFD_RELOC_386_TLS_TPOFF 1098@deffnx {} BFD_RELOC_386_TLS_IE 1099@deffnx {} BFD_RELOC_386_TLS_GOTIE 1100@deffnx {} BFD_RELOC_386_TLS_LE 1101@deffnx {} BFD_RELOC_386_TLS_GD 1102@deffnx {} BFD_RELOC_386_TLS_LDM 1103@deffnx {} BFD_RELOC_386_TLS_LDO_32 1104@deffnx {} BFD_RELOC_386_TLS_IE_32 1105@deffnx {} BFD_RELOC_386_TLS_LE_32 1106@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1107@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1108@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1109@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1110@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1111@deffnx {} BFD_RELOC_386_TLS_DESC 1112@deffnx {} BFD_RELOC_386_IRELATIVE 1113@deffnx {} BFD_RELOC_386_GOT32X 1114i386/elf relocations 1115@end deffn 1116@deffn {} BFD_RELOC_X86_64_GOT32 1117@deffnx {} BFD_RELOC_X86_64_PLT32 1118@deffnx {} BFD_RELOC_X86_64_COPY 1119@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1120@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1121@deffnx {} BFD_RELOC_X86_64_RELATIVE 1122@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1123@deffnx {} BFD_RELOC_X86_64_32S 1124@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1125@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1126@deffnx {} BFD_RELOC_X86_64_TPOFF64 1127@deffnx {} BFD_RELOC_X86_64_TLSGD 1128@deffnx {} BFD_RELOC_X86_64_TLSLD 1129@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1130@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1131@deffnx {} BFD_RELOC_X86_64_TPOFF32 1132@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1133@deffnx {} BFD_RELOC_X86_64_GOTPC32 1134@deffnx {} BFD_RELOC_X86_64_GOT64 1135@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1136@deffnx {} BFD_RELOC_X86_64_GOTPC64 1137@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1138@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1139@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1140@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1141@deffnx {} BFD_RELOC_X86_64_TLSDESC 1142@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1143@deffnx {} BFD_RELOC_X86_64_PC32_BND 1144@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1145@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1146@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1147x86-64/elf relocations 1148@end deffn 1149@deffn {} BFD_RELOC_NS32K_IMM_8 1150@deffnx {} BFD_RELOC_NS32K_IMM_16 1151@deffnx {} BFD_RELOC_NS32K_IMM_32 1152@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1153@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1154@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1155@deffnx {} BFD_RELOC_NS32K_DISP_8 1156@deffnx {} BFD_RELOC_NS32K_DISP_16 1157@deffnx {} BFD_RELOC_NS32K_DISP_32 1158@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1159@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1160@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1161ns32k relocations 1162@end deffn 1163@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1164@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1165PDP11 relocations 1166@end deffn 1167@deffn {} BFD_RELOC_PJ_CODE_HI16 1168@deffnx {} BFD_RELOC_PJ_CODE_LO16 1169@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1170@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1171@deffnx {} BFD_RELOC_PJ_CODE_REL16 1172@deffnx {} BFD_RELOC_PJ_CODE_REL32 1173Picojava relocs. Not all of these appear in object files. 1174@end deffn 1175@deffn {} BFD_RELOC_PPC_B26 1176@deffnx {} BFD_RELOC_PPC_BA26 1177@deffnx {} BFD_RELOC_PPC_TOC16 1178@deffnx {} BFD_RELOC_PPC_B16 1179@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1180@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1181@deffnx {} BFD_RELOC_PPC_BA16 1182@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1183@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1184@deffnx {} BFD_RELOC_PPC_COPY 1185@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1186@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1187@deffnx {} BFD_RELOC_PPC_RELATIVE 1188@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1189@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1190@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1191@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1192@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1193@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1194@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1195@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1196@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1197@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1198@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1199@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1200@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1201@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1202@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1203@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1204@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1205@deffnx {} BFD_RELOC_PPC_VLE_REL8 1206@deffnx {} BFD_RELOC_PPC_VLE_REL15 1207@deffnx {} BFD_RELOC_PPC_VLE_REL24 1208@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1209@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1210@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1211@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1212@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1213@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1214@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1215@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1216@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1217@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1218@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1219@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1220@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1221@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1222@deffnx {} BFD_RELOC_PPC_16DX_HA 1223@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1224@deffnx {} BFD_RELOC_PPC64_HIGHER 1225@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1226@deffnx {} BFD_RELOC_PPC64_HIGHEST 1227@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1228@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1229@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1230@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1231@deffnx {} BFD_RELOC_PPC64_TOC 1232@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1233@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1234@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1235@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1236@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1237@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1238@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1239@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1240@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1241@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1242@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1243@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1244@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1245@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1246@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1247@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1248@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1249@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1250@deffnx {} BFD_RELOC_PPC64_ENTRY 1251Power(rs6000) and PowerPC relocations. 1252@end deffn 1253@deffn {} BFD_RELOC_PPC_TLS 1254@deffnx {} BFD_RELOC_PPC_TLSGD 1255@deffnx {} BFD_RELOC_PPC_TLSLD 1256@deffnx {} BFD_RELOC_PPC_DTPMOD 1257@deffnx {} BFD_RELOC_PPC_TPREL16 1258@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1259@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1260@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1261@deffnx {} BFD_RELOC_PPC_TPREL 1262@deffnx {} BFD_RELOC_PPC_DTPREL16 1263@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1264@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1265@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1266@deffnx {} BFD_RELOC_PPC_DTPREL 1267@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1268@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1269@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1270@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1271@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1272@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1273@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1274@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1275@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1276@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1277@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1278@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1279@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1280@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1281@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1282@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1283@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1284@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1285@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1286@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1287@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1288@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1289@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1290@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1291@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1292@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1293@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1294@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1295@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1296@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1297@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1298@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1299PowerPC and PowerPC64 thread-local storage relocations. 1300@end deffn 1301@deffn {} BFD_RELOC_I370_D12 1302IBM 370/390 relocations 1303@end deffn 1304@deffn {} BFD_RELOC_CTOR 1305The type of reloc used to build a constructor table - at the moment 1306probably a 32 bit wide absolute relocation, but the target can choose. 1307It generally does map to one of the other relocation types. 1308@end deffn 1309@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1310ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1311not stored in the instruction. 1312@end deffn 1313@deffn {} BFD_RELOC_ARM_PCREL_BLX 1314ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1315not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1316field in the instruction. 1317@end deffn 1318@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1319Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1320not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1321field in the instruction. 1322@end deffn 1323@deffn {} BFD_RELOC_ARM_PCREL_CALL 1324ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1325@end deffn 1326@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1327ARM 26-bit pc-relative branch for B or conditional BL instruction. 1328@end deffn 1329@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1330@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1331@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1332@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1333@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1334@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1335Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1336The lowest bit must be zero and is not stored in the instruction. 1337Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1338"nn" one smaller in all cases. Note further that BRANCH23 1339corresponds to R_ARM_THM_CALL. 1340@end deffn 1341@deffn {} BFD_RELOC_ARM_OFFSET_IMM 134212-bit immediate offset, used in ARM-format ldr and str instructions. 1343@end deffn 1344@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13455-bit immediate offset, used in Thumb-format ldr and str instructions. 1346@end deffn 1347@deffn {} BFD_RELOC_ARM_TARGET1 1348Pc-relative or absolute relocation depending on target. Used for 1349entries in .init_array sections. 1350@end deffn 1351@deffn {} BFD_RELOC_ARM_ROSEGREL32 1352Read-only segment base relative address. 1353@end deffn 1354@deffn {} BFD_RELOC_ARM_SBREL32 1355Data segment base relative address. 1356@end deffn 1357@deffn {} BFD_RELOC_ARM_TARGET2 1358This reloc is used for references to RTTI data from exception handling 1359tables. The actual definition depends on the target. It may be a 1360pc-relative or some form of GOT-indirect relocation. 1361@end deffn 1362@deffn {} BFD_RELOC_ARM_PREL31 136331-bit PC relative address. 1364@end deffn 1365@deffn {} BFD_RELOC_ARM_MOVW 1366@deffnx {} BFD_RELOC_ARM_MOVT 1367@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1368@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1369@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1370@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1371@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1372@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1373Low and High halfword relocations for MOVW and MOVT instructions. 1374@end deffn 1375@deffn {} BFD_RELOC_ARM_GOTFUNCDESC 1376@deffnx {} BFD_RELOC_ARM_GOTOFFFUNCDESC 1377@deffnx {} BFD_RELOC_ARM_FUNCDESC 1378@deffnx {} BFD_RELOC_ARM_FUNCDESC_VALUE 1379@deffnx {} BFD_RELOC_ARM_TLS_GD32_FDPIC 1380@deffnx {} BFD_RELOC_ARM_TLS_LDM32_FDPIC 1381@deffnx {} BFD_RELOC_ARM_TLS_IE32_FDPIC 1382ARM FDPIC specific relocations. 1383@end deffn 1384@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1385@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1386@deffnx {} BFD_RELOC_ARM_GOT32 1387@deffnx {} BFD_RELOC_ARM_PLT32 1388@deffnx {} BFD_RELOC_ARM_RELATIVE 1389@deffnx {} BFD_RELOC_ARM_GOTOFF 1390@deffnx {} BFD_RELOC_ARM_GOTPC 1391@deffnx {} BFD_RELOC_ARM_GOT_PREL 1392Relocations for setting up GOTs and PLTs for shared libraries. 1393@end deffn 1394@deffn {} BFD_RELOC_ARM_TLS_GD32 1395@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1396@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1397@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1398@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1399@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1400@deffnx {} BFD_RELOC_ARM_TLS_IE32 1401@deffnx {} BFD_RELOC_ARM_TLS_LE32 1402@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1403@deffnx {} BFD_RELOC_ARM_TLS_CALL 1404@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1405@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1406@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1407@deffnx {} BFD_RELOC_ARM_TLS_DESC 1408ARM thread-local storage relocations. 1409@end deffn 1410@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1411@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1412@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1413@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1414@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1415@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1416@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1417@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1418@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1419@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1420@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1421@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1422@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1423@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1424@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1425@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1426@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1427@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1428@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1429@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1430@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1431@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1432@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1433@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1434@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1435@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1436@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1437@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1438ARM group relocations. 1439@end deffn 1440@deffn {} BFD_RELOC_ARM_V4BX 1441Annotation of BX instructions. 1442@end deffn 1443@deffn {} BFD_RELOC_ARM_IRELATIVE 1444ARM support for STT_GNU_IFUNC. 1445@end deffn 1446@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1447@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1448@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1449@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1450Thumb1 relocations to support execute-only code. 1451@end deffn 1452@deffn {} BFD_RELOC_ARM_IMMEDIATE 1453@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1454@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1455@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1456@deffnx {} BFD_RELOC_ARM_T32_IMM12 1457@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1458@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1459@deffnx {} BFD_RELOC_ARM_SMC 1460@deffnx {} BFD_RELOC_ARM_HVC 1461@deffnx {} BFD_RELOC_ARM_SWI 1462@deffnx {} BFD_RELOC_ARM_MULTI 1463@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1464@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1465@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1466@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1467@deffnx {} BFD_RELOC_ARM_ADR_IMM 1468@deffnx {} BFD_RELOC_ARM_LDR_IMM 1469@deffnx {} BFD_RELOC_ARM_LITERAL 1470@deffnx {} BFD_RELOC_ARM_IN_POOL 1471@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1472@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1473@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1474@deffnx {} BFD_RELOC_ARM_HWLITERAL 1475@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1476@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1477@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1478These relocs are only used within the ARM assembler. They are not 1479(at present) written to any object files. 1480@end deffn 1481@deffn {} BFD_RELOC_SH_PCDISP8BY2 1482@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1483@deffnx {} BFD_RELOC_SH_IMM3 1484@deffnx {} BFD_RELOC_SH_IMM3U 1485@deffnx {} BFD_RELOC_SH_DISP12 1486@deffnx {} BFD_RELOC_SH_DISP12BY2 1487@deffnx {} BFD_RELOC_SH_DISP12BY4 1488@deffnx {} BFD_RELOC_SH_DISP12BY8 1489@deffnx {} BFD_RELOC_SH_DISP20 1490@deffnx {} BFD_RELOC_SH_DISP20BY8 1491@deffnx {} BFD_RELOC_SH_IMM4 1492@deffnx {} BFD_RELOC_SH_IMM4BY2 1493@deffnx {} BFD_RELOC_SH_IMM4BY4 1494@deffnx {} BFD_RELOC_SH_IMM8 1495@deffnx {} BFD_RELOC_SH_IMM8BY2 1496@deffnx {} BFD_RELOC_SH_IMM8BY4 1497@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1498@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1499@deffnx {} BFD_RELOC_SH_SWITCH16 1500@deffnx {} BFD_RELOC_SH_SWITCH32 1501@deffnx {} BFD_RELOC_SH_USES 1502@deffnx {} BFD_RELOC_SH_COUNT 1503@deffnx {} BFD_RELOC_SH_ALIGN 1504@deffnx {} BFD_RELOC_SH_CODE 1505@deffnx {} BFD_RELOC_SH_DATA 1506@deffnx {} BFD_RELOC_SH_LABEL 1507@deffnx {} BFD_RELOC_SH_LOOP_START 1508@deffnx {} BFD_RELOC_SH_LOOP_END 1509@deffnx {} BFD_RELOC_SH_COPY 1510@deffnx {} BFD_RELOC_SH_GLOB_DAT 1511@deffnx {} BFD_RELOC_SH_JMP_SLOT 1512@deffnx {} BFD_RELOC_SH_RELATIVE 1513@deffnx {} BFD_RELOC_SH_GOTPC 1514@deffnx {} BFD_RELOC_SH_GOT_LOW16 1515@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1516@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1517@deffnx {} BFD_RELOC_SH_GOT_HI16 1518@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1519@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1520@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1521@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1522@deffnx {} BFD_RELOC_SH_PLT_LOW16 1523@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1524@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1525@deffnx {} BFD_RELOC_SH_PLT_HI16 1526@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1527@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1528@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1529@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1530@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1531@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1532@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1533@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1534@deffnx {} BFD_RELOC_SH_COPY64 1535@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1536@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1537@deffnx {} BFD_RELOC_SH_RELATIVE64 1538@deffnx {} BFD_RELOC_SH_GOT10BY4 1539@deffnx {} BFD_RELOC_SH_GOT10BY8 1540@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1541@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1542@deffnx {} BFD_RELOC_SH_GOTPLT32 1543@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1544@deffnx {} BFD_RELOC_SH_IMMU5 1545@deffnx {} BFD_RELOC_SH_IMMS6 1546@deffnx {} BFD_RELOC_SH_IMMS6BY32 1547@deffnx {} BFD_RELOC_SH_IMMU6 1548@deffnx {} BFD_RELOC_SH_IMMS10 1549@deffnx {} BFD_RELOC_SH_IMMS10BY2 1550@deffnx {} BFD_RELOC_SH_IMMS10BY4 1551@deffnx {} BFD_RELOC_SH_IMMS10BY8 1552@deffnx {} BFD_RELOC_SH_IMMS16 1553@deffnx {} BFD_RELOC_SH_IMMU16 1554@deffnx {} BFD_RELOC_SH_IMM_LOW16 1555@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1556@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1557@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1558@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1559@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1560@deffnx {} BFD_RELOC_SH_IMM_HI16 1561@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1562@deffnx {} BFD_RELOC_SH_PT_16 1563@deffnx {} BFD_RELOC_SH_TLS_GD_32 1564@deffnx {} BFD_RELOC_SH_TLS_LD_32 1565@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1566@deffnx {} BFD_RELOC_SH_TLS_IE_32 1567@deffnx {} BFD_RELOC_SH_TLS_LE_32 1568@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1569@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1570@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1571@deffnx {} BFD_RELOC_SH_GOT20 1572@deffnx {} BFD_RELOC_SH_GOTOFF20 1573@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1574@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1575@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1576@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1577@deffnx {} BFD_RELOC_SH_FUNCDESC 1578Renesas / SuperH SH relocs. Not all of these appear in object files. 1579@end deffn 1580@deffn {} BFD_RELOC_ARC_NONE 1581@deffnx {} BFD_RELOC_ARC_8 1582@deffnx {} BFD_RELOC_ARC_16 1583@deffnx {} BFD_RELOC_ARC_24 1584@deffnx {} BFD_RELOC_ARC_32 1585@deffnx {} BFD_RELOC_ARC_N8 1586@deffnx {} BFD_RELOC_ARC_N16 1587@deffnx {} BFD_RELOC_ARC_N24 1588@deffnx {} BFD_RELOC_ARC_N32 1589@deffnx {} BFD_RELOC_ARC_SDA 1590@deffnx {} BFD_RELOC_ARC_SECTOFF 1591@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1592@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1593@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1594@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1595@deffnx {} BFD_RELOC_ARC_SDA32 1596@deffnx {} BFD_RELOC_ARC_SDA_LDST 1597@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1598@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1599@deffnx {} BFD_RELOC_ARC_SDA16_LD 1600@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1601@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1602@deffnx {} BFD_RELOC_ARC_S13_PCREL 1603@deffnx {} BFD_RELOC_ARC_W 1604@deffnx {} BFD_RELOC_ARC_32_ME 1605@deffnx {} BFD_RELOC_ARC_32_ME_S 1606@deffnx {} BFD_RELOC_ARC_N32_ME 1607@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1608@deffnx {} BFD_RELOC_ARC_SDA32_ME 1609@deffnx {} BFD_RELOC_ARC_W_ME 1610@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1611@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1612@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1613@deffnx {} BFD_RELOC_AC_SECTOFF_S9 1614@deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1615@deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1616@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1617@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1618@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1619@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1620@deffnx {} BFD_RELOC_ARC_SDA_12 1621@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1622@deffnx {} BFD_RELOC_ARC_32_PCREL 1623@deffnx {} BFD_RELOC_ARC_PC32 1624@deffnx {} BFD_RELOC_ARC_GOT32 1625@deffnx {} BFD_RELOC_ARC_GOTPC32 1626@deffnx {} BFD_RELOC_ARC_PLT32 1627@deffnx {} BFD_RELOC_ARC_COPY 1628@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1629@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1630@deffnx {} BFD_RELOC_ARC_RELATIVE 1631@deffnx {} BFD_RELOC_ARC_GOTOFF 1632@deffnx {} BFD_RELOC_ARC_GOTPC 1633@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1634@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1635@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1636@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1637@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1638@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1639@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1640@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1641@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1642@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1643@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1644@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1645@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1646@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1647@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1648@deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1649ARC relocs. 1650@end deffn 1651@deffn {} BFD_RELOC_BFIN_16_IMM 1652ADI Blackfin 16 bit immediate absolute reloc. 1653@end deffn 1654@deffn {} BFD_RELOC_BFIN_16_HIGH 1655ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1656@end deffn 1657@deffn {} BFD_RELOC_BFIN_4_PCREL 1658ADI Blackfin 'a' part of LSETUP. 1659@end deffn 1660@deffn {} BFD_RELOC_BFIN_5_PCREL 1661ADI Blackfin. 1662@end deffn 1663@deffn {} BFD_RELOC_BFIN_16_LOW 1664ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1665@end deffn 1666@deffn {} BFD_RELOC_BFIN_10_PCREL 1667ADI Blackfin. 1668@end deffn 1669@deffn {} BFD_RELOC_BFIN_11_PCREL 1670ADI Blackfin 'b' part of LSETUP. 1671@end deffn 1672@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1673ADI Blackfin. 1674@end deffn 1675@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1676ADI Blackfin Short jump, pcrel. 1677@end deffn 1678@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1679ADI Blackfin Call.x not implemented. 1680@end deffn 1681@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1682ADI Blackfin Long Jump pcrel. 1683@end deffn 1684@deffn {} BFD_RELOC_BFIN_GOT17M4 1685@deffnx {} BFD_RELOC_BFIN_GOTHI 1686@deffnx {} BFD_RELOC_BFIN_GOTLO 1687@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1688@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1689@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1690@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1691@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1692@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1693@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1694@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1695@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1696@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1697@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1698ADI Blackfin FD-PIC relocations. 1699@end deffn 1700@deffn {} BFD_RELOC_BFIN_GOT 1701ADI Blackfin GOT relocation. 1702@end deffn 1703@deffn {} BFD_RELOC_BFIN_PLTPC 1704ADI Blackfin PLTPC relocation. 1705@end deffn 1706@deffn {} BFD_ARELOC_BFIN_PUSH 1707ADI Blackfin arithmetic relocation. 1708@end deffn 1709@deffn {} BFD_ARELOC_BFIN_CONST 1710ADI Blackfin arithmetic relocation. 1711@end deffn 1712@deffn {} BFD_ARELOC_BFIN_ADD 1713ADI Blackfin arithmetic relocation. 1714@end deffn 1715@deffn {} BFD_ARELOC_BFIN_SUB 1716ADI Blackfin arithmetic relocation. 1717@end deffn 1718@deffn {} BFD_ARELOC_BFIN_MULT 1719ADI Blackfin arithmetic relocation. 1720@end deffn 1721@deffn {} BFD_ARELOC_BFIN_DIV 1722ADI Blackfin arithmetic relocation. 1723@end deffn 1724@deffn {} BFD_ARELOC_BFIN_MOD 1725ADI Blackfin arithmetic relocation. 1726@end deffn 1727@deffn {} BFD_ARELOC_BFIN_LSHIFT 1728ADI Blackfin arithmetic relocation. 1729@end deffn 1730@deffn {} BFD_ARELOC_BFIN_RSHIFT 1731ADI Blackfin arithmetic relocation. 1732@end deffn 1733@deffn {} BFD_ARELOC_BFIN_AND 1734ADI Blackfin arithmetic relocation. 1735@end deffn 1736@deffn {} BFD_ARELOC_BFIN_OR 1737ADI Blackfin arithmetic relocation. 1738@end deffn 1739@deffn {} BFD_ARELOC_BFIN_XOR 1740ADI Blackfin arithmetic relocation. 1741@end deffn 1742@deffn {} BFD_ARELOC_BFIN_LAND 1743ADI Blackfin arithmetic relocation. 1744@end deffn 1745@deffn {} BFD_ARELOC_BFIN_LOR 1746ADI Blackfin arithmetic relocation. 1747@end deffn 1748@deffn {} BFD_ARELOC_BFIN_LEN 1749ADI Blackfin arithmetic relocation. 1750@end deffn 1751@deffn {} BFD_ARELOC_BFIN_NEG 1752ADI Blackfin arithmetic relocation. 1753@end deffn 1754@deffn {} BFD_ARELOC_BFIN_COMP 1755ADI Blackfin arithmetic relocation. 1756@end deffn 1757@deffn {} BFD_ARELOC_BFIN_PAGE 1758ADI Blackfin arithmetic relocation. 1759@end deffn 1760@deffn {} BFD_ARELOC_BFIN_HWPAGE 1761ADI Blackfin arithmetic relocation. 1762@end deffn 1763@deffn {} BFD_ARELOC_BFIN_ADDR 1764ADI Blackfin arithmetic relocation. 1765@end deffn 1766@deffn {} BFD_RELOC_D10V_10_PCREL_R 1767Mitsubishi D10V relocs. 1768This is a 10-bit reloc with the right 2 bits 1769assumed to be 0. 1770@end deffn 1771@deffn {} BFD_RELOC_D10V_10_PCREL_L 1772Mitsubishi D10V relocs. 1773This is a 10-bit reloc with the right 2 bits 1774assumed to be 0. This is the same as the previous reloc 1775except it is in the left container, i.e., 1776shifted left 15 bits. 1777@end deffn 1778@deffn {} BFD_RELOC_D10V_18 1779This is an 18-bit reloc with the right 2 bits 1780assumed to be 0. 1781@end deffn 1782@deffn {} BFD_RELOC_D10V_18_PCREL 1783This is an 18-bit reloc with the right 2 bits 1784assumed to be 0. 1785@end deffn 1786@deffn {} BFD_RELOC_D30V_6 1787Mitsubishi D30V relocs. 1788This is a 6-bit absolute reloc. 1789@end deffn 1790@deffn {} BFD_RELOC_D30V_9_PCREL 1791This is a 6-bit pc-relative reloc with 1792the right 3 bits assumed to be 0. 1793@end deffn 1794@deffn {} BFD_RELOC_D30V_9_PCREL_R 1795This is a 6-bit pc-relative reloc with 1796the right 3 bits assumed to be 0. Same 1797as the previous reloc but on the right side 1798of the container. 1799@end deffn 1800@deffn {} BFD_RELOC_D30V_15 1801This is a 12-bit absolute reloc with the 1802right 3 bitsassumed to be 0. 1803@end deffn 1804@deffn {} BFD_RELOC_D30V_15_PCREL 1805This is a 12-bit pc-relative reloc with 1806the right 3 bits assumed to be 0. 1807@end deffn 1808@deffn {} BFD_RELOC_D30V_15_PCREL_R 1809This is a 12-bit pc-relative reloc with 1810the right 3 bits assumed to be 0. Same 1811as the previous reloc but on the right side 1812of the container. 1813@end deffn 1814@deffn {} BFD_RELOC_D30V_21 1815This is an 18-bit absolute reloc with 1816the right 3 bits assumed to be 0. 1817@end deffn 1818@deffn {} BFD_RELOC_D30V_21_PCREL 1819This is an 18-bit pc-relative reloc with 1820the right 3 bits assumed to be 0. 1821@end deffn 1822@deffn {} BFD_RELOC_D30V_21_PCREL_R 1823This is an 18-bit pc-relative reloc with 1824the right 3 bits assumed to be 0. Same 1825as the previous reloc but on the right side 1826of the container. 1827@end deffn 1828@deffn {} BFD_RELOC_D30V_32 1829This is a 32-bit absolute reloc. 1830@end deffn 1831@deffn {} BFD_RELOC_D30V_32_PCREL 1832This is a 32-bit pc-relative reloc. 1833@end deffn 1834@deffn {} BFD_RELOC_DLX_HI16_S 1835DLX relocs 1836@end deffn 1837@deffn {} BFD_RELOC_DLX_LO16 1838DLX relocs 1839@end deffn 1840@deffn {} BFD_RELOC_DLX_JMP26 1841DLX relocs 1842@end deffn 1843@deffn {} BFD_RELOC_M32C_HI8 1844@deffnx {} BFD_RELOC_M32C_RL_JUMP 1845@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1846@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1847Renesas M16C/M32C Relocations. 1848@end deffn 1849@deffn {} BFD_RELOC_M32R_24 1850Renesas M32R (formerly Mitsubishi M32R) relocs. 1851This is a 24 bit absolute address. 1852@end deffn 1853@deffn {} BFD_RELOC_M32R_10_PCREL 1854This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1855@end deffn 1856@deffn {} BFD_RELOC_M32R_18_PCREL 1857This is an 18-bit reloc with the right 2 bits assumed to be 0. 1858@end deffn 1859@deffn {} BFD_RELOC_M32R_26_PCREL 1860This is a 26-bit reloc with the right 2 bits assumed to be 0. 1861@end deffn 1862@deffn {} BFD_RELOC_M32R_HI16_ULO 1863This is a 16-bit reloc containing the high 16 bits of an address 1864used when the lower 16 bits are treated as unsigned. 1865@end deffn 1866@deffn {} BFD_RELOC_M32R_HI16_SLO 1867This is a 16-bit reloc containing the high 16 bits of an address 1868used when the lower 16 bits are treated as signed. 1869@end deffn 1870@deffn {} BFD_RELOC_M32R_LO16 1871This is a 16-bit reloc containing the lower 16 bits of an address. 1872@end deffn 1873@deffn {} BFD_RELOC_M32R_SDA16 1874This is a 16-bit reloc containing the small data area offset for use in 1875add3, load, and store instructions. 1876@end deffn 1877@deffn {} BFD_RELOC_M32R_GOT24 1878@deffnx {} BFD_RELOC_M32R_26_PLTREL 1879@deffnx {} BFD_RELOC_M32R_COPY 1880@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1881@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1882@deffnx {} BFD_RELOC_M32R_RELATIVE 1883@deffnx {} BFD_RELOC_M32R_GOTOFF 1884@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1885@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1886@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1887@deffnx {} BFD_RELOC_M32R_GOTPC24 1888@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1889@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1890@deffnx {} BFD_RELOC_M32R_GOT16_LO 1891@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1892@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1893@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1894For PIC. 1895@end deffn 1896@deffn {} BFD_RELOC_NDS32_20 1897NDS32 relocs. 1898This is a 20 bit absolute address. 1899@end deffn 1900@deffn {} BFD_RELOC_NDS32_9_PCREL 1901This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1902@end deffn 1903@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1904This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1905@end deffn 1906@deffn {} BFD_RELOC_NDS32_15_PCREL 1907This is an 15-bit reloc with the right 1 bit assumed to be 0. 1908@end deffn 1909@deffn {} BFD_RELOC_NDS32_17_PCREL 1910This is an 17-bit reloc with the right 1 bit assumed to be 0. 1911@end deffn 1912@deffn {} BFD_RELOC_NDS32_25_PCREL 1913This is a 25-bit reloc with the right 1 bit assumed to be 0. 1914@end deffn 1915@deffn {} BFD_RELOC_NDS32_HI20 1916This is a 20-bit reloc containing the high 20 bits of an address 1917used with the lower 12 bits 1918@end deffn 1919@deffn {} BFD_RELOC_NDS32_LO12S3 1920This is a 12-bit reloc containing the lower 12 bits of an address 1921then shift right by 3. This is used with ldi,sdi... 1922@end deffn 1923@deffn {} BFD_RELOC_NDS32_LO12S2 1924This is a 12-bit reloc containing the lower 12 bits of an address 1925then shift left by 2. This is used with lwi,swi... 1926@end deffn 1927@deffn {} BFD_RELOC_NDS32_LO12S1 1928This is a 12-bit reloc containing the lower 12 bits of an address 1929then shift left by 1. This is used with lhi,shi... 1930@end deffn 1931@deffn {} BFD_RELOC_NDS32_LO12S0 1932This is a 12-bit reloc containing the lower 12 bits of an address 1933then shift left by 0. This is used with lbisbi... 1934@end deffn 1935@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1936This is a 12-bit reloc containing the lower 12 bits of an address 1937then shift left by 0. This is only used with branch relaxations 1938@end deffn 1939@deffn {} BFD_RELOC_NDS32_SDA15S3 1940This is a 15-bit reloc containing the small data area 18-bit signed offset 1941and shift left by 3 for use in ldi, sdi... 1942@end deffn 1943@deffn {} BFD_RELOC_NDS32_SDA15S2 1944This is a 15-bit reloc containing the small data area 17-bit signed offset 1945and shift left by 2 for use in lwi, swi... 1946@end deffn 1947@deffn {} BFD_RELOC_NDS32_SDA15S1 1948This is a 15-bit reloc containing the small data area 16-bit signed offset 1949and shift left by 1 for use in lhi, shi... 1950@end deffn 1951@deffn {} BFD_RELOC_NDS32_SDA15S0 1952This is a 15-bit reloc containing the small data area 15-bit signed offset 1953and shift left by 0 for use in lbi, sbi... 1954@end deffn 1955@deffn {} BFD_RELOC_NDS32_SDA16S3 1956This is a 16-bit reloc containing the small data area 16-bit signed offset 1957and shift left by 3 1958@end deffn 1959@deffn {} BFD_RELOC_NDS32_SDA17S2 1960This is a 17-bit reloc containing the small data area 17-bit signed offset 1961and shift left by 2 for use in lwi.gp, swi.gp... 1962@end deffn 1963@deffn {} BFD_RELOC_NDS32_SDA18S1 1964This is a 18-bit reloc containing the small data area 18-bit signed offset 1965and shift left by 1 for use in lhi.gp, shi.gp... 1966@end deffn 1967@deffn {} BFD_RELOC_NDS32_SDA19S0 1968This is a 19-bit reloc containing the small data area 19-bit signed offset 1969and shift left by 0 for use in lbi.gp, sbi.gp... 1970@end deffn 1971@deffn {} BFD_RELOC_NDS32_GOT20 1972@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1973@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1974@deffnx {} BFD_RELOC_NDS32_COPY 1975@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1976@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1977@deffnx {} BFD_RELOC_NDS32_RELATIVE 1978@deffnx {} BFD_RELOC_NDS32_GOTOFF 1979@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1980@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1981@deffnx {} BFD_RELOC_NDS32_GOTPC20 1982@deffnx {} BFD_RELOC_NDS32_GOT_HI20 1983@deffnx {} BFD_RELOC_NDS32_GOT_LO12 1984@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1985@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1986for PIC 1987@end deffn 1988@deffn {} BFD_RELOC_NDS32_INSN16 1989@deffnx {} BFD_RELOC_NDS32_LABEL 1990@deffnx {} BFD_RELOC_NDS32_LONGCALL1 1991@deffnx {} BFD_RELOC_NDS32_LONGCALL2 1992@deffnx {} BFD_RELOC_NDS32_LONGCALL3 1993@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1994@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1995@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1996@deffnx {} BFD_RELOC_NDS32_LOADSTORE 1997@deffnx {} BFD_RELOC_NDS32_9_FIXED 1998@deffnx {} BFD_RELOC_NDS32_15_FIXED 1999@deffnx {} BFD_RELOC_NDS32_17_FIXED 2000@deffnx {} BFD_RELOC_NDS32_25_FIXED 2001@deffnx {} BFD_RELOC_NDS32_LONGCALL4 2002@deffnx {} BFD_RELOC_NDS32_LONGCALL5 2003@deffnx {} BFD_RELOC_NDS32_LONGCALL6 2004@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 2005@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 2006@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 2007@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 2008for relax 2009@end deffn 2010@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 2011@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 2012@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 2013@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 2014for PIC 2015@end deffn 2016@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 2017@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 2018@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 2019@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 2020for floating point 2021@end deffn 2022@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 2023@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 2024@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 2025for dwarf2 debug_line. 2026@end deffn 2027@deffn {} BFD_RELOC_NDS32_UPDATE_TA 2028for eliminate 16-bit instructions 2029@end deffn 2030@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2031@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2032@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2033@deffnx {} BFD_RELOC_NDS32_GOT_LO15 2034@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2035@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2036@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2037@deffnx {} BFD_RELOC_NDS32_GOT15S2 2038@deffnx {} BFD_RELOC_NDS32_GOT17S2 2039for PIC object relaxation 2040@end deffn 2041@deffn {} BFD_RELOC_NDS32_5 2042NDS32 relocs. 2043This is a 5 bit absolute address. 2044@end deffn 2045@deffn {} BFD_RELOC_NDS32_10_UPCREL 2046This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2047@end deffn 2048@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2049If fp were omitted, fp can used as another gp. 2050@end deffn 2051@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2052@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2053@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2054@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2055@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2056@deffnx {} BFD_RELOC_NDS32_PTR 2057@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2058@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2059@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2060@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2061@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2062@deffnx {} BFD_RELOC_NDS32_MINUEND 2063@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2064@deffnx {} BFD_RELOC_NDS32_DIFF8 2065@deffnx {} BFD_RELOC_NDS32_DIFF16 2066@deffnx {} BFD_RELOC_NDS32_DIFF32 2067@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2068@deffnx {} BFD_RELOC_NDS32_EMPTY 2069relaxation relative relocation types 2070@end deffn 2071@deffn {} BFD_RELOC_NDS32_25_ABS 2072This is a 25 bit absolute address. 2073@end deffn 2074@deffn {} BFD_RELOC_NDS32_DATA 2075@deffnx {} BFD_RELOC_NDS32_TRAN 2076@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2077@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2078For ex9 and ifc using. 2079@end deffn 2080@deffn {} BFD_RELOC_NDS32_TPOFF 2081@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2082@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2083@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2084@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2085@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2086@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2087@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2088@deffnx {} BFD_RELOC_NDS32_TLS_TPOFF 2089@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2090@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2091@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2092@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2093For TLS. 2094@end deffn 2095@deffn {} BFD_RELOC_V850_9_PCREL 2096This is a 9-bit reloc 2097@end deffn 2098@deffn {} BFD_RELOC_V850_22_PCREL 2099This is a 22-bit reloc 2100@end deffn 2101@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2102This is a 16 bit offset from the short data area pointer. 2103@end deffn 2104@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2105This is a 16 bit offset (of which only 15 bits are used) from the 2106short data area pointer. 2107@end deffn 2108@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2109This is a 16 bit offset from the zero data area pointer. 2110@end deffn 2111@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2112This is a 16 bit offset (of which only 15 bits are used) from the 2113zero data area pointer. 2114@end deffn 2115@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2116This is an 8 bit offset (of which only 6 bits are used) from the 2117tiny data area pointer. 2118@end deffn 2119@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2120This is an 8bit offset (of which only 7 bits are used) from the tiny 2121data area pointer. 2122@end deffn 2123@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2124This is a 7 bit offset from the tiny data area pointer. 2125@end deffn 2126@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2127This is a 16 bit offset from the tiny data area pointer. 2128@end deffn 2129@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2130This is a 5 bit offset (of which only 4 bits are used) from the tiny 2131data area pointer. 2132@end deffn 2133@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2134This is a 4 bit offset from the tiny data area pointer. 2135@end deffn 2136@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2137This is a 16 bit offset from the short data area pointer, with the 2138bits placed non-contiguously in the instruction. 2139@end deffn 2140@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2141This is a 16 bit offset from the zero data area pointer, with the 2142bits placed non-contiguously in the instruction. 2143@end deffn 2144@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2145This is a 6 bit offset from the call table base pointer. 2146@end deffn 2147@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2148This is a 16 bit offset from the call table base pointer. 2149@end deffn 2150@deffn {} BFD_RELOC_V850_LONGCALL 2151Used for relaxing indirect function calls. 2152@end deffn 2153@deffn {} BFD_RELOC_V850_LONGJUMP 2154Used for relaxing indirect jumps. 2155@end deffn 2156@deffn {} BFD_RELOC_V850_ALIGN 2157Used to maintain alignment whilst relaxing. 2158@end deffn 2159@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2160This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2161instructions. 2162@end deffn 2163@deffn {} BFD_RELOC_V850_16_PCREL 2164This is a 16-bit reloc. 2165@end deffn 2166@deffn {} BFD_RELOC_V850_17_PCREL 2167This is a 17-bit reloc. 2168@end deffn 2169@deffn {} BFD_RELOC_V850_23 2170This is a 23-bit reloc. 2171@end deffn 2172@deffn {} BFD_RELOC_V850_32_PCREL 2173This is a 32-bit reloc. 2174@end deffn 2175@deffn {} BFD_RELOC_V850_32_ABS 2176This is a 32-bit reloc. 2177@end deffn 2178@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2179This is a 16-bit reloc. 2180@end deffn 2181@deffn {} BFD_RELOC_V850_16_S1 2182This is a 16-bit reloc. 2183@end deffn 2184@deffn {} BFD_RELOC_V850_LO16_S1 2185Low 16 bits. 16 bit shifted by 1. 2186@end deffn 2187@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2188This is a 16 bit offset from the call table base pointer. 2189@end deffn 2190@deffn {} BFD_RELOC_V850_32_GOTPCREL 2191DSO relocations. 2192@end deffn 2193@deffn {} BFD_RELOC_V850_16_GOT 2194DSO relocations. 2195@end deffn 2196@deffn {} BFD_RELOC_V850_32_GOT 2197DSO relocations. 2198@end deffn 2199@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2200DSO relocations. 2201@end deffn 2202@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2203DSO relocations. 2204@end deffn 2205@deffn {} BFD_RELOC_V850_COPY 2206DSO relocations. 2207@end deffn 2208@deffn {} BFD_RELOC_V850_GLOB_DAT 2209DSO relocations. 2210@end deffn 2211@deffn {} BFD_RELOC_V850_JMP_SLOT 2212DSO relocations. 2213@end deffn 2214@deffn {} BFD_RELOC_V850_RELATIVE 2215DSO relocations. 2216@end deffn 2217@deffn {} BFD_RELOC_V850_16_GOTOFF 2218DSO relocations. 2219@end deffn 2220@deffn {} BFD_RELOC_V850_32_GOTOFF 2221DSO relocations. 2222@end deffn 2223@deffn {} BFD_RELOC_V850_CODE 2224start code. 2225@end deffn 2226@deffn {} BFD_RELOC_V850_DATA 2227start data in text. 2228@end deffn 2229@deffn {} BFD_RELOC_TIC30_LDP 2230This is a 8bit DP reloc for the tms320c30, where the most 2231significant 8 bits of a 24 bit word are placed into the least 2232significant 8 bits of the opcode. 2233@end deffn 2234@deffn {} BFD_RELOC_TIC54X_PARTLS7 2235This is a 7bit reloc for the tms320c54x, where the least 2236significant 7 bits of a 16 bit word are placed into the least 2237significant 7 bits of the opcode. 2238@end deffn 2239@deffn {} BFD_RELOC_TIC54X_PARTMS9 2240This is a 9bit DP reloc for the tms320c54x, where the most 2241significant 9 bits of a 16 bit word are placed into the least 2242significant 9 bits of the opcode. 2243@end deffn 2244@deffn {} BFD_RELOC_TIC54X_23 2245This is an extended address 23-bit reloc for the tms320c54x. 2246@end deffn 2247@deffn {} BFD_RELOC_TIC54X_16_OF_23 2248This is a 16-bit reloc for the tms320c54x, where the least 2249significant 16 bits of a 23-bit extended address are placed into 2250the opcode. 2251@end deffn 2252@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2253This is a reloc for the tms320c54x, where the most 2254significant 7 bits of a 23-bit extended address are placed into 2255the opcode. 2256@end deffn 2257@deffn {} BFD_RELOC_C6000_PCR_S21 2258@deffnx {} BFD_RELOC_C6000_PCR_S12 2259@deffnx {} BFD_RELOC_C6000_PCR_S10 2260@deffnx {} BFD_RELOC_C6000_PCR_S7 2261@deffnx {} BFD_RELOC_C6000_ABS_S16 2262@deffnx {} BFD_RELOC_C6000_ABS_L16 2263@deffnx {} BFD_RELOC_C6000_ABS_H16 2264@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2265@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2266@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2267@deffnx {} BFD_RELOC_C6000_SBR_S16 2268@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2269@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2270@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2271@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2272@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2273@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2274@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2275@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2276@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2277@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2278@deffnx {} BFD_RELOC_C6000_PREL31 2279@deffnx {} BFD_RELOC_C6000_COPY 2280@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2281@deffnx {} BFD_RELOC_C6000_EHTYPE 2282@deffnx {} BFD_RELOC_C6000_PCR_H16 2283@deffnx {} BFD_RELOC_C6000_PCR_L16 2284@deffnx {} BFD_RELOC_C6000_ALIGN 2285@deffnx {} BFD_RELOC_C6000_FPHEAD 2286@deffnx {} BFD_RELOC_C6000_NOCMP 2287TMS320C6000 relocations. 2288@end deffn 2289@deffn {} BFD_RELOC_FR30_48 2290This is a 48 bit reloc for the FR30 that stores 32 bits. 2291@end deffn 2292@deffn {} BFD_RELOC_FR30_20 2293This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2294two sections. 2295@end deffn 2296@deffn {} BFD_RELOC_FR30_6_IN_4 2297This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 22984 bits. 2299@end deffn 2300@deffn {} BFD_RELOC_FR30_8_IN_8 2301This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2302into 8 bits. 2303@end deffn 2304@deffn {} BFD_RELOC_FR30_9_IN_8 2305This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2306into 8 bits. 2307@end deffn 2308@deffn {} BFD_RELOC_FR30_10_IN_8 2309This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2310into 8 bits. 2311@end deffn 2312@deffn {} BFD_RELOC_FR30_9_PCREL 2313This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2314short offset into 8 bits. 2315@end deffn 2316@deffn {} BFD_RELOC_FR30_12_PCREL 2317This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2318short offset into 11 bits. 2319@end deffn 2320@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2321@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2322@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2323@deffnx {} BFD_RELOC_MCORE_PCREL_32 2324@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2325@deffnx {} BFD_RELOC_MCORE_RVA 2326Motorola Mcore relocations. 2327@end deffn 2328@deffn {} BFD_RELOC_MEP_8 2329@deffnx {} BFD_RELOC_MEP_16 2330@deffnx {} BFD_RELOC_MEP_32 2331@deffnx {} BFD_RELOC_MEP_PCREL8A2 2332@deffnx {} BFD_RELOC_MEP_PCREL12A2 2333@deffnx {} BFD_RELOC_MEP_PCREL17A2 2334@deffnx {} BFD_RELOC_MEP_PCREL24A2 2335@deffnx {} BFD_RELOC_MEP_PCABS24A2 2336@deffnx {} BFD_RELOC_MEP_LOW16 2337@deffnx {} BFD_RELOC_MEP_HI16U 2338@deffnx {} BFD_RELOC_MEP_HI16S 2339@deffnx {} BFD_RELOC_MEP_GPREL 2340@deffnx {} BFD_RELOC_MEP_TPREL 2341@deffnx {} BFD_RELOC_MEP_TPREL7 2342@deffnx {} BFD_RELOC_MEP_TPREL7A2 2343@deffnx {} BFD_RELOC_MEP_TPREL7A4 2344@deffnx {} BFD_RELOC_MEP_UIMM24 2345@deffnx {} BFD_RELOC_MEP_ADDR24A4 2346@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2347@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2348Toshiba Media Processor Relocations. 2349@end deffn 2350@deffn {} BFD_RELOC_METAG_HIADDR16 2351@deffnx {} BFD_RELOC_METAG_LOADDR16 2352@deffnx {} BFD_RELOC_METAG_RELBRANCH 2353@deffnx {} BFD_RELOC_METAG_GETSETOFF 2354@deffnx {} BFD_RELOC_METAG_HIOG 2355@deffnx {} BFD_RELOC_METAG_LOOG 2356@deffnx {} BFD_RELOC_METAG_REL8 2357@deffnx {} BFD_RELOC_METAG_REL16 2358@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2359@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2360@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2361@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2362@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2363@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2364@deffnx {} BFD_RELOC_METAG_HI16_PLT 2365@deffnx {} BFD_RELOC_METAG_LO16_PLT 2366@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2367@deffnx {} BFD_RELOC_METAG_GOTOFF 2368@deffnx {} BFD_RELOC_METAG_PLT 2369@deffnx {} BFD_RELOC_METAG_COPY 2370@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2371@deffnx {} BFD_RELOC_METAG_RELATIVE 2372@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2373@deffnx {} BFD_RELOC_METAG_TLS_GD 2374@deffnx {} BFD_RELOC_METAG_TLS_LDM 2375@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2376@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2377@deffnx {} BFD_RELOC_METAG_TLS_LDO 2378@deffnx {} BFD_RELOC_METAG_TLS_IE 2379@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2380@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2381@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2382@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2383@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2384@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2385@deffnx {} BFD_RELOC_METAG_TLS_LE 2386@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2387@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2388Imagination Technologies Meta relocations. 2389@end deffn 2390@deffn {} BFD_RELOC_MMIX_GETA 2391@deffnx {} BFD_RELOC_MMIX_GETA_1 2392@deffnx {} BFD_RELOC_MMIX_GETA_2 2393@deffnx {} BFD_RELOC_MMIX_GETA_3 2394These are relocations for the GETA instruction. 2395@end deffn 2396@deffn {} BFD_RELOC_MMIX_CBRANCH 2397@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2398@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2399@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2400@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2401These are relocations for a conditional branch instruction. 2402@end deffn 2403@deffn {} BFD_RELOC_MMIX_PUSHJ 2404@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2405@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2406@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2407@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2408These are relocations for the PUSHJ instruction. 2409@end deffn 2410@deffn {} BFD_RELOC_MMIX_JMP 2411@deffnx {} BFD_RELOC_MMIX_JMP_1 2412@deffnx {} BFD_RELOC_MMIX_JMP_2 2413@deffnx {} BFD_RELOC_MMIX_JMP_3 2414These are relocations for the JMP instruction. 2415@end deffn 2416@deffn {} BFD_RELOC_MMIX_ADDR19 2417This is a relocation for a relative address as in a GETA instruction or 2418a branch. 2419@end deffn 2420@deffn {} BFD_RELOC_MMIX_ADDR27 2421This is a relocation for a relative address as in a JMP instruction. 2422@end deffn 2423@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2424This is a relocation for an instruction field that may be a general 2425register or a value 0..255. 2426@end deffn 2427@deffn {} BFD_RELOC_MMIX_REG 2428This is a relocation for an instruction field that may be a general 2429register. 2430@end deffn 2431@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2432This is a relocation for two instruction fields holding a register and 2433an offset, the equivalent of the relocation. 2434@end deffn 2435@deffn {} BFD_RELOC_MMIX_LOCAL 2436This relocation is an assertion that the expression is not allocated as 2437a global register. It does not modify contents. 2438@end deffn 2439@deffn {} BFD_RELOC_AVR_7_PCREL 2440This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2441short offset into 7 bits. 2442@end deffn 2443@deffn {} BFD_RELOC_AVR_13_PCREL 2444This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2445short offset into 12 bits. 2446@end deffn 2447@deffn {} BFD_RELOC_AVR_16_PM 2448This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2449program memory address) into 16 bits. 2450@end deffn 2451@deffn {} BFD_RELOC_AVR_LO8_LDI 2452This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2453data memory address) into 8 bit immediate value of LDI insn. 2454@end deffn 2455@deffn {} BFD_RELOC_AVR_HI8_LDI 2456This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2457of data memory address) into 8 bit immediate value of LDI insn. 2458@end deffn 2459@deffn {} BFD_RELOC_AVR_HH8_LDI 2460This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2461of program memory address) into 8 bit immediate value of LDI insn. 2462@end deffn 2463@deffn {} BFD_RELOC_AVR_MS8_LDI 2464This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2465of 32 bit value) into 8 bit immediate value of LDI insn. 2466@end deffn 2467@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2468This is a 16 bit reloc for the AVR that stores negated 8 bit value 2469(usually data memory address) into 8 bit immediate value of SUBI insn. 2470@end deffn 2471@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2472This is a 16 bit reloc for the AVR that stores negated 8 bit value 2473(high 8 bit of data memory address) into 8 bit immediate value of 2474SUBI insn. 2475@end deffn 2476@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2477This is a 16 bit reloc for the AVR that stores negated 8 bit value 2478(most high 8 bit of program memory address) into 8 bit immediate value 2479of LDI or SUBI insn. 2480@end deffn 2481@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2482This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2483of 32 bit value) into 8 bit immediate value of LDI insn. 2484@end deffn 2485@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2486This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2487command address) into 8 bit immediate value of LDI insn. 2488@end deffn 2489@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2490This is a 16 bit reloc for the AVR that stores 8 bit value 2491(command address) into 8 bit immediate value of LDI insn. If the address 2492is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2493in the lower 128k. 2494@end deffn 2495@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2496This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2497of command address) into 8 bit immediate value of LDI insn. 2498@end deffn 2499@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2500This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2501of command address) into 8 bit immediate value of LDI insn. If the address 2502is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2503below 128k. 2504@end deffn 2505@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2506This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2507of command address) into 8 bit immediate value of LDI insn. 2508@end deffn 2509@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2510This is a 16 bit reloc for the AVR that stores negated 8 bit value 2511(usually command address) into 8 bit immediate value of SUBI insn. 2512@end deffn 2513@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2514This is a 16 bit reloc for the AVR that stores negated 8 bit value 2515(high 8 bit of 16 bit command address) into 8 bit immediate value 2516of SUBI insn. 2517@end deffn 2518@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2519This is a 16 bit reloc for the AVR that stores negated 8 bit value 2520(high 6 bit of 22 bit command address) into 8 bit immediate 2521value of SUBI insn. 2522@end deffn 2523@deffn {} BFD_RELOC_AVR_CALL 2524This is a 32 bit reloc for the AVR that stores 23 bit value 2525into 22 bits. 2526@end deffn 2527@deffn {} BFD_RELOC_AVR_LDI 2528This is a 16 bit reloc for the AVR that stores all needed bits 2529for absolute addressing with ldi with overflow check to linktime 2530@end deffn 2531@deffn {} BFD_RELOC_AVR_6 2532This is a 6 bit reloc for the AVR that stores offset for ldd/std 2533instructions 2534@end deffn 2535@deffn {} BFD_RELOC_AVR_6_ADIW 2536This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2537instructions 2538@end deffn 2539@deffn {} BFD_RELOC_AVR_8_LO 2540This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2541in .byte lo8(symbol) 2542@end deffn 2543@deffn {} BFD_RELOC_AVR_8_HI 2544This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2545in .byte hi8(symbol) 2546@end deffn 2547@deffn {} BFD_RELOC_AVR_8_HLO 2548This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2549in .byte hlo8(symbol) 2550@end deffn 2551@deffn {} BFD_RELOC_AVR_DIFF8 2552@deffnx {} BFD_RELOC_AVR_DIFF16 2553@deffnx {} BFD_RELOC_AVR_DIFF32 2554AVR relocations to mark the difference of two local symbols. 2555These are only needed to support linker relaxation and can be ignored 2556when not relaxing. The field is set to the value of the difference 2557assuming no relaxation. The relocation encodes the position of the 2558second symbol so the linker can determine whether to adjust the field 2559value. 2560@end deffn 2561@deffn {} BFD_RELOC_AVR_LDS_STS_16 2562This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2563lds and sts instructions supported only tiny core. 2564@end deffn 2565@deffn {} BFD_RELOC_AVR_PORT6 2566This is a 6 bit reloc for the AVR that stores an I/O register 2567number for the IN and OUT instructions 2568@end deffn 2569@deffn {} BFD_RELOC_AVR_PORT5 2570This is a 5 bit reloc for the AVR that stores an I/O register 2571number for the SBIC, SBIS, SBI and CBI instructions 2572@end deffn 2573@deffn {} BFD_RELOC_RISCV_HI20 2574@deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2575@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2576@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2577@deffnx {} BFD_RELOC_RISCV_LO12_I 2578@deffnx {} BFD_RELOC_RISCV_LO12_S 2579@deffnx {} BFD_RELOC_RISCV_GPREL12_I 2580@deffnx {} BFD_RELOC_RISCV_GPREL12_S 2581@deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2582@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2583@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2584@deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2585@deffnx {} BFD_RELOC_RISCV_CALL 2586@deffnx {} BFD_RELOC_RISCV_CALL_PLT 2587@deffnx {} BFD_RELOC_RISCV_ADD8 2588@deffnx {} BFD_RELOC_RISCV_ADD16 2589@deffnx {} BFD_RELOC_RISCV_ADD32 2590@deffnx {} BFD_RELOC_RISCV_ADD64 2591@deffnx {} BFD_RELOC_RISCV_SUB8 2592@deffnx {} BFD_RELOC_RISCV_SUB16 2593@deffnx {} BFD_RELOC_RISCV_SUB32 2594@deffnx {} BFD_RELOC_RISCV_SUB64 2595@deffnx {} BFD_RELOC_RISCV_GOT_HI20 2596@deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2597@deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2598@deffnx {} BFD_RELOC_RISCV_JMP 2599@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2600@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2601@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2602@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2603@deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2604@deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2605@deffnx {} BFD_RELOC_RISCV_ALIGN 2606@deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2607@deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2608@deffnx {} BFD_RELOC_RISCV_RVC_LUI 2609@deffnx {} BFD_RELOC_RISCV_GPREL_I 2610@deffnx {} BFD_RELOC_RISCV_GPREL_S 2611@deffnx {} BFD_RELOC_RISCV_TPREL_I 2612@deffnx {} BFD_RELOC_RISCV_TPREL_S 2613@deffnx {} BFD_RELOC_RISCV_RELAX 2614@deffnx {} BFD_RELOC_RISCV_CFA 2615@deffnx {} BFD_RELOC_RISCV_SUB6 2616@deffnx {} BFD_RELOC_RISCV_SET6 2617@deffnx {} BFD_RELOC_RISCV_SET8 2618@deffnx {} BFD_RELOC_RISCV_SET16 2619@deffnx {} BFD_RELOC_RISCV_SET32 2620@deffnx {} BFD_RELOC_RISCV_32_PCREL 2621RISC-V relocations. 2622@end deffn 2623@deffn {} BFD_RELOC_RL78_NEG8 2624@deffnx {} BFD_RELOC_RL78_NEG16 2625@deffnx {} BFD_RELOC_RL78_NEG24 2626@deffnx {} BFD_RELOC_RL78_NEG32 2627@deffnx {} BFD_RELOC_RL78_16_OP 2628@deffnx {} BFD_RELOC_RL78_24_OP 2629@deffnx {} BFD_RELOC_RL78_32_OP 2630@deffnx {} BFD_RELOC_RL78_8U 2631@deffnx {} BFD_RELOC_RL78_16U 2632@deffnx {} BFD_RELOC_RL78_24U 2633@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2634@deffnx {} BFD_RELOC_RL78_DIFF 2635@deffnx {} BFD_RELOC_RL78_GPRELB 2636@deffnx {} BFD_RELOC_RL78_GPRELW 2637@deffnx {} BFD_RELOC_RL78_GPRELL 2638@deffnx {} BFD_RELOC_RL78_SYM 2639@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2640@deffnx {} BFD_RELOC_RL78_OP_NEG 2641@deffnx {} BFD_RELOC_RL78_OP_AND 2642@deffnx {} BFD_RELOC_RL78_OP_SHRA 2643@deffnx {} BFD_RELOC_RL78_ABS8 2644@deffnx {} BFD_RELOC_RL78_ABS16 2645@deffnx {} BFD_RELOC_RL78_ABS16_REV 2646@deffnx {} BFD_RELOC_RL78_ABS32 2647@deffnx {} BFD_RELOC_RL78_ABS32_REV 2648@deffnx {} BFD_RELOC_RL78_ABS16U 2649@deffnx {} BFD_RELOC_RL78_ABS16UW 2650@deffnx {} BFD_RELOC_RL78_ABS16UL 2651@deffnx {} BFD_RELOC_RL78_RELAX 2652@deffnx {} BFD_RELOC_RL78_HI16 2653@deffnx {} BFD_RELOC_RL78_HI8 2654@deffnx {} BFD_RELOC_RL78_LO16 2655@deffnx {} BFD_RELOC_RL78_CODE 2656@deffnx {} BFD_RELOC_RL78_SADDR 2657Renesas RL78 Relocations. 2658@end deffn 2659@deffn {} BFD_RELOC_RX_NEG8 2660@deffnx {} BFD_RELOC_RX_NEG16 2661@deffnx {} BFD_RELOC_RX_NEG24 2662@deffnx {} BFD_RELOC_RX_NEG32 2663@deffnx {} BFD_RELOC_RX_16_OP 2664@deffnx {} BFD_RELOC_RX_24_OP 2665@deffnx {} BFD_RELOC_RX_32_OP 2666@deffnx {} BFD_RELOC_RX_8U 2667@deffnx {} BFD_RELOC_RX_16U 2668@deffnx {} BFD_RELOC_RX_24U 2669@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2670@deffnx {} BFD_RELOC_RX_DIFF 2671@deffnx {} BFD_RELOC_RX_GPRELB 2672@deffnx {} BFD_RELOC_RX_GPRELW 2673@deffnx {} BFD_RELOC_RX_GPRELL 2674@deffnx {} BFD_RELOC_RX_SYM 2675@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2676@deffnx {} BFD_RELOC_RX_OP_NEG 2677@deffnx {} BFD_RELOC_RX_ABS8 2678@deffnx {} BFD_RELOC_RX_ABS16 2679@deffnx {} BFD_RELOC_RX_ABS16_REV 2680@deffnx {} BFD_RELOC_RX_ABS32 2681@deffnx {} BFD_RELOC_RX_ABS32_REV 2682@deffnx {} BFD_RELOC_RX_ABS16U 2683@deffnx {} BFD_RELOC_RX_ABS16UW 2684@deffnx {} BFD_RELOC_RX_ABS16UL 2685@deffnx {} BFD_RELOC_RX_RELAX 2686Renesas RX Relocations. 2687@end deffn 2688@deffn {} BFD_RELOC_390_12 2689Direct 12 bit. 2690@end deffn 2691@deffn {} BFD_RELOC_390_GOT12 269212 bit GOT offset. 2693@end deffn 2694@deffn {} BFD_RELOC_390_PLT32 269532 bit PC relative PLT address. 2696@end deffn 2697@deffn {} BFD_RELOC_390_COPY 2698Copy symbol at runtime. 2699@end deffn 2700@deffn {} BFD_RELOC_390_GLOB_DAT 2701Create GOT entry. 2702@end deffn 2703@deffn {} BFD_RELOC_390_JMP_SLOT 2704Create PLT entry. 2705@end deffn 2706@deffn {} BFD_RELOC_390_RELATIVE 2707Adjust by program base. 2708@end deffn 2709@deffn {} BFD_RELOC_390_GOTPC 271032 bit PC relative offset to GOT. 2711@end deffn 2712@deffn {} BFD_RELOC_390_GOT16 271316 bit GOT offset. 2714@end deffn 2715@deffn {} BFD_RELOC_390_PC12DBL 2716PC relative 12 bit shifted by 1. 2717@end deffn 2718@deffn {} BFD_RELOC_390_PLT12DBL 271912 bit PC rel. PLT shifted by 1. 2720@end deffn 2721@deffn {} BFD_RELOC_390_PC16DBL 2722PC relative 16 bit shifted by 1. 2723@end deffn 2724@deffn {} BFD_RELOC_390_PLT16DBL 272516 bit PC rel. PLT shifted by 1. 2726@end deffn 2727@deffn {} BFD_RELOC_390_PC24DBL 2728PC relative 24 bit shifted by 1. 2729@end deffn 2730@deffn {} BFD_RELOC_390_PLT24DBL 273124 bit PC rel. PLT shifted by 1. 2732@end deffn 2733@deffn {} BFD_RELOC_390_PC32DBL 2734PC relative 32 bit shifted by 1. 2735@end deffn 2736@deffn {} BFD_RELOC_390_PLT32DBL 273732 bit PC rel. PLT shifted by 1. 2738@end deffn 2739@deffn {} BFD_RELOC_390_GOTPCDBL 274032 bit PC rel. GOT shifted by 1. 2741@end deffn 2742@deffn {} BFD_RELOC_390_GOT64 274364 bit GOT offset. 2744@end deffn 2745@deffn {} BFD_RELOC_390_PLT64 274664 bit PC relative PLT address. 2747@end deffn 2748@deffn {} BFD_RELOC_390_GOTENT 274932 bit rel. offset to GOT entry. 2750@end deffn 2751@deffn {} BFD_RELOC_390_GOTOFF64 275264 bit offset to GOT. 2753@end deffn 2754@deffn {} BFD_RELOC_390_GOTPLT12 275512-bit offset to symbol-entry within GOT, with PLT handling. 2756@end deffn 2757@deffn {} BFD_RELOC_390_GOTPLT16 275816-bit offset to symbol-entry within GOT, with PLT handling. 2759@end deffn 2760@deffn {} BFD_RELOC_390_GOTPLT32 276132-bit offset to symbol-entry within GOT, with PLT handling. 2762@end deffn 2763@deffn {} BFD_RELOC_390_GOTPLT64 276464-bit offset to symbol-entry within GOT, with PLT handling. 2765@end deffn 2766@deffn {} BFD_RELOC_390_GOTPLTENT 276732-bit rel. offset to symbol-entry within GOT, with PLT handling. 2768@end deffn 2769@deffn {} BFD_RELOC_390_PLTOFF16 277016-bit rel. offset from the GOT to a PLT entry. 2771@end deffn 2772@deffn {} BFD_RELOC_390_PLTOFF32 277332-bit rel. offset from the GOT to a PLT entry. 2774@end deffn 2775@deffn {} BFD_RELOC_390_PLTOFF64 277664-bit rel. offset from the GOT to a PLT entry. 2777@end deffn 2778@deffn {} BFD_RELOC_390_TLS_LOAD 2779@deffnx {} BFD_RELOC_390_TLS_GDCALL 2780@deffnx {} BFD_RELOC_390_TLS_LDCALL 2781@deffnx {} BFD_RELOC_390_TLS_GD32 2782@deffnx {} BFD_RELOC_390_TLS_GD64 2783@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2784@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2785@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2786@deffnx {} BFD_RELOC_390_TLS_LDM32 2787@deffnx {} BFD_RELOC_390_TLS_LDM64 2788@deffnx {} BFD_RELOC_390_TLS_IE32 2789@deffnx {} BFD_RELOC_390_TLS_IE64 2790@deffnx {} BFD_RELOC_390_TLS_IEENT 2791@deffnx {} BFD_RELOC_390_TLS_LE32 2792@deffnx {} BFD_RELOC_390_TLS_LE64 2793@deffnx {} BFD_RELOC_390_TLS_LDO32 2794@deffnx {} BFD_RELOC_390_TLS_LDO64 2795@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2796@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2797@deffnx {} BFD_RELOC_390_TLS_TPOFF 2798s390 tls relocations. 2799@end deffn 2800@deffn {} BFD_RELOC_390_20 2801@deffnx {} BFD_RELOC_390_GOT20 2802@deffnx {} BFD_RELOC_390_GOTPLT20 2803@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2804Long displacement extension. 2805@end deffn 2806@deffn {} BFD_RELOC_390_IRELATIVE 2807STT_GNU_IFUNC relocation. 2808@end deffn 2809@deffn {} BFD_RELOC_SCORE_GPREL15 2810Score relocations 2811Low 16 bit for load/store 2812@end deffn 2813@deffn {} BFD_RELOC_SCORE_DUMMY2 2814@deffnx {} BFD_RELOC_SCORE_JMP 2815This is a 24-bit reloc with the right 1 bit assumed to be 0 2816@end deffn 2817@deffn {} BFD_RELOC_SCORE_BRANCH 2818This is a 19-bit reloc with the right 1 bit assumed to be 0 2819@end deffn 2820@deffn {} BFD_RELOC_SCORE_IMM30 2821This is a 32-bit reloc for 48-bit instructions. 2822@end deffn 2823@deffn {} BFD_RELOC_SCORE_IMM32 2824This is a 32-bit reloc for 48-bit instructions. 2825@end deffn 2826@deffn {} BFD_RELOC_SCORE16_JMP 2827This is a 11-bit reloc with the right 1 bit assumed to be 0 2828@end deffn 2829@deffn {} BFD_RELOC_SCORE16_BRANCH 2830This is a 8-bit reloc with the right 1 bit assumed to be 0 2831@end deffn 2832@deffn {} BFD_RELOC_SCORE_BCMP 2833This is a 9-bit reloc with the right 1 bit assumed to be 0 2834@end deffn 2835@deffn {} BFD_RELOC_SCORE_GOT15 2836@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2837@deffnx {} BFD_RELOC_SCORE_CALL15 2838@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2839Undocumented Score relocs 2840@end deffn 2841@deffn {} BFD_RELOC_IP2K_FR9 2842Scenix IP2K - 9-bit register number / data address 2843@end deffn 2844@deffn {} BFD_RELOC_IP2K_BANK 2845Scenix IP2K - 4-bit register/data bank number 2846@end deffn 2847@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2848Scenix IP2K - low 13 bits of instruction word address 2849@end deffn 2850@deffn {} BFD_RELOC_IP2K_PAGE3 2851Scenix IP2K - high 3 bits of instruction word address 2852@end deffn 2853@deffn {} BFD_RELOC_IP2K_LO8DATA 2854@deffnx {} BFD_RELOC_IP2K_HI8DATA 2855@deffnx {} BFD_RELOC_IP2K_EX8DATA 2856Scenix IP2K - ext/low/high 8 bits of data address 2857@end deffn 2858@deffn {} BFD_RELOC_IP2K_LO8INSN 2859@deffnx {} BFD_RELOC_IP2K_HI8INSN 2860Scenix IP2K - low/high 8 bits of instruction word address 2861@end deffn 2862@deffn {} BFD_RELOC_IP2K_PC_SKIP 2863Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2864@end deffn 2865@deffn {} BFD_RELOC_IP2K_TEXT 2866Scenix IP2K - 16 bit word address in text section. 2867@end deffn 2868@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2869Scenix IP2K - 7-bit sp or dp offset 2870@end deffn 2871@deffn {} BFD_RELOC_VPE4KMATH_DATA 2872@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2873Scenix VPE4K coprocessor - data/insn-space addressing 2874@end deffn 2875@deffn {} BFD_RELOC_VTABLE_INHERIT 2876@deffnx {} BFD_RELOC_VTABLE_ENTRY 2877These two relocations are used by the linker to determine which of 2878the entries in a C++ virtual function table are actually used. When 2879the --gc-sections option is given, the linker will zero out the entries 2880that are not used, so that the code for those functions need not be 2881included in the output. 2882 2883VTABLE_INHERIT is a zero-space relocation used to describe to the 2884linker the inheritance tree of a C++ virtual function table. The 2885relocation's symbol should be the parent class' vtable, and the 2886relocation should be located at the child vtable. 2887 2888VTABLE_ENTRY is a zero-space relocation that describes the use of a 2889virtual function table entry. The reloc's symbol should refer to the 2890table of the class mentioned in the code. Off of that base, an offset 2891describes the entry that is being used. For Rela hosts, this offset 2892is stored in the reloc's addend. For Rel hosts, we are forced to put 2893this offset in the reloc's section offset. 2894@end deffn 2895@deffn {} BFD_RELOC_IA64_IMM14 2896@deffnx {} BFD_RELOC_IA64_IMM22 2897@deffnx {} BFD_RELOC_IA64_IMM64 2898@deffnx {} BFD_RELOC_IA64_DIR32MSB 2899@deffnx {} BFD_RELOC_IA64_DIR32LSB 2900@deffnx {} BFD_RELOC_IA64_DIR64MSB 2901@deffnx {} BFD_RELOC_IA64_DIR64LSB 2902@deffnx {} BFD_RELOC_IA64_GPREL22 2903@deffnx {} BFD_RELOC_IA64_GPREL64I 2904@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2905@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2906@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2907@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2908@deffnx {} BFD_RELOC_IA64_LTOFF22 2909@deffnx {} BFD_RELOC_IA64_LTOFF64I 2910@deffnx {} BFD_RELOC_IA64_PLTOFF22 2911@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2912@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2913@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2914@deffnx {} BFD_RELOC_IA64_FPTR64I 2915@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2916@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2917@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2918@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2919@deffnx {} BFD_RELOC_IA64_PCREL21B 2920@deffnx {} BFD_RELOC_IA64_PCREL21BI 2921@deffnx {} BFD_RELOC_IA64_PCREL21M 2922@deffnx {} BFD_RELOC_IA64_PCREL21F 2923@deffnx {} BFD_RELOC_IA64_PCREL22 2924@deffnx {} BFD_RELOC_IA64_PCREL60B 2925@deffnx {} BFD_RELOC_IA64_PCREL64I 2926@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2927@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2928@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2929@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2930@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2931@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2932@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2933@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2934@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2935@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2936@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2937@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2938@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2939@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2940@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2941@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2942@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2943@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2944@deffnx {} BFD_RELOC_IA64_REL32MSB 2945@deffnx {} BFD_RELOC_IA64_REL32LSB 2946@deffnx {} BFD_RELOC_IA64_REL64MSB 2947@deffnx {} BFD_RELOC_IA64_REL64LSB 2948@deffnx {} BFD_RELOC_IA64_LTV32MSB 2949@deffnx {} BFD_RELOC_IA64_LTV32LSB 2950@deffnx {} BFD_RELOC_IA64_LTV64MSB 2951@deffnx {} BFD_RELOC_IA64_LTV64LSB 2952@deffnx {} BFD_RELOC_IA64_IPLTMSB 2953@deffnx {} BFD_RELOC_IA64_IPLTLSB 2954@deffnx {} BFD_RELOC_IA64_COPY 2955@deffnx {} BFD_RELOC_IA64_LTOFF22X 2956@deffnx {} BFD_RELOC_IA64_LDXMOV 2957@deffnx {} BFD_RELOC_IA64_TPREL14 2958@deffnx {} BFD_RELOC_IA64_TPREL22 2959@deffnx {} BFD_RELOC_IA64_TPREL64I 2960@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2961@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2962@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2963@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2964@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2965@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2966@deffnx {} BFD_RELOC_IA64_DTPREL14 2967@deffnx {} BFD_RELOC_IA64_DTPREL22 2968@deffnx {} BFD_RELOC_IA64_DTPREL64I 2969@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2970@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2971@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2972@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2973@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2974Intel IA64 Relocations. 2975@end deffn 2976@deffn {} BFD_RELOC_M68HC11_HI8 2977Motorola 68HC11 reloc. 2978This is the 8 bit high part of an absolute address. 2979@end deffn 2980@deffn {} BFD_RELOC_M68HC11_LO8 2981Motorola 68HC11 reloc. 2982This is the 8 bit low part of an absolute address. 2983@end deffn 2984@deffn {} BFD_RELOC_M68HC11_3B 2985Motorola 68HC11 reloc. 2986This is the 3 bit of a value. 2987@end deffn 2988@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2989Motorola 68HC11 reloc. 2990This reloc marks the beginning of a jump/call instruction. 2991It is used for linker relaxation to correctly identify beginning 2992of instruction and change some branches to use PC-relative 2993addressing mode. 2994@end deffn 2995@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2996Motorola 68HC11 reloc. 2997This reloc marks a group of several instructions that gcc generates 2998and for which the linker relaxation pass can modify and/or remove 2999some of them. 3000@end deffn 3001@deffn {} BFD_RELOC_M68HC11_LO16 3002Motorola 68HC11 reloc. 3003This is the 16-bit lower part of an address. It is used for 'call' 3004instruction to specify the symbol address without any special 3005transformation (due to memory bank window). 3006@end deffn 3007@deffn {} BFD_RELOC_M68HC11_PAGE 3008Motorola 68HC11 reloc. 3009This is a 8-bit reloc that specifies the page number of an address. 3010It is used by 'call' instruction to specify the page number of 3011the symbol. 3012@end deffn 3013@deffn {} BFD_RELOC_M68HC11_24 3014Motorola 68HC11 reloc. 3015This is a 24-bit reloc that represents the address with a 16-bit 3016value and a 8-bit page number. The symbol address is transformed 3017to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 3018@end deffn 3019@deffn {} BFD_RELOC_M68HC12_5B 3020Motorola 68HC12 reloc. 3021This is the 5 bits of a value. 3022@end deffn 3023@deffn {} BFD_RELOC_XGATE_RL_JUMP 3024Freescale XGATE reloc. 3025This reloc marks the beginning of a bra/jal instruction. 3026@end deffn 3027@deffn {} BFD_RELOC_XGATE_RL_GROUP 3028Freescale XGATE reloc. 3029This reloc marks a group of several instructions that gcc generates 3030and for which the linker relaxation pass can modify and/or remove 3031some of them. 3032@end deffn 3033@deffn {} BFD_RELOC_XGATE_LO16 3034Freescale XGATE reloc. 3035This is the 16-bit lower part of an address. It is used for the '16-bit' 3036instructions. 3037@end deffn 3038@deffn {} BFD_RELOC_XGATE_GPAGE 3039Freescale XGATE reloc. 3040@end deffn 3041@deffn {} BFD_RELOC_XGATE_24 3042Freescale XGATE reloc. 3043@end deffn 3044@deffn {} BFD_RELOC_XGATE_PCREL_9 3045Freescale XGATE reloc. 3046This is a 9-bit pc-relative reloc. 3047@end deffn 3048@deffn {} BFD_RELOC_XGATE_PCREL_10 3049Freescale XGATE reloc. 3050This is a 10-bit pc-relative reloc. 3051@end deffn 3052@deffn {} BFD_RELOC_XGATE_IMM8_LO 3053Freescale XGATE reloc. 3054This is the 16-bit lower part of an address. It is used for the '16-bit' 3055instructions. 3056@end deffn 3057@deffn {} BFD_RELOC_XGATE_IMM8_HI 3058Freescale XGATE reloc. 3059This is the 16-bit higher part of an address. It is used for the '16-bit' 3060instructions. 3061@end deffn 3062@deffn {} BFD_RELOC_XGATE_IMM3 3063Freescale XGATE reloc. 3064This is a 3-bit pc-relative reloc. 3065@end deffn 3066@deffn {} BFD_RELOC_XGATE_IMM4 3067Freescale XGATE reloc. 3068This is a 4-bit pc-relative reloc. 3069@end deffn 3070@deffn {} BFD_RELOC_XGATE_IMM5 3071Freescale XGATE reloc. 3072This is a 5-bit pc-relative reloc. 3073@end deffn 3074@deffn {} BFD_RELOC_M68HC12_9B 3075Motorola 68HC12 reloc. 3076This is the 9 bits of a value. 3077@end deffn 3078@deffn {} BFD_RELOC_M68HC12_16B 3079Motorola 68HC12 reloc. 3080This is the 16 bits of a value. 3081@end deffn 3082@deffn {} BFD_RELOC_M68HC12_9_PCREL 3083Motorola 68HC12/XGATE reloc. 3084This is a PCREL9 branch. 3085@end deffn 3086@deffn {} BFD_RELOC_M68HC12_10_PCREL 3087Motorola 68HC12/XGATE reloc. 3088This is a PCREL10 branch. 3089@end deffn 3090@deffn {} BFD_RELOC_M68HC12_LO8XG 3091Motorola 68HC12/XGATE reloc. 3092This is the 8 bit low part of an absolute address and immediately precedes 3093a matching HI8XG part. 3094@end deffn 3095@deffn {} BFD_RELOC_M68HC12_HI8XG 3096Motorola 68HC12/XGATE reloc. 3097This is the 8 bit high part of an absolute address and immediately follows 3098a matching LO8XG part. 3099@end deffn 3100@deffn {} BFD_RELOC_S12Z_15_PCREL 3101Freescale S12Z reloc. 3102This is a 15 bit relative address. If the most significant bits are all zero 3103then it may be truncated to 8 bits. 3104@end deffn 3105@deffn {} BFD_RELOC_16C_NUM08 3106@deffnx {} BFD_RELOC_16C_NUM08_C 3107@deffnx {} BFD_RELOC_16C_NUM16 3108@deffnx {} BFD_RELOC_16C_NUM16_C 3109@deffnx {} BFD_RELOC_16C_NUM32 3110@deffnx {} BFD_RELOC_16C_NUM32_C 3111@deffnx {} BFD_RELOC_16C_DISP04 3112@deffnx {} BFD_RELOC_16C_DISP04_C 3113@deffnx {} BFD_RELOC_16C_DISP08 3114@deffnx {} BFD_RELOC_16C_DISP08_C 3115@deffnx {} BFD_RELOC_16C_DISP16 3116@deffnx {} BFD_RELOC_16C_DISP16_C 3117@deffnx {} BFD_RELOC_16C_DISP24 3118@deffnx {} BFD_RELOC_16C_DISP24_C 3119@deffnx {} BFD_RELOC_16C_DISP24a 3120@deffnx {} BFD_RELOC_16C_DISP24a_C 3121@deffnx {} BFD_RELOC_16C_REG04 3122@deffnx {} BFD_RELOC_16C_REG04_C 3123@deffnx {} BFD_RELOC_16C_REG04a 3124@deffnx {} BFD_RELOC_16C_REG04a_C 3125@deffnx {} BFD_RELOC_16C_REG14 3126@deffnx {} BFD_RELOC_16C_REG14_C 3127@deffnx {} BFD_RELOC_16C_REG16 3128@deffnx {} BFD_RELOC_16C_REG16_C 3129@deffnx {} BFD_RELOC_16C_REG20 3130@deffnx {} BFD_RELOC_16C_REG20_C 3131@deffnx {} BFD_RELOC_16C_ABS20 3132@deffnx {} BFD_RELOC_16C_ABS20_C 3133@deffnx {} BFD_RELOC_16C_ABS24 3134@deffnx {} BFD_RELOC_16C_ABS24_C 3135@deffnx {} BFD_RELOC_16C_IMM04 3136@deffnx {} BFD_RELOC_16C_IMM04_C 3137@deffnx {} BFD_RELOC_16C_IMM16 3138@deffnx {} BFD_RELOC_16C_IMM16_C 3139@deffnx {} BFD_RELOC_16C_IMM20 3140@deffnx {} BFD_RELOC_16C_IMM20_C 3141@deffnx {} BFD_RELOC_16C_IMM24 3142@deffnx {} BFD_RELOC_16C_IMM24_C 3143@deffnx {} BFD_RELOC_16C_IMM32 3144@deffnx {} BFD_RELOC_16C_IMM32_C 3145NS CR16C Relocations. 3146@end deffn 3147@deffn {} BFD_RELOC_CR16_NUM8 3148@deffnx {} BFD_RELOC_CR16_NUM16 3149@deffnx {} BFD_RELOC_CR16_NUM32 3150@deffnx {} BFD_RELOC_CR16_NUM32a 3151@deffnx {} BFD_RELOC_CR16_REGREL0 3152@deffnx {} BFD_RELOC_CR16_REGREL4 3153@deffnx {} BFD_RELOC_CR16_REGREL4a 3154@deffnx {} BFD_RELOC_CR16_REGREL14 3155@deffnx {} BFD_RELOC_CR16_REGREL14a 3156@deffnx {} BFD_RELOC_CR16_REGREL16 3157@deffnx {} BFD_RELOC_CR16_REGREL20 3158@deffnx {} BFD_RELOC_CR16_REGREL20a 3159@deffnx {} BFD_RELOC_CR16_ABS20 3160@deffnx {} BFD_RELOC_CR16_ABS24 3161@deffnx {} BFD_RELOC_CR16_IMM4 3162@deffnx {} BFD_RELOC_CR16_IMM8 3163@deffnx {} BFD_RELOC_CR16_IMM16 3164@deffnx {} BFD_RELOC_CR16_IMM20 3165@deffnx {} BFD_RELOC_CR16_IMM24 3166@deffnx {} BFD_RELOC_CR16_IMM32 3167@deffnx {} BFD_RELOC_CR16_IMM32a 3168@deffnx {} BFD_RELOC_CR16_DISP4 3169@deffnx {} BFD_RELOC_CR16_DISP8 3170@deffnx {} BFD_RELOC_CR16_DISP16 3171@deffnx {} BFD_RELOC_CR16_DISP20 3172@deffnx {} BFD_RELOC_CR16_DISP24 3173@deffnx {} BFD_RELOC_CR16_DISP24a 3174@deffnx {} BFD_RELOC_CR16_SWITCH8 3175@deffnx {} BFD_RELOC_CR16_SWITCH16 3176@deffnx {} BFD_RELOC_CR16_SWITCH32 3177@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3178@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3179@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3180NS CR16 Relocations. 3181@end deffn 3182@deffn {} BFD_RELOC_CRX_REL4 3183@deffnx {} BFD_RELOC_CRX_REL8 3184@deffnx {} BFD_RELOC_CRX_REL8_CMP 3185@deffnx {} BFD_RELOC_CRX_REL16 3186@deffnx {} BFD_RELOC_CRX_REL24 3187@deffnx {} BFD_RELOC_CRX_REL32 3188@deffnx {} BFD_RELOC_CRX_REGREL12 3189@deffnx {} BFD_RELOC_CRX_REGREL22 3190@deffnx {} BFD_RELOC_CRX_REGREL28 3191@deffnx {} BFD_RELOC_CRX_REGREL32 3192@deffnx {} BFD_RELOC_CRX_ABS16 3193@deffnx {} BFD_RELOC_CRX_ABS32 3194@deffnx {} BFD_RELOC_CRX_NUM8 3195@deffnx {} BFD_RELOC_CRX_NUM16 3196@deffnx {} BFD_RELOC_CRX_NUM32 3197@deffnx {} BFD_RELOC_CRX_IMM16 3198@deffnx {} BFD_RELOC_CRX_IMM32 3199@deffnx {} BFD_RELOC_CRX_SWITCH8 3200@deffnx {} BFD_RELOC_CRX_SWITCH16 3201@deffnx {} BFD_RELOC_CRX_SWITCH32 3202NS CRX Relocations. 3203@end deffn 3204@deffn {} BFD_RELOC_CRIS_BDISP8 3205@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3206@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3207@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3208@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3209@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3210@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3211@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3212@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3213@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3214These relocs are only used within the CRIS assembler. They are not 3215(at present) written to any object files. 3216@end deffn 3217@deffn {} BFD_RELOC_CRIS_COPY 3218@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3219@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3220@deffnx {} BFD_RELOC_CRIS_RELATIVE 3221Relocs used in ELF shared libraries for CRIS. 3222@end deffn 3223@deffn {} BFD_RELOC_CRIS_32_GOT 322432-bit offset to symbol-entry within GOT. 3225@end deffn 3226@deffn {} BFD_RELOC_CRIS_16_GOT 322716-bit offset to symbol-entry within GOT. 3228@end deffn 3229@deffn {} BFD_RELOC_CRIS_32_GOTPLT 323032-bit offset to symbol-entry within GOT, with PLT handling. 3231@end deffn 3232@deffn {} BFD_RELOC_CRIS_16_GOTPLT 323316-bit offset to symbol-entry within GOT, with PLT handling. 3234@end deffn 3235@deffn {} BFD_RELOC_CRIS_32_GOTREL 323632-bit offset to symbol, relative to GOT. 3237@end deffn 3238@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 323932-bit offset to symbol with PLT entry, relative to GOT. 3240@end deffn 3241@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 324232-bit offset to symbol with PLT entry, relative to this relocation. 3243@end deffn 3244@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3245@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3246@deffnx {} BFD_RELOC_CRIS_32_GD 3247@deffnx {} BFD_RELOC_CRIS_DTP 3248@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3249@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3250@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3251@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3252@deffnx {} BFD_RELOC_CRIS_32_TPREL 3253@deffnx {} BFD_RELOC_CRIS_16_TPREL 3254@deffnx {} BFD_RELOC_CRIS_DTPMOD 3255@deffnx {} BFD_RELOC_CRIS_32_IE 3256Relocs used in TLS code for CRIS. 3257@end deffn 3258@deffn {} BFD_RELOC_OR1K_REL_26 3259@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3260@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3261@deffnx {} BFD_RELOC_OR1K_GOT16 3262@deffnx {} BFD_RELOC_OR1K_PLT26 3263@deffnx {} BFD_RELOC_OR1K_GOTOFF_HI16 3264@deffnx {} BFD_RELOC_OR1K_GOTOFF_LO16 3265@deffnx {} BFD_RELOC_OR1K_COPY 3266@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3267@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3268@deffnx {} BFD_RELOC_OR1K_RELATIVE 3269@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3270@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3271@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3272@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3273@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3274@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3275@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3276@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3277@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3278@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3279@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3280@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3281@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3282OpenRISC 1000 Relocations. 3283@end deffn 3284@deffn {} BFD_RELOC_H8_DIR16A8 3285@deffnx {} BFD_RELOC_H8_DIR16R8 3286@deffnx {} BFD_RELOC_H8_DIR24A8 3287@deffnx {} BFD_RELOC_H8_DIR24R8 3288@deffnx {} BFD_RELOC_H8_DIR32A16 3289@deffnx {} BFD_RELOC_H8_DISP32A16 3290H8 elf Relocations. 3291@end deffn 3292@deffn {} BFD_RELOC_XSTORMY16_REL_12 3293@deffnx {} BFD_RELOC_XSTORMY16_12 3294@deffnx {} BFD_RELOC_XSTORMY16_24 3295@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3296Sony Xstormy16 Relocations. 3297@end deffn 3298@deffn {} BFD_RELOC_RELC 3299Self-describing complex relocations. 3300@end deffn 3301@deffn {} BFD_RELOC_XC16X_PAG 3302@deffnx {} BFD_RELOC_XC16X_POF 3303@deffnx {} BFD_RELOC_XC16X_SEG 3304@deffnx {} BFD_RELOC_XC16X_SOF 3305Infineon Relocations. 3306@end deffn 3307@deffn {} BFD_RELOC_VAX_GLOB_DAT 3308@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3309@deffnx {} BFD_RELOC_VAX_RELATIVE 3310Relocations used by VAX ELF. 3311@end deffn 3312@deffn {} BFD_RELOC_MT_PC16 3313Morpho MT - 16 bit immediate relocation. 3314@end deffn 3315@deffn {} BFD_RELOC_MT_HI16 3316Morpho MT - Hi 16 bits of an address. 3317@end deffn 3318@deffn {} BFD_RELOC_MT_LO16 3319Morpho MT - Low 16 bits of an address. 3320@end deffn 3321@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3322Morpho MT - Used to tell the linker which vtable entries are used. 3323@end deffn 3324@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3325Morpho MT - Used to tell the linker which vtable entries are used. 3326@end deffn 3327@deffn {} BFD_RELOC_MT_PCINSN8 3328Morpho MT - 8 bit immediate relocation. 3329@end deffn 3330@deffn {} BFD_RELOC_MSP430_10_PCREL 3331@deffnx {} BFD_RELOC_MSP430_16_PCREL 3332@deffnx {} BFD_RELOC_MSP430_16 3333@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3334@deffnx {} BFD_RELOC_MSP430_16_BYTE 3335@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3336@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3337@deffnx {} BFD_RELOC_MSP430_ABS8 3338@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3339@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3340@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3341@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3342@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3343@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3344@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3345@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3346@deffnx {} BFD_RELOC_MSP430X_PCR16 3347@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3348@deffnx {} BFD_RELOC_MSP430X_ABS16 3349@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3350@deffnx {} BFD_RELOC_MSP430_PREL31 3351@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3352msp430 specific relocation codes 3353@end deffn 3354@deffn {} BFD_RELOC_NIOS2_S16 3355@deffnx {} BFD_RELOC_NIOS2_U16 3356@deffnx {} BFD_RELOC_NIOS2_CALL26 3357@deffnx {} BFD_RELOC_NIOS2_IMM5 3358@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3359@deffnx {} BFD_RELOC_NIOS2_IMM6 3360@deffnx {} BFD_RELOC_NIOS2_IMM8 3361@deffnx {} BFD_RELOC_NIOS2_HI16 3362@deffnx {} BFD_RELOC_NIOS2_LO16 3363@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3364@deffnx {} BFD_RELOC_NIOS2_GPREL 3365@deffnx {} BFD_RELOC_NIOS2_UJMP 3366@deffnx {} BFD_RELOC_NIOS2_CJMP 3367@deffnx {} BFD_RELOC_NIOS2_CALLR 3368@deffnx {} BFD_RELOC_NIOS2_ALIGN 3369@deffnx {} BFD_RELOC_NIOS2_GOT16 3370@deffnx {} BFD_RELOC_NIOS2_CALL16 3371@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3372@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3373@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3374@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3375@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3376@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3377@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3378@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3379@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3380@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3381@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3382@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3383@deffnx {} BFD_RELOC_NIOS2_COPY 3384@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3385@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3386@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3387@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3388@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3389@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3390@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3391@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3392@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3393@deffnx {} BFD_RELOC_NIOS2_R2_S12 3394@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3395@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3396@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3397@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3398@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3399@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3400@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3401@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3402@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3403@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3404@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3405@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3406Relocations used by the Altera Nios II core. 3407@end deffn 3408@deffn {} BFD_RELOC_PRU_U16 3409PRU LDI 16-bit unsigned data-memory relocation. 3410@end deffn 3411@deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3412PRU LDI 16-bit unsigned instruction-memory relocation. 3413@end deffn 3414@deffn {} BFD_RELOC_PRU_LDI32 3415PRU relocation for two consecutive LDI load instructions that load a 341632 bit value into a register. If the higher bits are all zero, then 3417the second instruction may be relaxed. 3418@end deffn 3419@deffn {} BFD_RELOC_PRU_S10_PCREL 3420PRU QBBx 10-bit signed PC-relative relocation. 3421@end deffn 3422@deffn {} BFD_RELOC_PRU_U8_PCREL 3423PRU 8-bit unsigned relocation used for the LOOP instruction. 3424@end deffn 3425@deffn {} BFD_RELOC_PRU_32_PMEM 3426@deffnx {} BFD_RELOC_PRU_16_PMEM 3427PRU Program Memory relocations. Used to convert from byte addressing to 342832-bit word addressing. 3429@end deffn 3430@deffn {} BFD_RELOC_PRU_GNU_DIFF8 3431@deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3432@deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3433@deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3434@deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3435PRU relocations to mark the difference of two local symbols. 3436These are only needed to support linker relaxation and can be ignored 3437when not relaxing. The field is set to the value of the difference 3438assuming no relaxation. The relocation encodes the position of the 3439second symbol so the linker can determine whether to adjust the field 3440value. The PMEM variants encode the word difference, instead of byte 3441difference between symbols. 3442@end deffn 3443@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3444@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3445@deffnx {} BFD_RELOC_IQ2000_UHI16 3446IQ2000 Relocations. 3447@end deffn 3448@deffn {} BFD_RELOC_XTENSA_RTLD 3449Special Xtensa relocation used only by PLT entries in ELF shared 3450objects to indicate that the runtime linker should set the value 3451to one of its own internal functions or data structures. 3452@end deffn 3453@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3454@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3455@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3456Xtensa relocations for ELF shared objects. 3457@end deffn 3458@deffn {} BFD_RELOC_XTENSA_PLT 3459Xtensa relocation used in ELF object files for symbols that may require 3460PLT entries. Otherwise, this is just a generic 32-bit relocation. 3461@end deffn 3462@deffn {} BFD_RELOC_XTENSA_DIFF8 3463@deffnx {} BFD_RELOC_XTENSA_DIFF16 3464@deffnx {} BFD_RELOC_XTENSA_DIFF32 3465Xtensa relocations to mark the difference of two local symbols. 3466These are only needed to support linker relaxation and can be ignored 3467when not relaxing. The field is set to the value of the difference 3468assuming no relaxation. The relocation encodes the position of the 3469first symbol so the linker can determine whether to adjust the field 3470value. 3471@end deffn 3472@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3473@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3474@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3475@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3476@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3477@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3478@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3479@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3480@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3481@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3482@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3483@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3484@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3485@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3486@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3487Generic Xtensa relocations for instruction operands. Only the slot 3488number is encoded in the relocation. The relocation applies to the 3489last PC-relative immediate operand, or if there are no PC-relative 3490immediates, to the last immediate operand. 3491@end deffn 3492@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3493@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3494@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3495@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3496@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3497@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3498@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3499@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3500@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3501@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3502@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3503@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3504@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3505@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3506@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3507Alternate Xtensa relocations. Only the slot is encoded in the 3508relocation. The meaning of these relocations is opcode-specific. 3509@end deffn 3510@deffn {} BFD_RELOC_XTENSA_OP0 3511@deffnx {} BFD_RELOC_XTENSA_OP1 3512@deffnx {} BFD_RELOC_XTENSA_OP2 3513Xtensa relocations for backward compatibility. These have all been 3514replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3515@end deffn 3516@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3517Xtensa relocation to mark that the assembler expanded the 3518instructions from an original target. The expansion size is 3519encoded in the reloc size. 3520@end deffn 3521@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3522Xtensa relocation to mark that the linker should simplify 3523assembler-expanded instructions. This is commonly used 3524internally by the linker after analysis of a 3525BFD_RELOC_XTENSA_ASM_EXPAND. 3526@end deffn 3527@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3528@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3529@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3530@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3531@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3532@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3533@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3534Xtensa TLS relocations. 3535@end deffn 3536@deffn {} BFD_RELOC_Z80_DISP8 35378 bit signed offset in (ix+d) or (iy+d). 3538@end deffn 3539@deffn {} BFD_RELOC_Z8K_DISP7 3540DJNZ offset. 3541@end deffn 3542@deffn {} BFD_RELOC_Z8K_CALLR 3543CALR offset. 3544@end deffn 3545@deffn {} BFD_RELOC_Z8K_IMM4L 35464 bit value. 3547@end deffn 3548@deffn {} BFD_RELOC_LM32_CALL 3549@deffnx {} BFD_RELOC_LM32_BRANCH 3550@deffnx {} BFD_RELOC_LM32_16_GOT 3551@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3552@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3553@deffnx {} BFD_RELOC_LM32_COPY 3554@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3555@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3556@deffnx {} BFD_RELOC_LM32_RELATIVE 3557Lattice Mico32 relocations. 3558@end deffn 3559@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3560Difference between two section addreses. Must be followed by a 3561BFD_RELOC_MACH_O_PAIR. 3562@end deffn 3563@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3564Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3565@end deffn 3566@deffn {} BFD_RELOC_MACH_O_PAIR 3567Pair of relocation. Contains the first symbol. 3568@end deffn 3569@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3570Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3571@end deffn 3572@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3573Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3574@end deffn 3575@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3576@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3577PCREL relocations. They are marked as branch to create PLT entry if 3578required. 3579@end deffn 3580@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3581Used when referencing a GOT entry. 3582@end deffn 3583@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3584Used when loading a GOT entry with movq. It is specially marked so that 3585the linker could optimize the movq to a leaq if possible. 3586@end deffn 3587@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3588Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3589@end deffn 3590@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3591Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3592@end deffn 3593@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3594Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3595@end deffn 3596@deffn {} BFD_RELOC_MACH_O_X86_64_TLV 3597Used when referencing a TLV entry. 3598@end deffn 3599@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3600Addend for PAGE or PAGEOFF. 3601@end deffn 3602@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3603Relative offset to page of GOT slot. 3604@end deffn 3605@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3606Relative offset within page of GOT slot. 3607@end deffn 3608@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3609Address of a GOT entry. 3610@end deffn 3611@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3612This is a 32 bit reloc for the microblaze that stores the 3613low 16 bits of a value 3614@end deffn 3615@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3616This is a 32 bit pc-relative reloc for the microblaze that 3617stores the low 16 bits of a value 3618@end deffn 3619@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3620This is a 32 bit reloc for the microblaze that stores a 3621value relative to the read-only small data area anchor 3622@end deffn 3623@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3624This is a 32 bit reloc for the microblaze that stores a 3625value relative to the read-write small data area anchor 3626@end deffn 3627@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3628This is a 32 bit reloc for the microblaze to handle 3629expressions of the form "Symbol Op Symbol" 3630@end deffn 3631@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3632This is a 64 bit reloc that stores the 32 bit pc relative 3633value in two words (with an imm instruction). No relocation is 3634done here - only used for relaxing 3635@end deffn 3636@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3637This is a 64 bit reloc that stores the 32 bit pc relative 3638value in two words (with an imm instruction). The relocation is 3639PC-relative GOT offset 3640@end deffn 3641@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3642This is a 64 bit reloc that stores the 32 bit pc relative 3643value in two words (with an imm instruction). The relocation is 3644GOT offset 3645@end deffn 3646@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3647This is a 64 bit reloc that stores the 32 bit pc relative 3648value in two words (with an imm instruction). The relocation is 3649PC-relative offset into PLT 3650@end deffn 3651@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3652This is a 64 bit reloc that stores the 32 bit GOT relative 3653value in two words (with an imm instruction). The relocation is 3654relative offset from _GLOBAL_OFFSET_TABLE_ 3655@end deffn 3656@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3657This is a 32 bit reloc that stores the 32 bit GOT relative 3658value in a word. The relocation is relative offset from 3659@end deffn 3660@deffn {} BFD_RELOC_MICROBLAZE_COPY 3661This is used to tell the dynamic linker to copy the value out of 3662the dynamic object into the runtime process image. 3663@end deffn 3664@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3665Unused Reloc 3666@end deffn 3667@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3668This is a 64 bit reloc that stores the 32 bit GOT relative value 3669of the GOT TLS GD info entry in two words (with an imm instruction). The 3670relocation is GOT offset. 3671@end deffn 3672@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3673This is a 64 bit reloc that stores the 32 bit GOT relative value 3674of the GOT TLS LD info entry in two words (with an imm instruction). The 3675relocation is GOT offset. 3676@end deffn 3677@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3678This is a 32 bit reloc that stores the Module ID to GOT(n). 3679@end deffn 3680@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3681This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3682@end deffn 3683@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3684This is a 32 bit reloc for storing TLS offset to two words (uses imm 3685instruction) 3686@end deffn 3687@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3688This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3689to two words (uses imm instruction). 3690@end deffn 3691@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3692This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3693to two words (uses imm instruction). 3694@end deffn 3695@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTPCREL 3696This is a 64 bit reloc that stores the 32 bit pc relative 3697value in two words (with an imm instruction). The relocation is 3698PC-relative offset from start of TEXT. 3699@end deffn 3700@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTREL 3701This is a 64 bit reloc that stores the 32 bit offset 3702value in two words (with an imm instruction). The relocation is 3703relative offset from start of TEXT. 3704@end deffn 3705@deffn {} BFD_RELOC_AARCH64_RELOC_START 3706AArch64 pseudo relocation code to mark the start of the AArch64 3707relocation enumerators. N.B. the order of the enumerators is 3708important as several tables in the AArch64 bfd backend are indexed 3709by these enumerators; make sure they are all synced. 3710@end deffn 3711@deffn {} BFD_RELOC_AARCH64_NULL 3712Deprecated AArch64 null relocation code. 3713@end deffn 3714@deffn {} BFD_RELOC_AARCH64_NONE 3715AArch64 null relocation code. 3716@end deffn 3717@deffn {} BFD_RELOC_AARCH64_64 3718@deffnx {} BFD_RELOC_AARCH64_32 3719@deffnx {} BFD_RELOC_AARCH64_16 3720Basic absolute relocations of N bits. These are equivalent to 3721BFD_RELOC_N and they were added to assist the indexing of the howto 3722table. 3723@end deffn 3724@deffn {} BFD_RELOC_AARCH64_64_PCREL 3725@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3726@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3727PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3728and they were added to assist the indexing of the howto table. 3729@end deffn 3730@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3731AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3732of an unsigned address/value. 3733@end deffn 3734@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3735AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3736an address/value. No overflow checking. 3737@end deffn 3738@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3739AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3740of an unsigned address/value. 3741@end deffn 3742@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3743AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3744of an address/value. No overflow checking. 3745@end deffn 3746@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3747AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3748of an unsigned address/value. 3749@end deffn 3750@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3751AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3752of an address/value. No overflow checking. 3753@end deffn 3754@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3755AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3756of a signed or unsigned address/value. 3757@end deffn 3758@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3759AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3760of a signed value. Changes instruction to MOVZ or MOVN depending on the 3761value's sign. 3762@end deffn 3763@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3764AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3765of a signed value. Changes instruction to MOVZ or MOVN depending on the 3766value's sign. 3767@end deffn 3768@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3769AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3770of a signed value. Changes instruction to MOVZ or MOVN depending on the 3771value's sign. 3772@end deffn 3773@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0 3774AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3775of a signed value. Changes instruction to MOVZ or MOVN depending on the 3776value's sign. 3777@end deffn 3778@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0_NC 3779AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3780of a signed value. Changes instruction to MOVZ or MOVN depending on the 3781value's sign. 3782@end deffn 3783@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1 3784AArch64 MOVK instruction with most significant bits 16 to 31 3785of a signed value. 3786@end deffn 3787@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1_NC 3788AArch64 MOVK instruction with most significant bits 16 to 31 3789of a signed value. 3790@end deffn 3791@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2 3792AArch64 MOVK instruction with most significant bits 32 to 47 3793of a signed value. 3794@end deffn 3795@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2_NC 3796AArch64 MOVK instruction with most significant bits 32 to 47 3797of a signed value. 3798@end deffn 3799@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G3 3800AArch64 MOVK instruction with most significant bits 47 to 63 3801of a signed value. 3802@end deffn 3803@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3804AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3805offset. The lowest two bits must be zero and are not stored in the 3806instruction, giving a 21 bit signed byte offset. 3807@end deffn 3808@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3809AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3810@end deffn 3811@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3812AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3813offset, giving a 4KB aligned page base address. 3814@end deffn 3815@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3816AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3817offset, giving a 4KB aligned page base address, but with no overflow 3818checking. 3819@end deffn 3820@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3821AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3822Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3823@end deffn 3824@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3825AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3826address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3827@end deffn 3828@deffn {} BFD_RELOC_AARCH64_TSTBR14 3829AArch64 14 bit pc-relative test bit and branch. 3830The lowest two bits must be zero and are not stored in the instruction, 3831giving a 16 bit signed byte offset. 3832@end deffn 3833@deffn {} BFD_RELOC_AARCH64_BRANCH19 3834AArch64 19 bit pc-relative conditional branch and compare & branch. 3835The lowest two bits must be zero and are not stored in the instruction, 3836giving a 21 bit signed byte offset. 3837@end deffn 3838@deffn {} BFD_RELOC_AARCH64_JUMP26 3839AArch64 26 bit pc-relative unconditional branch. 3840The lowest two bits must be zero and are not stored in the instruction, 3841giving a 28 bit signed byte offset. 3842@end deffn 3843@deffn {} BFD_RELOC_AARCH64_CALL26 3844AArch64 26 bit pc-relative unconditional branch and link. 3845The lowest two bits must be zero and are not stored in the instruction, 3846giving a 28 bit signed byte offset. 3847@end deffn 3848@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3849AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3850address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3851@end deffn 3852@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3853AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3854address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3855@end deffn 3856@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3857AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3858address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3859@end deffn 3860@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3861AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3862address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3863@end deffn 3864@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3865AArch64 Load Literal instruction, holding a 19 bit PC relative word 3866offset of the global offset table entry for a symbol. The lowest two 3867bits must be zero and are not stored in the instruction, giving a 21 3868bit signed byte offset. This relocation type requires signed overflow 3869checking. 3870@end deffn 3871@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3872Get to the page base of the global offset table entry for a symbol as 3873part of an ADRP instruction using a 21 bit PC relative value.Used in 3874conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3875@end deffn 3876@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3877Unsigned 12 bit byte offset for 64 bit load/store from the page of 3878the GOT entry for this symbol. Used in conjunction with 3879BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3880@end deffn 3881@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3882Unsigned 12 bit byte offset for 32 bit load/store from the page of 3883the GOT entry for this symbol. Used in conjunction with 3884BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3885@end deffn 3886@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3887Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3888for this symbol. Valid in LP64 ABI only. 3889@end deffn 3890@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3891Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3892for this symbol. Valid in LP64 ABI only. 3893@end deffn 3894@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3895Unsigned 15 bit byte offset for 64 bit load/store from the page of 3896the GOT entry for this symbol. Valid in LP64 ABI only. 3897@end deffn 3898@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3899Scaled 14 bit byte offset to the page base of the global offset table. 3900@end deffn 3901@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3902Scaled 15 bit byte offset to the page base of the global offset table. 3903@end deffn 3904@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3905Get to the page base of the global offset table entry for a symbols 3906tls_index structure as part of an adrp instruction using a 21 bit PC 3907relative value. Used in conjunction with 3908BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3909@end deffn 3910@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3911AArch64 TLS General Dynamic 3912@end deffn 3913@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3914Unsigned 12 bit byte offset to global offset table entry for a symbols 3915tls_index structure. Used in conjunction with 3916BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3917@end deffn 3918@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3919AArch64 TLS General Dynamic relocation. 3920@end deffn 3921@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3922AArch64 TLS General Dynamic relocation. 3923@end deffn 3924@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3925AArch64 TLS INITIAL EXEC relocation. 3926@end deffn 3927@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3928AArch64 TLS INITIAL EXEC relocation. 3929@end deffn 3930@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3931AArch64 TLS INITIAL EXEC relocation. 3932@end deffn 3933@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3934AArch64 TLS INITIAL EXEC relocation. 3935@end deffn 3936@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3937AArch64 TLS INITIAL EXEC relocation. 3938@end deffn 3939@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3940AArch64 TLS INITIAL EXEC relocation. 3941@end deffn 3942@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3943bit[23:12] of byte offset to module TLS base address. 3944@end deffn 3945@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3946Unsigned 12 bit byte offset to module TLS base address. 3947@end deffn 3948@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3949No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3950@end deffn 3951@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3952Unsigned 12 bit byte offset to global offset table entry for a symbols 3953tls_index structure. Used in conjunction with 3954BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3955@end deffn 3956@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3957GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3958instruction. 3959@end deffn 3960@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3961GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 3962@end deffn 3963@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 3964bit[11:1] of byte offset to module TLS base address, encoded in ldst 3965instructions. 3966@end deffn 3967@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 3968Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 3969@end deffn 3970@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 3971bit[11:2] of byte offset to module TLS base address, encoded in ldst 3972instructions. 3973@end deffn 3974@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 3975Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 3976@end deffn 3977@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 3978bit[11:3] of byte offset to module TLS base address, encoded in ldst 3979instructions. 3980@end deffn 3981@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 3982Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 3983@end deffn 3984@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 3985bit[11:0] of byte offset to module TLS base address, encoded in ldst 3986instructions. 3987@end deffn 3988@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 3989Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 3990@end deffn 3991@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3992bit[15:0] of byte offset to module TLS base address. 3993@end deffn 3994@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 3995No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3996@end deffn 3997@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3998bit[31:16] of byte offset to module TLS base address. 3999@end deffn 4000@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 4001No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4002@end deffn 4003@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 4004bit[47:32] of byte offset to module TLS base address. 4005@end deffn 4006@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 4007AArch64 TLS LOCAL EXEC relocation. 4008@end deffn 4009@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 4010AArch64 TLS LOCAL EXEC relocation. 4011@end deffn 4012@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 4013AArch64 TLS LOCAL EXEC relocation. 4014@end deffn 4015@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4016AArch64 TLS LOCAL EXEC relocation. 4017@end deffn 4018@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4019AArch64 TLS LOCAL EXEC relocation. 4020@end deffn 4021@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4022AArch64 TLS LOCAL EXEC relocation. 4023@end deffn 4024@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4025AArch64 TLS LOCAL EXEC relocation. 4026@end deffn 4027@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4028AArch64 TLS LOCAL EXEC relocation. 4029@end deffn 4030@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 4031bit[11:1] of byte offset to module TLS base address, encoded in ldst 4032instructions. 4033@end deffn 4034@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 4035Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check. 4036@end deffn 4037@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 4038bit[11:2] of byte offset to module TLS base address, encoded in ldst 4039instructions. 4040@end deffn 4041@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 4042Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check. 4043@end deffn 4044@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 4045bit[11:3] of byte offset to module TLS base address, encoded in ldst 4046instructions. 4047@end deffn 4048@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 4049Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check. 4050@end deffn 4051@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 4052bit[11:0] of byte offset to module TLS base address, encoded in ldst 4053instructions. 4054@end deffn 4055@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 4056Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check. 4057@end deffn 4058@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4059AArch64 TLS DESC relocation. 4060@end deffn 4061@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4062AArch64 TLS DESC relocation. 4063@end deffn 4064@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4065AArch64 TLS DESC relocation. 4066@end deffn 4067@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4068AArch64 TLS DESC relocation. 4069@end deffn 4070@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4071AArch64 TLS DESC relocation. 4072@end deffn 4073@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4074AArch64 TLS DESC relocation. 4075@end deffn 4076@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4077AArch64 TLS DESC relocation. 4078@end deffn 4079@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4080AArch64 TLS DESC relocation. 4081@end deffn 4082@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 4083AArch64 TLS DESC relocation. 4084@end deffn 4085@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 4086AArch64 TLS DESC relocation. 4087@end deffn 4088@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 4089AArch64 TLS DESC relocation. 4090@end deffn 4091@deffn {} BFD_RELOC_AARCH64_COPY 4092AArch64 TLS relocation. 4093@end deffn 4094@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 4095AArch64 TLS relocation. 4096@end deffn 4097@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 4098AArch64 TLS relocation. 4099@end deffn 4100@deffn {} BFD_RELOC_AARCH64_RELATIVE 4101AArch64 TLS relocation. 4102@end deffn 4103@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4104AArch64 TLS relocation. 4105@end deffn 4106@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 4107AArch64 TLS relocation. 4108@end deffn 4109@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 4110AArch64 TLS relocation. 4111@end deffn 4112@deffn {} BFD_RELOC_AARCH64_TLSDESC 4113AArch64 TLS relocation. 4114@end deffn 4115@deffn {} BFD_RELOC_AARCH64_IRELATIVE 4116AArch64 support for STT_GNU_IFUNC. 4117@end deffn 4118@deffn {} BFD_RELOC_AARCH64_RELOC_END 4119AArch64 pseudo relocation code to mark the end of the AArch64 4120relocation enumerators that have direct mapping to ELF reloc codes. 4121There are a few more enumerators after this one; those are mainly 4122used by the AArch64 assembler for the internal fixup or to select 4123one of the above enumerators. 4124@end deffn 4125@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4126AArch64 pseudo relocation code to be used internally by the AArch64 4127assembler and not (currently) written to any object files. 4128@end deffn 4129@deffn {} BFD_RELOC_AARCH64_LDST_LO12 4130AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4131address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4132@end deffn 4133@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4134AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 4135used internally by the AArch64 assembler and not (currently) written to 4136any object files. 4137@end deffn 4138@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4139Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 4140@end deffn 4141@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 4142AArch64 pseudo relocation code for TLS local exec mode. It's to be 4143used internally by the AArch64 assembler and not (currently) written to 4144any object files. 4145@end deffn 4146@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC 4147Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check. 4148@end deffn 4149@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4150AArch64 pseudo relocation code to be used internally by the AArch64 4151assembler and not (currently) written to any object files. 4152@end deffn 4153@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4154AArch64 pseudo relocation code to be used internally by the AArch64 4155assembler and not (currently) written to any object files. 4156@end deffn 4157@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4158AArch64 pseudo relocation code to be used internally by the AArch64 4159assembler and not (currently) written to any object files. 4160@end deffn 4161@deffn {} BFD_RELOC_TILEPRO_COPY 4162@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4163@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4164@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4165@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4166@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4167@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4168@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4169@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4170@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4171@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4172@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4173@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4174@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4175@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4176@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4177@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4178@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4179@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4180@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4181@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4182@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4183@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4184@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4185@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4186@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4187@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4188@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4189@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4190@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4191@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4192@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4193@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4194@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4195@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4196@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4197@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4198@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4199@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4200@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4201@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4202@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4203@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4204@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4205@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4206@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4207@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4208@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4209@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4210@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4211@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4212@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4213@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4214@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4215@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4216@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4217@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4218@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4219@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4220@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4221@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4222@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4223@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4224@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4225@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4226@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4227@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4228@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4229@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4230@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4231@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4232@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4233@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4234@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4235@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4236@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4237@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4238@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4239@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4240Tilera TILEPro Relocations. 4241@end deffn 4242@deffn {} BFD_RELOC_TILEGX_HW0 4243@deffnx {} BFD_RELOC_TILEGX_HW1 4244@deffnx {} BFD_RELOC_TILEGX_HW2 4245@deffnx {} BFD_RELOC_TILEGX_HW3 4246@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4247@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4248@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4249@deffnx {} BFD_RELOC_TILEGX_COPY 4250@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4251@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4252@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4253@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4254@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4255@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4256@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4257@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4258@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4259@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4260@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4261@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4262@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4263@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4264@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4265@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4266@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4267@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4268@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4269@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4270@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4271@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4272@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4273@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4274@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4275@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4276@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4277@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4278@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4279@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4280@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4281@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4282@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4283@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4284@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4285@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4286@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4287@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4288@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4289@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4290@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4291@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4292@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4293@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4294@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4295@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4296@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4297@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4298@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4299@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4300@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4301@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4302@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4303@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4304@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4305@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4306@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4307@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4308@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4309@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4310@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4311@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4312@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4313@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4314@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4315@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4316@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4317@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4318@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4319@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4320@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4321@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4322@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4323@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4324@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4325@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4326@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4327@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4328@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4329@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4330@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4331@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4332@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4333@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4334@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4335@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4336@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4337@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4338@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4339@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4340@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4341@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4342@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4343@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4344@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4345@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4346@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4347@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4348@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4349@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4350@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4351Tilera TILE-Gx Relocations. 4352@end deffn 4353@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4354Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4355@end deffn 4356@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4357Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4358@end deffn 4359@deffn {} BFD_RELOC_EPIPHANY_HIGH 4360Adapteva EPIPHANY - 16 most-significant bits of absolute address 4361@end deffn 4362@deffn {} BFD_RELOC_EPIPHANY_LOW 4363Adapteva EPIPHANY - 16 least-significant bits of absolute address 4364@end deffn 4365@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4366Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4367@end deffn 4368@deffn {} BFD_RELOC_EPIPHANY_IMM11 4369Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4370@end deffn 4371@deffn {} BFD_RELOC_EPIPHANY_IMM8 4372Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4373@end deffn 4374@deffn {} BFD_RELOC_VISIUM_HI16 4375@deffnx {} BFD_RELOC_VISIUM_LO16 4376@deffnx {} BFD_RELOC_VISIUM_IM16 4377@deffnx {} BFD_RELOC_VISIUM_REL16 4378@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4379@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4380@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4381Visium Relocations. 4382@end deffn 4383@deffn {} BFD_RELOC_WASM32_LEB128 4384@deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4385@deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4386@deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4387@deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4388@deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4389@deffnx {} BFD_RELOC_WASM32_COPY 4390@deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4391@deffnx {} BFD_RELOC_WASM32_INDEX 4392@deffnx {} BFD_RELOC_WASM32_PLT_SIG 4393WebAssembly relocations. 4394@end deffn 4395 4396@example 4397 4398typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4399@end example 4400@findex bfd_reloc_type_lookup 4401@subsubsection @code{bfd_reloc_type_lookup} 4402@strong{Synopsis} 4403@example 4404reloc_howto_type *bfd_reloc_type_lookup 4405 (bfd *abfd, bfd_reloc_code_real_type code); 4406reloc_howto_type *bfd_reloc_name_lookup 4407 (bfd *abfd, const char *reloc_name); 4408@end example 4409@strong{Description}@* 4410Return a pointer to a howto structure which, when 4411invoked, will perform the relocation @var{code} on data from the 4412architecture noted. 4413 4414@findex bfd_default_reloc_type_lookup 4415@subsubsection @code{bfd_default_reloc_type_lookup} 4416@strong{Synopsis} 4417@example 4418reloc_howto_type *bfd_default_reloc_type_lookup 4419 (bfd *abfd, bfd_reloc_code_real_type code); 4420@end example 4421@strong{Description}@* 4422Provides a default relocation lookup routine for any architecture. 4423 4424@findex bfd_get_reloc_code_name 4425@subsubsection @code{bfd_get_reloc_code_name} 4426@strong{Synopsis} 4427@example 4428const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4429@end example 4430@strong{Description}@* 4431Provides a printable name for the supplied relocation code. 4432Useful mainly for printing error messages. 4433 4434@findex bfd_generic_relax_section 4435@subsubsection @code{bfd_generic_relax_section} 4436@strong{Synopsis} 4437@example 4438bfd_boolean bfd_generic_relax_section 4439 (bfd *abfd, 4440 asection *section, 4441 struct bfd_link_info *, 4442 bfd_boolean *); 4443@end example 4444@strong{Description}@* 4445Provides default handling for relaxing for back ends which 4446don't do relaxing. 4447 4448@findex bfd_generic_gc_sections 4449@subsubsection @code{bfd_generic_gc_sections} 4450@strong{Synopsis} 4451@example 4452bfd_boolean bfd_generic_gc_sections 4453 (bfd *, struct bfd_link_info *); 4454@end example 4455@strong{Description}@* 4456Provides default handling for relaxing for back ends which 4457don't do section gc -- i.e., does nothing. 4458 4459@findex bfd_generic_lookup_section_flags 4460@subsubsection @code{bfd_generic_lookup_section_flags} 4461@strong{Synopsis} 4462@example 4463bfd_boolean bfd_generic_lookup_section_flags 4464 (struct bfd_link_info *, struct flag_info *, asection *); 4465@end example 4466@strong{Description}@* 4467Provides default handling for section flags lookup 4468-- i.e., does nothing. 4469Returns FALSE if the section should be omitted, otherwise TRUE. 4470 4471@findex bfd_generic_merge_sections 4472@subsubsection @code{bfd_generic_merge_sections} 4473@strong{Synopsis} 4474@example 4475bfd_boolean bfd_generic_merge_sections 4476 (bfd *, struct bfd_link_info *); 4477@end example 4478@strong{Description}@* 4479Provides default handling for SEC_MERGE section merging for back ends 4480which don't have SEC_MERGE support -- i.e., does nothing. 4481 4482@findex bfd_generic_get_relocated_section_contents 4483@subsubsection @code{bfd_generic_get_relocated_section_contents} 4484@strong{Synopsis} 4485@example 4486bfd_byte *bfd_generic_get_relocated_section_contents 4487 (bfd *abfd, 4488 struct bfd_link_info *link_info, 4489 struct bfd_link_order *link_order, 4490 bfd_byte *data, 4491 bfd_boolean relocatable, 4492 asymbol **symbols); 4493@end example 4494@strong{Description}@* 4495Provides default handling of relocation effort for back ends 4496which can't be bothered to do it efficiently. 4497 4498@findex _bfd_generic_set_reloc 4499@subsubsection @code{_bfd_generic_set_reloc} 4500@strong{Synopsis} 4501@example 4502void _bfd_generic_set_reloc 4503 (bfd *abfd, 4504 sec_ptr section, 4505 arelent **relptr, 4506 unsigned int count); 4507@end example 4508@strong{Description}@* 4509Installs a new set of internal relocations in SECTION. 4510 4511@findex _bfd_unrecognized_reloc 4512@subsubsection @code{_bfd_unrecognized_reloc} 4513@strong{Synopsis} 4514@example 4515bfd_boolean _bfd_unrecognized_reloc 4516 (bfd * abfd, 4517 sec_ptr section, 4518 unsigned int r_type); 4519@end example 4520@strong{Description}@* 4521Reports an unrecognized reloc. 4522Written as a function in order to reduce code duplication. 4523Returns FALSE so that it can be called from a return statement. 4524 4525