1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. Note - the value 2 is used so that it 31 will not be mistaken for the boolean TRUE or FALSE values. */ 32 bfd_reloc_ok = 2, 33 34 /* The relocation was performed, but there was an overflow. */ 35 bfd_reloc_overflow, 36 37 /* The address to relocate was not within the section supplied. */ 38 bfd_reloc_outofrange, 39 40 /* Used by special functions. */ 41 bfd_reloc_continue, 42 43 /* Unsupported relocation size requested. */ 44 bfd_reloc_notsupported, 45 46 /* Unused. */ 47 bfd_reloc_other, 48 49 /* The symbol to relocate against was undefined. */ 50 bfd_reloc_undefined, 51 52 /* The relocation was performed, but may not be ok. If this type is 53 returned, the error_message argument to bfd_perform_relocation 54 will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59typedef const struct reloc_howto_struct reloc_howto_type; 60 61typedef struct reloc_cache_entry 62@{ 63 /* A pointer into the canonical table of pointers. */ 64 struct bfd_symbol **sym_ptr_ptr; 65 66 /* offset in section. */ 67 bfd_size_type address; 68 69 /* addend for relocation value. */ 70 bfd_vma addend; 71 72 /* Pointer to how to perform the required relocation. */ 73 reloc_howto_type *howto; 74 75@} 76arelent; 77 78@end example 79@strong{Description}@* 80Here is a description of each of the fields within an @code{arelent}: 81 82@itemize @bullet 83 84@item 85@code{sym_ptr_ptr} 86@end itemize 87The symbol table pointer points to a pointer to the symbol 88associated with the relocation request. It is the pointer 89into the table returned by the back end's 90@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 91referenced through a pointer to a pointer so that tools like 92the linker can fix up all the symbols of the same name by 93modifying only one pointer. The relocation routine looks in 94the symbol and uses the base of the section the symbol is 95attached to and the value of the symbol as the initial 96relocation offset. If the symbol pointer is zero, then the 97section provided is looked up. 98 99@itemize @bullet 100 101@item 102@code{address} 103@end itemize 104The @code{address} field gives the offset in bytes from the base of 105the section data which owns the relocation record to the first 106byte of relocatable information. The actual data relocated 107will be relative to this point; for example, a relocation 108type which modifies the bottom two bytes of a four byte word 109would not touch the first byte pointed to in a big endian 110world. 111 112@itemize @bullet 113 114@item 115@code{addend} 116@end itemize 117The @code{addend} is a value provided by the back end to be added (!) 118to the relocation offset. Its interpretation is dependent upon 119the howto. For example, on the 68k the code: 120 121@example 122 char foo[]; 123 main() 124 @{ 125 return foo[0x12345678]; 126 @} 127@end example 128 129Could be compiled into: 130 131@example 132 linkw fp,#-4 133 moveb @@#12345678,d0 134 extbl d0 135 unlk fp 136 rts 137@end example 138 139This could create a reloc pointing to @code{foo}, but leave the 140offset in the data, something like: 141 142@example 143RELOCATION RECORDS FOR [.text]: 144offset type value 14500000006 32 _foo 146 14700000000 4e56 fffc ; linkw fp,#-4 14800000004 1039 1234 5678 ; moveb @@#12345678,d0 1490000000a 49c0 ; extbl d0 1500000000c 4e5e ; unlk fp 1510000000e 4e75 ; rts 152@end example 153 154Using coff and an 88k, some instructions don't have enough 155space in them to represent the full address range, and 156pointers have to be loaded in two parts. So you'd get something like: 157 158@example 159 or.u r13,r0,hi16(_foo+0x12345678) 160 ld.b r2,r13,lo16(_foo+0x12345678) 161 jmp r1 162@end example 163 164This should create two relocs, both pointing to @code{_foo}, and with 1650x12340000 in their addend field. The data would consist of: 166 167@example 168RELOCATION RECORDS FOR [.text]: 169offset type value 17000000002 HVRT16 _foo+0x12340000 17100000006 LVRT16 _foo+0x12340000 172 17300000000 5da05678 ; or.u r13,r0,0x5678 17400000004 1c4d5678 ; ld.b r2,r13,0x5678 17500000008 f400c001 ; jmp r1 176@end example 177 178The relocation routine digs out the value from the data, adds 179it to the addend to get the original offset, and then adds the 180value of @code{_foo}. Note that all 32 bits have to be kept around 181somewhere, to cope with carry from bit 15 to bit 16. 182 183One further example is the sparc and the a.out format. The 184sparc has a similar problem to the 88k, in that some 185instructions don't have room for an entire offset, but on the 186sparc the parts are created in odd sized lumps. The designers of 187the a.out format chose to not use the data within the section 188for storing part of the offset; all the offset is kept within 189the reloc. Anything in the data should be ignored. 190 191@example 192 save %sp,-112,%sp 193 sethi %hi(_foo+0x12345678),%g2 194 ldsb [%g2+%lo(_foo+0x12345678)],%i0 195 ret 196 restore 197@end example 198 199Both relocs contain a pointer to @code{foo}, and the offsets 200contain junk. 201 202@example 203RELOCATION RECORDS FOR [.text]: 204offset type value 20500000004 HI22 _foo+0x12345678 20600000008 LO10 _foo+0x12345678 207 20800000000 9de3bf90 ; save %sp,-112,%sp 20900000004 05000000 ; sethi %hi(_foo+0),%g2 21000000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2110000000c 81c7e008 ; ret 21200000010 81e80000 ; restore 213@end example 214 215@itemize @bullet 216 217@item 218@code{howto} 219@end itemize 220The @code{howto} field can be imagined as a 221relocation instruction. It is a pointer to a structure which 222contains information on what to do with all of the other 223information in the reloc record and data section. A back end 224would normally have a relocation instruction set and turn 225relocations into pointers to the correct structure on input - 226but it would be possible to create each howto field on demand. 227 228@subsubsection @code{enum complain_overflow} 229Indicates what sort of overflow checking should be done when 230performing a relocation. 231 232 233@example 234 235enum complain_overflow 236@{ 237 /* Do not complain on overflow. */ 238 complain_overflow_dont, 239 240 /* Complain if the value overflows when considered as a signed 241 number one bit larger than the field. ie. A bitfield of N bits 242 is allowed to represent -2**n to 2**n-1. */ 243 complain_overflow_bitfield, 244 245 /* Complain if the value overflows when considered as a signed 246 number. */ 247 complain_overflow_signed, 248 249 /* Complain if the value overflows when considered as an 250 unsigned number. */ 251 complain_overflow_unsigned 252@}; 253@end example 254@subsubsection @code{reloc_howto_type} 255The @code{reloc_howto_type} is a structure which contains all the 256information that libbfd needs to know to tie up a back end's data. 257 258 259@example 260struct reloc_howto_struct 261@{ 262 /* The type field has mainly a documentary use - the back end can 263 do what it wants with it, though normally the back end's idea of 264 an external reloc number is stored in this field. */ 265 unsigned int type; 266 267 /* The size of the item to be relocated in bytes. */ 268 unsigned int size:4; 269 270 /* The number of bits in the field to be relocated. This is used 271 when doing overflow checking. */ 272 unsigned int bitsize:7; 273 274 /* The value the final relocation is shifted right by. This drops 275 unwanted data from the relocation. */ 276 unsigned int rightshift:6; 277 278 /* The bit position of the reloc value in the destination. 279 The relocated value is left shifted by this amount. */ 280 unsigned int bitpos:6; 281 282 /* What type of overflow error should be checked for when 283 relocating. */ 284 ENUM_BITFIELD (complain_overflow) complain_on_overflow:2; 285 286 /* The relocation value should be negated before applying. */ 287 unsigned int negate:1; 288 289 /* The relocation is relative to the item being relocated. */ 290 unsigned int pc_relative:1; 291 292 /* Some formats record a relocation addend in the section contents 293 rather than with the relocation. For ELF formats this is the 294 distinction between USE_REL and USE_RELA (though the code checks 295 for USE_REL == 1/0). The value of this field is TRUE if the 296 addend is recorded with the section contents; when performing a 297 partial link (ld -r) the section contents (the data) will be 298 modified. The value of this field is FALSE if addends are 299 recorded with the relocation (in arelent.addend); when performing 300 a partial link the relocation will be modified. 301 All relocations for all ELF USE_RELA targets should set this field 302 to FALSE (values of TRUE should be looked on with suspicion). 303 However, the converse is not true: not all relocations of all ELF 304 USE_REL targets set this field to TRUE. Why this is so is peculiar 305 to each particular target. For relocs that aren't used in partial 306 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 307 unsigned int partial_inplace:1; 308 309 /* When some formats create PC relative instructions, they leave 310 the value of the pc of the place being relocated in the offset 311 slot of the instruction, so that a PC relative relocation can 312 be made just by adding in an ordinary offset (e.g., sun3 a.out). 313 Some formats leave the displacement part of an instruction 314 empty (e.g., ELF); this flag signals the fact. */ 315 unsigned int pcrel_offset:1; 316 317 /* src_mask selects the part of the instruction (or data) to be used 318 in the relocation sum. If the target relocations don't have an 319 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 320 dst_mask to extract the addend from the section contents. If 321 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 322 field should normally be zero. Non-zero values for ELF USE_RELA 323 targets should be viewed with suspicion as normally the value in 324 the dst_mask part of the section contents should be ignored. */ 325 bfd_vma src_mask; 326 327 /* dst_mask selects which parts of the instruction (or data) are 328 replaced with a relocated value. */ 329 bfd_vma dst_mask; 330 331 /* If this field is non null, then the supplied function is 332 called rather than the normal function. This allows really 333 strange relocation methods to be accommodated. */ 334 bfd_reloc_status_type (*special_function) 335 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 336 bfd *, char **); 337 338 /* The textual name of the relocation type. */ 339 const char *name; 340@}; 341 342@end example 343@findex The HOWTO Macro 344@subsubsection @code{The HOWTO Macro} 345@strong{Description}@* 346The HOWTO macro fills in a reloc_howto_type (a typedef for 347const struct reloc_howto_struct). 348@example 349#define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz)) 350#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \ 351 inplace, src_mask, dst_mask, pcrel_off) \ 352 @{ (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \ 353 size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name @} 354@end example 355 356@strong{Description}@* 357This is used to fill in an empty howto entry in an array. 358@example 359#define EMPTY_HOWTO(C) \ 360 HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \ 361 NULL, false, 0, 0, false) 362 363static inline unsigned int 364bfd_get_reloc_size (reloc_howto_type *howto) 365@{ 366 return howto->size; 367@} 368 369@end example 370 371@findex arelent_chain 372@subsubsection @code{arelent_chain} 373@strong{Description}@* 374How relocs are tied together in an @code{asection}: 375@example 376typedef struct relent_chain 377@{ 378 arelent relent; 379 struct relent_chain *next; 380@} 381arelent_chain; 382 383@end example 384 385@findex bfd_check_overflow 386@subsubsection @code{bfd_check_overflow} 387@strong{Synopsis} 388@example 389bfd_reloc_status_type bfd_check_overflow 390 (enum complain_overflow how, 391 unsigned int bitsize, 392 unsigned int rightshift, 393 unsigned int addrsize, 394 bfd_vma relocation); 395@end example 396@strong{Description}@* 397Perform overflow checking on @var{relocation} which has 398@var{bitsize} significant bits and will be shifted right by 399@var{rightshift} bits, on a machine with addresses containing 400@var{addrsize} significant bits. The result is either of 401@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 402 403@findex bfd_reloc_offset_in_range 404@subsubsection @code{bfd_reloc_offset_in_range} 405@strong{Synopsis} 406@example 407bool bfd_reloc_offset_in_range 408 (reloc_howto_type *howto, 409 bfd *abfd, 410 asection *section, 411 bfd_size_type offset); 412@end example 413@strong{Description}@* 414Returns TRUE if the reloc described by @var{HOWTO} can be 415applied at @var{OFFSET} octets in @var{SECTION}. 416 417@findex bfd_perform_relocation 418@subsubsection @code{bfd_perform_relocation} 419@strong{Synopsis} 420@example 421bfd_reloc_status_type bfd_perform_relocation 422 (bfd *abfd, 423 arelent *reloc_entry, 424 void *data, 425 asection *input_section, 426 bfd *output_bfd, 427 char **error_message); 428@end example 429@strong{Description}@* 430If @var{output_bfd} is supplied to this function, the 431generated image will be relocatable; the relocations are 432copied to the output file after they have been changed to 433reflect the new state of the world. There are two ways of 434reflecting the results of partial linkage in an output file: 435by modifying the output data in place, and by modifying the 436relocation record. Some native formats (e.g., basic a.out and 437basic coff) have no way of specifying an addend in the 438relocation type, so the addend has to go in the output data. 439This is no big deal since in these formats the output data 440slot will always be big enough for the addend. Complex reloc 441types with addends were invented to solve just this problem. 442The @var{error_message} argument is set to an error message if 443this return @code{bfd_reloc_dangerous}. 444 445@findex bfd_install_relocation 446@subsubsection @code{bfd_install_relocation} 447@strong{Synopsis} 448@example 449bfd_reloc_status_type bfd_install_relocation 450 (bfd *abfd, 451 arelent *reloc_entry, 452 void *data, bfd_vma data_start, 453 asection *input_section, 454 char **error_message); 455@end example 456@strong{Description}@* 457This looks remarkably like @code{bfd_perform_relocation}, except it 458does not expect that the section contents have been filled in. 459I.e., it's suitable for use when creating, rather than applying 460a relocation. 461 462For now, this function should be considered reserved for the 463assembler. 464 465 466@node howto manager, , typedef arelent, Relocations 467@subsection The howto manager 468When an application wants to create a relocation, but doesn't 469know what the target machine might call it, it can find out by 470using this bit of code. 471 472@findex bfd_reloc_code_type 473@subsubsection @code{bfd_reloc_code_type} 474@strong{Description}@* 475The insides of a reloc code. The idea is that, eventually, there 476will be one enumerator for every type of relocation we ever do. 477Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 478return a howto pointer. 479 480This does mean that the application must determine the correct 481enumerator value; you can't get a howto pointer from a random set 482of attributes. 483 484Here are the possible values for @code{enum bfd_reloc_code_real}: 485 486@deffn {} BFD_RELOC_64 487@deffnx {} BFD_RELOC_32 488@deffnx {} BFD_RELOC_26 489@deffnx {} BFD_RELOC_24 490@deffnx {} BFD_RELOC_16 491@deffnx {} BFD_RELOC_14 492@deffnx {} BFD_RELOC_8 493Basic absolute relocations of N bits. 494@end deffn 495@deffn {} BFD_RELOC_64_PCREL 496@deffnx {} BFD_RELOC_32_PCREL 497@deffnx {} BFD_RELOC_24_PCREL 498@deffnx {} BFD_RELOC_16_PCREL 499@deffnx {} BFD_RELOC_12_PCREL 500@deffnx {} BFD_RELOC_8_PCREL 501PC-relative relocations. Sometimes these are relative to the address 502of the relocation itself; sometimes they are relative to the start of 503the section containing the relocation. It depends on the specific target. 504@end deffn 505@deffn {} BFD_RELOC_32_SECREL 506@deffnx {} BFD_RELOC_16_SECIDX 507Section relative relocations. Some targets need this for DWARF2. 508@end deffn 509@deffn {} BFD_RELOC_32_GOT_PCREL 510@deffnx {} BFD_RELOC_16_GOT_PCREL 511@deffnx {} BFD_RELOC_8_GOT_PCREL 512@deffnx {} BFD_RELOC_32_GOTOFF 513@deffnx {} BFD_RELOC_16_GOTOFF 514@deffnx {} BFD_RELOC_LO16_GOTOFF 515@deffnx {} BFD_RELOC_HI16_GOTOFF 516@deffnx {} BFD_RELOC_HI16_S_GOTOFF 517@deffnx {} BFD_RELOC_8_GOTOFF 518@deffnx {} BFD_RELOC_64_PLT_PCREL 519@deffnx {} BFD_RELOC_32_PLT_PCREL 520@deffnx {} BFD_RELOC_24_PLT_PCREL 521@deffnx {} BFD_RELOC_16_PLT_PCREL 522@deffnx {} BFD_RELOC_8_PLT_PCREL 523@deffnx {} BFD_RELOC_64_PLTOFF 524@deffnx {} BFD_RELOC_32_PLTOFF 525@deffnx {} BFD_RELOC_16_PLTOFF 526@deffnx {} BFD_RELOC_LO16_PLTOFF 527@deffnx {} BFD_RELOC_HI16_PLTOFF 528@deffnx {} BFD_RELOC_HI16_S_PLTOFF 529@deffnx {} BFD_RELOC_8_PLTOFF 530For ELF. 531@end deffn 532@deffn {} BFD_RELOC_SIZE32 533@deffnx {} BFD_RELOC_SIZE64 534Size relocations. 535@end deffn 536@deffn {} BFD_RELOC_68K_GLOB_DAT 537@deffnx {} BFD_RELOC_68K_JMP_SLOT 538@deffnx {} BFD_RELOC_68K_RELATIVE 539@deffnx {} BFD_RELOC_68K_TLS_GD32 540@deffnx {} BFD_RELOC_68K_TLS_GD16 541@deffnx {} BFD_RELOC_68K_TLS_GD8 542@deffnx {} BFD_RELOC_68K_TLS_LDM32 543@deffnx {} BFD_RELOC_68K_TLS_LDM16 544@deffnx {} BFD_RELOC_68K_TLS_LDM8 545@deffnx {} BFD_RELOC_68K_TLS_LDO32 546@deffnx {} BFD_RELOC_68K_TLS_LDO16 547@deffnx {} BFD_RELOC_68K_TLS_LDO8 548@deffnx {} BFD_RELOC_68K_TLS_IE32 549@deffnx {} BFD_RELOC_68K_TLS_IE16 550@deffnx {} BFD_RELOC_68K_TLS_IE8 551@deffnx {} BFD_RELOC_68K_TLS_LE32 552@deffnx {} BFD_RELOC_68K_TLS_LE16 553@deffnx {} BFD_RELOC_68K_TLS_LE8 554Relocations used by 68K ELF. 555@end deffn 556@deffn {} BFD_RELOC_VAX_GLOB_DAT 557@deffnx {} BFD_RELOC_VAX_GLOB_REF 558@deffnx {} BFD_RELOC_VAX_JMP_SLOT 559@deffnx {} BFD_RELOC_VAX_RELATIVE 560Relocations used by VAX ELF. 561@end deffn 562@deffn {} BFD_RELOC_32_BASEREL 563@deffnx {} BFD_RELOC_16_BASEREL 564@deffnx {} BFD_RELOC_LO16_BASEREL 565@deffnx {} BFD_RELOC_HI16_BASEREL 566@deffnx {} BFD_RELOC_HI16_S_BASEREL 567@deffnx {} BFD_RELOC_8_BASEREL 568@deffnx {} BFD_RELOC_RVA 569Linkage-table relative. 570@end deffn 571@deffn {} BFD_RELOC_8_FFnn 572Absolute 8-bit relocation, but used to form an address like 0xFFnn. 573@end deffn 574@deffn {} BFD_RELOC_32_PCREL_S2 575@deffnx {} BFD_RELOC_16_PCREL_S2 576@deffnx {} BFD_RELOC_23_PCREL_S2 577These PC-relative relocations are stored as word displacements -- 578i.e., byte displacements shifted right two bits. The 30-bit word 579displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 580SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 581signed 16-bit displacement is used on the MIPS, and the 23-bit 582displacement is used on the Alpha. 583@end deffn 584@deffn {} BFD_RELOC_HI22 585@deffnx {} BFD_RELOC_LO10 586High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 587the target word. These are used on the SPARC. 588@end deffn 589@deffn {} BFD_RELOC_GPREL16 590@deffnx {} BFD_RELOC_GPREL32 591For systems that allocate a Global Pointer register, these are 592displacements off that register. These relocation types are 593handled specially, because the value the register will have is 594decided relatively late. 595@end deffn 596@deffn {} BFD_RELOC_NONE 597@deffnx {} BFD_RELOC_SPARC_WDISP22 598@deffnx {} BFD_RELOC_SPARC22 599@deffnx {} BFD_RELOC_SPARC13 600@deffnx {} BFD_RELOC_SPARC_GOT10 601@deffnx {} BFD_RELOC_SPARC_GOT13 602@deffnx {} BFD_RELOC_SPARC_GOT22 603@deffnx {} BFD_RELOC_SPARC_PC10 604@deffnx {} BFD_RELOC_SPARC_PC22 605@deffnx {} BFD_RELOC_SPARC_WPLT30 606@deffnx {} BFD_RELOC_SPARC_COPY 607@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 608@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 609@deffnx {} BFD_RELOC_SPARC_RELATIVE 610@deffnx {} BFD_RELOC_SPARC_UA16 611@deffnx {} BFD_RELOC_SPARC_UA32 612@deffnx {} BFD_RELOC_SPARC_UA64 613@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 614@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 615@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 616@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 617@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 618@deffnx {} BFD_RELOC_SPARC_JMP_IREL 619@deffnx {} BFD_RELOC_SPARC_IRELATIVE 620SPARC ELF relocations. There is probably some overlap with other 621relocation types already defined. 622@end deffn 623@deffn {} BFD_RELOC_SPARC_BASE13 624@deffnx {} BFD_RELOC_SPARC_BASE22 625I think these are specific to SPARC a.out (e.g., Sun 4). 626@end deffn 627@deffn {} BFD_RELOC_SPARC_64 628@deffnx {} BFD_RELOC_SPARC_10 629@deffnx {} BFD_RELOC_SPARC_11 630@deffnx {} BFD_RELOC_SPARC_OLO10 631@deffnx {} BFD_RELOC_SPARC_HH22 632@deffnx {} BFD_RELOC_SPARC_HM10 633@deffnx {} BFD_RELOC_SPARC_LM22 634@deffnx {} BFD_RELOC_SPARC_PC_HH22 635@deffnx {} BFD_RELOC_SPARC_PC_HM10 636@deffnx {} BFD_RELOC_SPARC_PC_LM22 637@deffnx {} BFD_RELOC_SPARC_WDISP16 638@deffnx {} BFD_RELOC_SPARC_WDISP19 639@deffnx {} BFD_RELOC_SPARC_7 640@deffnx {} BFD_RELOC_SPARC_6 641@deffnx {} BFD_RELOC_SPARC_5 642@deffnx {} BFD_RELOC_SPARC_DISP64 643@deffnx {} BFD_RELOC_SPARC_PLT32 644@deffnx {} BFD_RELOC_SPARC_PLT64 645@deffnx {} BFD_RELOC_SPARC_HIX22 646@deffnx {} BFD_RELOC_SPARC_LOX10 647@deffnx {} BFD_RELOC_SPARC_H44 648@deffnx {} BFD_RELOC_SPARC_M44 649@deffnx {} BFD_RELOC_SPARC_L44 650@deffnx {} BFD_RELOC_SPARC_REGISTER 651@deffnx {} BFD_RELOC_SPARC_H34 652@deffnx {} BFD_RELOC_SPARC_SIZE32 653@deffnx {} BFD_RELOC_SPARC_SIZE64 654@deffnx {} BFD_RELOC_SPARC_WDISP10 655SPARC64 relocations 656@end deffn 657@deffn {} BFD_RELOC_SPARC_REV32 658SPARC little endian relocation 659@end deffn 660@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 661@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 662@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 663@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 664@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 665@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 666@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 667@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 668@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 669@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 670@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 671@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 672@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 673@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 674@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 675@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 676@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 677@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 678@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 679@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 680@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 681@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 682@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 683@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 684SPARC TLS relocations 685@end deffn 686@deffn {} BFD_RELOC_SPU_IMM7 687@deffnx {} BFD_RELOC_SPU_IMM8 688@deffnx {} BFD_RELOC_SPU_IMM10 689@deffnx {} BFD_RELOC_SPU_IMM10W 690@deffnx {} BFD_RELOC_SPU_IMM16 691@deffnx {} BFD_RELOC_SPU_IMM16W 692@deffnx {} BFD_RELOC_SPU_IMM18 693@deffnx {} BFD_RELOC_SPU_PCREL9a 694@deffnx {} BFD_RELOC_SPU_PCREL9b 695@deffnx {} BFD_RELOC_SPU_PCREL16 696@deffnx {} BFD_RELOC_SPU_LO16 697@deffnx {} BFD_RELOC_SPU_HI16 698@deffnx {} BFD_RELOC_SPU_PPU32 699@deffnx {} BFD_RELOC_SPU_PPU64 700@deffnx {} BFD_RELOC_SPU_ADD_PIC 701SPU Relocations. 702@end deffn 703@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 704Alpha ECOFF and ELF relocations. Some of these treat the symbol or 705"addend" in some special way. 706For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 707writing; when reading, it will be the absolute section symbol. The 708addend is the displacement in bytes of the "lda" instruction from 709the "ldah" instruction (which is at the address of this reloc). 710@end deffn 711@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 712For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 713with GPDISP_HI16 relocs. The addend is ignored when writing the 714relocations out, and is filled in with the file's GP value on 715reading, for convenience. 716@end deffn 717@deffn {} BFD_RELOC_ALPHA_GPDISP 718The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 719relocation except that there is no accompanying GPDISP_LO16 720relocation. 721@end deffn 722@deffn {} BFD_RELOC_ALPHA_LITERAL 723@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 724@deffnx {} BFD_RELOC_ALPHA_LITUSE 725The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 726the assembler turns it into a LDQ instruction to load the address of 727the symbol, and then fills in a register in the real instruction. 728 729The LITERAL reloc, at the LDQ instruction, refers to the .lita 730section symbol. The addend is ignored when writing, but is filled 731in with the file's GP value on reading, for convenience, as with the 732GPDISP_LO16 reloc. 733 734The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 735It should refer to the symbol to be referenced, as with 16_GOTOFF, 736but it generates output not based on the position within the .got 737section, but relative to the GP value chosen for the file during the 738final link stage. 739 740The LITUSE reloc, on the instruction using the loaded address, gives 741information to the linker that it might be able to use to optimize 742away some literal section references. The symbol is ignored (read 743as the absolute section symbol), and the "addend" indicates the type 744of instruction using the register: 7451 - "memory" fmt insn 7462 - byte-manipulation (byte offset reg) 7473 - jsr (target of branch) 748@end deffn 749@deffn {} BFD_RELOC_ALPHA_HINT 750The HINT relocation indicates a value that should be filled into the 751"hint" field of a jmp/jsr/ret instruction, for possible branch- 752prediction logic which may be provided on some processors. 753@end deffn 754@deffn {} BFD_RELOC_ALPHA_LINKAGE 755The LINKAGE relocation outputs a linkage pair in the object file, 756which is filled by the linker. 757@end deffn 758@deffn {} BFD_RELOC_ALPHA_CODEADDR 759The CODEADDR relocation outputs a STO_CA in the object file, 760which is filled by the linker. 761@end deffn 762@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 763@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 764The GPREL_HI/LO relocations together form a 32-bit offset from the 765GP register. 766@end deffn 767@deffn {} BFD_RELOC_ALPHA_BRSGP 768Like BFD_RELOC_23_PCREL_S2, except that the source and target must 769share a common GP, and the target address is adjusted for 770STO_ALPHA_STD_GPLOAD. 771@end deffn 772@deffn {} BFD_RELOC_ALPHA_NOP 773The NOP relocation outputs a NOP if the longword displacement 774between two procedure entry points is < 2^21. 775@end deffn 776@deffn {} BFD_RELOC_ALPHA_BSR 777The BSR relocation outputs a BSR if the longword displacement 778between two procedure entry points is < 2^21. 779@end deffn 780@deffn {} BFD_RELOC_ALPHA_LDA 781The LDA relocation outputs a LDA if the longword displacement 782between two procedure entry points is < 2^16. 783@end deffn 784@deffn {} BFD_RELOC_ALPHA_BOH 785The BOH relocation outputs a BSR if the longword displacement 786between two procedure entry points is < 2^21, or else a hint. 787@end deffn 788@deffn {} BFD_RELOC_ALPHA_TLSGD 789@deffnx {} BFD_RELOC_ALPHA_TLSLDM 790@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 791@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 792@deffnx {} BFD_RELOC_ALPHA_DTPREL64 793@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 794@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 795@deffnx {} BFD_RELOC_ALPHA_DTPREL16 796@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 797@deffnx {} BFD_RELOC_ALPHA_TPREL64 798@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 799@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 800@deffnx {} BFD_RELOC_ALPHA_TPREL16 801Alpha thread-local storage relocations. 802@end deffn 803@deffn {} BFD_RELOC_MIPS_JMP 804@deffnx {} BFD_RELOC_MICROMIPS_JMP 805The MIPS jump instruction. 806@end deffn 807@deffn {} BFD_RELOC_MIPS16_JMP 808The MIPS16 jump instruction. 809@end deffn 810@deffn {} BFD_RELOC_MIPS16_GPREL 811MIPS16 GP relative reloc. 812@end deffn 813@deffn {} BFD_RELOC_HI16 814High 16 bits of 32-bit value; simple reloc. 815@end deffn 816@deffn {} BFD_RELOC_HI16_S 817High 16 bits of 32-bit value but the low 16 bits will be sign 818extended and added to form the final result. If the low 16 819bits form a negative number, we need to add one to the high value 820to compensate for the borrow when the low bits are added. 821@end deffn 822@deffn {} BFD_RELOC_LO16 823Low 16 bits. 824@end deffn 825@deffn {} BFD_RELOC_HI16_PCREL 826High 16 bits of 32-bit pc-relative value 827@end deffn 828@deffn {} BFD_RELOC_HI16_S_PCREL 829High 16 bits of 32-bit pc-relative value, adjusted 830@end deffn 831@deffn {} BFD_RELOC_LO16_PCREL 832Low 16 bits of pc-relative value 833@end deffn 834@deffn {} BFD_RELOC_MIPS16_GOT16 835@deffnx {} BFD_RELOC_MIPS16_CALL16 836Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 83716-bit immediate fields 838@end deffn 839@deffn {} BFD_RELOC_MIPS16_HI16 840MIPS16 high 16 bits of 32-bit value. 841@end deffn 842@deffn {} BFD_RELOC_MIPS16_HI16_S 843MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 844extended and added to form the final result. If the low 16 845bits form a negative number, we need to add one to the high value 846to compensate for the borrow when the low bits are added. 847@end deffn 848@deffn {} BFD_RELOC_MIPS16_LO16 849MIPS16 low 16 bits. 850@end deffn 851@deffn {} BFD_RELOC_MIPS16_TLS_GD 852@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 853@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 854@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 855@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 856@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 857@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 858MIPS16 TLS relocations 859@end deffn 860@deffn {} BFD_RELOC_MIPS_LITERAL 861@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 862Relocation against a MIPS literal section. 863@end deffn 864@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 865@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 866@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 867microMIPS PC-relative relocations. 868@end deffn 869@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 870MIPS16 PC-relative relocation. 871@end deffn 872@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 873@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 874@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 875@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 876MIPS PC-relative relocations. 877@end deffn 878@deffn {} BFD_RELOC_MICROMIPS_GPREL16 879@deffnx {} BFD_RELOC_MICROMIPS_HI16 880@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 881@deffnx {} BFD_RELOC_MICROMIPS_LO16 882microMIPS versions of generic BFD relocs. 883@end deffn 884@deffn {} BFD_RELOC_MIPS_GOT16 885@deffnx {} BFD_RELOC_MICROMIPS_GOT16 886@deffnx {} BFD_RELOC_MIPS_CALL16 887@deffnx {} BFD_RELOC_MICROMIPS_CALL16 888@deffnx {} BFD_RELOC_MIPS_GOT_HI16 889@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 890@deffnx {} BFD_RELOC_MIPS_GOT_LO16 891@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 892@deffnx {} BFD_RELOC_MIPS_CALL_HI16 893@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 894@deffnx {} BFD_RELOC_MIPS_CALL_LO16 895@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 896@deffnx {} BFD_RELOC_MIPS_SUB 897@deffnx {} BFD_RELOC_MICROMIPS_SUB 898@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 899@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 900@deffnx {} BFD_RELOC_MIPS_GOT_OFST 901@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 902@deffnx {} BFD_RELOC_MIPS_GOT_DISP 903@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 904@deffnx {} BFD_RELOC_MIPS_SHIFT5 905@deffnx {} BFD_RELOC_MIPS_SHIFT6 906@deffnx {} BFD_RELOC_MIPS_INSERT_A 907@deffnx {} BFD_RELOC_MIPS_INSERT_B 908@deffnx {} BFD_RELOC_MIPS_DELETE 909@deffnx {} BFD_RELOC_MIPS_HIGHEST 910@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 911@deffnx {} BFD_RELOC_MIPS_HIGHER 912@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 913@deffnx {} BFD_RELOC_MIPS_SCN_DISP 914@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 915@deffnx {} BFD_RELOC_MIPS_16 916@deffnx {} BFD_RELOC_MIPS_RELGOT 917@deffnx {} BFD_RELOC_MIPS_JALR 918@deffnx {} BFD_RELOC_MICROMIPS_JALR 919@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 920@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 921@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 922@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 923@deffnx {} BFD_RELOC_MIPS_TLS_GD 924@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 925@deffnx {} BFD_RELOC_MIPS_TLS_LDM 926@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 927@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 928@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 929@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 930@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 931@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 932@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 933@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 934@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 935@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 936@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 937@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 938@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 939@deffnx {} BFD_RELOC_MIPS_EH 940MIPS ELF relocations. 941@end deffn 942@deffn {} BFD_RELOC_MIPS_COPY 943@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 944MIPS ELF relocations (VxWorks and PLT extensions). 945@end deffn 946@deffn {} BFD_RELOC_MOXIE_10_PCREL 947Moxie ELF relocations. 948@end deffn 949@deffn {} BFD_RELOC_FT32_10 950@deffnx {} BFD_RELOC_FT32_20 951@deffnx {} BFD_RELOC_FT32_17 952@deffnx {} BFD_RELOC_FT32_18 953@deffnx {} BFD_RELOC_FT32_RELAX 954@deffnx {} BFD_RELOC_FT32_SC0 955@deffnx {} BFD_RELOC_FT32_SC1 956@deffnx {} BFD_RELOC_FT32_15 957@deffnx {} BFD_RELOC_FT32_DIFF32 958FT32 ELF relocations. 959@end deffn 960@deffn {} BFD_RELOC_FRV_LABEL16 961@deffnx {} BFD_RELOC_FRV_LABEL24 962@deffnx {} BFD_RELOC_FRV_LO16 963@deffnx {} BFD_RELOC_FRV_HI16 964@deffnx {} BFD_RELOC_FRV_GPREL12 965@deffnx {} BFD_RELOC_FRV_GPRELU12 966@deffnx {} BFD_RELOC_FRV_GPREL32 967@deffnx {} BFD_RELOC_FRV_GPRELHI 968@deffnx {} BFD_RELOC_FRV_GPRELLO 969@deffnx {} BFD_RELOC_FRV_GOT12 970@deffnx {} BFD_RELOC_FRV_GOTHI 971@deffnx {} BFD_RELOC_FRV_GOTLO 972@deffnx {} BFD_RELOC_FRV_FUNCDESC 973@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 974@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 975@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 976@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 977@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 978@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 979@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 980@deffnx {} BFD_RELOC_FRV_GOTOFF12 981@deffnx {} BFD_RELOC_FRV_GOTOFFHI 982@deffnx {} BFD_RELOC_FRV_GOTOFFLO 983@deffnx {} BFD_RELOC_FRV_GETTLSOFF 984@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 985@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 986@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 987@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 988@deffnx {} BFD_RELOC_FRV_TLSMOFF12 989@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 990@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 991@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 992@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 993@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 994@deffnx {} BFD_RELOC_FRV_TLSOFF 995@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 996@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 997@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 998@deffnx {} BFD_RELOC_FRV_TLSMOFF 999Fujitsu Frv Relocations. 1000@end deffn 1001@deffn {} BFD_RELOC_MN10300_GOTOFF24 1002This is a 24bit GOT-relative reloc for the mn10300. 1003@end deffn 1004@deffn {} BFD_RELOC_MN10300_GOT32 1005This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1006in the instruction. 1007@end deffn 1008@deffn {} BFD_RELOC_MN10300_GOT24 1009This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1010in the instruction. 1011@end deffn 1012@deffn {} BFD_RELOC_MN10300_GOT16 1013This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1014in the instruction. 1015@end deffn 1016@deffn {} BFD_RELOC_MN10300_COPY 1017Copy symbol at runtime. 1018@end deffn 1019@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1020Create GOT entry. 1021@end deffn 1022@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1023Create PLT entry. 1024@end deffn 1025@deffn {} BFD_RELOC_MN10300_RELATIVE 1026Adjust by program base. 1027@end deffn 1028@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1029Together with another reloc targeted at the same location, 1030allows for a value that is the difference of two symbols 1031in the same section. 1032@end deffn 1033@deffn {} BFD_RELOC_MN10300_ALIGN 1034The addend of this reloc is an alignment power that must 1035be honoured at the offset's location, regardless of linker 1036relaxation. 1037@end deffn 1038@deffn {} BFD_RELOC_MN10300_TLS_GD 1039@deffnx {} BFD_RELOC_MN10300_TLS_LD 1040@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1041@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1042@deffnx {} BFD_RELOC_MN10300_TLS_IE 1043@deffnx {} BFD_RELOC_MN10300_TLS_LE 1044@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1045@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1046@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1047Various TLS-related relocations. 1048@end deffn 1049@deffn {} BFD_RELOC_MN10300_32_PCREL 1050This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1051instruction. 1052@end deffn 1053@deffn {} BFD_RELOC_MN10300_16_PCREL 1054This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1055instruction. 1056@end deffn 1057@deffn {} BFD_RELOC_386_GOT32 1058@deffnx {} BFD_RELOC_386_PLT32 1059@deffnx {} BFD_RELOC_386_COPY 1060@deffnx {} BFD_RELOC_386_GLOB_DAT 1061@deffnx {} BFD_RELOC_386_JUMP_SLOT 1062@deffnx {} BFD_RELOC_386_RELATIVE 1063@deffnx {} BFD_RELOC_386_GOTOFF 1064@deffnx {} BFD_RELOC_386_GOTPC 1065@deffnx {} BFD_RELOC_386_TLS_TPOFF 1066@deffnx {} BFD_RELOC_386_TLS_IE 1067@deffnx {} BFD_RELOC_386_TLS_GOTIE 1068@deffnx {} BFD_RELOC_386_TLS_LE 1069@deffnx {} BFD_RELOC_386_TLS_GD 1070@deffnx {} BFD_RELOC_386_TLS_LDM 1071@deffnx {} BFD_RELOC_386_TLS_LDO_32 1072@deffnx {} BFD_RELOC_386_TLS_IE_32 1073@deffnx {} BFD_RELOC_386_TLS_LE_32 1074@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1075@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1076@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1077@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1078@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1079@deffnx {} BFD_RELOC_386_TLS_DESC 1080@deffnx {} BFD_RELOC_386_IRELATIVE 1081@deffnx {} BFD_RELOC_386_GOT32X 1082i386/elf relocations 1083@end deffn 1084@deffn {} BFD_RELOC_X86_64_GOT32 1085@deffnx {} BFD_RELOC_X86_64_PLT32 1086@deffnx {} BFD_RELOC_X86_64_COPY 1087@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1088@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1089@deffnx {} BFD_RELOC_X86_64_RELATIVE 1090@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1091@deffnx {} BFD_RELOC_X86_64_32S 1092@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1093@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1094@deffnx {} BFD_RELOC_X86_64_TPOFF64 1095@deffnx {} BFD_RELOC_X86_64_TLSGD 1096@deffnx {} BFD_RELOC_X86_64_TLSLD 1097@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1098@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1099@deffnx {} BFD_RELOC_X86_64_TPOFF32 1100@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1101@deffnx {} BFD_RELOC_X86_64_GOTPC32 1102@deffnx {} BFD_RELOC_X86_64_GOT64 1103@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1104@deffnx {} BFD_RELOC_X86_64_GOTPC64 1105@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1106@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1107@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1108@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1109@deffnx {} BFD_RELOC_X86_64_TLSDESC 1110@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1111@deffnx {} BFD_RELOC_X86_64_PC32_BND 1112@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1113@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1114@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1115x86-64/elf relocations 1116@end deffn 1117@deffn {} BFD_RELOC_NS32K_IMM_8 1118@deffnx {} BFD_RELOC_NS32K_IMM_16 1119@deffnx {} BFD_RELOC_NS32K_IMM_32 1120@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1121@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1122@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1123@deffnx {} BFD_RELOC_NS32K_DISP_8 1124@deffnx {} BFD_RELOC_NS32K_DISP_16 1125@deffnx {} BFD_RELOC_NS32K_DISP_32 1126@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1127@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1128@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1129ns32k relocations 1130@end deffn 1131@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1132@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1133PDP11 relocations 1134@end deffn 1135@deffn {} BFD_RELOC_PJ_CODE_HI16 1136@deffnx {} BFD_RELOC_PJ_CODE_LO16 1137@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1138@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1139@deffnx {} BFD_RELOC_PJ_CODE_REL16 1140@deffnx {} BFD_RELOC_PJ_CODE_REL32 1141Picojava relocs. Not all of these appear in object files. 1142@end deffn 1143@deffn {} BFD_RELOC_PPC_B26 1144@deffnx {} BFD_RELOC_PPC_BA26 1145@deffnx {} BFD_RELOC_PPC_TOC16 1146@deffnx {} BFD_RELOC_PPC_TOC16_LO 1147@deffnx {} BFD_RELOC_PPC_TOC16_HI 1148@deffnx {} BFD_RELOC_PPC_B16 1149@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1150@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1151@deffnx {} BFD_RELOC_PPC_BA16 1152@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1153@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1154@deffnx {} BFD_RELOC_PPC_COPY 1155@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1156@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1157@deffnx {} BFD_RELOC_PPC_RELATIVE 1158@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1159@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1160@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1161@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1162@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1163@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1164@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1165@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1166@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1167@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1168@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1169@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1170@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1171@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1172@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1173@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1174@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1175@deffnx {} BFD_RELOC_PPC_VLE_REL8 1176@deffnx {} BFD_RELOC_PPC_VLE_REL15 1177@deffnx {} BFD_RELOC_PPC_VLE_REL24 1178@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1179@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1180@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1181@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1182@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1183@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1184@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1185@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1186@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1187@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1188@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1189@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1190@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1191@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1192@deffnx {} BFD_RELOC_PPC_16DX_HA 1193@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1194@deffnx {} BFD_RELOC_PPC_NEG 1195@deffnx {} BFD_RELOC_PPC64_HIGHER 1196@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1197@deffnx {} BFD_RELOC_PPC64_HIGHEST 1198@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1199@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1200@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1201@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1202@deffnx {} BFD_RELOC_PPC64_TOC 1203@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1204@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1205@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1206@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1207@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1208@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1209@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1210@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1211@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1212@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1213@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1214@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1215@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1216@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1217@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1218@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1219@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1220@deffnx {} BFD_RELOC_PPC64_REL16_HIGH 1221@deffnx {} BFD_RELOC_PPC64_REL16_HIGHA 1222@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER 1223@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA 1224@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST 1225@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA 1226@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1227@deffnx {} BFD_RELOC_PPC64_ENTRY 1228@deffnx {} BFD_RELOC_PPC64_REL24_NOTOC 1229@deffnx {} BFD_RELOC_PPC64_REL24_P9NOTOC 1230@deffnx {} BFD_RELOC_PPC64_D34 1231@deffnx {} BFD_RELOC_PPC64_D34_LO 1232@deffnx {} BFD_RELOC_PPC64_D34_HI30 1233@deffnx {} BFD_RELOC_PPC64_D34_HA30 1234@deffnx {} BFD_RELOC_PPC64_PCREL34 1235@deffnx {} BFD_RELOC_PPC64_GOT_PCREL34 1236@deffnx {} BFD_RELOC_PPC64_PLT_PCREL34 1237@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHER34 1238@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHERA34 1239@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHEST34 1240@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHESTA34 1241@deffnx {} BFD_RELOC_PPC64_REL16_HIGHER34 1242@deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA34 1243@deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST34 1244@deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA34 1245@deffnx {} BFD_RELOC_PPC64_D28 1246@deffnx {} BFD_RELOC_PPC64_PCREL28 1247Power(rs6000) and PowerPC relocations. 1248@end deffn 1249@deffn {} BFD_RELOC_PPC_TLS 1250@deffnx {} BFD_RELOC_PPC_TLSGD 1251@deffnx {} BFD_RELOC_PPC_TLSLD 1252@deffnx {} BFD_RELOC_PPC_TLSLE 1253@deffnx {} BFD_RELOC_PPC_TLSIE 1254@deffnx {} BFD_RELOC_PPC_TLSM 1255@deffnx {} BFD_RELOC_PPC_TLSML 1256@deffnx {} BFD_RELOC_PPC_DTPMOD 1257@deffnx {} BFD_RELOC_PPC_TPREL16 1258@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1259@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1260@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1261@deffnx {} BFD_RELOC_PPC_TPREL 1262@deffnx {} BFD_RELOC_PPC_DTPREL16 1263@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1264@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1265@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1266@deffnx {} BFD_RELOC_PPC_DTPREL 1267@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1268@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1269@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1270@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1271@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1272@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1273@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1274@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1275@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1276@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1277@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1278@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1279@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1280@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1281@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1282@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1283@deffnx {} BFD_RELOC_PPC64_TLSGD 1284@deffnx {} BFD_RELOC_PPC64_TLSLD 1285@deffnx {} BFD_RELOC_PPC64_TLSLE 1286@deffnx {} BFD_RELOC_PPC64_TLSIE 1287@deffnx {} BFD_RELOC_PPC64_TLSM 1288@deffnx {} BFD_RELOC_PPC64_TLSML 1289@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1290@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1291@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1292@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1293@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1294@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1295@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1296@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1297@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1298@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1299@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1300@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1301@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1302@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1303@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1304@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1305@deffnx {} BFD_RELOC_PPC64_TPREL34 1306@deffnx {} BFD_RELOC_PPC64_DTPREL34 1307@deffnx {} BFD_RELOC_PPC64_GOT_TLSGD_PCREL34 1308@deffnx {} BFD_RELOC_PPC64_GOT_TLSLD_PCREL34 1309@deffnx {} BFD_RELOC_PPC64_GOT_TPREL_PCREL34 1310@deffnx {} BFD_RELOC_PPC64_GOT_DTPREL_PCREL34 1311@deffnx {} BFD_RELOC_PPC64_TLS_PCREL 1312PowerPC and PowerPC64 thread-local storage relocations. 1313@end deffn 1314@deffn {} BFD_RELOC_I370_D12 1315IBM 370/390 relocations 1316@end deffn 1317@deffn {} BFD_RELOC_CTOR 1318The type of reloc used to build a constructor table - at the moment 1319probably a 32 bit wide absolute relocation, but the target can choose. 1320It generally does map to one of the other relocation types. 1321@end deffn 1322@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1323ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1324not stored in the instruction. 1325@end deffn 1326@deffn {} BFD_RELOC_ARM_PCREL_BLX 1327ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1328not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1329field in the instruction. 1330@end deffn 1331@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1332Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1333not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1334field in the instruction. 1335@end deffn 1336@deffn {} BFD_RELOC_ARM_PCREL_CALL 1337ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1338@end deffn 1339@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1340ARM 26-bit pc-relative branch for B or conditional BL instruction. 1341@end deffn 1342@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH5 1343ARM 5-bit pc-relative branch for Branch Future instructions. 1344@end deffn 1345@deffn {} BFD_RELOC_THUMB_PCREL_BFCSEL 1346ARM 6-bit pc-relative branch for BFCSEL instruction. 1347@end deffn 1348@deffn {} BFD_RELOC_ARM_THUMB_BF17 1349ARM 17-bit pc-relative branch for Branch Future instructions. 1350@end deffn 1351@deffn {} BFD_RELOC_ARM_THUMB_BF13 1352ARM 13-bit pc-relative branch for BFCSEL instruction. 1353@end deffn 1354@deffn {} BFD_RELOC_ARM_THUMB_BF19 1355ARM 19-bit pc-relative branch for Branch Future Link instruction. 1356@end deffn 1357@deffn {} BFD_RELOC_ARM_THUMB_LOOP12 1358ARM 12-bit pc-relative branch for Low Overhead Loop instructions. 1359@end deffn 1360@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1361@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1362@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1363@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1364@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1365@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1366Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1367The lowest bit must be zero and is not stored in the instruction. 1368Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1369"nn" one smaller in all cases. Note further that BRANCH23 1370corresponds to R_ARM_THM_CALL. 1371@end deffn 1372@deffn {} BFD_RELOC_ARM_OFFSET_IMM 137312-bit immediate offset, used in ARM-format ldr and str instructions. 1374@end deffn 1375@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13765-bit immediate offset, used in Thumb-format ldr and str instructions. 1377@end deffn 1378@deffn {} BFD_RELOC_ARM_TARGET1 1379Pc-relative or absolute relocation depending on target. Used for 1380entries in .init_array sections. 1381@end deffn 1382@deffn {} BFD_RELOC_ARM_ROSEGREL32 1383Read-only segment base relative address. 1384@end deffn 1385@deffn {} BFD_RELOC_ARM_SBREL32 1386Data segment base relative address. 1387@end deffn 1388@deffn {} BFD_RELOC_ARM_TARGET2 1389This reloc is used for references to RTTI data from exception handling 1390tables. The actual definition depends on the target. It may be a 1391pc-relative or some form of GOT-indirect relocation. 1392@end deffn 1393@deffn {} BFD_RELOC_ARM_PREL31 139431-bit PC relative address. 1395@end deffn 1396@deffn {} BFD_RELOC_ARM_MOVW 1397@deffnx {} BFD_RELOC_ARM_MOVT 1398@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1399@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1400@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1401@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1402@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1403@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1404Low and High halfword relocations for MOVW and MOVT instructions. 1405@end deffn 1406@deffn {} BFD_RELOC_ARM_GOTFUNCDESC 1407@deffnx {} BFD_RELOC_ARM_GOTOFFFUNCDESC 1408@deffnx {} BFD_RELOC_ARM_FUNCDESC 1409@deffnx {} BFD_RELOC_ARM_FUNCDESC_VALUE 1410@deffnx {} BFD_RELOC_ARM_TLS_GD32_FDPIC 1411@deffnx {} BFD_RELOC_ARM_TLS_LDM32_FDPIC 1412@deffnx {} BFD_RELOC_ARM_TLS_IE32_FDPIC 1413ARM FDPIC specific relocations. 1414@end deffn 1415@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1416@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1417@deffnx {} BFD_RELOC_ARM_GOT32 1418@deffnx {} BFD_RELOC_ARM_PLT32 1419@deffnx {} BFD_RELOC_ARM_RELATIVE 1420@deffnx {} BFD_RELOC_ARM_GOTOFF 1421@deffnx {} BFD_RELOC_ARM_GOTPC 1422@deffnx {} BFD_RELOC_ARM_GOT_PREL 1423Relocations for setting up GOTs and PLTs for shared libraries. 1424@end deffn 1425@deffn {} BFD_RELOC_ARM_TLS_GD32 1426@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1427@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1428@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1429@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1430@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1431@deffnx {} BFD_RELOC_ARM_TLS_IE32 1432@deffnx {} BFD_RELOC_ARM_TLS_LE32 1433@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1434@deffnx {} BFD_RELOC_ARM_TLS_CALL 1435@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1436@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1437@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1438@deffnx {} BFD_RELOC_ARM_TLS_DESC 1439ARM thread-local storage relocations. 1440@end deffn 1441@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1442@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1443@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1444@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1445@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1446@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1447@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1448@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1449@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1450@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1451@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1452@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1453@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1454@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1455@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1456@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1457@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1458@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1459@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1460@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1461@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1462@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1463@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1464@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1465@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1466@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1467@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1468@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1469ARM group relocations. 1470@end deffn 1471@deffn {} BFD_RELOC_ARM_V4BX 1472Annotation of BX instructions. 1473@end deffn 1474@deffn {} BFD_RELOC_ARM_IRELATIVE 1475ARM support for STT_GNU_IFUNC. 1476@end deffn 1477@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1478@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1479@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1480@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1481Thumb1 relocations to support execute-only code. 1482@end deffn 1483@deffn {} BFD_RELOC_ARM_IMMEDIATE 1484@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1485@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1486@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1487@deffnx {} BFD_RELOC_ARM_T32_IMM12 1488@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1489@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1490@deffnx {} BFD_RELOC_ARM_SMC 1491@deffnx {} BFD_RELOC_ARM_HVC 1492@deffnx {} BFD_RELOC_ARM_SWI 1493@deffnx {} BFD_RELOC_ARM_MULTI 1494@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1495@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1496@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1497@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1498@deffnx {} BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM 1499@deffnx {} BFD_RELOC_ARM_ADR_IMM 1500@deffnx {} BFD_RELOC_ARM_LDR_IMM 1501@deffnx {} BFD_RELOC_ARM_LITERAL 1502@deffnx {} BFD_RELOC_ARM_IN_POOL 1503@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1504@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1505@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1506@deffnx {} BFD_RELOC_ARM_HWLITERAL 1507@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1508@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1509@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1510These relocs are only used within the ARM assembler. They are not 1511(at present) written to any object files. 1512@end deffn 1513@deffn {} BFD_RELOC_SH_PCDISP8BY2 1514@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1515@deffnx {} BFD_RELOC_SH_IMM3 1516@deffnx {} BFD_RELOC_SH_IMM3U 1517@deffnx {} BFD_RELOC_SH_DISP12 1518@deffnx {} BFD_RELOC_SH_DISP12BY2 1519@deffnx {} BFD_RELOC_SH_DISP12BY4 1520@deffnx {} BFD_RELOC_SH_DISP12BY8 1521@deffnx {} BFD_RELOC_SH_DISP20 1522@deffnx {} BFD_RELOC_SH_DISP20BY8 1523@deffnx {} BFD_RELOC_SH_IMM4 1524@deffnx {} BFD_RELOC_SH_IMM4BY2 1525@deffnx {} BFD_RELOC_SH_IMM4BY4 1526@deffnx {} BFD_RELOC_SH_IMM8 1527@deffnx {} BFD_RELOC_SH_IMM8BY2 1528@deffnx {} BFD_RELOC_SH_IMM8BY4 1529@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1530@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1531@deffnx {} BFD_RELOC_SH_SWITCH16 1532@deffnx {} BFD_RELOC_SH_SWITCH32 1533@deffnx {} BFD_RELOC_SH_USES 1534@deffnx {} BFD_RELOC_SH_COUNT 1535@deffnx {} BFD_RELOC_SH_ALIGN 1536@deffnx {} BFD_RELOC_SH_CODE 1537@deffnx {} BFD_RELOC_SH_DATA 1538@deffnx {} BFD_RELOC_SH_LABEL 1539@deffnx {} BFD_RELOC_SH_LOOP_START 1540@deffnx {} BFD_RELOC_SH_LOOP_END 1541@deffnx {} BFD_RELOC_SH_COPY 1542@deffnx {} BFD_RELOC_SH_GLOB_DAT 1543@deffnx {} BFD_RELOC_SH_JMP_SLOT 1544@deffnx {} BFD_RELOC_SH_RELATIVE 1545@deffnx {} BFD_RELOC_SH_GOTPC 1546@deffnx {} BFD_RELOC_SH_GOT_LOW16 1547@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1548@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1549@deffnx {} BFD_RELOC_SH_GOT_HI16 1550@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1551@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1552@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1553@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1554@deffnx {} BFD_RELOC_SH_PLT_LOW16 1555@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1556@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1557@deffnx {} BFD_RELOC_SH_PLT_HI16 1558@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1559@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1560@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1561@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1562@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1563@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1564@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1565@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1566@deffnx {} BFD_RELOC_SH_COPY64 1567@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1568@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1569@deffnx {} BFD_RELOC_SH_RELATIVE64 1570@deffnx {} BFD_RELOC_SH_GOT10BY4 1571@deffnx {} BFD_RELOC_SH_GOT10BY8 1572@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1573@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1574@deffnx {} BFD_RELOC_SH_GOTPLT32 1575@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1576@deffnx {} BFD_RELOC_SH_IMMU5 1577@deffnx {} BFD_RELOC_SH_IMMS6 1578@deffnx {} BFD_RELOC_SH_IMMS6BY32 1579@deffnx {} BFD_RELOC_SH_IMMU6 1580@deffnx {} BFD_RELOC_SH_IMMS10 1581@deffnx {} BFD_RELOC_SH_IMMS10BY2 1582@deffnx {} BFD_RELOC_SH_IMMS10BY4 1583@deffnx {} BFD_RELOC_SH_IMMS10BY8 1584@deffnx {} BFD_RELOC_SH_IMMS16 1585@deffnx {} BFD_RELOC_SH_IMMU16 1586@deffnx {} BFD_RELOC_SH_IMM_LOW16 1587@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1588@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1589@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1590@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1591@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1592@deffnx {} BFD_RELOC_SH_IMM_HI16 1593@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1594@deffnx {} BFD_RELOC_SH_PT_16 1595@deffnx {} BFD_RELOC_SH_TLS_GD_32 1596@deffnx {} BFD_RELOC_SH_TLS_LD_32 1597@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1598@deffnx {} BFD_RELOC_SH_TLS_IE_32 1599@deffnx {} BFD_RELOC_SH_TLS_LE_32 1600@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1601@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1602@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1603@deffnx {} BFD_RELOC_SH_GOT20 1604@deffnx {} BFD_RELOC_SH_GOTOFF20 1605@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1606@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1607@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1608@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1609@deffnx {} BFD_RELOC_SH_FUNCDESC 1610Renesas / SuperH SH relocs. Not all of these appear in object files. 1611@end deffn 1612@deffn {} BFD_RELOC_ARC_NONE 1613@deffnx {} BFD_RELOC_ARC_8 1614@deffnx {} BFD_RELOC_ARC_16 1615@deffnx {} BFD_RELOC_ARC_24 1616@deffnx {} BFD_RELOC_ARC_32 1617@deffnx {} BFD_RELOC_ARC_N8 1618@deffnx {} BFD_RELOC_ARC_N16 1619@deffnx {} BFD_RELOC_ARC_N24 1620@deffnx {} BFD_RELOC_ARC_N32 1621@deffnx {} BFD_RELOC_ARC_SDA 1622@deffnx {} BFD_RELOC_ARC_SECTOFF 1623@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1624@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1625@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1626@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1627@deffnx {} BFD_RELOC_ARC_SDA32 1628@deffnx {} BFD_RELOC_ARC_SDA_LDST 1629@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1630@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1631@deffnx {} BFD_RELOC_ARC_SDA16_LD 1632@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1633@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1634@deffnx {} BFD_RELOC_ARC_S13_PCREL 1635@deffnx {} BFD_RELOC_ARC_W 1636@deffnx {} BFD_RELOC_ARC_32_ME 1637@deffnx {} BFD_RELOC_ARC_32_ME_S 1638@deffnx {} BFD_RELOC_ARC_N32_ME 1639@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1640@deffnx {} BFD_RELOC_ARC_SDA32_ME 1641@deffnx {} BFD_RELOC_ARC_W_ME 1642@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1643@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1644@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1645@deffnx {} BFD_RELOC_AC_SECTOFF_S9 1646@deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1647@deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1648@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1649@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1650@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1651@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1652@deffnx {} BFD_RELOC_ARC_SDA_12 1653@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1654@deffnx {} BFD_RELOC_ARC_32_PCREL 1655@deffnx {} BFD_RELOC_ARC_PC32 1656@deffnx {} BFD_RELOC_ARC_GOT32 1657@deffnx {} BFD_RELOC_ARC_GOTPC32 1658@deffnx {} BFD_RELOC_ARC_PLT32 1659@deffnx {} BFD_RELOC_ARC_COPY 1660@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1661@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1662@deffnx {} BFD_RELOC_ARC_RELATIVE 1663@deffnx {} BFD_RELOC_ARC_GOTOFF 1664@deffnx {} BFD_RELOC_ARC_GOTPC 1665@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1666@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1667@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1668@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1669@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1670@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1671@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1672@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1673@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1674@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1675@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1676@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1677@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1678@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1679@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1680@deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1681ARC relocs. 1682@end deffn 1683@deffn {} BFD_RELOC_BFIN_16_IMM 1684ADI Blackfin 16 bit immediate absolute reloc. 1685@end deffn 1686@deffn {} BFD_RELOC_BFIN_16_HIGH 1687ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1688@end deffn 1689@deffn {} BFD_RELOC_BFIN_4_PCREL 1690ADI Blackfin 'a' part of LSETUP. 1691@end deffn 1692@deffn {} BFD_RELOC_BFIN_5_PCREL 1693ADI Blackfin. 1694@end deffn 1695@deffn {} BFD_RELOC_BFIN_16_LOW 1696ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1697@end deffn 1698@deffn {} BFD_RELOC_BFIN_10_PCREL 1699ADI Blackfin. 1700@end deffn 1701@deffn {} BFD_RELOC_BFIN_11_PCREL 1702ADI Blackfin 'b' part of LSETUP. 1703@end deffn 1704@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1705ADI Blackfin. 1706@end deffn 1707@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1708ADI Blackfin Short jump, pcrel. 1709@end deffn 1710@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1711ADI Blackfin Call.x not implemented. 1712@end deffn 1713@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1714ADI Blackfin Long Jump pcrel. 1715@end deffn 1716@deffn {} BFD_RELOC_BFIN_GOT17M4 1717@deffnx {} BFD_RELOC_BFIN_GOTHI 1718@deffnx {} BFD_RELOC_BFIN_GOTLO 1719@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1720@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1721@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1722@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1723@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1724@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1725@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1726@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1727@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1728@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1729@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1730ADI Blackfin FD-PIC relocations. 1731@end deffn 1732@deffn {} BFD_RELOC_BFIN_GOT 1733ADI Blackfin GOT relocation. 1734@end deffn 1735@deffn {} BFD_RELOC_BFIN_PLTPC 1736ADI Blackfin PLTPC relocation. 1737@end deffn 1738@deffn {} BFD_ARELOC_BFIN_PUSH 1739ADI Blackfin arithmetic relocation. 1740@end deffn 1741@deffn {} BFD_ARELOC_BFIN_CONST 1742ADI Blackfin arithmetic relocation. 1743@end deffn 1744@deffn {} BFD_ARELOC_BFIN_ADD 1745ADI Blackfin arithmetic relocation. 1746@end deffn 1747@deffn {} BFD_ARELOC_BFIN_SUB 1748ADI Blackfin arithmetic relocation. 1749@end deffn 1750@deffn {} BFD_ARELOC_BFIN_MULT 1751ADI Blackfin arithmetic relocation. 1752@end deffn 1753@deffn {} BFD_ARELOC_BFIN_DIV 1754ADI Blackfin arithmetic relocation. 1755@end deffn 1756@deffn {} BFD_ARELOC_BFIN_MOD 1757ADI Blackfin arithmetic relocation. 1758@end deffn 1759@deffn {} BFD_ARELOC_BFIN_LSHIFT 1760ADI Blackfin arithmetic relocation. 1761@end deffn 1762@deffn {} BFD_ARELOC_BFIN_RSHIFT 1763ADI Blackfin arithmetic relocation. 1764@end deffn 1765@deffn {} BFD_ARELOC_BFIN_AND 1766ADI Blackfin arithmetic relocation. 1767@end deffn 1768@deffn {} BFD_ARELOC_BFIN_OR 1769ADI Blackfin arithmetic relocation. 1770@end deffn 1771@deffn {} BFD_ARELOC_BFIN_XOR 1772ADI Blackfin arithmetic relocation. 1773@end deffn 1774@deffn {} BFD_ARELOC_BFIN_LAND 1775ADI Blackfin arithmetic relocation. 1776@end deffn 1777@deffn {} BFD_ARELOC_BFIN_LOR 1778ADI Blackfin arithmetic relocation. 1779@end deffn 1780@deffn {} BFD_ARELOC_BFIN_LEN 1781ADI Blackfin arithmetic relocation. 1782@end deffn 1783@deffn {} BFD_ARELOC_BFIN_NEG 1784ADI Blackfin arithmetic relocation. 1785@end deffn 1786@deffn {} BFD_ARELOC_BFIN_COMP 1787ADI Blackfin arithmetic relocation. 1788@end deffn 1789@deffn {} BFD_ARELOC_BFIN_PAGE 1790ADI Blackfin arithmetic relocation. 1791@end deffn 1792@deffn {} BFD_ARELOC_BFIN_HWPAGE 1793ADI Blackfin arithmetic relocation. 1794@end deffn 1795@deffn {} BFD_ARELOC_BFIN_ADDR 1796ADI Blackfin arithmetic relocation. 1797@end deffn 1798@deffn {} BFD_RELOC_D10V_10_PCREL_R 1799Mitsubishi D10V relocs. 1800This is a 10-bit reloc with the right 2 bits 1801assumed to be 0. 1802@end deffn 1803@deffn {} BFD_RELOC_D10V_10_PCREL_L 1804Mitsubishi D10V relocs. 1805This is a 10-bit reloc with the right 2 bits 1806assumed to be 0. This is the same as the previous reloc 1807except it is in the left container, i.e., 1808shifted left 15 bits. 1809@end deffn 1810@deffn {} BFD_RELOC_D10V_18 1811This is an 18-bit reloc with the right 2 bits 1812assumed to be 0. 1813@end deffn 1814@deffn {} BFD_RELOC_D10V_18_PCREL 1815This is an 18-bit reloc with the right 2 bits 1816assumed to be 0. 1817@end deffn 1818@deffn {} BFD_RELOC_D30V_6 1819Mitsubishi D30V relocs. 1820This is a 6-bit absolute reloc. 1821@end deffn 1822@deffn {} BFD_RELOC_D30V_9_PCREL 1823This is a 6-bit pc-relative reloc with 1824the right 3 bits assumed to be 0. 1825@end deffn 1826@deffn {} BFD_RELOC_D30V_9_PCREL_R 1827This is a 6-bit pc-relative reloc with 1828the right 3 bits assumed to be 0. Same 1829as the previous reloc but on the right side 1830of the container. 1831@end deffn 1832@deffn {} BFD_RELOC_D30V_15 1833This is a 12-bit absolute reloc with the 1834right 3 bitsassumed to be 0. 1835@end deffn 1836@deffn {} BFD_RELOC_D30V_15_PCREL 1837This is a 12-bit pc-relative reloc with 1838the right 3 bits assumed to be 0. 1839@end deffn 1840@deffn {} BFD_RELOC_D30V_15_PCREL_R 1841This is a 12-bit pc-relative reloc with 1842the right 3 bits assumed to be 0. Same 1843as the previous reloc but on the right side 1844of the container. 1845@end deffn 1846@deffn {} BFD_RELOC_D30V_21 1847This is an 18-bit absolute reloc with 1848the right 3 bits assumed to be 0. 1849@end deffn 1850@deffn {} BFD_RELOC_D30V_21_PCREL 1851This is an 18-bit pc-relative reloc with 1852the right 3 bits assumed to be 0. 1853@end deffn 1854@deffn {} BFD_RELOC_D30V_21_PCREL_R 1855This is an 18-bit pc-relative reloc with 1856the right 3 bits assumed to be 0. Same 1857as the previous reloc but on the right side 1858of the container. 1859@end deffn 1860@deffn {} BFD_RELOC_D30V_32 1861This is a 32-bit absolute reloc. 1862@end deffn 1863@deffn {} BFD_RELOC_D30V_32_PCREL 1864This is a 32-bit pc-relative reloc. 1865@end deffn 1866@deffn {} BFD_RELOC_DLX_HI16_S 1867DLX relocs 1868@end deffn 1869@deffn {} BFD_RELOC_DLX_LO16 1870DLX relocs 1871@end deffn 1872@deffn {} BFD_RELOC_DLX_JMP26 1873DLX relocs 1874@end deffn 1875@deffn {} BFD_RELOC_M32C_HI8 1876@deffnx {} BFD_RELOC_M32C_RL_JUMP 1877@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1878@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1879Renesas M16C/M32C Relocations. 1880@end deffn 1881@deffn {} BFD_RELOC_M32R_24 1882Renesas M32R (formerly Mitsubishi M32R) relocs. 1883This is a 24 bit absolute address. 1884@end deffn 1885@deffn {} BFD_RELOC_M32R_10_PCREL 1886This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1887@end deffn 1888@deffn {} BFD_RELOC_M32R_18_PCREL 1889This is an 18-bit reloc with the right 2 bits assumed to be 0. 1890@end deffn 1891@deffn {} BFD_RELOC_M32R_26_PCREL 1892This is a 26-bit reloc with the right 2 bits assumed to be 0. 1893@end deffn 1894@deffn {} BFD_RELOC_M32R_HI16_ULO 1895This is a 16-bit reloc containing the high 16 bits of an address 1896used when the lower 16 bits are treated as unsigned. 1897@end deffn 1898@deffn {} BFD_RELOC_M32R_HI16_SLO 1899This is a 16-bit reloc containing the high 16 bits of an address 1900used when the lower 16 bits are treated as signed. 1901@end deffn 1902@deffn {} BFD_RELOC_M32R_LO16 1903This is a 16-bit reloc containing the lower 16 bits of an address. 1904@end deffn 1905@deffn {} BFD_RELOC_M32R_SDA16 1906This is a 16-bit reloc containing the small data area offset for use in 1907add3, load, and store instructions. 1908@end deffn 1909@deffn {} BFD_RELOC_M32R_GOT24 1910@deffnx {} BFD_RELOC_M32R_26_PLTREL 1911@deffnx {} BFD_RELOC_M32R_COPY 1912@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1913@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1914@deffnx {} BFD_RELOC_M32R_RELATIVE 1915@deffnx {} BFD_RELOC_M32R_GOTOFF 1916@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1917@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1918@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1919@deffnx {} BFD_RELOC_M32R_GOTPC24 1920@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1921@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1922@deffnx {} BFD_RELOC_M32R_GOT16_LO 1923@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1924@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1925@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1926For PIC. 1927@end deffn 1928@deffn {} BFD_RELOC_NDS32_20 1929NDS32 relocs. 1930This is a 20 bit absolute address. 1931@end deffn 1932@deffn {} BFD_RELOC_NDS32_9_PCREL 1933This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1934@end deffn 1935@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1936This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1937@end deffn 1938@deffn {} BFD_RELOC_NDS32_15_PCREL 1939This is an 15-bit reloc with the right 1 bit assumed to be 0. 1940@end deffn 1941@deffn {} BFD_RELOC_NDS32_17_PCREL 1942This is an 17-bit reloc with the right 1 bit assumed to be 0. 1943@end deffn 1944@deffn {} BFD_RELOC_NDS32_25_PCREL 1945This is a 25-bit reloc with the right 1 bit assumed to be 0. 1946@end deffn 1947@deffn {} BFD_RELOC_NDS32_HI20 1948This is a 20-bit reloc containing the high 20 bits of an address 1949used with the lower 12 bits 1950@end deffn 1951@deffn {} BFD_RELOC_NDS32_LO12S3 1952This is a 12-bit reloc containing the lower 12 bits of an address 1953then shift right by 3. This is used with ldi,sdi... 1954@end deffn 1955@deffn {} BFD_RELOC_NDS32_LO12S2 1956This is a 12-bit reloc containing the lower 12 bits of an address 1957then shift left by 2. This is used with lwi,swi... 1958@end deffn 1959@deffn {} BFD_RELOC_NDS32_LO12S1 1960This is a 12-bit reloc containing the lower 12 bits of an address 1961then shift left by 1. This is used with lhi,shi... 1962@end deffn 1963@deffn {} BFD_RELOC_NDS32_LO12S0 1964This is a 12-bit reloc containing the lower 12 bits of an address 1965then shift left by 0. This is used with lbisbi... 1966@end deffn 1967@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1968This is a 12-bit reloc containing the lower 12 bits of an address 1969then shift left by 0. This is only used with branch relaxations 1970@end deffn 1971@deffn {} BFD_RELOC_NDS32_SDA15S3 1972This is a 15-bit reloc containing the small data area 18-bit signed offset 1973and shift left by 3 for use in ldi, sdi... 1974@end deffn 1975@deffn {} BFD_RELOC_NDS32_SDA15S2 1976This is a 15-bit reloc containing the small data area 17-bit signed offset 1977and shift left by 2 for use in lwi, swi... 1978@end deffn 1979@deffn {} BFD_RELOC_NDS32_SDA15S1 1980This is a 15-bit reloc containing the small data area 16-bit signed offset 1981and shift left by 1 for use in lhi, shi... 1982@end deffn 1983@deffn {} BFD_RELOC_NDS32_SDA15S0 1984This is a 15-bit reloc containing the small data area 15-bit signed offset 1985and shift left by 0 for use in lbi, sbi... 1986@end deffn 1987@deffn {} BFD_RELOC_NDS32_SDA16S3 1988This is a 16-bit reloc containing the small data area 16-bit signed offset 1989and shift left by 3 1990@end deffn 1991@deffn {} BFD_RELOC_NDS32_SDA17S2 1992This is a 17-bit reloc containing the small data area 17-bit signed offset 1993and shift left by 2 for use in lwi.gp, swi.gp... 1994@end deffn 1995@deffn {} BFD_RELOC_NDS32_SDA18S1 1996This is a 18-bit reloc containing the small data area 18-bit signed offset 1997and shift left by 1 for use in lhi.gp, shi.gp... 1998@end deffn 1999@deffn {} BFD_RELOC_NDS32_SDA19S0 2000This is a 19-bit reloc containing the small data area 19-bit signed offset 2001and shift left by 0 for use in lbi.gp, sbi.gp... 2002@end deffn 2003@deffn {} BFD_RELOC_NDS32_GOT20 2004@deffnx {} BFD_RELOC_NDS32_9_PLTREL 2005@deffnx {} BFD_RELOC_NDS32_25_PLTREL 2006@deffnx {} BFD_RELOC_NDS32_COPY 2007@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 2008@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 2009@deffnx {} BFD_RELOC_NDS32_RELATIVE 2010@deffnx {} BFD_RELOC_NDS32_GOTOFF 2011@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 2012@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 2013@deffnx {} BFD_RELOC_NDS32_GOTPC20 2014@deffnx {} BFD_RELOC_NDS32_GOT_HI20 2015@deffnx {} BFD_RELOC_NDS32_GOT_LO12 2016@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 2017@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 2018for PIC 2019@end deffn 2020@deffn {} BFD_RELOC_NDS32_INSN16 2021@deffnx {} BFD_RELOC_NDS32_LABEL 2022@deffnx {} BFD_RELOC_NDS32_LONGCALL1 2023@deffnx {} BFD_RELOC_NDS32_LONGCALL2 2024@deffnx {} BFD_RELOC_NDS32_LONGCALL3 2025@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 2026@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 2027@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 2028@deffnx {} BFD_RELOC_NDS32_LOADSTORE 2029@deffnx {} BFD_RELOC_NDS32_9_FIXED 2030@deffnx {} BFD_RELOC_NDS32_15_FIXED 2031@deffnx {} BFD_RELOC_NDS32_17_FIXED 2032@deffnx {} BFD_RELOC_NDS32_25_FIXED 2033@deffnx {} BFD_RELOC_NDS32_LONGCALL4 2034@deffnx {} BFD_RELOC_NDS32_LONGCALL5 2035@deffnx {} BFD_RELOC_NDS32_LONGCALL6 2036@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 2037@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 2038@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 2039@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 2040for relax 2041@end deffn 2042@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 2043@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 2044@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 2045@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 2046for PIC 2047@end deffn 2048@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 2049@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 2050@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 2051@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 2052for floating point 2053@end deffn 2054@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 2055@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 2056@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 2057for dwarf2 debug_line. 2058@end deffn 2059@deffn {} BFD_RELOC_NDS32_UPDATE_TA 2060for eliminate 16-bit instructions 2061@end deffn 2062@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2063@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2064@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2065@deffnx {} BFD_RELOC_NDS32_GOT_LO15 2066@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2067@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2068@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2069@deffnx {} BFD_RELOC_NDS32_GOT15S2 2070@deffnx {} BFD_RELOC_NDS32_GOT17S2 2071for PIC object relaxation 2072@end deffn 2073@deffn {} BFD_RELOC_NDS32_5 2074NDS32 relocs. 2075This is a 5 bit absolute address. 2076@end deffn 2077@deffn {} BFD_RELOC_NDS32_10_UPCREL 2078This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2079@end deffn 2080@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2081If fp were omitted, fp can used as another gp. 2082@end deffn 2083@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2084@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2085@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2086@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2087@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2088@deffnx {} BFD_RELOC_NDS32_PTR 2089@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2090@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2091@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2092@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2093@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2094@deffnx {} BFD_RELOC_NDS32_MINUEND 2095@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2096@deffnx {} BFD_RELOC_NDS32_DIFF8 2097@deffnx {} BFD_RELOC_NDS32_DIFF16 2098@deffnx {} BFD_RELOC_NDS32_DIFF32 2099@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2100@deffnx {} BFD_RELOC_NDS32_EMPTY 2101relaxation relative relocation types 2102@end deffn 2103@deffn {} BFD_RELOC_NDS32_25_ABS 2104This is a 25 bit absolute address. 2105@end deffn 2106@deffn {} BFD_RELOC_NDS32_DATA 2107@deffnx {} BFD_RELOC_NDS32_TRAN 2108@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2109@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2110For ex9 and ifc using. 2111@end deffn 2112@deffn {} BFD_RELOC_NDS32_TPOFF 2113@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2114@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2115@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2116@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2117@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2118@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2119@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2120@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2121@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2122@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2123@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12 2124@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2125@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_HI20 2126@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12 2127@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12S2 2128@deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LW 2129@deffnx {} BFD_RELOC_NDS32_TLS_DESC 2130@deffnx {} BFD_RELOC_NDS32_TLS_DESC_HI20 2131@deffnx {} BFD_RELOC_NDS32_TLS_DESC_LO12 2132@deffnx {} BFD_RELOC_NDS32_TLS_DESC_20 2133@deffnx {} BFD_RELOC_NDS32_TLS_DESC_SDA17S2 2134@deffnx {} BFD_RELOC_NDS32_TLS_DESC_ADD 2135@deffnx {} BFD_RELOC_NDS32_TLS_DESC_FUNC 2136@deffnx {} BFD_RELOC_NDS32_TLS_DESC_CALL 2137@deffnx {} BFD_RELOC_NDS32_TLS_DESC_MEM 2138@deffnx {} BFD_RELOC_NDS32_REMOVE 2139@deffnx {} BFD_RELOC_NDS32_GROUP 2140For TLS. 2141@end deffn 2142@deffn {} BFD_RELOC_NDS32_LSI 2143For floating load store relaxation. 2144@end deffn 2145@deffn {} BFD_RELOC_V850_9_PCREL 2146This is a 9-bit reloc 2147@end deffn 2148@deffn {} BFD_RELOC_V850_22_PCREL 2149This is a 22-bit reloc 2150@end deffn 2151@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2152This is a 16 bit offset from the short data area pointer. 2153@end deffn 2154@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2155This is a 16 bit offset (of which only 15 bits are used) from the 2156short data area pointer. 2157@end deffn 2158@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2159This is a 16 bit offset from the zero data area pointer. 2160@end deffn 2161@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2162This is a 16 bit offset (of which only 15 bits are used) from the 2163zero data area pointer. 2164@end deffn 2165@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2166This is an 8 bit offset (of which only 6 bits are used) from the 2167tiny data area pointer. 2168@end deffn 2169@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2170This is an 8bit offset (of which only 7 bits are used) from the tiny 2171data area pointer. 2172@end deffn 2173@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2174This is a 7 bit offset from the tiny data area pointer. 2175@end deffn 2176@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2177This is a 16 bit offset from the tiny data area pointer. 2178@end deffn 2179@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2180This is a 5 bit offset (of which only 4 bits are used) from the tiny 2181data area pointer. 2182@end deffn 2183@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2184This is a 4 bit offset from the tiny data area pointer. 2185@end deffn 2186@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2187This is a 16 bit offset from the short data area pointer, with the 2188bits placed non-contiguously in the instruction. 2189@end deffn 2190@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2191This is a 16 bit offset from the zero data area pointer, with the 2192bits placed non-contiguously in the instruction. 2193@end deffn 2194@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2195This is a 6 bit offset from the call table base pointer. 2196@end deffn 2197@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2198This is a 16 bit offset from the call table base pointer. 2199@end deffn 2200@deffn {} BFD_RELOC_V850_LONGCALL 2201Used for relaxing indirect function calls. 2202@end deffn 2203@deffn {} BFD_RELOC_V850_LONGJUMP 2204Used for relaxing indirect jumps. 2205@end deffn 2206@deffn {} BFD_RELOC_V850_ALIGN 2207Used to maintain alignment whilst relaxing. 2208@end deffn 2209@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2210This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2211instructions. 2212@end deffn 2213@deffn {} BFD_RELOC_V850_16_PCREL 2214This is a 16-bit reloc. 2215@end deffn 2216@deffn {} BFD_RELOC_V850_17_PCREL 2217This is a 17-bit reloc. 2218@end deffn 2219@deffn {} BFD_RELOC_V850_23 2220This is a 23-bit reloc. 2221@end deffn 2222@deffn {} BFD_RELOC_V850_32_PCREL 2223This is a 32-bit reloc. 2224@end deffn 2225@deffn {} BFD_RELOC_V850_32_ABS 2226This is a 32-bit reloc. 2227@end deffn 2228@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2229This is a 16-bit reloc. 2230@end deffn 2231@deffn {} BFD_RELOC_V850_16_S1 2232This is a 16-bit reloc. 2233@end deffn 2234@deffn {} BFD_RELOC_V850_LO16_S1 2235Low 16 bits. 16 bit shifted by 1. 2236@end deffn 2237@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2238This is a 16 bit offset from the call table base pointer. 2239@end deffn 2240@deffn {} BFD_RELOC_V850_32_GOTPCREL 2241DSO relocations. 2242@end deffn 2243@deffn {} BFD_RELOC_V850_16_GOT 2244DSO relocations. 2245@end deffn 2246@deffn {} BFD_RELOC_V850_32_GOT 2247DSO relocations. 2248@end deffn 2249@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2250DSO relocations. 2251@end deffn 2252@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2253DSO relocations. 2254@end deffn 2255@deffn {} BFD_RELOC_V850_COPY 2256DSO relocations. 2257@end deffn 2258@deffn {} BFD_RELOC_V850_GLOB_DAT 2259DSO relocations. 2260@end deffn 2261@deffn {} BFD_RELOC_V850_JMP_SLOT 2262DSO relocations. 2263@end deffn 2264@deffn {} BFD_RELOC_V850_RELATIVE 2265DSO relocations. 2266@end deffn 2267@deffn {} BFD_RELOC_V850_16_GOTOFF 2268DSO relocations. 2269@end deffn 2270@deffn {} BFD_RELOC_V850_32_GOTOFF 2271DSO relocations. 2272@end deffn 2273@deffn {} BFD_RELOC_V850_CODE 2274start code. 2275@end deffn 2276@deffn {} BFD_RELOC_V850_DATA 2277start data in text. 2278@end deffn 2279@deffn {} BFD_RELOC_TIC30_LDP 2280This is a 8bit DP reloc for the tms320c30, where the most 2281significant 8 bits of a 24 bit word are placed into the least 2282significant 8 bits of the opcode. 2283@end deffn 2284@deffn {} BFD_RELOC_TIC54X_PARTLS7 2285This is a 7bit reloc for the tms320c54x, where the least 2286significant 7 bits of a 16 bit word are placed into the least 2287significant 7 bits of the opcode. 2288@end deffn 2289@deffn {} BFD_RELOC_TIC54X_PARTMS9 2290This is a 9bit DP reloc for the tms320c54x, where the most 2291significant 9 bits of a 16 bit word are placed into the least 2292significant 9 bits of the opcode. 2293@end deffn 2294@deffn {} BFD_RELOC_TIC54X_23 2295This is an extended address 23-bit reloc for the tms320c54x. 2296@end deffn 2297@deffn {} BFD_RELOC_TIC54X_16_OF_23 2298This is a 16-bit reloc for the tms320c54x, where the least 2299significant 16 bits of a 23-bit extended address are placed into 2300the opcode. 2301@end deffn 2302@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2303This is a reloc for the tms320c54x, where the most 2304significant 7 bits of a 23-bit extended address are placed into 2305the opcode. 2306@end deffn 2307@deffn {} BFD_RELOC_C6000_PCR_S21 2308@deffnx {} BFD_RELOC_C6000_PCR_S12 2309@deffnx {} BFD_RELOC_C6000_PCR_S10 2310@deffnx {} BFD_RELOC_C6000_PCR_S7 2311@deffnx {} BFD_RELOC_C6000_ABS_S16 2312@deffnx {} BFD_RELOC_C6000_ABS_L16 2313@deffnx {} BFD_RELOC_C6000_ABS_H16 2314@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2315@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2316@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2317@deffnx {} BFD_RELOC_C6000_SBR_S16 2318@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2319@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2320@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2321@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2322@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2323@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2324@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2325@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2326@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2327@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2328@deffnx {} BFD_RELOC_C6000_PREL31 2329@deffnx {} BFD_RELOC_C6000_COPY 2330@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2331@deffnx {} BFD_RELOC_C6000_EHTYPE 2332@deffnx {} BFD_RELOC_C6000_PCR_H16 2333@deffnx {} BFD_RELOC_C6000_PCR_L16 2334@deffnx {} BFD_RELOC_C6000_ALIGN 2335@deffnx {} BFD_RELOC_C6000_FPHEAD 2336@deffnx {} BFD_RELOC_C6000_NOCMP 2337TMS320C6000 relocations. 2338@end deffn 2339@deffn {} BFD_RELOC_FR30_48 2340This is a 48 bit reloc for the FR30 that stores 32 bits. 2341@end deffn 2342@deffn {} BFD_RELOC_FR30_20 2343This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2344two sections. 2345@end deffn 2346@deffn {} BFD_RELOC_FR30_6_IN_4 2347This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 23484 bits. 2349@end deffn 2350@deffn {} BFD_RELOC_FR30_8_IN_8 2351This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2352into 8 bits. 2353@end deffn 2354@deffn {} BFD_RELOC_FR30_9_IN_8 2355This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2356into 8 bits. 2357@end deffn 2358@deffn {} BFD_RELOC_FR30_10_IN_8 2359This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2360into 8 bits. 2361@end deffn 2362@deffn {} BFD_RELOC_FR30_9_PCREL 2363This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2364short offset into 8 bits. 2365@end deffn 2366@deffn {} BFD_RELOC_FR30_12_PCREL 2367This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2368short offset into 11 bits. 2369@end deffn 2370@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2371@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2372@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2373@deffnx {} BFD_RELOC_MCORE_PCREL_32 2374@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2375@deffnx {} BFD_RELOC_MCORE_RVA 2376Motorola Mcore relocations. 2377@end deffn 2378@deffn {} BFD_RELOC_MEP_8 2379@deffnx {} BFD_RELOC_MEP_16 2380@deffnx {} BFD_RELOC_MEP_32 2381@deffnx {} BFD_RELOC_MEP_PCREL8A2 2382@deffnx {} BFD_RELOC_MEP_PCREL12A2 2383@deffnx {} BFD_RELOC_MEP_PCREL17A2 2384@deffnx {} BFD_RELOC_MEP_PCREL24A2 2385@deffnx {} BFD_RELOC_MEP_PCABS24A2 2386@deffnx {} BFD_RELOC_MEP_LOW16 2387@deffnx {} BFD_RELOC_MEP_HI16U 2388@deffnx {} BFD_RELOC_MEP_HI16S 2389@deffnx {} BFD_RELOC_MEP_GPREL 2390@deffnx {} BFD_RELOC_MEP_TPREL 2391@deffnx {} BFD_RELOC_MEP_TPREL7 2392@deffnx {} BFD_RELOC_MEP_TPREL7A2 2393@deffnx {} BFD_RELOC_MEP_TPREL7A4 2394@deffnx {} BFD_RELOC_MEP_UIMM24 2395@deffnx {} BFD_RELOC_MEP_ADDR24A4 2396@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2397@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2398Toshiba Media Processor Relocations. 2399@end deffn 2400@deffn {} BFD_RELOC_METAG_HIADDR16 2401@deffnx {} BFD_RELOC_METAG_LOADDR16 2402@deffnx {} BFD_RELOC_METAG_RELBRANCH 2403@deffnx {} BFD_RELOC_METAG_GETSETOFF 2404@deffnx {} BFD_RELOC_METAG_HIOG 2405@deffnx {} BFD_RELOC_METAG_LOOG 2406@deffnx {} BFD_RELOC_METAG_REL8 2407@deffnx {} BFD_RELOC_METAG_REL16 2408@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2409@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2410@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2411@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2412@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2413@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2414@deffnx {} BFD_RELOC_METAG_HI16_PLT 2415@deffnx {} BFD_RELOC_METAG_LO16_PLT 2416@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2417@deffnx {} BFD_RELOC_METAG_GOTOFF 2418@deffnx {} BFD_RELOC_METAG_PLT 2419@deffnx {} BFD_RELOC_METAG_COPY 2420@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2421@deffnx {} BFD_RELOC_METAG_RELATIVE 2422@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2423@deffnx {} BFD_RELOC_METAG_TLS_GD 2424@deffnx {} BFD_RELOC_METAG_TLS_LDM 2425@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2426@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2427@deffnx {} BFD_RELOC_METAG_TLS_LDO 2428@deffnx {} BFD_RELOC_METAG_TLS_IE 2429@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2430@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2431@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2432@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2433@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2434@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2435@deffnx {} BFD_RELOC_METAG_TLS_LE 2436@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2437@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2438Imagination Technologies Meta relocations. 2439@end deffn 2440@deffn {} BFD_RELOC_MMIX_GETA 2441@deffnx {} BFD_RELOC_MMIX_GETA_1 2442@deffnx {} BFD_RELOC_MMIX_GETA_2 2443@deffnx {} BFD_RELOC_MMIX_GETA_3 2444These are relocations for the GETA instruction. 2445@end deffn 2446@deffn {} BFD_RELOC_MMIX_CBRANCH 2447@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2448@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2449@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2450@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2451These are relocations for a conditional branch instruction. 2452@end deffn 2453@deffn {} BFD_RELOC_MMIX_PUSHJ 2454@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2455@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2456@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2457@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2458These are relocations for the PUSHJ instruction. 2459@end deffn 2460@deffn {} BFD_RELOC_MMIX_JMP 2461@deffnx {} BFD_RELOC_MMIX_JMP_1 2462@deffnx {} BFD_RELOC_MMIX_JMP_2 2463@deffnx {} BFD_RELOC_MMIX_JMP_3 2464These are relocations for the JMP instruction. 2465@end deffn 2466@deffn {} BFD_RELOC_MMIX_ADDR19 2467This is a relocation for a relative address as in a GETA instruction or 2468a branch. 2469@end deffn 2470@deffn {} BFD_RELOC_MMIX_ADDR27 2471This is a relocation for a relative address as in a JMP instruction. 2472@end deffn 2473@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2474This is a relocation for an instruction field that may be a general 2475register or a value 0..255. 2476@end deffn 2477@deffn {} BFD_RELOC_MMIX_REG 2478This is a relocation for an instruction field that may be a general 2479register. 2480@end deffn 2481@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2482This is a relocation for two instruction fields holding a register and 2483an offset, the equivalent of the relocation. 2484@end deffn 2485@deffn {} BFD_RELOC_MMIX_LOCAL 2486This relocation is an assertion that the expression is not allocated as 2487a global register. It does not modify contents. 2488@end deffn 2489@deffn {} BFD_RELOC_AVR_7_PCREL 2490This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2491short offset into 7 bits. 2492@end deffn 2493@deffn {} BFD_RELOC_AVR_13_PCREL 2494This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2495short offset into 12 bits. 2496@end deffn 2497@deffn {} BFD_RELOC_AVR_16_PM 2498This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2499program memory address) into 16 bits. 2500@end deffn 2501@deffn {} BFD_RELOC_AVR_LO8_LDI 2502This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2503data memory address) into 8 bit immediate value of LDI insn. 2504@end deffn 2505@deffn {} BFD_RELOC_AVR_HI8_LDI 2506This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2507of data memory address) into 8 bit immediate value of LDI insn. 2508@end deffn 2509@deffn {} BFD_RELOC_AVR_HH8_LDI 2510This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2511of program memory address) into 8 bit immediate value of LDI insn. 2512@end deffn 2513@deffn {} BFD_RELOC_AVR_MS8_LDI 2514This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2515of 32 bit value) into 8 bit immediate value of LDI insn. 2516@end deffn 2517@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2518This is a 16 bit reloc for the AVR that stores negated 8 bit value 2519(usually data memory address) into 8 bit immediate value of SUBI insn. 2520@end deffn 2521@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2522This is a 16 bit reloc for the AVR that stores negated 8 bit value 2523(high 8 bit of data memory address) into 8 bit immediate value of 2524SUBI insn. 2525@end deffn 2526@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2527This is a 16 bit reloc for the AVR that stores negated 8 bit value 2528(most high 8 bit of program memory address) into 8 bit immediate value 2529of LDI or SUBI insn. 2530@end deffn 2531@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2532This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2533of 32 bit value) into 8 bit immediate value of LDI insn. 2534@end deffn 2535@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2536This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2537command address) into 8 bit immediate value of LDI insn. 2538@end deffn 2539@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2540This is a 16 bit reloc for the AVR that stores 8 bit value 2541(command address) into 8 bit immediate value of LDI insn. If the address 2542is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2543in the lower 128k. 2544@end deffn 2545@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2546This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2547of command address) into 8 bit immediate value of LDI insn. 2548@end deffn 2549@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2550This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2551of command address) into 8 bit immediate value of LDI insn. If the address 2552is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2553below 128k. 2554@end deffn 2555@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2556This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2557of command address) into 8 bit immediate value of LDI insn. 2558@end deffn 2559@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2560This is a 16 bit reloc for the AVR that stores negated 8 bit value 2561(usually command address) into 8 bit immediate value of SUBI insn. 2562@end deffn 2563@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2564This is a 16 bit reloc for the AVR that stores negated 8 bit value 2565(high 8 bit of 16 bit command address) into 8 bit immediate value 2566of SUBI insn. 2567@end deffn 2568@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2569This is a 16 bit reloc for the AVR that stores negated 8 bit value 2570(high 6 bit of 22 bit command address) into 8 bit immediate 2571value of SUBI insn. 2572@end deffn 2573@deffn {} BFD_RELOC_AVR_CALL 2574This is a 32 bit reloc for the AVR that stores 23 bit value 2575into 22 bits. 2576@end deffn 2577@deffn {} BFD_RELOC_AVR_LDI 2578This is a 16 bit reloc for the AVR that stores all needed bits 2579for absolute addressing with ldi with overflow check to linktime 2580@end deffn 2581@deffn {} BFD_RELOC_AVR_6 2582This is a 6 bit reloc for the AVR that stores offset for ldd/std 2583instructions 2584@end deffn 2585@deffn {} BFD_RELOC_AVR_6_ADIW 2586This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2587instructions 2588@end deffn 2589@deffn {} BFD_RELOC_AVR_8_LO 2590This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2591in .byte lo8(symbol) 2592@end deffn 2593@deffn {} BFD_RELOC_AVR_8_HI 2594This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2595in .byte hi8(symbol) 2596@end deffn 2597@deffn {} BFD_RELOC_AVR_8_HLO 2598This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2599in .byte hlo8(symbol) 2600@end deffn 2601@deffn {} BFD_RELOC_AVR_DIFF8 2602@deffnx {} BFD_RELOC_AVR_DIFF16 2603@deffnx {} BFD_RELOC_AVR_DIFF32 2604AVR relocations to mark the difference of two local symbols. 2605These are only needed to support linker relaxation and can be ignored 2606when not relaxing. The field is set to the value of the difference 2607assuming no relaxation. The relocation encodes the position of the 2608second symbol so the linker can determine whether to adjust the field 2609value. 2610@end deffn 2611@deffn {} BFD_RELOC_AVR_LDS_STS_16 2612This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2613lds and sts instructions supported only tiny core. 2614@end deffn 2615@deffn {} BFD_RELOC_AVR_PORT6 2616This is a 6 bit reloc for the AVR that stores an I/O register 2617number for the IN and OUT instructions 2618@end deffn 2619@deffn {} BFD_RELOC_AVR_PORT5 2620This is a 5 bit reloc for the AVR that stores an I/O register 2621number for the SBIC, SBIS, SBI and CBI instructions 2622@end deffn 2623@deffn {} BFD_RELOC_RISCV_HI20 2624@deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2625@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2626@deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2627@deffnx {} BFD_RELOC_RISCV_LO12_I 2628@deffnx {} BFD_RELOC_RISCV_LO12_S 2629@deffnx {} BFD_RELOC_RISCV_GPREL12_I 2630@deffnx {} BFD_RELOC_RISCV_GPREL12_S 2631@deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2632@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2633@deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2634@deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2635@deffnx {} BFD_RELOC_RISCV_CALL 2636@deffnx {} BFD_RELOC_RISCV_CALL_PLT 2637@deffnx {} BFD_RELOC_RISCV_ADD8 2638@deffnx {} BFD_RELOC_RISCV_ADD16 2639@deffnx {} BFD_RELOC_RISCV_ADD32 2640@deffnx {} BFD_RELOC_RISCV_ADD64 2641@deffnx {} BFD_RELOC_RISCV_SUB8 2642@deffnx {} BFD_RELOC_RISCV_SUB16 2643@deffnx {} BFD_RELOC_RISCV_SUB32 2644@deffnx {} BFD_RELOC_RISCV_SUB64 2645@deffnx {} BFD_RELOC_RISCV_GOT_HI20 2646@deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2647@deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2648@deffnx {} BFD_RELOC_RISCV_JMP 2649@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2650@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2651@deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2652@deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2653@deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2654@deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2655@deffnx {} BFD_RELOC_RISCV_ALIGN 2656@deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2657@deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2658@deffnx {} BFD_RELOC_RISCV_RVC_LUI 2659@deffnx {} BFD_RELOC_RISCV_GPREL_I 2660@deffnx {} BFD_RELOC_RISCV_GPREL_S 2661@deffnx {} BFD_RELOC_RISCV_TPREL_I 2662@deffnx {} BFD_RELOC_RISCV_TPREL_S 2663@deffnx {} BFD_RELOC_RISCV_RELAX 2664@deffnx {} BFD_RELOC_RISCV_CFA 2665@deffnx {} BFD_RELOC_RISCV_SUB6 2666@deffnx {} BFD_RELOC_RISCV_SET6 2667@deffnx {} BFD_RELOC_RISCV_SET8 2668@deffnx {} BFD_RELOC_RISCV_SET16 2669@deffnx {} BFD_RELOC_RISCV_SET32 2670@deffnx {} BFD_RELOC_RISCV_32_PCREL 2671RISC-V relocations. 2672@end deffn 2673@deffn {} BFD_RELOC_RL78_NEG8 2674@deffnx {} BFD_RELOC_RL78_NEG16 2675@deffnx {} BFD_RELOC_RL78_NEG24 2676@deffnx {} BFD_RELOC_RL78_NEG32 2677@deffnx {} BFD_RELOC_RL78_16_OP 2678@deffnx {} BFD_RELOC_RL78_24_OP 2679@deffnx {} BFD_RELOC_RL78_32_OP 2680@deffnx {} BFD_RELOC_RL78_8U 2681@deffnx {} BFD_RELOC_RL78_16U 2682@deffnx {} BFD_RELOC_RL78_24U 2683@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2684@deffnx {} BFD_RELOC_RL78_DIFF 2685@deffnx {} BFD_RELOC_RL78_GPRELB 2686@deffnx {} BFD_RELOC_RL78_GPRELW 2687@deffnx {} BFD_RELOC_RL78_GPRELL 2688@deffnx {} BFD_RELOC_RL78_SYM 2689@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2690@deffnx {} BFD_RELOC_RL78_OP_NEG 2691@deffnx {} BFD_RELOC_RL78_OP_AND 2692@deffnx {} BFD_RELOC_RL78_OP_SHRA 2693@deffnx {} BFD_RELOC_RL78_ABS8 2694@deffnx {} BFD_RELOC_RL78_ABS16 2695@deffnx {} BFD_RELOC_RL78_ABS16_REV 2696@deffnx {} BFD_RELOC_RL78_ABS32 2697@deffnx {} BFD_RELOC_RL78_ABS32_REV 2698@deffnx {} BFD_RELOC_RL78_ABS16U 2699@deffnx {} BFD_RELOC_RL78_ABS16UW 2700@deffnx {} BFD_RELOC_RL78_ABS16UL 2701@deffnx {} BFD_RELOC_RL78_RELAX 2702@deffnx {} BFD_RELOC_RL78_HI16 2703@deffnx {} BFD_RELOC_RL78_HI8 2704@deffnx {} BFD_RELOC_RL78_LO16 2705@deffnx {} BFD_RELOC_RL78_CODE 2706@deffnx {} BFD_RELOC_RL78_SADDR 2707Renesas RL78 Relocations. 2708@end deffn 2709@deffn {} BFD_RELOC_RX_NEG8 2710@deffnx {} BFD_RELOC_RX_NEG16 2711@deffnx {} BFD_RELOC_RX_NEG24 2712@deffnx {} BFD_RELOC_RX_NEG32 2713@deffnx {} BFD_RELOC_RX_16_OP 2714@deffnx {} BFD_RELOC_RX_24_OP 2715@deffnx {} BFD_RELOC_RX_32_OP 2716@deffnx {} BFD_RELOC_RX_8U 2717@deffnx {} BFD_RELOC_RX_16U 2718@deffnx {} BFD_RELOC_RX_24U 2719@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2720@deffnx {} BFD_RELOC_RX_DIFF 2721@deffnx {} BFD_RELOC_RX_GPRELB 2722@deffnx {} BFD_RELOC_RX_GPRELW 2723@deffnx {} BFD_RELOC_RX_GPRELL 2724@deffnx {} BFD_RELOC_RX_SYM 2725@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2726@deffnx {} BFD_RELOC_RX_OP_NEG 2727@deffnx {} BFD_RELOC_RX_ABS8 2728@deffnx {} BFD_RELOC_RX_ABS16 2729@deffnx {} BFD_RELOC_RX_ABS16_REV 2730@deffnx {} BFD_RELOC_RX_ABS32 2731@deffnx {} BFD_RELOC_RX_ABS32_REV 2732@deffnx {} BFD_RELOC_RX_ABS16U 2733@deffnx {} BFD_RELOC_RX_ABS16UW 2734@deffnx {} BFD_RELOC_RX_ABS16UL 2735@deffnx {} BFD_RELOC_RX_RELAX 2736Renesas RX Relocations. 2737@end deffn 2738@deffn {} BFD_RELOC_390_12 2739Direct 12 bit. 2740@end deffn 2741@deffn {} BFD_RELOC_390_GOT12 274212 bit GOT offset. 2743@end deffn 2744@deffn {} BFD_RELOC_390_PLT32 274532 bit PC relative PLT address. 2746@end deffn 2747@deffn {} BFD_RELOC_390_COPY 2748Copy symbol at runtime. 2749@end deffn 2750@deffn {} BFD_RELOC_390_GLOB_DAT 2751Create GOT entry. 2752@end deffn 2753@deffn {} BFD_RELOC_390_JMP_SLOT 2754Create PLT entry. 2755@end deffn 2756@deffn {} BFD_RELOC_390_RELATIVE 2757Adjust by program base. 2758@end deffn 2759@deffn {} BFD_RELOC_390_GOTPC 276032 bit PC relative offset to GOT. 2761@end deffn 2762@deffn {} BFD_RELOC_390_GOT16 276316 bit GOT offset. 2764@end deffn 2765@deffn {} BFD_RELOC_390_PC12DBL 2766PC relative 12 bit shifted by 1. 2767@end deffn 2768@deffn {} BFD_RELOC_390_PLT12DBL 276912 bit PC rel. PLT shifted by 1. 2770@end deffn 2771@deffn {} BFD_RELOC_390_PC16DBL 2772PC relative 16 bit shifted by 1. 2773@end deffn 2774@deffn {} BFD_RELOC_390_PLT16DBL 277516 bit PC rel. PLT shifted by 1. 2776@end deffn 2777@deffn {} BFD_RELOC_390_PC24DBL 2778PC relative 24 bit shifted by 1. 2779@end deffn 2780@deffn {} BFD_RELOC_390_PLT24DBL 278124 bit PC rel. PLT shifted by 1. 2782@end deffn 2783@deffn {} BFD_RELOC_390_PC32DBL 2784PC relative 32 bit shifted by 1. 2785@end deffn 2786@deffn {} BFD_RELOC_390_PLT32DBL 278732 bit PC rel. PLT shifted by 1. 2788@end deffn 2789@deffn {} BFD_RELOC_390_GOTPCDBL 279032 bit PC rel. GOT shifted by 1. 2791@end deffn 2792@deffn {} BFD_RELOC_390_GOT64 279364 bit GOT offset. 2794@end deffn 2795@deffn {} BFD_RELOC_390_PLT64 279664 bit PC relative PLT address. 2797@end deffn 2798@deffn {} BFD_RELOC_390_GOTENT 279932 bit rel. offset to GOT entry. 2800@end deffn 2801@deffn {} BFD_RELOC_390_GOTOFF64 280264 bit offset to GOT. 2803@end deffn 2804@deffn {} BFD_RELOC_390_GOTPLT12 280512-bit offset to symbol-entry within GOT, with PLT handling. 2806@end deffn 2807@deffn {} BFD_RELOC_390_GOTPLT16 280816-bit offset to symbol-entry within GOT, with PLT handling. 2809@end deffn 2810@deffn {} BFD_RELOC_390_GOTPLT32 281132-bit offset to symbol-entry within GOT, with PLT handling. 2812@end deffn 2813@deffn {} BFD_RELOC_390_GOTPLT64 281464-bit offset to symbol-entry within GOT, with PLT handling. 2815@end deffn 2816@deffn {} BFD_RELOC_390_GOTPLTENT 281732-bit rel. offset to symbol-entry within GOT, with PLT handling. 2818@end deffn 2819@deffn {} BFD_RELOC_390_PLTOFF16 282016-bit rel. offset from the GOT to a PLT entry. 2821@end deffn 2822@deffn {} BFD_RELOC_390_PLTOFF32 282332-bit rel. offset from the GOT to a PLT entry. 2824@end deffn 2825@deffn {} BFD_RELOC_390_PLTOFF64 282664-bit rel. offset from the GOT to a PLT entry. 2827@end deffn 2828@deffn {} BFD_RELOC_390_TLS_LOAD 2829@deffnx {} BFD_RELOC_390_TLS_GDCALL 2830@deffnx {} BFD_RELOC_390_TLS_LDCALL 2831@deffnx {} BFD_RELOC_390_TLS_GD32 2832@deffnx {} BFD_RELOC_390_TLS_GD64 2833@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2834@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2835@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2836@deffnx {} BFD_RELOC_390_TLS_LDM32 2837@deffnx {} BFD_RELOC_390_TLS_LDM64 2838@deffnx {} BFD_RELOC_390_TLS_IE32 2839@deffnx {} BFD_RELOC_390_TLS_IE64 2840@deffnx {} BFD_RELOC_390_TLS_IEENT 2841@deffnx {} BFD_RELOC_390_TLS_LE32 2842@deffnx {} BFD_RELOC_390_TLS_LE64 2843@deffnx {} BFD_RELOC_390_TLS_LDO32 2844@deffnx {} BFD_RELOC_390_TLS_LDO64 2845@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2846@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2847@deffnx {} BFD_RELOC_390_TLS_TPOFF 2848s390 tls relocations. 2849@end deffn 2850@deffn {} BFD_RELOC_390_20 2851@deffnx {} BFD_RELOC_390_GOT20 2852@deffnx {} BFD_RELOC_390_GOTPLT20 2853@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2854Long displacement extension. 2855@end deffn 2856@deffn {} BFD_RELOC_390_IRELATIVE 2857STT_GNU_IFUNC relocation. 2858@end deffn 2859@deffn {} BFD_RELOC_SCORE_GPREL15 2860Score relocations 2861Low 16 bit for load/store 2862@end deffn 2863@deffn {} BFD_RELOC_SCORE_DUMMY2 2864@deffnx {} BFD_RELOC_SCORE_JMP 2865This is a 24-bit reloc with the right 1 bit assumed to be 0 2866@end deffn 2867@deffn {} BFD_RELOC_SCORE_BRANCH 2868This is a 19-bit reloc with the right 1 bit assumed to be 0 2869@end deffn 2870@deffn {} BFD_RELOC_SCORE_IMM30 2871This is a 32-bit reloc for 48-bit instructions. 2872@end deffn 2873@deffn {} BFD_RELOC_SCORE_IMM32 2874This is a 32-bit reloc for 48-bit instructions. 2875@end deffn 2876@deffn {} BFD_RELOC_SCORE16_JMP 2877This is a 11-bit reloc with the right 1 bit assumed to be 0 2878@end deffn 2879@deffn {} BFD_RELOC_SCORE16_BRANCH 2880This is a 8-bit reloc with the right 1 bit assumed to be 0 2881@end deffn 2882@deffn {} BFD_RELOC_SCORE_BCMP 2883This is a 9-bit reloc with the right 1 bit assumed to be 0 2884@end deffn 2885@deffn {} BFD_RELOC_SCORE_GOT15 2886@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2887@deffnx {} BFD_RELOC_SCORE_CALL15 2888@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2889Undocumented Score relocs 2890@end deffn 2891@deffn {} BFD_RELOC_IP2K_FR9 2892Scenix IP2K - 9-bit register number / data address 2893@end deffn 2894@deffn {} BFD_RELOC_IP2K_BANK 2895Scenix IP2K - 4-bit register/data bank number 2896@end deffn 2897@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2898Scenix IP2K - low 13 bits of instruction word address 2899@end deffn 2900@deffn {} BFD_RELOC_IP2K_PAGE3 2901Scenix IP2K - high 3 bits of instruction word address 2902@end deffn 2903@deffn {} BFD_RELOC_IP2K_LO8DATA 2904@deffnx {} BFD_RELOC_IP2K_HI8DATA 2905@deffnx {} BFD_RELOC_IP2K_EX8DATA 2906Scenix IP2K - ext/low/high 8 bits of data address 2907@end deffn 2908@deffn {} BFD_RELOC_IP2K_LO8INSN 2909@deffnx {} BFD_RELOC_IP2K_HI8INSN 2910Scenix IP2K - low/high 8 bits of instruction word address 2911@end deffn 2912@deffn {} BFD_RELOC_IP2K_PC_SKIP 2913Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2914@end deffn 2915@deffn {} BFD_RELOC_IP2K_TEXT 2916Scenix IP2K - 16 bit word address in text section. 2917@end deffn 2918@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2919Scenix IP2K - 7-bit sp or dp offset 2920@end deffn 2921@deffn {} BFD_RELOC_VPE4KMATH_DATA 2922@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2923Scenix VPE4K coprocessor - data/insn-space addressing 2924@end deffn 2925@deffn {} BFD_RELOC_VTABLE_INHERIT 2926@deffnx {} BFD_RELOC_VTABLE_ENTRY 2927These two relocations are used by the linker to determine which of 2928the entries in a C++ virtual function table are actually used. When 2929the --gc-sections option is given, the linker will zero out the entries 2930that are not used, so that the code for those functions need not be 2931included in the output. 2932 2933VTABLE_INHERIT is a zero-space relocation used to describe to the 2934linker the inheritance tree of a C++ virtual function table. The 2935relocation's symbol should be the parent class' vtable, and the 2936relocation should be located at the child vtable. 2937 2938VTABLE_ENTRY is a zero-space relocation that describes the use of a 2939virtual function table entry. The reloc's symbol should refer to the 2940table of the class mentioned in the code. Off of that base, an offset 2941describes the entry that is being used. For Rela hosts, this offset 2942is stored in the reloc's addend. For Rel hosts, we are forced to put 2943this offset in the reloc's section offset. 2944@end deffn 2945@deffn {} BFD_RELOC_IA64_IMM14 2946@deffnx {} BFD_RELOC_IA64_IMM22 2947@deffnx {} BFD_RELOC_IA64_IMM64 2948@deffnx {} BFD_RELOC_IA64_DIR32MSB 2949@deffnx {} BFD_RELOC_IA64_DIR32LSB 2950@deffnx {} BFD_RELOC_IA64_DIR64MSB 2951@deffnx {} BFD_RELOC_IA64_DIR64LSB 2952@deffnx {} BFD_RELOC_IA64_GPREL22 2953@deffnx {} BFD_RELOC_IA64_GPREL64I 2954@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2955@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2956@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2957@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2958@deffnx {} BFD_RELOC_IA64_LTOFF22 2959@deffnx {} BFD_RELOC_IA64_LTOFF64I 2960@deffnx {} BFD_RELOC_IA64_PLTOFF22 2961@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2962@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2963@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2964@deffnx {} BFD_RELOC_IA64_FPTR64I 2965@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2966@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2967@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2968@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2969@deffnx {} BFD_RELOC_IA64_PCREL21B 2970@deffnx {} BFD_RELOC_IA64_PCREL21BI 2971@deffnx {} BFD_RELOC_IA64_PCREL21M 2972@deffnx {} BFD_RELOC_IA64_PCREL21F 2973@deffnx {} BFD_RELOC_IA64_PCREL22 2974@deffnx {} BFD_RELOC_IA64_PCREL60B 2975@deffnx {} BFD_RELOC_IA64_PCREL64I 2976@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2977@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2978@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2979@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2980@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2981@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2982@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2983@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2984@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2985@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2986@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2987@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2988@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2989@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2990@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2991@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2992@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2993@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2994@deffnx {} BFD_RELOC_IA64_REL32MSB 2995@deffnx {} BFD_RELOC_IA64_REL32LSB 2996@deffnx {} BFD_RELOC_IA64_REL64MSB 2997@deffnx {} BFD_RELOC_IA64_REL64LSB 2998@deffnx {} BFD_RELOC_IA64_LTV32MSB 2999@deffnx {} BFD_RELOC_IA64_LTV32LSB 3000@deffnx {} BFD_RELOC_IA64_LTV64MSB 3001@deffnx {} BFD_RELOC_IA64_LTV64LSB 3002@deffnx {} BFD_RELOC_IA64_IPLTMSB 3003@deffnx {} BFD_RELOC_IA64_IPLTLSB 3004@deffnx {} BFD_RELOC_IA64_COPY 3005@deffnx {} BFD_RELOC_IA64_LTOFF22X 3006@deffnx {} BFD_RELOC_IA64_LDXMOV 3007@deffnx {} BFD_RELOC_IA64_TPREL14 3008@deffnx {} BFD_RELOC_IA64_TPREL22 3009@deffnx {} BFD_RELOC_IA64_TPREL64I 3010@deffnx {} BFD_RELOC_IA64_TPREL64MSB 3011@deffnx {} BFD_RELOC_IA64_TPREL64LSB 3012@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 3013@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 3014@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 3015@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 3016@deffnx {} BFD_RELOC_IA64_DTPREL14 3017@deffnx {} BFD_RELOC_IA64_DTPREL22 3018@deffnx {} BFD_RELOC_IA64_DTPREL64I 3019@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 3020@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 3021@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 3022@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 3023@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 3024Intel IA64 Relocations. 3025@end deffn 3026@deffn {} BFD_RELOC_M68HC11_HI8 3027Motorola 68HC11 reloc. 3028This is the 8 bit high part of an absolute address. 3029@end deffn 3030@deffn {} BFD_RELOC_M68HC11_LO8 3031Motorola 68HC11 reloc. 3032This is the 8 bit low part of an absolute address. 3033@end deffn 3034@deffn {} BFD_RELOC_M68HC11_3B 3035Motorola 68HC11 reloc. 3036This is the 3 bit of a value. 3037@end deffn 3038@deffn {} BFD_RELOC_M68HC11_RL_JUMP 3039Motorola 68HC11 reloc. 3040This reloc marks the beginning of a jump/call instruction. 3041It is used for linker relaxation to correctly identify beginning 3042of instruction and change some branches to use PC-relative 3043addressing mode. 3044@end deffn 3045@deffn {} BFD_RELOC_M68HC11_RL_GROUP 3046Motorola 68HC11 reloc. 3047This reloc marks a group of several instructions that gcc generates 3048and for which the linker relaxation pass can modify and/or remove 3049some of them. 3050@end deffn 3051@deffn {} BFD_RELOC_M68HC11_LO16 3052Motorola 68HC11 reloc. 3053This is the 16-bit lower part of an address. It is used for 'call' 3054instruction to specify the symbol address without any special 3055transformation (due to memory bank window). 3056@end deffn 3057@deffn {} BFD_RELOC_M68HC11_PAGE 3058Motorola 68HC11 reloc. 3059This is a 8-bit reloc that specifies the page number of an address. 3060It is used by 'call' instruction to specify the page number of 3061the symbol. 3062@end deffn 3063@deffn {} BFD_RELOC_M68HC11_24 3064Motorola 68HC11 reloc. 3065This is a 24-bit reloc that represents the address with a 16-bit 3066value and a 8-bit page number. The symbol address is transformed 3067to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 3068@end deffn 3069@deffn {} BFD_RELOC_M68HC12_5B 3070Motorola 68HC12 reloc. 3071This is the 5 bits of a value. 3072@end deffn 3073@deffn {} BFD_RELOC_XGATE_RL_JUMP 3074Freescale XGATE reloc. 3075This reloc marks the beginning of a bra/jal instruction. 3076@end deffn 3077@deffn {} BFD_RELOC_XGATE_RL_GROUP 3078Freescale XGATE reloc. 3079This reloc marks a group of several instructions that gcc generates 3080and for which the linker relaxation pass can modify and/or remove 3081some of them. 3082@end deffn 3083@deffn {} BFD_RELOC_XGATE_LO16 3084Freescale XGATE reloc. 3085This is the 16-bit lower part of an address. It is used for the '16-bit' 3086instructions. 3087@end deffn 3088@deffn {} BFD_RELOC_XGATE_GPAGE 3089Freescale XGATE reloc. 3090@end deffn 3091@deffn {} BFD_RELOC_XGATE_24 3092Freescale XGATE reloc. 3093@end deffn 3094@deffn {} BFD_RELOC_XGATE_PCREL_9 3095Freescale XGATE reloc. 3096This is a 9-bit pc-relative reloc. 3097@end deffn 3098@deffn {} BFD_RELOC_XGATE_PCREL_10 3099Freescale XGATE reloc. 3100This is a 10-bit pc-relative reloc. 3101@end deffn 3102@deffn {} BFD_RELOC_XGATE_IMM8_LO 3103Freescale XGATE reloc. 3104This is the 16-bit lower part of an address. It is used for the '16-bit' 3105instructions. 3106@end deffn 3107@deffn {} BFD_RELOC_XGATE_IMM8_HI 3108Freescale XGATE reloc. 3109This is the 16-bit higher part of an address. It is used for the '16-bit' 3110instructions. 3111@end deffn 3112@deffn {} BFD_RELOC_XGATE_IMM3 3113Freescale XGATE reloc. 3114This is a 3-bit pc-relative reloc. 3115@end deffn 3116@deffn {} BFD_RELOC_XGATE_IMM4 3117Freescale XGATE reloc. 3118This is a 4-bit pc-relative reloc. 3119@end deffn 3120@deffn {} BFD_RELOC_XGATE_IMM5 3121Freescale XGATE reloc. 3122This is a 5-bit pc-relative reloc. 3123@end deffn 3124@deffn {} BFD_RELOC_M68HC12_9B 3125Motorola 68HC12 reloc. 3126This is the 9 bits of a value. 3127@end deffn 3128@deffn {} BFD_RELOC_M68HC12_16B 3129Motorola 68HC12 reloc. 3130This is the 16 bits of a value. 3131@end deffn 3132@deffn {} BFD_RELOC_M68HC12_9_PCREL 3133Motorola 68HC12/XGATE reloc. 3134This is a PCREL9 branch. 3135@end deffn 3136@deffn {} BFD_RELOC_M68HC12_10_PCREL 3137Motorola 68HC12/XGATE reloc. 3138This is a PCREL10 branch. 3139@end deffn 3140@deffn {} BFD_RELOC_M68HC12_LO8XG 3141Motorola 68HC12/XGATE reloc. 3142This is the 8 bit low part of an absolute address and immediately precedes 3143a matching HI8XG part. 3144@end deffn 3145@deffn {} BFD_RELOC_M68HC12_HI8XG 3146Motorola 68HC12/XGATE reloc. 3147This is the 8 bit high part of an absolute address and immediately follows 3148a matching LO8XG part. 3149@end deffn 3150@deffn {} BFD_RELOC_S12Z_15_PCREL 3151Freescale S12Z reloc. 3152This is a 15 bit relative address. If the most significant bits are all zero 3153then it may be truncated to 8 bits. 3154@end deffn 3155@deffn {} BFD_RELOC_CR16_NUM8 3156@deffnx {} BFD_RELOC_CR16_NUM16 3157@deffnx {} BFD_RELOC_CR16_NUM32 3158@deffnx {} BFD_RELOC_CR16_NUM32a 3159@deffnx {} BFD_RELOC_CR16_REGREL0 3160@deffnx {} BFD_RELOC_CR16_REGREL4 3161@deffnx {} BFD_RELOC_CR16_REGREL4a 3162@deffnx {} BFD_RELOC_CR16_REGREL14 3163@deffnx {} BFD_RELOC_CR16_REGREL14a 3164@deffnx {} BFD_RELOC_CR16_REGREL16 3165@deffnx {} BFD_RELOC_CR16_REGREL20 3166@deffnx {} BFD_RELOC_CR16_REGREL20a 3167@deffnx {} BFD_RELOC_CR16_ABS20 3168@deffnx {} BFD_RELOC_CR16_ABS24 3169@deffnx {} BFD_RELOC_CR16_IMM4 3170@deffnx {} BFD_RELOC_CR16_IMM8 3171@deffnx {} BFD_RELOC_CR16_IMM16 3172@deffnx {} BFD_RELOC_CR16_IMM20 3173@deffnx {} BFD_RELOC_CR16_IMM24 3174@deffnx {} BFD_RELOC_CR16_IMM32 3175@deffnx {} BFD_RELOC_CR16_IMM32a 3176@deffnx {} BFD_RELOC_CR16_DISP4 3177@deffnx {} BFD_RELOC_CR16_DISP8 3178@deffnx {} BFD_RELOC_CR16_DISP16 3179@deffnx {} BFD_RELOC_CR16_DISP20 3180@deffnx {} BFD_RELOC_CR16_DISP24 3181@deffnx {} BFD_RELOC_CR16_DISP24a 3182@deffnx {} BFD_RELOC_CR16_SWITCH8 3183@deffnx {} BFD_RELOC_CR16_SWITCH16 3184@deffnx {} BFD_RELOC_CR16_SWITCH32 3185@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3186@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3187@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3188NS CR16 Relocations. 3189@end deffn 3190@deffn {} BFD_RELOC_CRX_REL4 3191@deffnx {} BFD_RELOC_CRX_REL8 3192@deffnx {} BFD_RELOC_CRX_REL8_CMP 3193@deffnx {} BFD_RELOC_CRX_REL16 3194@deffnx {} BFD_RELOC_CRX_REL24 3195@deffnx {} BFD_RELOC_CRX_REL32 3196@deffnx {} BFD_RELOC_CRX_REGREL12 3197@deffnx {} BFD_RELOC_CRX_REGREL22 3198@deffnx {} BFD_RELOC_CRX_REGREL28 3199@deffnx {} BFD_RELOC_CRX_REGREL32 3200@deffnx {} BFD_RELOC_CRX_ABS16 3201@deffnx {} BFD_RELOC_CRX_ABS32 3202@deffnx {} BFD_RELOC_CRX_NUM8 3203@deffnx {} BFD_RELOC_CRX_NUM16 3204@deffnx {} BFD_RELOC_CRX_NUM32 3205@deffnx {} BFD_RELOC_CRX_IMM16 3206@deffnx {} BFD_RELOC_CRX_IMM32 3207@deffnx {} BFD_RELOC_CRX_SWITCH8 3208@deffnx {} BFD_RELOC_CRX_SWITCH16 3209@deffnx {} BFD_RELOC_CRX_SWITCH32 3210NS CRX Relocations. 3211@end deffn 3212@deffn {} BFD_RELOC_CRIS_BDISP8 3213@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3214@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3215@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3216@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3217@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3218@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3219@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3220@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3221@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3222These relocs are only used within the CRIS assembler. They are not 3223(at present) written to any object files. 3224@end deffn 3225@deffn {} BFD_RELOC_CRIS_COPY 3226@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3227@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3228@deffnx {} BFD_RELOC_CRIS_RELATIVE 3229Relocs used in ELF shared libraries for CRIS. 3230@end deffn 3231@deffn {} BFD_RELOC_CRIS_32_GOT 323232-bit offset to symbol-entry within GOT. 3233@end deffn 3234@deffn {} BFD_RELOC_CRIS_16_GOT 323516-bit offset to symbol-entry within GOT. 3236@end deffn 3237@deffn {} BFD_RELOC_CRIS_32_GOTPLT 323832-bit offset to symbol-entry within GOT, with PLT handling. 3239@end deffn 3240@deffn {} BFD_RELOC_CRIS_16_GOTPLT 324116-bit offset to symbol-entry within GOT, with PLT handling. 3242@end deffn 3243@deffn {} BFD_RELOC_CRIS_32_GOTREL 324432-bit offset to symbol, relative to GOT. 3245@end deffn 3246@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 324732-bit offset to symbol with PLT entry, relative to GOT. 3248@end deffn 3249@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 325032-bit offset to symbol with PLT entry, relative to this relocation. 3251@end deffn 3252@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3253@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3254@deffnx {} BFD_RELOC_CRIS_32_GD 3255@deffnx {} BFD_RELOC_CRIS_DTP 3256@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3257@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3258@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3259@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3260@deffnx {} BFD_RELOC_CRIS_32_TPREL 3261@deffnx {} BFD_RELOC_CRIS_16_TPREL 3262@deffnx {} BFD_RELOC_CRIS_DTPMOD 3263@deffnx {} BFD_RELOC_CRIS_32_IE 3264Relocs used in TLS code for CRIS. 3265@end deffn 3266@deffn {} BFD_RELOC_OR1K_REL_26 3267@deffnx {} BFD_RELOC_OR1K_SLO16 3268@deffnx {} BFD_RELOC_OR1K_PCREL_PG21 3269@deffnx {} BFD_RELOC_OR1K_LO13 3270@deffnx {} BFD_RELOC_OR1K_SLO13 3271@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3272@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3273@deffnx {} BFD_RELOC_OR1K_GOT_AHI16 3274@deffnx {} BFD_RELOC_OR1K_GOT16 3275@deffnx {} BFD_RELOC_OR1K_GOT_PG21 3276@deffnx {} BFD_RELOC_OR1K_GOT_LO13 3277@deffnx {} BFD_RELOC_OR1K_PLT26 3278@deffnx {} BFD_RELOC_OR1K_PLTA26 3279@deffnx {} BFD_RELOC_OR1K_GOTOFF_SLO16 3280@deffnx {} BFD_RELOC_OR1K_COPY 3281@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3282@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3283@deffnx {} BFD_RELOC_OR1K_RELATIVE 3284@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3285@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3286@deffnx {} BFD_RELOC_OR1K_TLS_GD_PG21 3287@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO13 3288@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3289@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3290@deffnx {} BFD_RELOC_OR1K_TLS_LDM_PG21 3291@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO13 3292@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3293@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3294@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3295@deffnx {} BFD_RELOC_OR1K_TLS_IE_AHI16 3296@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3297@deffnx {} BFD_RELOC_OR1K_TLS_IE_PG21 3298@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO13 3299@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3300@deffnx {} BFD_RELOC_OR1K_TLS_LE_AHI16 3301@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3302@deffnx {} BFD_RELOC_OR1K_TLS_LE_SLO16 3303@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3304@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3305@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3306OpenRISC 1000 Relocations. 3307@end deffn 3308@deffn {} BFD_RELOC_H8_DIR16A8 3309@deffnx {} BFD_RELOC_H8_DIR16R8 3310@deffnx {} BFD_RELOC_H8_DIR24A8 3311@deffnx {} BFD_RELOC_H8_DIR24R8 3312@deffnx {} BFD_RELOC_H8_DIR32A16 3313@deffnx {} BFD_RELOC_H8_DISP32A16 3314H8 elf Relocations. 3315@end deffn 3316@deffn {} BFD_RELOC_XSTORMY16_REL_12 3317@deffnx {} BFD_RELOC_XSTORMY16_12 3318@deffnx {} BFD_RELOC_XSTORMY16_24 3319@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3320Sony Xstormy16 Relocations. 3321@end deffn 3322@deffn {} BFD_RELOC_RELC 3323Self-describing complex relocations. 3324@end deffn 3325@deffn {} BFD_RELOC_VAX_GLOB_DAT 3326@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3327@deffnx {} BFD_RELOC_VAX_RELATIVE 3328Relocations used by VAX ELF. 3329@end deffn 3330@deffn {} BFD_RELOC_MT_PC16 3331Morpho MT - 16 bit immediate relocation. 3332@end deffn 3333@deffn {} BFD_RELOC_MT_HI16 3334Morpho MT - Hi 16 bits of an address. 3335@end deffn 3336@deffn {} BFD_RELOC_MT_LO16 3337Morpho MT - Low 16 bits of an address. 3338@end deffn 3339@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3340Morpho MT - Used to tell the linker which vtable entries are used. 3341@end deffn 3342@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3343Morpho MT - Used to tell the linker which vtable entries are used. 3344@end deffn 3345@deffn {} BFD_RELOC_MT_PCINSN8 3346Morpho MT - 8 bit immediate relocation. 3347@end deffn 3348@deffn {} BFD_RELOC_MSP430_10_PCREL 3349@deffnx {} BFD_RELOC_MSP430_16_PCREL 3350@deffnx {} BFD_RELOC_MSP430_16 3351@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3352@deffnx {} BFD_RELOC_MSP430_16_BYTE 3353@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3354@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3355@deffnx {} BFD_RELOC_MSP430_ABS8 3356@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3357@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3358@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3359@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3360@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3361@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3362@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3363@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3364@deffnx {} BFD_RELOC_MSP430X_PCR16 3365@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3366@deffnx {} BFD_RELOC_MSP430X_ABS16 3367@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3368@deffnx {} BFD_RELOC_MSP430_PREL31 3369@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3370@deffnx {} BFD_RELOC_MSP430_SET_ULEB128 3371@deffnx {} BFD_RELOC_MSP430_SUB_ULEB128 3372msp430 specific relocation codes 3373@end deffn 3374@deffn {} BFD_RELOC_NIOS2_S16 3375@deffnx {} BFD_RELOC_NIOS2_U16 3376@deffnx {} BFD_RELOC_NIOS2_CALL26 3377@deffnx {} BFD_RELOC_NIOS2_IMM5 3378@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3379@deffnx {} BFD_RELOC_NIOS2_IMM6 3380@deffnx {} BFD_RELOC_NIOS2_IMM8 3381@deffnx {} BFD_RELOC_NIOS2_HI16 3382@deffnx {} BFD_RELOC_NIOS2_LO16 3383@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3384@deffnx {} BFD_RELOC_NIOS2_GPREL 3385@deffnx {} BFD_RELOC_NIOS2_UJMP 3386@deffnx {} BFD_RELOC_NIOS2_CJMP 3387@deffnx {} BFD_RELOC_NIOS2_CALLR 3388@deffnx {} BFD_RELOC_NIOS2_ALIGN 3389@deffnx {} BFD_RELOC_NIOS2_GOT16 3390@deffnx {} BFD_RELOC_NIOS2_CALL16 3391@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3392@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3393@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3394@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3395@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3396@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3397@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3398@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3399@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3400@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3401@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3402@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3403@deffnx {} BFD_RELOC_NIOS2_COPY 3404@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3405@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3406@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3407@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3408@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3409@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3410@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3411@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3412@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3413@deffnx {} BFD_RELOC_NIOS2_R2_S12 3414@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3415@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3416@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3417@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3418@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3419@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3420@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3421@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3422@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3423@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3424@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3425@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3426Relocations used by the Altera Nios II core. 3427@end deffn 3428@deffn {} BFD_RELOC_PRU_U16 3429PRU LDI 16-bit unsigned data-memory relocation. 3430@end deffn 3431@deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3432PRU LDI 16-bit unsigned instruction-memory relocation. 3433@end deffn 3434@deffn {} BFD_RELOC_PRU_LDI32 3435PRU relocation for two consecutive LDI load instructions that load a 343632 bit value into a register. If the higher bits are all zero, then 3437the second instruction may be relaxed. 3438@end deffn 3439@deffn {} BFD_RELOC_PRU_S10_PCREL 3440PRU QBBx 10-bit signed PC-relative relocation. 3441@end deffn 3442@deffn {} BFD_RELOC_PRU_U8_PCREL 3443PRU 8-bit unsigned relocation used for the LOOP instruction. 3444@end deffn 3445@deffn {} BFD_RELOC_PRU_32_PMEM 3446@deffnx {} BFD_RELOC_PRU_16_PMEM 3447PRU Program Memory relocations. Used to convert from byte addressing to 344832-bit word addressing. 3449@end deffn 3450@deffn {} BFD_RELOC_PRU_GNU_DIFF8 3451@deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3452@deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3453@deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3454@deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3455PRU relocations to mark the difference of two local symbols. 3456These are only needed to support linker relaxation and can be ignored 3457when not relaxing. The field is set to the value of the difference 3458assuming no relaxation. The relocation encodes the position of the 3459second symbol so the linker can determine whether to adjust the field 3460value. The PMEM variants encode the word difference, instead of byte 3461difference between symbols. 3462@end deffn 3463@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3464@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3465@deffnx {} BFD_RELOC_IQ2000_UHI16 3466IQ2000 Relocations. 3467@end deffn 3468@deffn {} BFD_RELOC_XTENSA_RTLD 3469Special Xtensa relocation used only by PLT entries in ELF shared 3470objects to indicate that the runtime linker should set the value 3471to one of its own internal functions or data structures. 3472@end deffn 3473@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3474@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3475@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3476Xtensa relocations for ELF shared objects. 3477@end deffn 3478@deffn {} BFD_RELOC_XTENSA_PLT 3479Xtensa relocation used in ELF object files for symbols that may require 3480PLT entries. Otherwise, this is just a generic 32-bit relocation. 3481@end deffn 3482@deffn {} BFD_RELOC_XTENSA_DIFF8 3483@deffnx {} BFD_RELOC_XTENSA_DIFF16 3484@deffnx {} BFD_RELOC_XTENSA_DIFF32 3485Xtensa relocations for backward compatibility. These have been replaced 3486by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF. 3487Xtensa relocations to mark the difference of two local symbols. 3488These are only needed to support linker relaxation and can be ignored 3489when not relaxing. The field is set to the value of the difference 3490assuming no relaxation. The relocation encodes the position of the 3491first symbol so the linker can determine whether to adjust the field 3492value. 3493@end deffn 3494@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3495@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3496@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3497@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3498@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3499@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3500@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3501@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3502@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3503@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3504@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3505@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3506@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3507@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3508@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3509Generic Xtensa relocations for instruction operands. Only the slot 3510number is encoded in the relocation. The relocation applies to the 3511last PC-relative immediate operand, or if there are no PC-relative 3512immediates, to the last immediate operand. 3513@end deffn 3514@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3515@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3516@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3517@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3518@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3519@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3520@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3521@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3522@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3523@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3524@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3525@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3526@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3527@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3528@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3529Alternate Xtensa relocations. Only the slot is encoded in the 3530relocation. The meaning of these relocations is opcode-specific. 3531@end deffn 3532@deffn {} BFD_RELOC_XTENSA_OP0 3533@deffnx {} BFD_RELOC_XTENSA_OP1 3534@deffnx {} BFD_RELOC_XTENSA_OP2 3535Xtensa relocations for backward compatibility. These have all been 3536replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3537@end deffn 3538@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3539Xtensa relocation to mark that the assembler expanded the 3540instructions from an original target. The expansion size is 3541encoded in the reloc size. 3542@end deffn 3543@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3544Xtensa relocation to mark that the linker should simplify 3545assembler-expanded instructions. This is commonly used 3546internally by the linker after analysis of a 3547BFD_RELOC_XTENSA_ASM_EXPAND. 3548@end deffn 3549@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3550@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3551@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3552@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3553@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3554@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3555@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3556Xtensa TLS relocations. 3557@end deffn 3558@deffn {} BFD_RELOC_XTENSA_PDIFF8 3559@deffnx {} BFD_RELOC_XTENSA_PDIFF16 3560@deffnx {} BFD_RELOC_XTENSA_PDIFF32 3561@deffnx {} BFD_RELOC_XTENSA_NDIFF8 3562@deffnx {} BFD_RELOC_XTENSA_NDIFF16 3563@deffnx {} BFD_RELOC_XTENSA_NDIFF32 3564Xtensa relocations to mark the difference of two local symbols. 3565These are only needed to support linker relaxation and can be ignored 3566when not relaxing. The field is set to the value of the difference 3567assuming no relaxation. The relocation encodes the position of the 3568subtracted symbol so the linker can determine whether to adjust the field 3569value. PDIFF relocations are used for positive differences, NDIFF 3570relocations are used for negative differences. The difference value 3571is treated as unsigned with these relocation types, giving full 35728/16 value ranges. 3573@end deffn 3574@deffn {} BFD_RELOC_Z80_DISP8 35758 bit signed offset in (ix+d) or (iy+d). 3576@end deffn 3577@deffn {} BFD_RELOC_Z80_BYTE0 3578First 8 bits of multibyte (32, 24 or 16 bit) value. 3579@end deffn 3580@deffn {} BFD_RELOC_Z80_BYTE1 3581Second 8 bits of multibyte (32, 24 or 16 bit) value. 3582@end deffn 3583@deffn {} BFD_RELOC_Z80_BYTE2 3584Third 8 bits of multibyte (32 or 24 bit) value. 3585@end deffn 3586@deffn {} BFD_RELOC_Z80_BYTE3 3587Fourth 8 bits of multibyte (32 bit) value. 3588@end deffn 3589@deffn {} BFD_RELOC_Z80_WORD0 3590Lowest 16 bits of multibyte (32 or 24 bit) value. 3591@end deffn 3592@deffn {} BFD_RELOC_Z80_WORD1 3593Highest 16 bits of multibyte (32 or 24 bit) value. 3594@end deffn 3595@deffn {} BFD_RELOC_Z80_16_BE 3596Like BFD_RELOC_16 but big-endian. 3597@end deffn 3598@deffn {} BFD_RELOC_Z8K_DISP7 3599DJNZ offset. 3600@end deffn 3601@deffn {} BFD_RELOC_Z8K_CALLR 3602CALR offset. 3603@end deffn 3604@deffn {} BFD_RELOC_Z8K_IMM4L 36054 bit value. 3606@end deffn 3607@deffn {} BFD_RELOC_LM32_CALL 3608@deffnx {} BFD_RELOC_LM32_BRANCH 3609@deffnx {} BFD_RELOC_LM32_16_GOT 3610@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3611@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3612@deffnx {} BFD_RELOC_LM32_COPY 3613@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3614@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3615@deffnx {} BFD_RELOC_LM32_RELATIVE 3616Lattice Mico32 relocations. 3617@end deffn 3618@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3619Difference between two section addreses. Must be followed by a 3620BFD_RELOC_MACH_O_PAIR. 3621@end deffn 3622@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3623Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3624@end deffn 3625@deffn {} BFD_RELOC_MACH_O_PAIR 3626Pair of relocation. Contains the first symbol. 3627@end deffn 3628@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3629Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3630@end deffn 3631@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3632Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3633@end deffn 3634@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3635@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3636PCREL relocations. They are marked as branch to create PLT entry if 3637required. 3638@end deffn 3639@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3640Used when referencing a GOT entry. 3641@end deffn 3642@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3643Used when loading a GOT entry with movq. It is specially marked so that 3644the linker could optimize the movq to a leaq if possible. 3645@end deffn 3646@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3647Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3648@end deffn 3649@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3650Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3651@end deffn 3652@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3653Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3654@end deffn 3655@deffn {} BFD_RELOC_MACH_O_X86_64_TLV 3656Used when referencing a TLV entry. 3657@end deffn 3658@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3659Addend for PAGE or PAGEOFF. 3660@end deffn 3661@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3662Relative offset to page of GOT slot. 3663@end deffn 3664@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3665Relative offset within page of GOT slot. 3666@end deffn 3667@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3668Address of a GOT entry. 3669@end deffn 3670@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3671This is a 32 bit reloc for the microblaze that stores the 3672low 16 bits of a value 3673@end deffn 3674@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3675This is a 32 bit pc-relative reloc for the microblaze that 3676stores the low 16 bits of a value 3677@end deffn 3678@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3679This is a 32 bit reloc for the microblaze that stores a 3680value relative to the read-only small data area anchor 3681@end deffn 3682@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3683This is a 32 bit reloc for the microblaze that stores a 3684value relative to the read-write small data area anchor 3685@end deffn 3686@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3687This is a 32 bit reloc for the microblaze to handle 3688expressions of the form "Symbol Op Symbol" 3689@end deffn 3690@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3691This is a 64 bit reloc that stores the 32 bit pc relative 3692value in two words (with an imm instruction). No relocation is 3693done here - only used for relaxing 3694@end deffn 3695@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3696This is a 64 bit reloc that stores the 32 bit pc relative 3697value in two words (with an imm instruction). The relocation is 3698PC-relative GOT offset 3699@end deffn 3700@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3701This is a 64 bit reloc that stores the 32 bit pc relative 3702value in two words (with an imm instruction). The relocation is 3703GOT offset 3704@end deffn 3705@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3706This is a 64 bit reloc that stores the 32 bit pc relative 3707value in two words (with an imm instruction). The relocation is 3708PC-relative offset into PLT 3709@end deffn 3710@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3711This is a 64 bit reloc that stores the 32 bit GOT relative 3712value in two words (with an imm instruction). The relocation is 3713relative offset from _GLOBAL_OFFSET_TABLE_ 3714@end deffn 3715@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3716This is a 32 bit reloc that stores the 32 bit GOT relative 3717value in a word. The relocation is relative offset from 3718@end deffn 3719@deffn {} BFD_RELOC_MICROBLAZE_COPY 3720This is used to tell the dynamic linker to copy the value out of 3721the dynamic object into the runtime process image. 3722@end deffn 3723@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3724Unused Reloc 3725@end deffn 3726@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3727This is a 64 bit reloc that stores the 32 bit GOT relative value 3728of the GOT TLS GD info entry in two words (with an imm instruction). The 3729relocation is GOT offset. 3730@end deffn 3731@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3732This is a 64 bit reloc that stores the 32 bit GOT relative value 3733of the GOT TLS LD info entry in two words (with an imm instruction). The 3734relocation is GOT offset. 3735@end deffn 3736@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3737This is a 32 bit reloc that stores the Module ID to GOT(n). 3738@end deffn 3739@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3740This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3741@end deffn 3742@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3743This is a 32 bit reloc for storing TLS offset to two words (uses imm 3744instruction) 3745@end deffn 3746@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3747This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3748to two words (uses imm instruction). 3749@end deffn 3750@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3751This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3752to two words (uses imm instruction). 3753@end deffn 3754@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTPCREL 3755This is a 64 bit reloc that stores the 32 bit pc relative 3756value in two words (with an imm instruction). The relocation is 3757PC-relative offset from start of TEXT. 3758@end deffn 3759@deffn {} BFD_RELOC_MICROBLAZE_64_TEXTREL 3760This is a 64 bit reloc that stores the 32 bit offset 3761value in two words (with an imm instruction). The relocation is 3762relative offset from start of TEXT. 3763@end deffn 3764@deffn {} BFD_RELOC_AARCH64_RELOC_START 3765AArch64 pseudo relocation code to mark the start of the AArch64 3766relocation enumerators. N.B. the order of the enumerators is 3767important as several tables in the AArch64 bfd backend are indexed 3768by these enumerators; make sure they are all synced. 3769@end deffn 3770@deffn {} BFD_RELOC_AARCH64_NULL 3771Deprecated AArch64 null relocation code. 3772@end deffn 3773@deffn {} BFD_RELOC_AARCH64_NONE 3774AArch64 null relocation code. 3775@end deffn 3776@deffn {} BFD_RELOC_AARCH64_64 3777@deffnx {} BFD_RELOC_AARCH64_32 3778@deffnx {} BFD_RELOC_AARCH64_16 3779Basic absolute relocations of N bits. These are equivalent to 3780BFD_RELOC_N and they were added to assist the indexing of the howto 3781table. 3782@end deffn 3783@deffn {} BFD_RELOC_AARCH64_64_PCREL 3784@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3785@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3786PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3787and they were added to assist the indexing of the howto table. 3788@end deffn 3789@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3790AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3791of an unsigned address/value. 3792@end deffn 3793@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3794AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3795an address/value. No overflow checking. 3796@end deffn 3797@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3798AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3799of an unsigned address/value. 3800@end deffn 3801@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3802AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3803of an address/value. No overflow checking. 3804@end deffn 3805@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3806AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3807of an unsigned address/value. 3808@end deffn 3809@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3810AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3811of an address/value. No overflow checking. 3812@end deffn 3813@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3814AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3815of a signed or unsigned address/value. 3816@end deffn 3817@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3818AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3819of a signed value. Changes instruction to MOVZ or MOVN depending on the 3820value's sign. 3821@end deffn 3822@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3823AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3824of a signed value. Changes instruction to MOVZ or MOVN depending on the 3825value's sign. 3826@end deffn 3827@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3828AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3829of a signed value. Changes instruction to MOVZ or MOVN depending on the 3830value's sign. 3831@end deffn 3832@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0 3833AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3834of a signed value. Changes instruction to MOVZ or MOVN depending on the 3835value's sign. 3836@end deffn 3837@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0_NC 3838AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3839of a signed value. Changes instruction to MOVZ or MOVN depending on the 3840value's sign. 3841@end deffn 3842@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1 3843AArch64 MOVK instruction with most significant bits 16 to 31 3844of a signed value. 3845@end deffn 3846@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1_NC 3847AArch64 MOVK instruction with most significant bits 16 to 31 3848of a signed value. 3849@end deffn 3850@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2 3851AArch64 MOVK instruction with most significant bits 32 to 47 3852of a signed value. 3853@end deffn 3854@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2_NC 3855AArch64 MOVK instruction with most significant bits 32 to 47 3856of a signed value. 3857@end deffn 3858@deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G3 3859AArch64 MOVK instruction with most significant bits 47 to 63 3860of a signed value. 3861@end deffn 3862@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3863AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3864offset. The lowest two bits must be zero and are not stored in the 3865instruction, giving a 21 bit signed byte offset. 3866@end deffn 3867@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3868AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3869@end deffn 3870@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3871AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3872offset, giving a 4KB aligned page base address. 3873@end deffn 3874@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3875AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3876offset, giving a 4KB aligned page base address, but with no overflow 3877checking. 3878@end deffn 3879@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3880AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3881Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3882@end deffn 3883@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3884AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3885address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3886@end deffn 3887@deffn {} BFD_RELOC_AARCH64_TSTBR14 3888AArch64 14 bit pc-relative test bit and branch. 3889The lowest two bits must be zero and are not stored in the instruction, 3890giving a 16 bit signed byte offset. 3891@end deffn 3892@deffn {} BFD_RELOC_AARCH64_BRANCH19 3893AArch64 19 bit pc-relative conditional branch and compare & branch. 3894The lowest two bits must be zero and are not stored in the instruction, 3895giving a 21 bit signed byte offset. 3896@end deffn 3897@deffn {} BFD_RELOC_AARCH64_JUMP26 3898AArch64 26 bit pc-relative unconditional branch. 3899The lowest two bits must be zero and are not stored in the instruction, 3900giving a 28 bit signed byte offset. 3901@end deffn 3902@deffn {} BFD_RELOC_AARCH64_CALL26 3903AArch64 26 bit pc-relative unconditional branch and link. 3904The lowest two bits must be zero and are not stored in the instruction, 3905giving a 28 bit signed byte offset. 3906@end deffn 3907@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3908AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3909address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3910@end deffn 3911@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3912AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3913address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3914@end deffn 3915@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3916AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3917address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3918@end deffn 3919@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3920AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3921address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3922@end deffn 3923@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3924AArch64 Load Literal instruction, holding a 19 bit PC relative word 3925offset of the global offset table entry for a symbol. The lowest two 3926bits must be zero and are not stored in the instruction, giving a 21 3927bit signed byte offset. This relocation type requires signed overflow 3928checking. 3929@end deffn 3930@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3931Get to the page base of the global offset table entry for a symbol as 3932part of an ADRP instruction using a 21 bit PC relative value.Used in 3933conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3934@end deffn 3935@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3936Unsigned 12 bit byte offset for 64 bit load/store from the page of 3937the GOT entry for this symbol. Used in conjunction with 3938BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3939@end deffn 3940@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3941Unsigned 12 bit byte offset for 32 bit load/store from the page of 3942the GOT entry for this symbol. Used in conjunction with 3943BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3944@end deffn 3945@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3946Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3947for this symbol. Valid in LP64 ABI only. 3948@end deffn 3949@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3950Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3951for this symbol. Valid in LP64 ABI only. 3952@end deffn 3953@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3954Unsigned 15 bit byte offset for 64 bit load/store from the page of 3955the GOT entry for this symbol. Valid in LP64 ABI only. 3956@end deffn 3957@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3958Scaled 14 bit byte offset to the page base of the global offset table. 3959@end deffn 3960@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3961Scaled 15 bit byte offset to the page base of the global offset table. 3962@end deffn 3963@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3964Get to the page base of the global offset table entry for a symbols 3965tls_index structure as part of an adrp instruction using a 21 bit PC 3966relative value. Used in conjunction with 3967BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3968@end deffn 3969@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3970AArch64 TLS General Dynamic 3971@end deffn 3972@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3973Unsigned 12 bit byte offset to global offset table entry for a symbols 3974tls_index structure. Used in conjunction with 3975BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3976@end deffn 3977@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3978AArch64 TLS General Dynamic relocation. 3979@end deffn 3980@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3981AArch64 TLS General Dynamic relocation. 3982@end deffn 3983@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3984AArch64 TLS INITIAL EXEC relocation. 3985@end deffn 3986@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3987AArch64 TLS INITIAL EXEC relocation. 3988@end deffn 3989@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3990AArch64 TLS INITIAL EXEC relocation. 3991@end deffn 3992@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3993AArch64 TLS INITIAL EXEC relocation. 3994@end deffn 3995@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3996AArch64 TLS INITIAL EXEC relocation. 3997@end deffn 3998@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3999AArch64 TLS INITIAL EXEC relocation. 4000@end deffn 4001@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 4002bit[23:12] of byte offset to module TLS base address. 4003@end deffn 4004@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 4005Unsigned 12 bit byte offset to module TLS base address. 4006@end deffn 4007@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 4008No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 4009@end deffn 4010@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 4011Unsigned 12 bit byte offset to global offset table entry for a symbols 4012tls_index structure. Used in conjunction with 4013BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 4014@end deffn 4015@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 4016GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 4017instruction. 4018@end deffn 4019@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 4020GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 4021@end deffn 4022@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 4023bit[11:1] of byte offset to module TLS base address, encoded in ldst 4024instructions. 4025@end deffn 4026@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 4027Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 4028@end deffn 4029@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 4030bit[11:2] of byte offset to module TLS base address, encoded in ldst 4031instructions. 4032@end deffn 4033@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 4034Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 4035@end deffn 4036@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 4037bit[11:3] of byte offset to module TLS base address, encoded in ldst 4038instructions. 4039@end deffn 4040@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 4041Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 4042@end deffn 4043@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 4044bit[11:0] of byte offset to module TLS base address, encoded in ldst 4045instructions. 4046@end deffn 4047@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 4048Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 4049@end deffn 4050@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4051bit[15:0] of byte offset to module TLS base address. 4052@end deffn 4053@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 4054No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4055@end deffn 4056@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4057bit[31:16] of byte offset to module TLS base address. 4058@end deffn 4059@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 4060No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4061@end deffn 4062@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 4063bit[47:32] of byte offset to module TLS base address. 4064@end deffn 4065@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 4066AArch64 TLS LOCAL EXEC relocation. 4067@end deffn 4068@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 4069AArch64 TLS LOCAL EXEC relocation. 4070@end deffn 4071@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 4072AArch64 TLS LOCAL EXEC relocation. 4073@end deffn 4074@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4075AArch64 TLS LOCAL EXEC relocation. 4076@end deffn 4077@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4078AArch64 TLS LOCAL EXEC relocation. 4079@end deffn 4080@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4081AArch64 TLS LOCAL EXEC relocation. 4082@end deffn 4083@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4084AArch64 TLS LOCAL EXEC relocation. 4085@end deffn 4086@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4087AArch64 TLS LOCAL EXEC relocation. 4088@end deffn 4089@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 4090bit[11:1] of byte offset to module TLS base address, encoded in ldst 4091instructions. 4092@end deffn 4093@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 4094Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check. 4095@end deffn 4096@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 4097bit[11:2] of byte offset to module TLS base address, encoded in ldst 4098instructions. 4099@end deffn 4100@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 4101Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check. 4102@end deffn 4103@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 4104bit[11:3] of byte offset to module TLS base address, encoded in ldst 4105instructions. 4106@end deffn 4107@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 4108Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check. 4109@end deffn 4110@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 4111bit[11:0] of byte offset to module TLS base address, encoded in ldst 4112instructions. 4113@end deffn 4114@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 4115Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check. 4116@end deffn 4117@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4118AArch64 TLS DESC relocation. 4119@end deffn 4120@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4121AArch64 TLS DESC relocation. 4122@end deffn 4123@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4124AArch64 TLS DESC relocation. 4125@end deffn 4126@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4127AArch64 TLS DESC relocation. 4128@end deffn 4129@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4130AArch64 TLS DESC relocation. 4131@end deffn 4132@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4133AArch64 TLS DESC relocation. 4134@end deffn 4135@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4136AArch64 TLS DESC relocation. 4137@end deffn 4138@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4139AArch64 TLS DESC relocation. 4140@end deffn 4141@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 4142AArch64 TLS DESC relocation. 4143@end deffn 4144@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 4145AArch64 TLS DESC relocation. 4146@end deffn 4147@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 4148AArch64 TLS DESC relocation. 4149@end deffn 4150@deffn {} BFD_RELOC_AARCH64_COPY 4151AArch64 TLS relocation. 4152@end deffn 4153@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 4154AArch64 TLS relocation. 4155@end deffn 4156@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 4157AArch64 TLS relocation. 4158@end deffn 4159@deffn {} BFD_RELOC_AARCH64_RELATIVE 4160AArch64 TLS relocation. 4161@end deffn 4162@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4163AArch64 TLS relocation. 4164@end deffn 4165@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 4166AArch64 TLS relocation. 4167@end deffn 4168@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 4169AArch64 TLS relocation. 4170@end deffn 4171@deffn {} BFD_RELOC_AARCH64_TLSDESC 4172AArch64 TLS relocation. 4173@end deffn 4174@deffn {} BFD_RELOC_AARCH64_IRELATIVE 4175AArch64 support for STT_GNU_IFUNC. 4176@end deffn 4177@deffn {} BFD_RELOC_AARCH64_RELOC_END 4178AArch64 pseudo relocation code to mark the end of the AArch64 4179relocation enumerators that have direct mapping to ELF reloc codes. 4180There are a few more enumerators after this one; those are mainly 4181used by the AArch64 assembler for the internal fixup or to select 4182one of the above enumerators. 4183@end deffn 4184@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4185AArch64 pseudo relocation code to be used internally by the AArch64 4186assembler and not (currently) written to any object files. 4187@end deffn 4188@deffn {} BFD_RELOC_AARCH64_LDST_LO12 4189AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4190address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4191@end deffn 4192@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4193AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 4194used internally by the AArch64 assembler and not (currently) written to 4195any object files. 4196@end deffn 4197@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4198Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 4199@end deffn 4200@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 4201AArch64 pseudo relocation code for TLS local exec mode. It's to be 4202used internally by the AArch64 assembler and not (currently) written to 4203any object files. 4204@end deffn 4205@deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC 4206Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check. 4207@end deffn 4208@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4209AArch64 pseudo relocation code to be used internally by the AArch64 4210assembler and not (currently) written to any object files. 4211@end deffn 4212@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4213AArch64 pseudo relocation code to be used internally by the AArch64 4214assembler and not (currently) written to any object files. 4215@end deffn 4216@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4217AArch64 pseudo relocation code to be used internally by the AArch64 4218assembler and not (currently) written to any object files. 4219@end deffn 4220@deffn {} BFD_RELOC_TILEPRO_COPY 4221@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4222@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4223@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4224@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4225@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4226@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4227@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4228@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4229@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4230@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4231@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4232@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4233@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4234@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4235@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4236@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4237@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4238@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4239@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4240@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4241@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4242@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4243@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4244@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4245@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4246@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4247@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4248@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4249@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4250@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4251@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4252@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4253@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4254@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4255@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4256@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4257@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4258@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4259@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4260@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4261@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4262@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4263@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4264@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4265@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4266@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4267@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4268@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4269@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4270@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4271@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4272@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4273@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4274@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4275@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4276@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4277@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4278@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4279@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4280@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4281@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4282@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4283@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4284@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4285@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4286@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4287@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4288@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4289@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4290@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4291@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4292@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4293@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4294@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4295@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4296@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4297@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4298@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4299Tilera TILEPro Relocations. 4300@end deffn 4301@deffn {} BFD_RELOC_TILEGX_HW0 4302@deffnx {} BFD_RELOC_TILEGX_HW1 4303@deffnx {} BFD_RELOC_TILEGX_HW2 4304@deffnx {} BFD_RELOC_TILEGX_HW3 4305@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4306@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4307@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4308@deffnx {} BFD_RELOC_TILEGX_COPY 4309@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4310@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4311@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4312@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4313@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4314@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4315@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4316@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4317@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4318@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4319@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4320@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4321@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4322@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4323@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4324@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4325@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4326@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4327@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4328@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4329@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4330@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4331@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4332@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4333@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4334@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4335@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4336@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4337@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4338@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4339@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4340@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4341@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4342@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4343@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4344@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4345@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4346@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4347@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4348@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4349@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4350@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4351@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4352@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4353@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4354@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4355@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4356@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4357@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4358@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4359@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4360@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4361@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4362@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4363@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4364@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4365@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4366@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4367@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4368@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4369@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4370@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4371@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4372@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4373@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4374@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4375@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4376@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4377@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4378@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4379@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4380@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4381@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4382@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4383@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4384@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4385@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4386@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4387@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4388@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4389@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4390@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4391@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4392@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4393@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4394@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4395@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4396@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4397@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4398@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4399@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4400@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4401@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4402@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4403@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4404@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4405@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4406@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4407@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4408@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4409@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4410Tilera TILE-Gx Relocations. 4411@end deffn 4412@deffn {} BFD_RELOC_BPF_64 4413@deffnx {} BFD_RELOC_BPF_32 4414@deffnx {} BFD_RELOC_BPF_16 4415@deffnx {} BFD_RELOC_BPF_DISP16 4416@deffnx {} BFD_RELOC_BPF_DISP32 4417Linux eBPF relocations. 4418@end deffn 4419@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4420Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4421@end deffn 4422@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4423Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4424@end deffn 4425@deffn {} BFD_RELOC_EPIPHANY_HIGH 4426Adapteva EPIPHANY - 16 most-significant bits of absolute address 4427@end deffn 4428@deffn {} BFD_RELOC_EPIPHANY_LOW 4429Adapteva EPIPHANY - 16 least-significant bits of absolute address 4430@end deffn 4431@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4432Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4433@end deffn 4434@deffn {} BFD_RELOC_EPIPHANY_IMM11 4435Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4436@end deffn 4437@deffn {} BFD_RELOC_EPIPHANY_IMM8 4438Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4439@end deffn 4440@deffn {} BFD_RELOC_VISIUM_HI16 4441@deffnx {} BFD_RELOC_VISIUM_LO16 4442@deffnx {} BFD_RELOC_VISIUM_IM16 4443@deffnx {} BFD_RELOC_VISIUM_REL16 4444@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4445@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4446@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4447Visium Relocations. 4448@end deffn 4449@deffn {} BFD_RELOC_WASM32_LEB128 4450@deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4451@deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4452@deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4453@deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4454@deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4455@deffnx {} BFD_RELOC_WASM32_COPY 4456@deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4457@deffnx {} BFD_RELOC_WASM32_INDEX 4458@deffnx {} BFD_RELOC_WASM32_PLT_SIG 4459WebAssembly relocations. 4460@end deffn 4461@deffn {} BFD_RELOC_CKCORE_NONE 4462@deffnx {} BFD_RELOC_CKCORE_ADDR32 4463@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM8BY4 4464@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM11BY2 4465@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM4BY2 4466@deffnx {} BFD_RELOC_CKCORE_PCREL32 4467@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2 4468@deffnx {} BFD_RELOC_CKCORE_GNU_VTINHERIT 4469@deffnx {} BFD_RELOC_CKCORE_GNU_VTENTRY 4470@deffnx {} BFD_RELOC_CKCORE_RELATIVE 4471@deffnx {} BFD_RELOC_CKCORE_COPY 4472@deffnx {} BFD_RELOC_CKCORE_GLOB_DAT 4473@deffnx {} BFD_RELOC_CKCORE_JUMP_SLOT 4474@deffnx {} BFD_RELOC_CKCORE_GOTOFF 4475@deffnx {} BFD_RELOC_CKCORE_GOTPC 4476@deffnx {} BFD_RELOC_CKCORE_GOT32 4477@deffnx {} BFD_RELOC_CKCORE_PLT32 4478@deffnx {} BFD_RELOC_CKCORE_ADDRGOT 4479@deffnx {} BFD_RELOC_CKCORE_ADDRPLT 4480@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM26BY2 4481@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY2 4482@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY4 4483@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY2 4484@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY4 4485@deffnx {} BFD_RELOC_CKCORE_ADDR_HI16 4486@deffnx {} BFD_RELOC_CKCORE_ADDR_LO16 4487@deffnx {} BFD_RELOC_CKCORE_GOTPC_HI16 4488@deffnx {} BFD_RELOC_CKCORE_GOTPC_LO16 4489@deffnx {} BFD_RELOC_CKCORE_GOTOFF_HI16 4490@deffnx {} BFD_RELOC_CKCORE_GOTOFF_LO16 4491@deffnx {} BFD_RELOC_CKCORE_GOT12 4492@deffnx {} BFD_RELOC_CKCORE_GOT_HI16 4493@deffnx {} BFD_RELOC_CKCORE_GOT_LO16 4494@deffnx {} BFD_RELOC_CKCORE_PLT12 4495@deffnx {} BFD_RELOC_CKCORE_PLT_HI16 4496@deffnx {} BFD_RELOC_CKCORE_PLT_LO16 4497@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_HI16 4498@deffnx {} BFD_RELOC_CKCORE_ADDRGOT_LO16 4499@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_HI16 4500@deffnx {} BFD_RELOC_CKCORE_ADDRPLT_LO16 4501@deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2 4502@deffnx {} BFD_RELOC_CKCORE_TOFFSET_LO16 4503@deffnx {} BFD_RELOC_CKCORE_DOFFSET_LO16 4504@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM18BY2 4505@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18 4506@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 4507@deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 4508@deffnx {} BFD_RELOC_CKCORE_GOTOFF_IMM18 4509@deffnx {} BFD_RELOC_CKCORE_GOT_IMM18BY4 4510@deffnx {} BFD_RELOC_CKCORE_PLT_IMM18BY4 4511@deffnx {} BFD_RELOC_CKCORE_PCREL_IMM7BY4 4512@deffnx {} BFD_RELOC_CKCORE_TLS_LE32 4513@deffnx {} BFD_RELOC_CKCORE_TLS_IE32 4514@deffnx {} BFD_RELOC_CKCORE_TLS_GD32 4515@deffnx {} BFD_RELOC_CKCORE_TLS_LDM32 4516@deffnx {} BFD_RELOC_CKCORE_TLS_LDO32 4517@deffnx {} BFD_RELOC_CKCORE_TLS_DTPMOD32 4518@deffnx {} BFD_RELOC_CKCORE_TLS_DTPOFF32 4519@deffnx {} BFD_RELOC_CKCORE_TLS_TPOFF32 4520@deffnx {} BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 4521@deffnx {} BFD_RELOC_CKCORE_NOJSRI 4522@deffnx {} BFD_RELOC_CKCORE_CALLGRAPH 4523@deffnx {} BFD_RELOC_CKCORE_IRELATIVE 4524@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4 4525@deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4 4526C-SKY relocations. 4527@end deffn 4528@deffn {} BFD_RELOC_S12Z_OPR 4529S12Z relocations. 4530@end deffn 4531@deffn {} BFD_RELOC_LARCH_TLS_DTPMOD32 4532@deffnx {} BFD_RELOC_LARCH_TLS_DTPREL32 4533@deffnx {} BFD_RELOC_LARCH_TLS_DTPMOD64 4534@deffnx {} BFD_RELOC_LARCH_TLS_DTPREL64 4535@deffnx {} BFD_RELOC_LARCH_TLS_TPREL32 4536@deffnx {} BFD_RELOC_LARCH_TLS_TPREL64 4537@deffnx {} BFD_RELOC_LARCH_MARK_LA 4538@deffnx {} BFD_RELOC_LARCH_MARK_PCREL 4539@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PCREL 4540@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE 4541@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_DUP 4542@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_GPREL 4543@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL 4544@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT 4545@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GD 4546@deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL 4547@deffnx {} BFD_RELOC_LARCH_SOP_ASSERT 4548@deffnx {} BFD_RELOC_LARCH_SOP_NOT 4549@deffnx {} BFD_RELOC_LARCH_SOP_SUB 4550@deffnx {} BFD_RELOC_LARCH_SOP_SL 4551@deffnx {} BFD_RELOC_LARCH_SOP_SR 4552@deffnx {} BFD_RELOC_LARCH_SOP_ADD 4553@deffnx {} BFD_RELOC_LARCH_SOP_AND 4554@deffnx {} BFD_RELOC_LARCH_SOP_IF_ELSE 4555@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_5 4556@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U_10_12 4557@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_12 4558@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16 4559@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2 4560@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_5_20 4561@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2 4562@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2 4563@deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U 4564@deffnx {} BFD_RELOC_LARCH_ADD8 4565@deffnx {} BFD_RELOC_LARCH_ADD16 4566@deffnx {} BFD_RELOC_LARCH_ADD24 4567@deffnx {} BFD_RELOC_LARCH_ADD32 4568@deffnx {} BFD_RELOC_LARCH_ADD64 4569@deffnx {} BFD_RELOC_LARCH_SUB8 4570@deffnx {} BFD_RELOC_LARCH_SUB16 4571@deffnx {} BFD_RELOC_LARCH_SUB24 4572@deffnx {} BFD_RELOC_LARCH_SUB32 4573@deffnx {} BFD_RELOC_LARCH_SUB64 4574LARCH relocations. 4575@end deffn 4576 4577@example 4578 4579typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4580@end example 4581@findex bfd_reloc_type_lookup 4582@subsubsection @code{bfd_reloc_type_lookup} 4583@strong{Synopsis} 4584@example 4585reloc_howto_type *bfd_reloc_type_lookup 4586 (bfd *abfd, bfd_reloc_code_real_type code); 4587reloc_howto_type *bfd_reloc_name_lookup 4588 (bfd *abfd, const char *reloc_name); 4589@end example 4590@strong{Description}@* 4591Return a pointer to a howto structure which, when 4592invoked, will perform the relocation @var{code} on data from the 4593architecture noted. 4594 4595@findex bfd_default_reloc_type_lookup 4596@subsubsection @code{bfd_default_reloc_type_lookup} 4597@strong{Synopsis} 4598@example 4599reloc_howto_type *bfd_default_reloc_type_lookup 4600 (bfd *abfd, bfd_reloc_code_real_type code); 4601@end example 4602@strong{Description}@* 4603Provides a default relocation lookup routine for any architecture. 4604 4605@findex bfd_get_reloc_code_name 4606@subsubsection @code{bfd_get_reloc_code_name} 4607@strong{Synopsis} 4608@example 4609const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4610@end example 4611@strong{Description}@* 4612Provides a printable name for the supplied relocation code. 4613Useful mainly for printing error messages. 4614 4615@findex bfd_generic_relax_section 4616@subsubsection @code{bfd_generic_relax_section} 4617@strong{Synopsis} 4618@example 4619bool bfd_generic_relax_section 4620 (bfd *abfd, 4621 asection *section, 4622 struct bfd_link_info *, 4623 bool *); 4624@end example 4625@strong{Description}@* 4626Provides default handling for relaxing for back ends which 4627don't do relaxing. 4628 4629@findex bfd_generic_gc_sections 4630@subsubsection @code{bfd_generic_gc_sections} 4631@strong{Synopsis} 4632@example 4633bool bfd_generic_gc_sections 4634 (bfd *, struct bfd_link_info *); 4635@end example 4636@strong{Description}@* 4637Provides default handling for relaxing for back ends which 4638don't do section gc -- i.e., does nothing. 4639 4640@findex bfd_generic_lookup_section_flags 4641@subsubsection @code{bfd_generic_lookup_section_flags} 4642@strong{Synopsis} 4643@example 4644bool bfd_generic_lookup_section_flags 4645 (struct bfd_link_info *, struct flag_info *, asection *); 4646@end example 4647@strong{Description}@* 4648Provides default handling for section flags lookup 4649-- i.e., does nothing. 4650Returns FALSE if the section should be omitted, otherwise TRUE. 4651 4652@findex bfd_generic_merge_sections 4653@subsubsection @code{bfd_generic_merge_sections} 4654@strong{Synopsis} 4655@example 4656bool bfd_generic_merge_sections 4657 (bfd *, struct bfd_link_info *); 4658@end example 4659@strong{Description}@* 4660Provides default handling for SEC_MERGE section merging for back ends 4661which don't have SEC_MERGE support -- i.e., does nothing. 4662 4663@findex bfd_generic_get_relocated_section_contents 4664@subsubsection @code{bfd_generic_get_relocated_section_contents} 4665@strong{Synopsis} 4666@example 4667bfd_byte *bfd_generic_get_relocated_section_contents 4668 (bfd *abfd, 4669 struct bfd_link_info *link_info, 4670 struct bfd_link_order *link_order, 4671 bfd_byte *data, 4672 bool relocatable, 4673 asymbol **symbols); 4674@end example 4675@strong{Description}@* 4676Provides default handling of relocation effort for back ends 4677which can't be bothered to do it efficiently. 4678 4679@findex _bfd_generic_set_reloc 4680@subsubsection @code{_bfd_generic_set_reloc} 4681@strong{Synopsis} 4682@example 4683void _bfd_generic_set_reloc 4684 (bfd *abfd, 4685 sec_ptr section, 4686 arelent **relptr, 4687 unsigned int count); 4688@end example 4689@strong{Description}@* 4690Installs a new set of internal relocations in SECTION. 4691 4692@findex _bfd_unrecognized_reloc 4693@subsubsection @code{_bfd_unrecognized_reloc} 4694@strong{Synopsis} 4695@example 4696bool _bfd_unrecognized_reloc 4697 (bfd * abfd, 4698 sec_ptr section, 4699 unsigned int r_type); 4700@end example 4701@strong{Description}@* 4702Reports an unrecognized reloc. 4703Written as a function in order to reduce code duplication. 4704Returns FALSE so that it can be called from a return statement. 4705 4706