reloc.texi revision 1.5
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* The relocation is relative to the field being relocated. */ 285 bfd_boolean pc_relative; 286 287 /* The bit position of the reloc value in the destination. 288 The relocated value is left shifted by this amount. */ 289 unsigned int bitpos; 290 291 /* What type of overflow error should be checked for when 292 relocating. */ 293 enum complain_overflow complain_on_overflow; 294 295 /* If this field is non null, then the supplied function is 296 called rather than the normal function. This allows really 297 strange relocation methods to be accommodated (e.g., i960 callj 298 instructions). */ 299 bfd_reloc_status_type (*special_function) 300 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 301 bfd *, char **); 302 303 /* The textual name of the relocation type. */ 304 char *name; 305 306 /* Some formats record a relocation addend in the section contents 307 rather than with the relocation. For ELF formats this is the 308 distinction between USE_REL and USE_RELA (though the code checks 309 for USE_REL == 1/0). The value of this field is TRUE if the 310 addend is recorded with the section contents; when performing a 311 partial link (ld -r) the section contents (the data) will be 312 modified. The value of this field is FALSE if addends are 313 recorded with the relocation (in arelent.addend); when performing 314 a partial link the relocation will be modified. 315 All relocations for all ELF USE_RELA targets should set this field 316 to FALSE (values of TRUE should be looked on with suspicion). 317 However, the converse is not true: not all relocations of all ELF 318 USE_REL targets set this field to TRUE. Why this is so is peculiar 319 to each particular target. For relocs that aren't used in partial 320 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 321 bfd_boolean partial_inplace; 322 323 /* src_mask selects the part of the instruction (or data) to be used 324 in the relocation sum. If the target relocations don't have an 325 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 326 dst_mask to extract the addend from the section contents. If 327 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 328 field should be zero. Non-zero values for ELF USE_RELA targets are 329 bogus as in those cases the value in the dst_mask part of the 330 section contents should be treated as garbage. */ 331 bfd_vma src_mask; 332 333 /* dst_mask selects which parts of the instruction (or data) are 334 replaced with a relocated value. */ 335 bfd_vma dst_mask; 336 337 /* When some formats create PC relative instructions, they leave 338 the value of the pc of the place being relocated in the offset 339 slot of the instruction, so that a PC relative relocation can 340 be made just by adding in an ordinary offset (e.g., sun3 a.out). 341 Some formats leave the displacement part of an instruction 342 empty (e.g., m88k bcs); this flag signals the fact. */ 343 bfd_boolean pcrel_offset; 344@}; 345 346@end example 347@findex The HOWTO Macro 348@subsubsection @code{The HOWTO Macro} 349@strong{Description}@* 350The HOWTO define is horrible and will go away. 351@example 352#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 353 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 354@end example 355 356@strong{Description}@* 357And will be replaced with the totally magic way. But for the 358moment, we are compatible, so do it this way. 359@example 360#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 361 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 362 NAME, FALSE, 0, 0, IN) 363 364@end example 365 366@strong{Description}@* 367This is used to fill in an empty howto entry in an array. 368@example 369#define EMPTY_HOWTO(C) \ 370 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 371 NULL, FALSE, 0, 0, FALSE) 372 373@end example 374 375@strong{Description}@* 376Helper routine to turn a symbol into a relocation value. 377@example 378#define HOWTO_PREPARE(relocation, symbol) \ 379 @{ \ 380 if (symbol != NULL) \ 381 @{ \ 382 if (bfd_is_com_section (symbol->section)) \ 383 @{ \ 384 relocation = 0; \ 385 @} \ 386 else \ 387 @{ \ 388 relocation = symbol->value; \ 389 @} \ 390 @} \ 391 @} 392 393@end example 394 395@findex bfd_get_reloc_size 396@subsubsection @code{bfd_get_reloc_size} 397@strong{Synopsis} 398@example 399unsigned int bfd_get_reloc_size (reloc_howto_type *); 400@end example 401@strong{Description}@* 402For a reloc_howto_type that operates on a fixed number of bytes, 403this returns the number of bytes operated on. 404 405@findex arelent_chain 406@subsubsection @code{arelent_chain} 407@strong{Description}@* 408How relocs are tied together in an @code{asection}: 409@example 410typedef struct relent_chain 411@{ 412 arelent relent; 413 struct relent_chain *next; 414@} 415arelent_chain; 416 417@end example 418 419@findex bfd_check_overflow 420@subsubsection @code{bfd_check_overflow} 421@strong{Synopsis} 422@example 423bfd_reloc_status_type bfd_check_overflow 424 (enum complain_overflow how, 425 unsigned int bitsize, 426 unsigned int rightshift, 427 unsigned int addrsize, 428 bfd_vma relocation); 429@end example 430@strong{Description}@* 431Perform overflow checking on @var{relocation} which has 432@var{bitsize} significant bits and will be shifted right by 433@var{rightshift} bits, on a machine with addresses containing 434@var{addrsize} significant bits. The result is either of 435@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 436 437@findex bfd_perform_relocation 438@subsubsection @code{bfd_perform_relocation} 439@strong{Synopsis} 440@example 441bfd_reloc_status_type bfd_perform_relocation 442 (bfd *abfd, 443 arelent *reloc_entry, 444 void *data, 445 asection *input_section, 446 bfd *output_bfd, 447 char **error_message); 448@end example 449@strong{Description}@* 450If @var{output_bfd} is supplied to this function, the 451generated image will be relocatable; the relocations are 452copied to the output file after they have been changed to 453reflect the new state of the world. There are two ways of 454reflecting the results of partial linkage in an output file: 455by modifying the output data in place, and by modifying the 456relocation record. Some native formats (e.g., basic a.out and 457basic coff) have no way of specifying an addend in the 458relocation type, so the addend has to go in the output data. 459This is no big deal since in these formats the output data 460slot will always be big enough for the addend. Complex reloc 461types with addends were invented to solve just this problem. 462The @var{error_message} argument is set to an error message if 463this return @code{bfd_reloc_dangerous}. 464 465@findex bfd_install_relocation 466@subsubsection @code{bfd_install_relocation} 467@strong{Synopsis} 468@example 469bfd_reloc_status_type bfd_install_relocation 470 (bfd *abfd, 471 arelent *reloc_entry, 472 void *data, bfd_vma data_start, 473 asection *input_section, 474 char **error_message); 475@end example 476@strong{Description}@* 477This looks remarkably like @code{bfd_perform_relocation}, except it 478does not expect that the section contents have been filled in. 479I.e., it's suitable for use when creating, rather than applying 480a relocation. 481 482For now, this function should be considered reserved for the 483assembler. 484 485 486@node howto manager, , typedef arelent, Relocations 487@subsection The howto manager 488When an application wants to create a relocation, but doesn't 489know what the target machine might call it, it can find out by 490using this bit of code. 491 492@findex bfd_reloc_code_type 493@subsubsection @code{bfd_reloc_code_type} 494@strong{Description}@* 495The insides of a reloc code. The idea is that, eventually, there 496will be one enumerator for every type of relocation we ever do. 497Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 498return a howto pointer. 499 500This does mean that the application must determine the correct 501enumerator value; you can't get a howto pointer from a random set 502of attributes. 503 504Here are the possible values for @code{enum bfd_reloc_code_real}: 505 506@deffn {} BFD_RELOC_64 507@deffnx {} BFD_RELOC_32 508@deffnx {} BFD_RELOC_26 509@deffnx {} BFD_RELOC_24 510@deffnx {} BFD_RELOC_16 511@deffnx {} BFD_RELOC_14 512@deffnx {} BFD_RELOC_8 513Basic absolute relocations of N bits. 514@end deffn 515@deffn {} BFD_RELOC_64_PCREL 516@deffnx {} BFD_RELOC_32_PCREL 517@deffnx {} BFD_RELOC_24_PCREL 518@deffnx {} BFD_RELOC_16_PCREL 519@deffnx {} BFD_RELOC_12_PCREL 520@deffnx {} BFD_RELOC_8_PCREL 521PC-relative relocations. Sometimes these are relative to the address 522of the relocation itself; sometimes they are relative to the start of 523the section containing the relocation. It depends on the specific target. 524 525The 24-bit relocation is used in some Intel 960 configurations. 526@end deffn 527@deffn {} BFD_RELOC_32_SECREL 528Section relative relocations. Some targets need this for DWARF2. 529@end deffn 530@deffn {} BFD_RELOC_32_GOT_PCREL 531@deffnx {} BFD_RELOC_16_GOT_PCREL 532@deffnx {} BFD_RELOC_8_GOT_PCREL 533@deffnx {} BFD_RELOC_32_GOTOFF 534@deffnx {} BFD_RELOC_16_GOTOFF 535@deffnx {} BFD_RELOC_LO16_GOTOFF 536@deffnx {} BFD_RELOC_HI16_GOTOFF 537@deffnx {} BFD_RELOC_HI16_S_GOTOFF 538@deffnx {} BFD_RELOC_8_GOTOFF 539@deffnx {} BFD_RELOC_64_PLT_PCREL 540@deffnx {} BFD_RELOC_32_PLT_PCREL 541@deffnx {} BFD_RELOC_24_PLT_PCREL 542@deffnx {} BFD_RELOC_16_PLT_PCREL 543@deffnx {} BFD_RELOC_8_PLT_PCREL 544@deffnx {} BFD_RELOC_64_PLTOFF 545@deffnx {} BFD_RELOC_32_PLTOFF 546@deffnx {} BFD_RELOC_16_PLTOFF 547@deffnx {} BFD_RELOC_LO16_PLTOFF 548@deffnx {} BFD_RELOC_HI16_PLTOFF 549@deffnx {} BFD_RELOC_HI16_S_PLTOFF 550@deffnx {} BFD_RELOC_8_PLTOFF 551For ELF. 552@end deffn 553@deffn {} BFD_RELOC_SIZE32 554@deffnx {} BFD_RELOC_SIZE64 555Size relocations. 556@end deffn 557@deffn {} BFD_RELOC_68K_GLOB_DAT 558@deffnx {} BFD_RELOC_68K_JMP_SLOT 559@deffnx {} BFD_RELOC_68K_RELATIVE 560@deffnx {} BFD_RELOC_68K_TLS_GD32 561@deffnx {} BFD_RELOC_68K_TLS_GD16 562@deffnx {} BFD_RELOC_68K_TLS_GD8 563@deffnx {} BFD_RELOC_68K_TLS_LDM32 564@deffnx {} BFD_RELOC_68K_TLS_LDM16 565@deffnx {} BFD_RELOC_68K_TLS_LDM8 566@deffnx {} BFD_RELOC_68K_TLS_LDO32 567@deffnx {} BFD_RELOC_68K_TLS_LDO16 568@deffnx {} BFD_RELOC_68K_TLS_LDO8 569@deffnx {} BFD_RELOC_68K_TLS_IE32 570@deffnx {} BFD_RELOC_68K_TLS_IE16 571@deffnx {} BFD_RELOC_68K_TLS_IE8 572@deffnx {} BFD_RELOC_68K_TLS_LE32 573@deffnx {} BFD_RELOC_68K_TLS_LE16 574@deffnx {} BFD_RELOC_68K_TLS_LE8 575Relocations used by 68K ELF. 576@end deffn 577@deffn {} BFD_RELOC_VAX_GLOB_DAT 578@deffnx {} BFD_RELOC_VAX_GLOB_REF 579@deffnx {} BFD_RELOC_VAX_JMP_SLOT 580@deffnx {} BFD_RELOC_VAX_RELATIVE 581Relocations used by VAX ELF. 582@end deffn 583@deffn {} BFD_RELOC_32_BASEREL 584@deffnx {} BFD_RELOC_16_BASEREL 585@deffnx {} BFD_RELOC_LO16_BASEREL 586@deffnx {} BFD_RELOC_HI16_BASEREL 587@deffnx {} BFD_RELOC_HI16_S_BASEREL 588@deffnx {} BFD_RELOC_8_BASEREL 589@deffnx {} BFD_RELOC_RVA 590Linkage-table relative. 591@end deffn 592@deffn {} BFD_RELOC_8_FFnn 593Absolute 8-bit relocation, but used to form an address like 0xFFnn. 594@end deffn 595@deffn {} BFD_RELOC_32_PCREL_S2 596@deffnx {} BFD_RELOC_16_PCREL_S2 597@deffnx {} BFD_RELOC_23_PCREL_S2 598These PC-relative relocations are stored as word displacements -- 599i.e., byte displacements shifted right two bits. The 30-bit word 600displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 601SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 602signed 16-bit displacement is used on the MIPS, and the 23-bit 603displacement is used on the Alpha. 604@end deffn 605@deffn {} BFD_RELOC_HI22 606@deffnx {} BFD_RELOC_LO10 607High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 608the target word. These are used on the SPARC. 609@end deffn 610@deffn {} BFD_RELOC_GPREL16 611@deffnx {} BFD_RELOC_GPREL32 612For systems that allocate a Global Pointer register, these are 613displacements off that register. These relocation types are 614handled specially, because the value the register will have is 615decided relatively late. 616@end deffn 617@deffn {} BFD_RELOC_I960_CALLJ 618Reloc types used for i960/b.out. 619@end deffn 620@deffn {} BFD_RELOC_NONE 621@deffnx {} BFD_RELOC_SPARC_WDISP22 622@deffnx {} BFD_RELOC_SPARC22 623@deffnx {} BFD_RELOC_SPARC13 624@deffnx {} BFD_RELOC_SPARC_GOT10 625@deffnx {} BFD_RELOC_SPARC_GOT13 626@deffnx {} BFD_RELOC_SPARC_GOT22 627@deffnx {} BFD_RELOC_SPARC_PC10 628@deffnx {} BFD_RELOC_SPARC_PC22 629@deffnx {} BFD_RELOC_SPARC_WPLT30 630@deffnx {} BFD_RELOC_SPARC_COPY 631@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 632@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 633@deffnx {} BFD_RELOC_SPARC_RELATIVE 634@deffnx {} BFD_RELOC_SPARC_UA16 635@deffnx {} BFD_RELOC_SPARC_UA32 636@deffnx {} BFD_RELOC_SPARC_UA64 637@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 638@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 639@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 640@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 641@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 642@deffnx {} BFD_RELOC_SPARC_JMP_IREL 643@deffnx {} BFD_RELOC_SPARC_IRELATIVE 644SPARC ELF relocations. There is probably some overlap with other 645relocation types already defined. 646@end deffn 647@deffn {} BFD_RELOC_SPARC_BASE13 648@deffnx {} BFD_RELOC_SPARC_BASE22 649I think these are specific to SPARC a.out (e.g., Sun 4). 650@end deffn 651@deffn {} BFD_RELOC_SPARC_64 652@deffnx {} BFD_RELOC_SPARC_10 653@deffnx {} BFD_RELOC_SPARC_11 654@deffnx {} BFD_RELOC_SPARC_OLO10 655@deffnx {} BFD_RELOC_SPARC_HH22 656@deffnx {} BFD_RELOC_SPARC_HM10 657@deffnx {} BFD_RELOC_SPARC_LM22 658@deffnx {} BFD_RELOC_SPARC_PC_HH22 659@deffnx {} BFD_RELOC_SPARC_PC_HM10 660@deffnx {} BFD_RELOC_SPARC_PC_LM22 661@deffnx {} BFD_RELOC_SPARC_WDISP16 662@deffnx {} BFD_RELOC_SPARC_WDISP19 663@deffnx {} BFD_RELOC_SPARC_7 664@deffnx {} BFD_RELOC_SPARC_6 665@deffnx {} BFD_RELOC_SPARC_5 666@deffnx {} BFD_RELOC_SPARC_DISP64 667@deffnx {} BFD_RELOC_SPARC_PLT32 668@deffnx {} BFD_RELOC_SPARC_PLT64 669@deffnx {} BFD_RELOC_SPARC_HIX22 670@deffnx {} BFD_RELOC_SPARC_LOX10 671@deffnx {} BFD_RELOC_SPARC_H44 672@deffnx {} BFD_RELOC_SPARC_M44 673@deffnx {} BFD_RELOC_SPARC_L44 674@deffnx {} BFD_RELOC_SPARC_REGISTER 675@deffnx {} BFD_RELOC_SPARC_H34 676@deffnx {} BFD_RELOC_SPARC_SIZE32 677@deffnx {} BFD_RELOC_SPARC_SIZE64 678@deffnx {} BFD_RELOC_SPARC_WDISP10 679SPARC64 relocations 680@end deffn 681@deffn {} BFD_RELOC_SPARC_REV32 682SPARC little endian relocation 683@end deffn 684@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 685@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 686@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 687@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 688@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 689@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 690@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 691@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 692@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 693@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 694@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 695@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 696@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 697@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 698@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 699@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 700@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 701@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 702@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 703@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 704@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 705@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 706@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 707@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 708SPARC TLS relocations 709@end deffn 710@deffn {} BFD_RELOC_SPU_IMM7 711@deffnx {} BFD_RELOC_SPU_IMM8 712@deffnx {} BFD_RELOC_SPU_IMM10 713@deffnx {} BFD_RELOC_SPU_IMM10W 714@deffnx {} BFD_RELOC_SPU_IMM16 715@deffnx {} BFD_RELOC_SPU_IMM16W 716@deffnx {} BFD_RELOC_SPU_IMM18 717@deffnx {} BFD_RELOC_SPU_PCREL9a 718@deffnx {} BFD_RELOC_SPU_PCREL9b 719@deffnx {} BFD_RELOC_SPU_PCREL16 720@deffnx {} BFD_RELOC_SPU_LO16 721@deffnx {} BFD_RELOC_SPU_HI16 722@deffnx {} BFD_RELOC_SPU_PPU32 723@deffnx {} BFD_RELOC_SPU_PPU64 724@deffnx {} BFD_RELOC_SPU_ADD_PIC 725SPU Relocations. 726@end deffn 727@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 728Alpha ECOFF and ELF relocations. Some of these treat the symbol or 729"addend" in some special way. 730For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 731writing; when reading, it will be the absolute section symbol. The 732addend is the displacement in bytes of the "lda" instruction from 733the "ldah" instruction (which is at the address of this reloc). 734@end deffn 735@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 736For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 737with GPDISP_HI16 relocs. The addend is ignored when writing the 738relocations out, and is filled in with the file's GP value on 739reading, for convenience. 740@end deffn 741@deffn {} BFD_RELOC_ALPHA_GPDISP 742The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 743relocation except that there is no accompanying GPDISP_LO16 744relocation. 745@end deffn 746@deffn {} BFD_RELOC_ALPHA_LITERAL 747@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 748@deffnx {} BFD_RELOC_ALPHA_LITUSE 749The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 750the assembler turns it into a LDQ instruction to load the address of 751the symbol, and then fills in a register in the real instruction. 752 753The LITERAL reloc, at the LDQ instruction, refers to the .lita 754section symbol. The addend is ignored when writing, but is filled 755in with the file's GP value on reading, for convenience, as with the 756GPDISP_LO16 reloc. 757 758The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 759It should refer to the symbol to be referenced, as with 16_GOTOFF, 760but it generates output not based on the position within the .got 761section, but relative to the GP value chosen for the file during the 762final link stage. 763 764The LITUSE reloc, on the instruction using the loaded address, gives 765information to the linker that it might be able to use to optimize 766away some literal section references. The symbol is ignored (read 767as the absolute section symbol), and the "addend" indicates the type 768of instruction using the register: 7691 - "memory" fmt insn 7702 - byte-manipulation (byte offset reg) 7713 - jsr (target of branch) 772@end deffn 773@deffn {} BFD_RELOC_ALPHA_HINT 774The HINT relocation indicates a value that should be filled into the 775"hint" field of a jmp/jsr/ret instruction, for possible branch- 776prediction logic which may be provided on some processors. 777@end deffn 778@deffn {} BFD_RELOC_ALPHA_LINKAGE 779The LINKAGE relocation outputs a linkage pair in the object file, 780which is filled by the linker. 781@end deffn 782@deffn {} BFD_RELOC_ALPHA_CODEADDR 783The CODEADDR relocation outputs a STO_CA in the object file, 784which is filled by the linker. 785@end deffn 786@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 787@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 788The GPREL_HI/LO relocations together form a 32-bit offset from the 789GP register. 790@end deffn 791@deffn {} BFD_RELOC_ALPHA_BRSGP 792Like BFD_RELOC_23_PCREL_S2, except that the source and target must 793share a common GP, and the target address is adjusted for 794STO_ALPHA_STD_GPLOAD. 795@end deffn 796@deffn {} BFD_RELOC_ALPHA_NOP 797The NOP relocation outputs a NOP if the longword displacement 798between two procedure entry points is < 2^21. 799@end deffn 800@deffn {} BFD_RELOC_ALPHA_BSR 801The BSR relocation outputs a BSR if the longword displacement 802between two procedure entry points is < 2^21. 803@end deffn 804@deffn {} BFD_RELOC_ALPHA_LDA 805The LDA relocation outputs a LDA if the longword displacement 806between two procedure entry points is < 2^16. 807@end deffn 808@deffn {} BFD_RELOC_ALPHA_BOH 809The BOH relocation outputs a BSR if the longword displacement 810between two procedure entry points is < 2^21, or else a hint. 811@end deffn 812@deffn {} BFD_RELOC_ALPHA_TLSGD 813@deffnx {} BFD_RELOC_ALPHA_TLSLDM 814@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 815@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 816@deffnx {} BFD_RELOC_ALPHA_DTPREL64 817@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 818@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 819@deffnx {} BFD_RELOC_ALPHA_DTPREL16 820@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 821@deffnx {} BFD_RELOC_ALPHA_TPREL64 822@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 823@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 824@deffnx {} BFD_RELOC_ALPHA_TPREL16 825Alpha thread-local storage relocations. 826@end deffn 827@deffn {} BFD_RELOC_MIPS_JMP 828@deffnx {} BFD_RELOC_MICROMIPS_JMP 829The MIPS jump instruction. 830@end deffn 831@deffn {} BFD_RELOC_MIPS16_JMP 832The MIPS16 jump instruction. 833@end deffn 834@deffn {} BFD_RELOC_MIPS16_GPREL 835MIPS16 GP relative reloc. 836@end deffn 837@deffn {} BFD_RELOC_HI16 838High 16 bits of 32-bit value; simple reloc. 839@end deffn 840@deffn {} BFD_RELOC_HI16_S 841High 16 bits of 32-bit value but the low 16 bits will be sign 842extended and added to form the final result. If the low 16 843bits form a negative number, we need to add one to the high value 844to compensate for the borrow when the low bits are added. 845@end deffn 846@deffn {} BFD_RELOC_LO16 847Low 16 bits. 848@end deffn 849@deffn {} BFD_RELOC_HI16_PCREL 850High 16 bits of 32-bit pc-relative value 851@end deffn 852@deffn {} BFD_RELOC_HI16_S_PCREL 853High 16 bits of 32-bit pc-relative value, adjusted 854@end deffn 855@deffn {} BFD_RELOC_LO16_PCREL 856Low 16 bits of pc-relative value 857@end deffn 858@deffn {} BFD_RELOC_MIPS16_GOT16 859@deffnx {} BFD_RELOC_MIPS16_CALL16 860Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 86116-bit immediate fields 862@end deffn 863@deffn {} BFD_RELOC_MIPS16_HI16 864MIPS16 high 16 bits of 32-bit value. 865@end deffn 866@deffn {} BFD_RELOC_MIPS16_HI16_S 867MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 868extended and added to form the final result. If the low 16 869bits form a negative number, we need to add one to the high value 870to compensate for the borrow when the low bits are added. 871@end deffn 872@deffn {} BFD_RELOC_MIPS16_LO16 873MIPS16 low 16 bits. 874@end deffn 875@deffn {} BFD_RELOC_MIPS16_TLS_GD 876@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 877@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 878@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 879@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 880@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 881@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 882MIPS16 TLS relocations 883@end deffn 884@deffn {} BFD_RELOC_MIPS_LITERAL 885@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 886Relocation against a MIPS literal section. 887@end deffn 888@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 889@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 890@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 891microMIPS PC-relative relocations. 892@end deffn 893@deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 894MIPS16 PC-relative relocation. 895@end deffn 896@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 897@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 898@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 899@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 900MIPS PC-relative relocations. 901@end deffn 902@deffn {} BFD_RELOC_MICROMIPS_GPREL16 903@deffnx {} BFD_RELOC_MICROMIPS_HI16 904@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 905@deffnx {} BFD_RELOC_MICROMIPS_LO16 906microMIPS versions of generic BFD relocs. 907@end deffn 908@deffn {} BFD_RELOC_MIPS_GOT16 909@deffnx {} BFD_RELOC_MICROMIPS_GOT16 910@deffnx {} BFD_RELOC_MIPS_CALL16 911@deffnx {} BFD_RELOC_MICROMIPS_CALL16 912@deffnx {} BFD_RELOC_MIPS_GOT_HI16 913@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 914@deffnx {} BFD_RELOC_MIPS_GOT_LO16 915@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 916@deffnx {} BFD_RELOC_MIPS_CALL_HI16 917@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 918@deffnx {} BFD_RELOC_MIPS_CALL_LO16 919@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 920@deffnx {} BFD_RELOC_MIPS_SUB 921@deffnx {} BFD_RELOC_MICROMIPS_SUB 922@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 923@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 924@deffnx {} BFD_RELOC_MIPS_GOT_OFST 925@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 926@deffnx {} BFD_RELOC_MIPS_GOT_DISP 927@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 928@deffnx {} BFD_RELOC_MIPS_SHIFT5 929@deffnx {} BFD_RELOC_MIPS_SHIFT6 930@deffnx {} BFD_RELOC_MIPS_INSERT_A 931@deffnx {} BFD_RELOC_MIPS_INSERT_B 932@deffnx {} BFD_RELOC_MIPS_DELETE 933@deffnx {} BFD_RELOC_MIPS_HIGHEST 934@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 935@deffnx {} BFD_RELOC_MIPS_HIGHER 936@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 937@deffnx {} BFD_RELOC_MIPS_SCN_DISP 938@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 939@deffnx {} BFD_RELOC_MIPS_REL16 940@deffnx {} BFD_RELOC_MIPS_RELGOT 941@deffnx {} BFD_RELOC_MIPS_JALR 942@deffnx {} BFD_RELOC_MICROMIPS_JALR 943@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 944@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 945@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 946@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 947@deffnx {} BFD_RELOC_MIPS_TLS_GD 948@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 949@deffnx {} BFD_RELOC_MIPS_TLS_LDM 950@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 951@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 952@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 953@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 954@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 955@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 956@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 957@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 958@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 959@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 960@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 961@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 962@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 963@deffnx {} BFD_RELOC_MIPS_EH 964MIPS ELF relocations. 965@end deffn 966@deffn {} BFD_RELOC_MIPS_COPY 967@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 968MIPS ELF relocations (VxWorks and PLT extensions). 969@end deffn 970@deffn {} BFD_RELOC_MOXIE_10_PCREL 971Moxie ELF relocations. 972@end deffn 973@deffn {} BFD_RELOC_FT32_10 974@deffnx {} BFD_RELOC_FT32_20 975@deffnx {} BFD_RELOC_FT32_17 976@deffnx {} BFD_RELOC_FT32_18 977FT32 ELF relocations. 978@end deffn 979@deffn {} BFD_RELOC_FRV_LABEL16 980@deffnx {} BFD_RELOC_FRV_LABEL24 981@deffnx {} BFD_RELOC_FRV_LO16 982@deffnx {} BFD_RELOC_FRV_HI16 983@deffnx {} BFD_RELOC_FRV_GPREL12 984@deffnx {} BFD_RELOC_FRV_GPRELU12 985@deffnx {} BFD_RELOC_FRV_GPREL32 986@deffnx {} BFD_RELOC_FRV_GPRELHI 987@deffnx {} BFD_RELOC_FRV_GPRELLO 988@deffnx {} BFD_RELOC_FRV_GOT12 989@deffnx {} BFD_RELOC_FRV_GOTHI 990@deffnx {} BFD_RELOC_FRV_GOTLO 991@deffnx {} BFD_RELOC_FRV_FUNCDESC 992@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 993@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 994@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 995@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 996@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 997@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 998@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 999@deffnx {} BFD_RELOC_FRV_GOTOFF12 1000@deffnx {} BFD_RELOC_FRV_GOTOFFHI 1001@deffnx {} BFD_RELOC_FRV_GOTOFFLO 1002@deffnx {} BFD_RELOC_FRV_GETTLSOFF 1003@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 1004@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 1005@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 1006@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 1007@deffnx {} BFD_RELOC_FRV_TLSMOFF12 1008@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 1009@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 1010@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 1011@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 1012@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 1013@deffnx {} BFD_RELOC_FRV_TLSOFF 1014@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 1015@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 1016@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 1017@deffnx {} BFD_RELOC_FRV_TLSMOFF 1018Fujitsu Frv Relocations. 1019@end deffn 1020@deffn {} BFD_RELOC_MN10300_GOTOFF24 1021This is a 24bit GOT-relative reloc for the mn10300. 1022@end deffn 1023@deffn {} BFD_RELOC_MN10300_GOT32 1024This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1025in the instruction. 1026@end deffn 1027@deffn {} BFD_RELOC_MN10300_GOT24 1028This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1029in the instruction. 1030@end deffn 1031@deffn {} BFD_RELOC_MN10300_GOT16 1032This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1033in the instruction. 1034@end deffn 1035@deffn {} BFD_RELOC_MN10300_COPY 1036Copy symbol at runtime. 1037@end deffn 1038@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1039Create GOT entry. 1040@end deffn 1041@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1042Create PLT entry. 1043@end deffn 1044@deffn {} BFD_RELOC_MN10300_RELATIVE 1045Adjust by program base. 1046@end deffn 1047@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1048Together with another reloc targeted at the same location, 1049allows for a value that is the difference of two symbols 1050in the same section. 1051@end deffn 1052@deffn {} BFD_RELOC_MN10300_ALIGN 1053The addend of this reloc is an alignment power that must 1054be honoured at the offset's location, regardless of linker 1055relaxation. 1056@end deffn 1057@deffn {} BFD_RELOC_MN10300_TLS_GD 1058@deffnx {} BFD_RELOC_MN10300_TLS_LD 1059@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1060@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1061@deffnx {} BFD_RELOC_MN10300_TLS_IE 1062@deffnx {} BFD_RELOC_MN10300_TLS_LE 1063@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1064@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1065@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1066Various TLS-related relocations. 1067@end deffn 1068@deffn {} BFD_RELOC_MN10300_32_PCREL 1069This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1070instruction. 1071@end deffn 1072@deffn {} BFD_RELOC_MN10300_16_PCREL 1073This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1074instruction. 1075@end deffn 1076@deffn {} BFD_RELOC_386_GOT32 1077@deffnx {} BFD_RELOC_386_PLT32 1078@deffnx {} BFD_RELOC_386_COPY 1079@deffnx {} BFD_RELOC_386_GLOB_DAT 1080@deffnx {} BFD_RELOC_386_JUMP_SLOT 1081@deffnx {} BFD_RELOC_386_RELATIVE 1082@deffnx {} BFD_RELOC_386_GOTOFF 1083@deffnx {} BFD_RELOC_386_GOTPC 1084@deffnx {} BFD_RELOC_386_TLS_TPOFF 1085@deffnx {} BFD_RELOC_386_TLS_IE 1086@deffnx {} BFD_RELOC_386_TLS_GOTIE 1087@deffnx {} BFD_RELOC_386_TLS_LE 1088@deffnx {} BFD_RELOC_386_TLS_GD 1089@deffnx {} BFD_RELOC_386_TLS_LDM 1090@deffnx {} BFD_RELOC_386_TLS_LDO_32 1091@deffnx {} BFD_RELOC_386_TLS_IE_32 1092@deffnx {} BFD_RELOC_386_TLS_LE_32 1093@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1094@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1095@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1096@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1097@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1098@deffnx {} BFD_RELOC_386_TLS_DESC 1099@deffnx {} BFD_RELOC_386_IRELATIVE 1100@deffnx {} BFD_RELOC_386_GOT32X 1101i386/elf relocations 1102@end deffn 1103@deffn {} BFD_RELOC_X86_64_GOT32 1104@deffnx {} BFD_RELOC_X86_64_PLT32 1105@deffnx {} BFD_RELOC_X86_64_COPY 1106@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1107@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1108@deffnx {} BFD_RELOC_X86_64_RELATIVE 1109@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1110@deffnx {} BFD_RELOC_X86_64_32S 1111@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1112@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1113@deffnx {} BFD_RELOC_X86_64_TPOFF64 1114@deffnx {} BFD_RELOC_X86_64_TLSGD 1115@deffnx {} BFD_RELOC_X86_64_TLSLD 1116@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1117@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1118@deffnx {} BFD_RELOC_X86_64_TPOFF32 1119@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1120@deffnx {} BFD_RELOC_X86_64_GOTPC32 1121@deffnx {} BFD_RELOC_X86_64_GOT64 1122@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1123@deffnx {} BFD_RELOC_X86_64_GOTPC64 1124@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1125@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1126@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1127@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1128@deffnx {} BFD_RELOC_X86_64_TLSDESC 1129@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1130@deffnx {} BFD_RELOC_X86_64_PC32_BND 1131@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1132@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1133@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1134x86-64/elf relocations 1135@end deffn 1136@deffn {} BFD_RELOC_NS32K_IMM_8 1137@deffnx {} BFD_RELOC_NS32K_IMM_16 1138@deffnx {} BFD_RELOC_NS32K_IMM_32 1139@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1140@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1141@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1142@deffnx {} BFD_RELOC_NS32K_DISP_8 1143@deffnx {} BFD_RELOC_NS32K_DISP_16 1144@deffnx {} BFD_RELOC_NS32K_DISP_32 1145@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1146@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1147@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1148ns32k relocations 1149@end deffn 1150@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1151@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1152PDP11 relocations 1153@end deffn 1154@deffn {} BFD_RELOC_PJ_CODE_HI16 1155@deffnx {} BFD_RELOC_PJ_CODE_LO16 1156@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1157@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1158@deffnx {} BFD_RELOC_PJ_CODE_REL16 1159@deffnx {} BFD_RELOC_PJ_CODE_REL32 1160Picojava relocs. Not all of these appear in object files. 1161@end deffn 1162@deffn {} BFD_RELOC_PPC_B26 1163@deffnx {} BFD_RELOC_PPC_BA26 1164@deffnx {} BFD_RELOC_PPC_TOC16 1165@deffnx {} BFD_RELOC_PPC_B16 1166@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1167@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1168@deffnx {} BFD_RELOC_PPC_BA16 1169@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1170@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1171@deffnx {} BFD_RELOC_PPC_COPY 1172@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1173@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1174@deffnx {} BFD_RELOC_PPC_RELATIVE 1175@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1176@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1177@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1178@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1179@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1180@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1181@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1182@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1183@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1184@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1185@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1186@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1187@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1188@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1189@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1190@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1191@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1192@deffnx {} BFD_RELOC_PPC_VLE_REL8 1193@deffnx {} BFD_RELOC_PPC_VLE_REL15 1194@deffnx {} BFD_RELOC_PPC_VLE_REL24 1195@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1196@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1197@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1198@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1199@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1200@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1201@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1202@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1203@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1204@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1205@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1206@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1207@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1208@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1209@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1210@deffnx {} BFD_RELOC_PPC64_HIGHER 1211@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1212@deffnx {} BFD_RELOC_PPC64_HIGHEST 1213@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1214@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1215@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1216@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1217@deffnx {} BFD_RELOC_PPC64_TOC 1218@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1219@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1220@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1221@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1222@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1223@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1224@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1225@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1226@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1227@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1228@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1229@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1230@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1231@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1232@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1233@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1234@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1235@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1236@deffnx {} BFD_RELOC_PPC64_ENTRY 1237Power(rs6000) and PowerPC relocations. 1238@end deffn 1239@deffn {} BFD_RELOC_PPC_TLS 1240@deffnx {} BFD_RELOC_PPC_TLSGD 1241@deffnx {} BFD_RELOC_PPC_TLSLD 1242@deffnx {} BFD_RELOC_PPC_DTPMOD 1243@deffnx {} BFD_RELOC_PPC_TPREL16 1244@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1245@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1246@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1247@deffnx {} BFD_RELOC_PPC_TPREL 1248@deffnx {} BFD_RELOC_PPC_DTPREL16 1249@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1250@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1251@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1252@deffnx {} BFD_RELOC_PPC_DTPREL 1253@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1254@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1255@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1256@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1257@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1258@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1259@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1260@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1261@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1262@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1263@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1264@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1265@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1266@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1267@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1268@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1269@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1270@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1271@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1272@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1273@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1274@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1275@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1276@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1277@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1278@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1279@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1280@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1281@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1282@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1283@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1284@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1285PowerPC and PowerPC64 thread-local storage relocations. 1286@end deffn 1287@deffn {} BFD_RELOC_I370_D12 1288IBM 370/390 relocations 1289@end deffn 1290@deffn {} BFD_RELOC_CTOR 1291The type of reloc used to build a constructor table - at the moment 1292probably a 32 bit wide absolute relocation, but the target can choose. 1293It generally does map to one of the other relocation types. 1294@end deffn 1295@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1296ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1297not stored in the instruction. 1298@end deffn 1299@deffn {} BFD_RELOC_ARM_PCREL_BLX 1300ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1301not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1302field in the instruction. 1303@end deffn 1304@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1305Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1306not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1307field in the instruction. 1308@end deffn 1309@deffn {} BFD_RELOC_ARM_PCREL_CALL 1310ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1311@end deffn 1312@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1313ARM 26-bit pc-relative branch for B or conditional BL instruction. 1314@end deffn 1315@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1316@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1317@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1318@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1319@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1320@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1321Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1322The lowest bit must be zero and is not stored in the instruction. 1323Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1324"nn" one smaller in all cases. Note further that BRANCH23 1325corresponds to R_ARM_THM_CALL. 1326@end deffn 1327@deffn {} BFD_RELOC_ARM_OFFSET_IMM 132812-bit immediate offset, used in ARM-format ldr and str instructions. 1329@end deffn 1330@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13315-bit immediate offset, used in Thumb-format ldr and str instructions. 1332@end deffn 1333@deffn {} BFD_RELOC_ARM_TARGET1 1334Pc-relative or absolute relocation depending on target. Used for 1335entries in .init_array sections. 1336@end deffn 1337@deffn {} BFD_RELOC_ARM_ROSEGREL32 1338Read-only segment base relative address. 1339@end deffn 1340@deffn {} BFD_RELOC_ARM_SBREL32 1341Data segment base relative address. 1342@end deffn 1343@deffn {} BFD_RELOC_ARM_TARGET2 1344This reloc is used for references to RTTI data from exception handling 1345tables. The actual definition depends on the target. It may be a 1346pc-relative or some form of GOT-indirect relocation. 1347@end deffn 1348@deffn {} BFD_RELOC_ARM_PREL31 134931-bit PC relative address. 1350@end deffn 1351@deffn {} BFD_RELOC_ARM_MOVW 1352@deffnx {} BFD_RELOC_ARM_MOVT 1353@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1354@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1355@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1356@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1357@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1358@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1359Low and High halfword relocations for MOVW and MOVT instructions. 1360@end deffn 1361@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1362@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1363@deffnx {} BFD_RELOC_ARM_GOT32 1364@deffnx {} BFD_RELOC_ARM_PLT32 1365@deffnx {} BFD_RELOC_ARM_RELATIVE 1366@deffnx {} BFD_RELOC_ARM_GOTOFF 1367@deffnx {} BFD_RELOC_ARM_GOTPC 1368@deffnx {} BFD_RELOC_ARM_GOT_PREL 1369Relocations for setting up GOTs and PLTs for shared libraries. 1370@end deffn 1371@deffn {} BFD_RELOC_ARM_TLS_GD32 1372@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1373@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1374@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1375@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1376@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1377@deffnx {} BFD_RELOC_ARM_TLS_IE32 1378@deffnx {} BFD_RELOC_ARM_TLS_LE32 1379@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1380@deffnx {} BFD_RELOC_ARM_TLS_CALL 1381@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1382@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1383@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1384@deffnx {} BFD_RELOC_ARM_TLS_DESC 1385ARM thread-local storage relocations. 1386@end deffn 1387@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1388@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1389@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1390@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1391@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1392@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1393@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1394@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1395@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1396@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1397@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1398@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1399@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1400@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1401@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1402@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1403@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1404@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1405@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1406@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1407@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1408@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1409@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1410@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1411@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1412@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1413@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1414@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1415ARM group relocations. 1416@end deffn 1417@deffn {} BFD_RELOC_ARM_V4BX 1418Annotation of BX instructions. 1419@end deffn 1420@deffn {} BFD_RELOC_ARM_IRELATIVE 1421ARM support for STT_GNU_IFUNC. 1422@end deffn 1423@deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1424@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1425@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1426@deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1427Thumb1 relocations to support execute-only code. 1428@end deffn 1429@deffn {} BFD_RELOC_ARM_IMMEDIATE 1430@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1431@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1432@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1433@deffnx {} BFD_RELOC_ARM_T32_IMM12 1434@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1435@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1436@deffnx {} BFD_RELOC_ARM_SMC 1437@deffnx {} BFD_RELOC_ARM_HVC 1438@deffnx {} BFD_RELOC_ARM_SWI 1439@deffnx {} BFD_RELOC_ARM_MULTI 1440@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1441@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1442@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1443@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1444@deffnx {} BFD_RELOC_ARM_ADR_IMM 1445@deffnx {} BFD_RELOC_ARM_LDR_IMM 1446@deffnx {} BFD_RELOC_ARM_LITERAL 1447@deffnx {} BFD_RELOC_ARM_IN_POOL 1448@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1449@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1450@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1451@deffnx {} BFD_RELOC_ARM_HWLITERAL 1452@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1453@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1454@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1455These relocs are only used within the ARM assembler. They are not 1456(at present) written to any object files. 1457@end deffn 1458@deffn {} BFD_RELOC_SH_PCDISP8BY2 1459@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1460@deffnx {} BFD_RELOC_SH_IMM3 1461@deffnx {} BFD_RELOC_SH_IMM3U 1462@deffnx {} BFD_RELOC_SH_DISP12 1463@deffnx {} BFD_RELOC_SH_DISP12BY2 1464@deffnx {} BFD_RELOC_SH_DISP12BY4 1465@deffnx {} BFD_RELOC_SH_DISP12BY8 1466@deffnx {} BFD_RELOC_SH_DISP20 1467@deffnx {} BFD_RELOC_SH_DISP20BY8 1468@deffnx {} BFD_RELOC_SH_IMM4 1469@deffnx {} BFD_RELOC_SH_IMM4BY2 1470@deffnx {} BFD_RELOC_SH_IMM4BY4 1471@deffnx {} BFD_RELOC_SH_IMM8 1472@deffnx {} BFD_RELOC_SH_IMM8BY2 1473@deffnx {} BFD_RELOC_SH_IMM8BY4 1474@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1475@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1476@deffnx {} BFD_RELOC_SH_SWITCH16 1477@deffnx {} BFD_RELOC_SH_SWITCH32 1478@deffnx {} BFD_RELOC_SH_USES 1479@deffnx {} BFD_RELOC_SH_COUNT 1480@deffnx {} BFD_RELOC_SH_ALIGN 1481@deffnx {} BFD_RELOC_SH_CODE 1482@deffnx {} BFD_RELOC_SH_DATA 1483@deffnx {} BFD_RELOC_SH_LABEL 1484@deffnx {} BFD_RELOC_SH_LOOP_START 1485@deffnx {} BFD_RELOC_SH_LOOP_END 1486@deffnx {} BFD_RELOC_SH_COPY 1487@deffnx {} BFD_RELOC_SH_GLOB_DAT 1488@deffnx {} BFD_RELOC_SH_JMP_SLOT 1489@deffnx {} BFD_RELOC_SH_RELATIVE 1490@deffnx {} BFD_RELOC_SH_GOTPC 1491@deffnx {} BFD_RELOC_SH_GOT_LOW16 1492@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1493@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1494@deffnx {} BFD_RELOC_SH_GOT_HI16 1495@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1496@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1497@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1498@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1499@deffnx {} BFD_RELOC_SH_PLT_LOW16 1500@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1501@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1502@deffnx {} BFD_RELOC_SH_PLT_HI16 1503@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1504@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1505@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1506@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1507@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1508@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1509@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1510@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1511@deffnx {} BFD_RELOC_SH_COPY64 1512@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1513@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1514@deffnx {} BFD_RELOC_SH_RELATIVE64 1515@deffnx {} BFD_RELOC_SH_GOT10BY4 1516@deffnx {} BFD_RELOC_SH_GOT10BY8 1517@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1518@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1519@deffnx {} BFD_RELOC_SH_GOTPLT32 1520@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1521@deffnx {} BFD_RELOC_SH_IMMU5 1522@deffnx {} BFD_RELOC_SH_IMMS6 1523@deffnx {} BFD_RELOC_SH_IMMS6BY32 1524@deffnx {} BFD_RELOC_SH_IMMU6 1525@deffnx {} BFD_RELOC_SH_IMMS10 1526@deffnx {} BFD_RELOC_SH_IMMS10BY2 1527@deffnx {} BFD_RELOC_SH_IMMS10BY4 1528@deffnx {} BFD_RELOC_SH_IMMS10BY8 1529@deffnx {} BFD_RELOC_SH_IMMS16 1530@deffnx {} BFD_RELOC_SH_IMMU16 1531@deffnx {} BFD_RELOC_SH_IMM_LOW16 1532@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1533@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1534@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1535@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1536@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1537@deffnx {} BFD_RELOC_SH_IMM_HI16 1538@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1539@deffnx {} BFD_RELOC_SH_PT_16 1540@deffnx {} BFD_RELOC_SH_TLS_GD_32 1541@deffnx {} BFD_RELOC_SH_TLS_LD_32 1542@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1543@deffnx {} BFD_RELOC_SH_TLS_IE_32 1544@deffnx {} BFD_RELOC_SH_TLS_LE_32 1545@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1546@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1547@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1548@deffnx {} BFD_RELOC_SH_GOT20 1549@deffnx {} BFD_RELOC_SH_GOTOFF20 1550@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1551@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1552@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1553@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1554@deffnx {} BFD_RELOC_SH_FUNCDESC 1555Renesas / SuperH SH relocs. Not all of these appear in object files. 1556@end deffn 1557@deffn {} BFD_RELOC_ARC_NONE 1558@deffnx {} BFD_RELOC_ARC_8 1559@deffnx {} BFD_RELOC_ARC_16 1560@deffnx {} BFD_RELOC_ARC_24 1561@deffnx {} BFD_RELOC_ARC_32 1562@deffnx {} BFD_RELOC_ARC_N8 1563@deffnx {} BFD_RELOC_ARC_N16 1564@deffnx {} BFD_RELOC_ARC_N24 1565@deffnx {} BFD_RELOC_ARC_N32 1566@deffnx {} BFD_RELOC_ARC_SDA 1567@deffnx {} BFD_RELOC_ARC_SECTOFF 1568@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1569@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1570@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1571@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1572@deffnx {} BFD_RELOC_ARC_SDA32 1573@deffnx {} BFD_RELOC_ARC_SDA_LDST 1574@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1575@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1576@deffnx {} BFD_RELOC_ARC_SDA16_LD 1577@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1578@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1579@deffnx {} BFD_RELOC_ARC_S13_PCREL 1580@deffnx {} BFD_RELOC_ARC_W 1581@deffnx {} BFD_RELOC_ARC_32_ME 1582@deffnx {} BFD_RELOC_ARC_32_ME_S 1583@deffnx {} BFD_RELOC_ARC_N32_ME 1584@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1585@deffnx {} BFD_RELOC_ARC_SDA32_ME 1586@deffnx {} BFD_RELOC_ARC_W_ME 1587@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1588@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1589@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1590@deffnx {} BFD_RELOC_AC_SECTFOFF_S9 1591@deffnx {} BFD_RELOC_AC_SECTFOFF_S9_1 1592@deffnx {} BFD_RELOC_AC_SECTFOFF_S9_2 1593@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1594@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1595@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1596@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1597@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1598@deffnx {} BFD_RELOC_ARC_32_PCREL 1599@deffnx {} BFD_RELOC_ARC_PC32 1600@deffnx {} BFD_RELOC_ARC_GOT32 1601@deffnx {} BFD_RELOC_ARC_GOTPC32 1602@deffnx {} BFD_RELOC_ARC_PLT32 1603@deffnx {} BFD_RELOC_ARC_COPY 1604@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1605@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1606@deffnx {} BFD_RELOC_ARC_RELATIVE 1607@deffnx {} BFD_RELOC_ARC_GOTOFF 1608@deffnx {} BFD_RELOC_ARC_GOTPC 1609@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1610@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1611@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1612@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1613@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1614@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1615@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1616@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1617@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1618@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1619@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1620@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1621@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1622@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1623@deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1624ARC relocs. 1625@end deffn 1626@deffn {} BFD_RELOC_BFIN_16_IMM 1627ADI Blackfin 16 bit immediate absolute reloc. 1628@end deffn 1629@deffn {} BFD_RELOC_BFIN_16_HIGH 1630ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1631@end deffn 1632@deffn {} BFD_RELOC_BFIN_4_PCREL 1633ADI Blackfin 'a' part of LSETUP. 1634@end deffn 1635@deffn {} BFD_RELOC_BFIN_5_PCREL 1636ADI Blackfin. 1637@end deffn 1638@deffn {} BFD_RELOC_BFIN_16_LOW 1639ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1640@end deffn 1641@deffn {} BFD_RELOC_BFIN_10_PCREL 1642ADI Blackfin. 1643@end deffn 1644@deffn {} BFD_RELOC_BFIN_11_PCREL 1645ADI Blackfin 'b' part of LSETUP. 1646@end deffn 1647@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1648ADI Blackfin. 1649@end deffn 1650@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1651ADI Blackfin Short jump, pcrel. 1652@end deffn 1653@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1654ADI Blackfin Call.x not implemented. 1655@end deffn 1656@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1657ADI Blackfin Long Jump pcrel. 1658@end deffn 1659@deffn {} BFD_RELOC_BFIN_GOT17M4 1660@deffnx {} BFD_RELOC_BFIN_GOTHI 1661@deffnx {} BFD_RELOC_BFIN_GOTLO 1662@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1663@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1664@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1665@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1666@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1667@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1668@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1669@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1670@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1671@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1672@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1673ADI Blackfin FD-PIC relocations. 1674@end deffn 1675@deffn {} BFD_RELOC_BFIN_GOT 1676ADI Blackfin GOT relocation. 1677@end deffn 1678@deffn {} BFD_RELOC_BFIN_PLTPC 1679ADI Blackfin PLTPC relocation. 1680@end deffn 1681@deffn {} BFD_ARELOC_BFIN_PUSH 1682ADI Blackfin arithmetic relocation. 1683@end deffn 1684@deffn {} BFD_ARELOC_BFIN_CONST 1685ADI Blackfin arithmetic relocation. 1686@end deffn 1687@deffn {} BFD_ARELOC_BFIN_ADD 1688ADI Blackfin arithmetic relocation. 1689@end deffn 1690@deffn {} BFD_ARELOC_BFIN_SUB 1691ADI Blackfin arithmetic relocation. 1692@end deffn 1693@deffn {} BFD_ARELOC_BFIN_MULT 1694ADI Blackfin arithmetic relocation. 1695@end deffn 1696@deffn {} BFD_ARELOC_BFIN_DIV 1697ADI Blackfin arithmetic relocation. 1698@end deffn 1699@deffn {} BFD_ARELOC_BFIN_MOD 1700ADI Blackfin arithmetic relocation. 1701@end deffn 1702@deffn {} BFD_ARELOC_BFIN_LSHIFT 1703ADI Blackfin arithmetic relocation. 1704@end deffn 1705@deffn {} BFD_ARELOC_BFIN_RSHIFT 1706ADI Blackfin arithmetic relocation. 1707@end deffn 1708@deffn {} BFD_ARELOC_BFIN_AND 1709ADI Blackfin arithmetic relocation. 1710@end deffn 1711@deffn {} BFD_ARELOC_BFIN_OR 1712ADI Blackfin arithmetic relocation. 1713@end deffn 1714@deffn {} BFD_ARELOC_BFIN_XOR 1715ADI Blackfin arithmetic relocation. 1716@end deffn 1717@deffn {} BFD_ARELOC_BFIN_LAND 1718ADI Blackfin arithmetic relocation. 1719@end deffn 1720@deffn {} BFD_ARELOC_BFIN_LOR 1721ADI Blackfin arithmetic relocation. 1722@end deffn 1723@deffn {} BFD_ARELOC_BFIN_LEN 1724ADI Blackfin arithmetic relocation. 1725@end deffn 1726@deffn {} BFD_ARELOC_BFIN_NEG 1727ADI Blackfin arithmetic relocation. 1728@end deffn 1729@deffn {} BFD_ARELOC_BFIN_COMP 1730ADI Blackfin arithmetic relocation. 1731@end deffn 1732@deffn {} BFD_ARELOC_BFIN_PAGE 1733ADI Blackfin arithmetic relocation. 1734@end deffn 1735@deffn {} BFD_ARELOC_BFIN_HWPAGE 1736ADI Blackfin arithmetic relocation. 1737@end deffn 1738@deffn {} BFD_ARELOC_BFIN_ADDR 1739ADI Blackfin arithmetic relocation. 1740@end deffn 1741@deffn {} BFD_RELOC_D10V_10_PCREL_R 1742Mitsubishi D10V relocs. 1743This is a 10-bit reloc with the right 2 bits 1744assumed to be 0. 1745@end deffn 1746@deffn {} BFD_RELOC_D10V_10_PCREL_L 1747Mitsubishi D10V relocs. 1748This is a 10-bit reloc with the right 2 bits 1749assumed to be 0. This is the same as the previous reloc 1750except it is in the left container, i.e., 1751shifted left 15 bits. 1752@end deffn 1753@deffn {} BFD_RELOC_D10V_18 1754This is an 18-bit reloc with the right 2 bits 1755assumed to be 0. 1756@end deffn 1757@deffn {} BFD_RELOC_D10V_18_PCREL 1758This is an 18-bit reloc with the right 2 bits 1759assumed to be 0. 1760@end deffn 1761@deffn {} BFD_RELOC_D30V_6 1762Mitsubishi D30V relocs. 1763This is a 6-bit absolute reloc. 1764@end deffn 1765@deffn {} BFD_RELOC_D30V_9_PCREL 1766This is a 6-bit pc-relative reloc with 1767the right 3 bits assumed to be 0. 1768@end deffn 1769@deffn {} BFD_RELOC_D30V_9_PCREL_R 1770This is a 6-bit pc-relative reloc with 1771the right 3 bits assumed to be 0. Same 1772as the previous reloc but on the right side 1773of the container. 1774@end deffn 1775@deffn {} BFD_RELOC_D30V_15 1776This is a 12-bit absolute reloc with the 1777right 3 bitsassumed to be 0. 1778@end deffn 1779@deffn {} BFD_RELOC_D30V_15_PCREL 1780This is a 12-bit pc-relative reloc with 1781the right 3 bits assumed to be 0. 1782@end deffn 1783@deffn {} BFD_RELOC_D30V_15_PCREL_R 1784This is a 12-bit pc-relative reloc with 1785the right 3 bits assumed to be 0. Same 1786as the previous reloc but on the right side 1787of the container. 1788@end deffn 1789@deffn {} BFD_RELOC_D30V_21 1790This is an 18-bit absolute reloc with 1791the right 3 bits assumed to be 0. 1792@end deffn 1793@deffn {} BFD_RELOC_D30V_21_PCREL 1794This is an 18-bit pc-relative reloc with 1795the right 3 bits assumed to be 0. 1796@end deffn 1797@deffn {} BFD_RELOC_D30V_21_PCREL_R 1798This is an 18-bit pc-relative reloc with 1799the right 3 bits assumed to be 0. Same 1800as the previous reloc but on the right side 1801of the container. 1802@end deffn 1803@deffn {} BFD_RELOC_D30V_32 1804This is a 32-bit absolute reloc. 1805@end deffn 1806@deffn {} BFD_RELOC_D30V_32_PCREL 1807This is a 32-bit pc-relative reloc. 1808@end deffn 1809@deffn {} BFD_RELOC_DLX_HI16_S 1810DLX relocs 1811@end deffn 1812@deffn {} BFD_RELOC_DLX_LO16 1813DLX relocs 1814@end deffn 1815@deffn {} BFD_RELOC_DLX_JMP26 1816DLX relocs 1817@end deffn 1818@deffn {} BFD_RELOC_M32C_HI8 1819@deffnx {} BFD_RELOC_M32C_RL_JUMP 1820@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1821@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1822Renesas M16C/M32C Relocations. 1823@end deffn 1824@deffn {} BFD_RELOC_M32R_24 1825Renesas M32R (formerly Mitsubishi M32R) relocs. 1826This is a 24 bit absolute address. 1827@end deffn 1828@deffn {} BFD_RELOC_M32R_10_PCREL 1829This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1830@end deffn 1831@deffn {} BFD_RELOC_M32R_18_PCREL 1832This is an 18-bit reloc with the right 2 bits assumed to be 0. 1833@end deffn 1834@deffn {} BFD_RELOC_M32R_26_PCREL 1835This is a 26-bit reloc with the right 2 bits assumed to be 0. 1836@end deffn 1837@deffn {} BFD_RELOC_M32R_HI16_ULO 1838This is a 16-bit reloc containing the high 16 bits of an address 1839used when the lower 16 bits are treated as unsigned. 1840@end deffn 1841@deffn {} BFD_RELOC_M32R_HI16_SLO 1842This is a 16-bit reloc containing the high 16 bits of an address 1843used when the lower 16 bits are treated as signed. 1844@end deffn 1845@deffn {} BFD_RELOC_M32R_LO16 1846This is a 16-bit reloc containing the lower 16 bits of an address. 1847@end deffn 1848@deffn {} BFD_RELOC_M32R_SDA16 1849This is a 16-bit reloc containing the small data area offset for use in 1850add3, load, and store instructions. 1851@end deffn 1852@deffn {} BFD_RELOC_M32R_GOT24 1853@deffnx {} BFD_RELOC_M32R_26_PLTREL 1854@deffnx {} BFD_RELOC_M32R_COPY 1855@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1856@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1857@deffnx {} BFD_RELOC_M32R_RELATIVE 1858@deffnx {} BFD_RELOC_M32R_GOTOFF 1859@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1860@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1861@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1862@deffnx {} BFD_RELOC_M32R_GOTPC24 1863@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1864@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1865@deffnx {} BFD_RELOC_M32R_GOT16_LO 1866@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1867@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1868@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1869For PIC. 1870@end deffn 1871@deffn {} BFD_RELOC_NDS32_20 1872NDS32 relocs. 1873This is a 20 bit absolute address. 1874@end deffn 1875@deffn {} BFD_RELOC_NDS32_9_PCREL 1876This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1877@end deffn 1878@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1879This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1880@end deffn 1881@deffn {} BFD_RELOC_NDS32_15_PCREL 1882This is an 15-bit reloc with the right 1 bit assumed to be 0. 1883@end deffn 1884@deffn {} BFD_RELOC_NDS32_17_PCREL 1885This is an 17-bit reloc with the right 1 bit assumed to be 0. 1886@end deffn 1887@deffn {} BFD_RELOC_NDS32_25_PCREL 1888This is a 25-bit reloc with the right 1 bit assumed to be 0. 1889@end deffn 1890@deffn {} BFD_RELOC_NDS32_HI20 1891This is a 20-bit reloc containing the high 20 bits of an address 1892used with the lower 12 bits 1893@end deffn 1894@deffn {} BFD_RELOC_NDS32_LO12S3 1895This is a 12-bit reloc containing the lower 12 bits of an address 1896then shift right by 3. This is used with ldi,sdi... 1897@end deffn 1898@deffn {} BFD_RELOC_NDS32_LO12S2 1899This is a 12-bit reloc containing the lower 12 bits of an address 1900then shift left by 2. This is used with lwi,swi... 1901@end deffn 1902@deffn {} BFD_RELOC_NDS32_LO12S1 1903This is a 12-bit reloc containing the lower 12 bits of an address 1904then shift left by 1. This is used with lhi,shi... 1905@end deffn 1906@deffn {} BFD_RELOC_NDS32_LO12S0 1907This is a 12-bit reloc containing the lower 12 bits of an address 1908then shift left by 0. This is used with lbisbi... 1909@end deffn 1910@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1911This is a 12-bit reloc containing the lower 12 bits of an address 1912then shift left by 0. This is only used with branch relaxations 1913@end deffn 1914@deffn {} BFD_RELOC_NDS32_SDA15S3 1915This is a 15-bit reloc containing the small data area 18-bit signed offset 1916and shift left by 3 for use in ldi, sdi... 1917@end deffn 1918@deffn {} BFD_RELOC_NDS32_SDA15S2 1919This is a 15-bit reloc containing the small data area 17-bit signed offset 1920and shift left by 2 for use in lwi, swi... 1921@end deffn 1922@deffn {} BFD_RELOC_NDS32_SDA15S1 1923This is a 15-bit reloc containing the small data area 16-bit signed offset 1924and shift left by 1 for use in lhi, shi... 1925@end deffn 1926@deffn {} BFD_RELOC_NDS32_SDA15S0 1927This is a 15-bit reloc containing the small data area 15-bit signed offset 1928and shift left by 0 for use in lbi, sbi... 1929@end deffn 1930@deffn {} BFD_RELOC_NDS32_SDA16S3 1931This is a 16-bit reloc containing the small data area 16-bit signed offset 1932and shift left by 3 1933@end deffn 1934@deffn {} BFD_RELOC_NDS32_SDA17S2 1935This is a 17-bit reloc containing the small data area 17-bit signed offset 1936and shift left by 2 for use in lwi.gp, swi.gp... 1937@end deffn 1938@deffn {} BFD_RELOC_NDS32_SDA18S1 1939This is a 18-bit reloc containing the small data area 18-bit signed offset 1940and shift left by 1 for use in lhi.gp, shi.gp... 1941@end deffn 1942@deffn {} BFD_RELOC_NDS32_SDA19S0 1943This is a 19-bit reloc containing the small data area 19-bit signed offset 1944and shift left by 0 for use in lbi.gp, sbi.gp... 1945@end deffn 1946@deffn {} BFD_RELOC_NDS32_GOT20 1947@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1948@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1949@deffnx {} BFD_RELOC_NDS32_COPY 1950@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1951@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1952@deffnx {} BFD_RELOC_NDS32_RELATIVE 1953@deffnx {} BFD_RELOC_NDS32_GOTOFF 1954@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1955@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1956@deffnx {} BFD_RELOC_NDS32_GOTPC20 1957@deffnx {} BFD_RELOC_NDS32_GOT_HI20 1958@deffnx {} BFD_RELOC_NDS32_GOT_LO12 1959@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1960@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1961for PIC 1962@end deffn 1963@deffn {} BFD_RELOC_NDS32_INSN16 1964@deffnx {} BFD_RELOC_NDS32_LABEL 1965@deffnx {} BFD_RELOC_NDS32_LONGCALL1 1966@deffnx {} BFD_RELOC_NDS32_LONGCALL2 1967@deffnx {} BFD_RELOC_NDS32_LONGCALL3 1968@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1969@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1970@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1971@deffnx {} BFD_RELOC_NDS32_LOADSTORE 1972@deffnx {} BFD_RELOC_NDS32_9_FIXED 1973@deffnx {} BFD_RELOC_NDS32_15_FIXED 1974@deffnx {} BFD_RELOC_NDS32_17_FIXED 1975@deffnx {} BFD_RELOC_NDS32_25_FIXED 1976@deffnx {} BFD_RELOC_NDS32_LONGCALL4 1977@deffnx {} BFD_RELOC_NDS32_LONGCALL5 1978@deffnx {} BFD_RELOC_NDS32_LONGCALL6 1979@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 1980@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 1981@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 1982@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 1983for relax 1984@end deffn 1985@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 1986@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 1987@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 1988@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 1989for PIC 1990@end deffn 1991@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 1992@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 1993@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 1994@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 1995for floating point 1996@end deffn 1997@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 1998@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 1999@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 2000for dwarf2 debug_line. 2001@end deffn 2002@deffn {} BFD_RELOC_NDS32_UPDATE_TA 2003for eliminate 16-bit instructions 2004@end deffn 2005@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2006@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2007@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2008@deffnx {} BFD_RELOC_NDS32_GOT_LO15 2009@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2010@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2011@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2012@deffnx {} BFD_RELOC_NDS32_GOT15S2 2013@deffnx {} BFD_RELOC_NDS32_GOT17S2 2014for PIC object relaxation 2015@end deffn 2016@deffn {} BFD_RELOC_NDS32_5 2017NDS32 relocs. 2018This is a 5 bit absolute address. 2019@end deffn 2020@deffn {} BFD_RELOC_NDS32_10_UPCREL 2021This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2022@end deffn 2023@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2024If fp were omitted, fp can used as another gp. 2025@end deffn 2026@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2027@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2028@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2029@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2030@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2031@deffnx {} BFD_RELOC_NDS32_PTR 2032@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2033@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2034@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2035@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2036@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2037@deffnx {} BFD_RELOC_NDS32_MINUEND 2038@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2039@deffnx {} BFD_RELOC_NDS32_DIFF8 2040@deffnx {} BFD_RELOC_NDS32_DIFF16 2041@deffnx {} BFD_RELOC_NDS32_DIFF32 2042@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2043@deffnx {} BFD_RELOC_NDS32_EMPTY 2044relaxation relative relocation types 2045@end deffn 2046@deffn {} BFD_RELOC_NDS32_25_ABS 2047This is a 25 bit absolute address. 2048@end deffn 2049@deffn {} BFD_RELOC_NDS32_DATA 2050@deffnx {} BFD_RELOC_NDS32_TRAN 2051@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2052@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2053For ex9 and ifc using. 2054@end deffn 2055@deffn {} BFD_RELOC_NDS32_TPOFF 2056@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2057@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2058@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2059@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2060@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2061@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2062@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2063@deffnx {} BFD_RELOC_NDS32_TLS_TPOFF 2064@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2065@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2066@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2067@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2068For TLS. 2069@end deffn 2070@deffn {} BFD_RELOC_V850_9_PCREL 2071This is a 9-bit reloc 2072@end deffn 2073@deffn {} BFD_RELOC_V850_22_PCREL 2074This is a 22-bit reloc 2075@end deffn 2076@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2077This is a 16 bit offset from the short data area pointer. 2078@end deffn 2079@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2080This is a 16 bit offset (of which only 15 bits are used) from the 2081short data area pointer. 2082@end deffn 2083@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2084This is a 16 bit offset from the zero data area pointer. 2085@end deffn 2086@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2087This is a 16 bit offset (of which only 15 bits are used) from the 2088zero data area pointer. 2089@end deffn 2090@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2091This is an 8 bit offset (of which only 6 bits are used) from the 2092tiny data area pointer. 2093@end deffn 2094@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2095This is an 8bit offset (of which only 7 bits are used) from the tiny 2096data area pointer. 2097@end deffn 2098@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2099This is a 7 bit offset from the tiny data area pointer. 2100@end deffn 2101@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2102This is a 16 bit offset from the tiny data area pointer. 2103@end deffn 2104@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2105This is a 5 bit offset (of which only 4 bits are used) from the tiny 2106data area pointer. 2107@end deffn 2108@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2109This is a 4 bit offset from the tiny data area pointer. 2110@end deffn 2111@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2112This is a 16 bit offset from the short data area pointer, with the 2113bits placed non-contiguously in the instruction. 2114@end deffn 2115@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2116This is a 16 bit offset from the zero data area pointer, with the 2117bits placed non-contiguously in the instruction. 2118@end deffn 2119@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2120This is a 6 bit offset from the call table base pointer. 2121@end deffn 2122@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2123This is a 16 bit offset from the call table base pointer. 2124@end deffn 2125@deffn {} BFD_RELOC_V850_LONGCALL 2126Used for relaxing indirect function calls. 2127@end deffn 2128@deffn {} BFD_RELOC_V850_LONGJUMP 2129Used for relaxing indirect jumps. 2130@end deffn 2131@deffn {} BFD_RELOC_V850_ALIGN 2132Used to maintain alignment whilst relaxing. 2133@end deffn 2134@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2135This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2136instructions. 2137@end deffn 2138@deffn {} BFD_RELOC_V850_16_PCREL 2139This is a 16-bit reloc. 2140@end deffn 2141@deffn {} BFD_RELOC_V850_17_PCREL 2142This is a 17-bit reloc. 2143@end deffn 2144@deffn {} BFD_RELOC_V850_23 2145This is a 23-bit reloc. 2146@end deffn 2147@deffn {} BFD_RELOC_V850_32_PCREL 2148This is a 32-bit reloc. 2149@end deffn 2150@deffn {} BFD_RELOC_V850_32_ABS 2151This is a 32-bit reloc. 2152@end deffn 2153@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2154This is a 16-bit reloc. 2155@end deffn 2156@deffn {} BFD_RELOC_V850_16_S1 2157This is a 16-bit reloc. 2158@end deffn 2159@deffn {} BFD_RELOC_V850_LO16_S1 2160Low 16 bits. 16 bit shifted by 1. 2161@end deffn 2162@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2163This is a 16 bit offset from the call table base pointer. 2164@end deffn 2165@deffn {} BFD_RELOC_V850_32_GOTPCREL 2166DSO relocations. 2167@end deffn 2168@deffn {} BFD_RELOC_V850_16_GOT 2169DSO relocations. 2170@end deffn 2171@deffn {} BFD_RELOC_V850_32_GOT 2172DSO relocations. 2173@end deffn 2174@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2175DSO relocations. 2176@end deffn 2177@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2178DSO relocations. 2179@end deffn 2180@deffn {} BFD_RELOC_V850_COPY 2181DSO relocations. 2182@end deffn 2183@deffn {} BFD_RELOC_V850_GLOB_DAT 2184DSO relocations. 2185@end deffn 2186@deffn {} BFD_RELOC_V850_JMP_SLOT 2187DSO relocations. 2188@end deffn 2189@deffn {} BFD_RELOC_V850_RELATIVE 2190DSO relocations. 2191@end deffn 2192@deffn {} BFD_RELOC_V850_16_GOTOFF 2193DSO relocations. 2194@end deffn 2195@deffn {} BFD_RELOC_V850_32_GOTOFF 2196DSO relocations. 2197@end deffn 2198@deffn {} BFD_RELOC_V850_CODE 2199start code. 2200@end deffn 2201@deffn {} BFD_RELOC_V850_DATA 2202start data in text. 2203@end deffn 2204@deffn {} BFD_RELOC_TIC30_LDP 2205This is a 8bit DP reloc for the tms320c30, where the most 2206significant 8 bits of a 24 bit word are placed into the least 2207significant 8 bits of the opcode. 2208@end deffn 2209@deffn {} BFD_RELOC_TIC54X_PARTLS7 2210This is a 7bit reloc for the tms320c54x, where the least 2211significant 7 bits of a 16 bit word are placed into the least 2212significant 7 bits of the opcode. 2213@end deffn 2214@deffn {} BFD_RELOC_TIC54X_PARTMS9 2215This is a 9bit DP reloc for the tms320c54x, where the most 2216significant 9 bits of a 16 bit word are placed into the least 2217significant 9 bits of the opcode. 2218@end deffn 2219@deffn {} BFD_RELOC_TIC54X_23 2220This is an extended address 23-bit reloc for the tms320c54x. 2221@end deffn 2222@deffn {} BFD_RELOC_TIC54X_16_OF_23 2223This is a 16-bit reloc for the tms320c54x, where the least 2224significant 16 bits of a 23-bit extended address are placed into 2225the opcode. 2226@end deffn 2227@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2228This is a reloc for the tms320c54x, where the most 2229significant 7 bits of a 23-bit extended address are placed into 2230the opcode. 2231@end deffn 2232@deffn {} BFD_RELOC_C6000_PCR_S21 2233@deffnx {} BFD_RELOC_C6000_PCR_S12 2234@deffnx {} BFD_RELOC_C6000_PCR_S10 2235@deffnx {} BFD_RELOC_C6000_PCR_S7 2236@deffnx {} BFD_RELOC_C6000_ABS_S16 2237@deffnx {} BFD_RELOC_C6000_ABS_L16 2238@deffnx {} BFD_RELOC_C6000_ABS_H16 2239@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2240@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2241@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2242@deffnx {} BFD_RELOC_C6000_SBR_S16 2243@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2244@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2245@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2246@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2247@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2248@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2249@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2250@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2251@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2252@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2253@deffnx {} BFD_RELOC_C6000_PREL31 2254@deffnx {} BFD_RELOC_C6000_COPY 2255@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2256@deffnx {} BFD_RELOC_C6000_EHTYPE 2257@deffnx {} BFD_RELOC_C6000_PCR_H16 2258@deffnx {} BFD_RELOC_C6000_PCR_L16 2259@deffnx {} BFD_RELOC_C6000_ALIGN 2260@deffnx {} BFD_RELOC_C6000_FPHEAD 2261@deffnx {} BFD_RELOC_C6000_NOCMP 2262TMS320C6000 relocations. 2263@end deffn 2264@deffn {} BFD_RELOC_FR30_48 2265This is a 48 bit reloc for the FR30 that stores 32 bits. 2266@end deffn 2267@deffn {} BFD_RELOC_FR30_20 2268This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2269two sections. 2270@end deffn 2271@deffn {} BFD_RELOC_FR30_6_IN_4 2272This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 22734 bits. 2274@end deffn 2275@deffn {} BFD_RELOC_FR30_8_IN_8 2276This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2277into 8 bits. 2278@end deffn 2279@deffn {} BFD_RELOC_FR30_9_IN_8 2280This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2281into 8 bits. 2282@end deffn 2283@deffn {} BFD_RELOC_FR30_10_IN_8 2284This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2285into 8 bits. 2286@end deffn 2287@deffn {} BFD_RELOC_FR30_9_PCREL 2288This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2289short offset into 8 bits. 2290@end deffn 2291@deffn {} BFD_RELOC_FR30_12_PCREL 2292This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2293short offset into 11 bits. 2294@end deffn 2295@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2296@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2297@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2298@deffnx {} BFD_RELOC_MCORE_PCREL_32 2299@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2300@deffnx {} BFD_RELOC_MCORE_RVA 2301Motorola Mcore relocations. 2302@end deffn 2303@deffn {} BFD_RELOC_MEP_8 2304@deffnx {} BFD_RELOC_MEP_16 2305@deffnx {} BFD_RELOC_MEP_32 2306@deffnx {} BFD_RELOC_MEP_PCREL8A2 2307@deffnx {} BFD_RELOC_MEP_PCREL12A2 2308@deffnx {} BFD_RELOC_MEP_PCREL17A2 2309@deffnx {} BFD_RELOC_MEP_PCREL24A2 2310@deffnx {} BFD_RELOC_MEP_PCABS24A2 2311@deffnx {} BFD_RELOC_MEP_LOW16 2312@deffnx {} BFD_RELOC_MEP_HI16U 2313@deffnx {} BFD_RELOC_MEP_HI16S 2314@deffnx {} BFD_RELOC_MEP_GPREL 2315@deffnx {} BFD_RELOC_MEP_TPREL 2316@deffnx {} BFD_RELOC_MEP_TPREL7 2317@deffnx {} BFD_RELOC_MEP_TPREL7A2 2318@deffnx {} BFD_RELOC_MEP_TPREL7A4 2319@deffnx {} BFD_RELOC_MEP_UIMM24 2320@deffnx {} BFD_RELOC_MEP_ADDR24A4 2321@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2322@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2323Toshiba Media Processor Relocations. 2324@end deffn 2325@deffn {} BFD_RELOC_METAG_HIADDR16 2326@deffnx {} BFD_RELOC_METAG_LOADDR16 2327@deffnx {} BFD_RELOC_METAG_RELBRANCH 2328@deffnx {} BFD_RELOC_METAG_GETSETOFF 2329@deffnx {} BFD_RELOC_METAG_HIOG 2330@deffnx {} BFD_RELOC_METAG_LOOG 2331@deffnx {} BFD_RELOC_METAG_REL8 2332@deffnx {} BFD_RELOC_METAG_REL16 2333@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2334@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2335@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2336@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2337@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2338@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2339@deffnx {} BFD_RELOC_METAG_HI16_PLT 2340@deffnx {} BFD_RELOC_METAG_LO16_PLT 2341@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2342@deffnx {} BFD_RELOC_METAG_GOTOFF 2343@deffnx {} BFD_RELOC_METAG_PLT 2344@deffnx {} BFD_RELOC_METAG_COPY 2345@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2346@deffnx {} BFD_RELOC_METAG_RELATIVE 2347@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2348@deffnx {} BFD_RELOC_METAG_TLS_GD 2349@deffnx {} BFD_RELOC_METAG_TLS_LDM 2350@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2351@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2352@deffnx {} BFD_RELOC_METAG_TLS_LDO 2353@deffnx {} BFD_RELOC_METAG_TLS_IE 2354@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2355@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2356@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2357@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2358@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2359@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2360@deffnx {} BFD_RELOC_METAG_TLS_LE 2361@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2362@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2363Imagination Technologies Meta relocations. 2364@end deffn 2365@deffn {} BFD_RELOC_MMIX_GETA 2366@deffnx {} BFD_RELOC_MMIX_GETA_1 2367@deffnx {} BFD_RELOC_MMIX_GETA_2 2368@deffnx {} BFD_RELOC_MMIX_GETA_3 2369These are relocations for the GETA instruction. 2370@end deffn 2371@deffn {} BFD_RELOC_MMIX_CBRANCH 2372@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2373@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2374@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2375@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2376These are relocations for a conditional branch instruction. 2377@end deffn 2378@deffn {} BFD_RELOC_MMIX_PUSHJ 2379@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2380@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2381@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2382@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2383These are relocations for the PUSHJ instruction. 2384@end deffn 2385@deffn {} BFD_RELOC_MMIX_JMP 2386@deffnx {} BFD_RELOC_MMIX_JMP_1 2387@deffnx {} BFD_RELOC_MMIX_JMP_2 2388@deffnx {} BFD_RELOC_MMIX_JMP_3 2389These are relocations for the JMP instruction. 2390@end deffn 2391@deffn {} BFD_RELOC_MMIX_ADDR19 2392This is a relocation for a relative address as in a GETA instruction or 2393a branch. 2394@end deffn 2395@deffn {} BFD_RELOC_MMIX_ADDR27 2396This is a relocation for a relative address as in a JMP instruction. 2397@end deffn 2398@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2399This is a relocation for an instruction field that may be a general 2400register or a value 0..255. 2401@end deffn 2402@deffn {} BFD_RELOC_MMIX_REG 2403This is a relocation for an instruction field that may be a general 2404register. 2405@end deffn 2406@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2407This is a relocation for two instruction fields holding a register and 2408an offset, the equivalent of the relocation. 2409@end deffn 2410@deffn {} BFD_RELOC_MMIX_LOCAL 2411This relocation is an assertion that the expression is not allocated as 2412a global register. It does not modify contents. 2413@end deffn 2414@deffn {} BFD_RELOC_AVR_7_PCREL 2415This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2416short offset into 7 bits. 2417@end deffn 2418@deffn {} BFD_RELOC_AVR_13_PCREL 2419This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2420short offset into 12 bits. 2421@end deffn 2422@deffn {} BFD_RELOC_AVR_16_PM 2423This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2424program memory address) into 16 bits. 2425@end deffn 2426@deffn {} BFD_RELOC_AVR_LO8_LDI 2427This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2428data memory address) into 8 bit immediate value of LDI insn. 2429@end deffn 2430@deffn {} BFD_RELOC_AVR_HI8_LDI 2431This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2432of data memory address) into 8 bit immediate value of LDI insn. 2433@end deffn 2434@deffn {} BFD_RELOC_AVR_HH8_LDI 2435This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2436of program memory address) into 8 bit immediate value of LDI insn. 2437@end deffn 2438@deffn {} BFD_RELOC_AVR_MS8_LDI 2439This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2440of 32 bit value) into 8 bit immediate value of LDI insn. 2441@end deffn 2442@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2443This is a 16 bit reloc for the AVR that stores negated 8 bit value 2444(usually data memory address) into 8 bit immediate value of SUBI insn. 2445@end deffn 2446@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2447This is a 16 bit reloc for the AVR that stores negated 8 bit value 2448(high 8 bit of data memory address) into 8 bit immediate value of 2449SUBI insn. 2450@end deffn 2451@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2452This is a 16 bit reloc for the AVR that stores negated 8 bit value 2453(most high 8 bit of program memory address) into 8 bit immediate value 2454of LDI or SUBI insn. 2455@end deffn 2456@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2457This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2458of 32 bit value) into 8 bit immediate value of LDI insn. 2459@end deffn 2460@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2461This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2462command address) into 8 bit immediate value of LDI insn. 2463@end deffn 2464@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2465This is a 16 bit reloc for the AVR that stores 8 bit value 2466(command address) into 8 bit immediate value of LDI insn. If the address 2467is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2468in the lower 128k. 2469@end deffn 2470@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2471This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2472of command address) into 8 bit immediate value of LDI insn. 2473@end deffn 2474@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2475This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2476of command address) into 8 bit immediate value of LDI insn. If the address 2477is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2478below 128k. 2479@end deffn 2480@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2481This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2482of command address) into 8 bit immediate value of LDI insn. 2483@end deffn 2484@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2485This is a 16 bit reloc for the AVR that stores negated 8 bit value 2486(usually command address) into 8 bit immediate value of SUBI insn. 2487@end deffn 2488@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2489This is a 16 bit reloc for the AVR that stores negated 8 bit value 2490(high 8 bit of 16 bit command address) into 8 bit immediate value 2491of SUBI insn. 2492@end deffn 2493@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2494This is a 16 bit reloc for the AVR that stores negated 8 bit value 2495(high 6 bit of 22 bit command address) into 8 bit immediate 2496value of SUBI insn. 2497@end deffn 2498@deffn {} BFD_RELOC_AVR_CALL 2499This is a 32 bit reloc for the AVR that stores 23 bit value 2500into 22 bits. 2501@end deffn 2502@deffn {} BFD_RELOC_AVR_LDI 2503This is a 16 bit reloc for the AVR that stores all needed bits 2504for absolute addressing with ldi with overflow check to linktime 2505@end deffn 2506@deffn {} BFD_RELOC_AVR_6 2507This is a 6 bit reloc for the AVR that stores offset for ldd/std 2508instructions 2509@end deffn 2510@deffn {} BFD_RELOC_AVR_6_ADIW 2511This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2512instructions 2513@end deffn 2514@deffn {} BFD_RELOC_AVR_8_LO 2515This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2516in .byte lo8(symbol) 2517@end deffn 2518@deffn {} BFD_RELOC_AVR_8_HI 2519This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2520in .byte hi8(symbol) 2521@end deffn 2522@deffn {} BFD_RELOC_AVR_8_HLO 2523This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2524in .byte hlo8(symbol) 2525@end deffn 2526@deffn {} BFD_RELOC_AVR_DIFF8 2527@deffnx {} BFD_RELOC_AVR_DIFF16 2528@deffnx {} BFD_RELOC_AVR_DIFF32 2529AVR relocations to mark the difference of two local symbols. 2530These are only needed to support linker relaxation and can be ignored 2531when not relaxing. The field is set to the value of the difference 2532assuming no relaxation. The relocation encodes the position of the 2533second symbol so the linker can determine whether to adjust the field 2534value. 2535@end deffn 2536@deffn {} BFD_RELOC_AVR_LDS_STS_16 2537This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2538lds and sts instructions supported only tiny core. 2539@end deffn 2540@deffn {} BFD_RELOC_AVR_PORT6 2541This is a 6 bit reloc for the AVR that stores an I/O register 2542number for the IN and OUT instructions 2543@end deffn 2544@deffn {} BFD_RELOC_AVR_PORT5 2545This is a 5 bit reloc for the AVR that stores an I/O register 2546number for the SBIC, SBIS, SBI and CBI instructions 2547@end deffn 2548@deffn {} BFD_RELOC_RL78_NEG8 2549@deffnx {} BFD_RELOC_RL78_NEG16 2550@deffnx {} BFD_RELOC_RL78_NEG24 2551@deffnx {} BFD_RELOC_RL78_NEG32 2552@deffnx {} BFD_RELOC_RL78_16_OP 2553@deffnx {} BFD_RELOC_RL78_24_OP 2554@deffnx {} BFD_RELOC_RL78_32_OP 2555@deffnx {} BFD_RELOC_RL78_8U 2556@deffnx {} BFD_RELOC_RL78_16U 2557@deffnx {} BFD_RELOC_RL78_24U 2558@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2559@deffnx {} BFD_RELOC_RL78_DIFF 2560@deffnx {} BFD_RELOC_RL78_GPRELB 2561@deffnx {} BFD_RELOC_RL78_GPRELW 2562@deffnx {} BFD_RELOC_RL78_GPRELL 2563@deffnx {} BFD_RELOC_RL78_SYM 2564@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2565@deffnx {} BFD_RELOC_RL78_OP_NEG 2566@deffnx {} BFD_RELOC_RL78_OP_AND 2567@deffnx {} BFD_RELOC_RL78_OP_SHRA 2568@deffnx {} BFD_RELOC_RL78_ABS8 2569@deffnx {} BFD_RELOC_RL78_ABS16 2570@deffnx {} BFD_RELOC_RL78_ABS16_REV 2571@deffnx {} BFD_RELOC_RL78_ABS32 2572@deffnx {} BFD_RELOC_RL78_ABS32_REV 2573@deffnx {} BFD_RELOC_RL78_ABS16U 2574@deffnx {} BFD_RELOC_RL78_ABS16UW 2575@deffnx {} BFD_RELOC_RL78_ABS16UL 2576@deffnx {} BFD_RELOC_RL78_RELAX 2577@deffnx {} BFD_RELOC_RL78_HI16 2578@deffnx {} BFD_RELOC_RL78_HI8 2579@deffnx {} BFD_RELOC_RL78_LO16 2580@deffnx {} BFD_RELOC_RL78_CODE 2581@deffnx {} BFD_RELOC_RL78_SADDR 2582Renesas RL78 Relocations. 2583@end deffn 2584@deffn {} BFD_RELOC_RX_NEG8 2585@deffnx {} BFD_RELOC_RX_NEG16 2586@deffnx {} BFD_RELOC_RX_NEG24 2587@deffnx {} BFD_RELOC_RX_NEG32 2588@deffnx {} BFD_RELOC_RX_16_OP 2589@deffnx {} BFD_RELOC_RX_24_OP 2590@deffnx {} BFD_RELOC_RX_32_OP 2591@deffnx {} BFD_RELOC_RX_8U 2592@deffnx {} BFD_RELOC_RX_16U 2593@deffnx {} BFD_RELOC_RX_24U 2594@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2595@deffnx {} BFD_RELOC_RX_DIFF 2596@deffnx {} BFD_RELOC_RX_GPRELB 2597@deffnx {} BFD_RELOC_RX_GPRELW 2598@deffnx {} BFD_RELOC_RX_GPRELL 2599@deffnx {} BFD_RELOC_RX_SYM 2600@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2601@deffnx {} BFD_RELOC_RX_OP_NEG 2602@deffnx {} BFD_RELOC_RX_ABS8 2603@deffnx {} BFD_RELOC_RX_ABS16 2604@deffnx {} BFD_RELOC_RX_ABS16_REV 2605@deffnx {} BFD_RELOC_RX_ABS32 2606@deffnx {} BFD_RELOC_RX_ABS32_REV 2607@deffnx {} BFD_RELOC_RX_ABS16U 2608@deffnx {} BFD_RELOC_RX_ABS16UW 2609@deffnx {} BFD_RELOC_RX_ABS16UL 2610@deffnx {} BFD_RELOC_RX_RELAX 2611Renesas RX Relocations. 2612@end deffn 2613@deffn {} BFD_RELOC_390_12 2614Direct 12 bit. 2615@end deffn 2616@deffn {} BFD_RELOC_390_GOT12 261712 bit GOT offset. 2618@end deffn 2619@deffn {} BFD_RELOC_390_PLT32 262032 bit PC relative PLT address. 2621@end deffn 2622@deffn {} BFD_RELOC_390_COPY 2623Copy symbol at runtime. 2624@end deffn 2625@deffn {} BFD_RELOC_390_GLOB_DAT 2626Create GOT entry. 2627@end deffn 2628@deffn {} BFD_RELOC_390_JMP_SLOT 2629Create PLT entry. 2630@end deffn 2631@deffn {} BFD_RELOC_390_RELATIVE 2632Adjust by program base. 2633@end deffn 2634@deffn {} BFD_RELOC_390_GOTPC 263532 bit PC relative offset to GOT. 2636@end deffn 2637@deffn {} BFD_RELOC_390_GOT16 263816 bit GOT offset. 2639@end deffn 2640@deffn {} BFD_RELOC_390_PC12DBL 2641PC relative 12 bit shifted by 1. 2642@end deffn 2643@deffn {} BFD_RELOC_390_PLT12DBL 264412 bit PC rel. PLT shifted by 1. 2645@end deffn 2646@deffn {} BFD_RELOC_390_PC16DBL 2647PC relative 16 bit shifted by 1. 2648@end deffn 2649@deffn {} BFD_RELOC_390_PLT16DBL 265016 bit PC rel. PLT shifted by 1. 2651@end deffn 2652@deffn {} BFD_RELOC_390_PC24DBL 2653PC relative 24 bit shifted by 1. 2654@end deffn 2655@deffn {} BFD_RELOC_390_PLT24DBL 265624 bit PC rel. PLT shifted by 1. 2657@end deffn 2658@deffn {} BFD_RELOC_390_PC32DBL 2659PC relative 32 bit shifted by 1. 2660@end deffn 2661@deffn {} BFD_RELOC_390_PLT32DBL 266232 bit PC rel. PLT shifted by 1. 2663@end deffn 2664@deffn {} BFD_RELOC_390_GOTPCDBL 266532 bit PC rel. GOT shifted by 1. 2666@end deffn 2667@deffn {} BFD_RELOC_390_GOT64 266864 bit GOT offset. 2669@end deffn 2670@deffn {} BFD_RELOC_390_PLT64 267164 bit PC relative PLT address. 2672@end deffn 2673@deffn {} BFD_RELOC_390_GOTENT 267432 bit rel. offset to GOT entry. 2675@end deffn 2676@deffn {} BFD_RELOC_390_GOTOFF64 267764 bit offset to GOT. 2678@end deffn 2679@deffn {} BFD_RELOC_390_GOTPLT12 268012-bit offset to symbol-entry within GOT, with PLT handling. 2681@end deffn 2682@deffn {} BFD_RELOC_390_GOTPLT16 268316-bit offset to symbol-entry within GOT, with PLT handling. 2684@end deffn 2685@deffn {} BFD_RELOC_390_GOTPLT32 268632-bit offset to symbol-entry within GOT, with PLT handling. 2687@end deffn 2688@deffn {} BFD_RELOC_390_GOTPLT64 268964-bit offset to symbol-entry within GOT, with PLT handling. 2690@end deffn 2691@deffn {} BFD_RELOC_390_GOTPLTENT 269232-bit rel. offset to symbol-entry within GOT, with PLT handling. 2693@end deffn 2694@deffn {} BFD_RELOC_390_PLTOFF16 269516-bit rel. offset from the GOT to a PLT entry. 2696@end deffn 2697@deffn {} BFD_RELOC_390_PLTOFF32 269832-bit rel. offset from the GOT to a PLT entry. 2699@end deffn 2700@deffn {} BFD_RELOC_390_PLTOFF64 270164-bit rel. offset from the GOT to a PLT entry. 2702@end deffn 2703@deffn {} BFD_RELOC_390_TLS_LOAD 2704@deffnx {} BFD_RELOC_390_TLS_GDCALL 2705@deffnx {} BFD_RELOC_390_TLS_LDCALL 2706@deffnx {} BFD_RELOC_390_TLS_GD32 2707@deffnx {} BFD_RELOC_390_TLS_GD64 2708@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2709@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2710@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2711@deffnx {} BFD_RELOC_390_TLS_LDM32 2712@deffnx {} BFD_RELOC_390_TLS_LDM64 2713@deffnx {} BFD_RELOC_390_TLS_IE32 2714@deffnx {} BFD_RELOC_390_TLS_IE64 2715@deffnx {} BFD_RELOC_390_TLS_IEENT 2716@deffnx {} BFD_RELOC_390_TLS_LE32 2717@deffnx {} BFD_RELOC_390_TLS_LE64 2718@deffnx {} BFD_RELOC_390_TLS_LDO32 2719@deffnx {} BFD_RELOC_390_TLS_LDO64 2720@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2721@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2722@deffnx {} BFD_RELOC_390_TLS_TPOFF 2723s390 tls relocations. 2724@end deffn 2725@deffn {} BFD_RELOC_390_20 2726@deffnx {} BFD_RELOC_390_GOT20 2727@deffnx {} BFD_RELOC_390_GOTPLT20 2728@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2729Long displacement extension. 2730@end deffn 2731@deffn {} BFD_RELOC_390_IRELATIVE 2732STT_GNU_IFUNC relocation. 2733@end deffn 2734@deffn {} BFD_RELOC_SCORE_GPREL15 2735Score relocations 2736Low 16 bit for load/store 2737@end deffn 2738@deffn {} BFD_RELOC_SCORE_DUMMY2 2739@deffnx {} BFD_RELOC_SCORE_JMP 2740This is a 24-bit reloc with the right 1 bit assumed to be 0 2741@end deffn 2742@deffn {} BFD_RELOC_SCORE_BRANCH 2743This is a 19-bit reloc with the right 1 bit assumed to be 0 2744@end deffn 2745@deffn {} BFD_RELOC_SCORE_IMM30 2746This is a 32-bit reloc for 48-bit instructions. 2747@end deffn 2748@deffn {} BFD_RELOC_SCORE_IMM32 2749This is a 32-bit reloc for 48-bit instructions. 2750@end deffn 2751@deffn {} BFD_RELOC_SCORE16_JMP 2752This is a 11-bit reloc with the right 1 bit assumed to be 0 2753@end deffn 2754@deffn {} BFD_RELOC_SCORE16_BRANCH 2755This is a 8-bit reloc with the right 1 bit assumed to be 0 2756@end deffn 2757@deffn {} BFD_RELOC_SCORE_BCMP 2758This is a 9-bit reloc with the right 1 bit assumed to be 0 2759@end deffn 2760@deffn {} BFD_RELOC_SCORE_GOT15 2761@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2762@deffnx {} BFD_RELOC_SCORE_CALL15 2763@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2764Undocumented Score relocs 2765@end deffn 2766@deffn {} BFD_RELOC_IP2K_FR9 2767Scenix IP2K - 9-bit register number / data address 2768@end deffn 2769@deffn {} BFD_RELOC_IP2K_BANK 2770Scenix IP2K - 4-bit register/data bank number 2771@end deffn 2772@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2773Scenix IP2K - low 13 bits of instruction word address 2774@end deffn 2775@deffn {} BFD_RELOC_IP2K_PAGE3 2776Scenix IP2K - high 3 bits of instruction word address 2777@end deffn 2778@deffn {} BFD_RELOC_IP2K_LO8DATA 2779@deffnx {} BFD_RELOC_IP2K_HI8DATA 2780@deffnx {} BFD_RELOC_IP2K_EX8DATA 2781Scenix IP2K - ext/low/high 8 bits of data address 2782@end deffn 2783@deffn {} BFD_RELOC_IP2K_LO8INSN 2784@deffnx {} BFD_RELOC_IP2K_HI8INSN 2785Scenix IP2K - low/high 8 bits of instruction word address 2786@end deffn 2787@deffn {} BFD_RELOC_IP2K_PC_SKIP 2788Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2789@end deffn 2790@deffn {} BFD_RELOC_IP2K_TEXT 2791Scenix IP2K - 16 bit word address in text section. 2792@end deffn 2793@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2794Scenix IP2K - 7-bit sp or dp offset 2795@end deffn 2796@deffn {} BFD_RELOC_VPE4KMATH_DATA 2797@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2798Scenix VPE4K coprocessor - data/insn-space addressing 2799@end deffn 2800@deffn {} BFD_RELOC_VTABLE_INHERIT 2801@deffnx {} BFD_RELOC_VTABLE_ENTRY 2802These two relocations are used by the linker to determine which of 2803the entries in a C++ virtual function table are actually used. When 2804the --gc-sections option is given, the linker will zero out the entries 2805that are not used, so that the code for those functions need not be 2806included in the output. 2807 2808VTABLE_INHERIT is a zero-space relocation used to describe to the 2809linker the inheritance tree of a C++ virtual function table. The 2810relocation's symbol should be the parent class' vtable, and the 2811relocation should be located at the child vtable. 2812 2813VTABLE_ENTRY is a zero-space relocation that describes the use of a 2814virtual function table entry. The reloc's symbol should refer to the 2815table of the class mentioned in the code. Off of that base, an offset 2816describes the entry that is being used. For Rela hosts, this offset 2817is stored in the reloc's addend. For Rel hosts, we are forced to put 2818this offset in the reloc's section offset. 2819@end deffn 2820@deffn {} BFD_RELOC_IA64_IMM14 2821@deffnx {} BFD_RELOC_IA64_IMM22 2822@deffnx {} BFD_RELOC_IA64_IMM64 2823@deffnx {} BFD_RELOC_IA64_DIR32MSB 2824@deffnx {} BFD_RELOC_IA64_DIR32LSB 2825@deffnx {} BFD_RELOC_IA64_DIR64MSB 2826@deffnx {} BFD_RELOC_IA64_DIR64LSB 2827@deffnx {} BFD_RELOC_IA64_GPREL22 2828@deffnx {} BFD_RELOC_IA64_GPREL64I 2829@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2830@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2831@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2832@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2833@deffnx {} BFD_RELOC_IA64_LTOFF22 2834@deffnx {} BFD_RELOC_IA64_LTOFF64I 2835@deffnx {} BFD_RELOC_IA64_PLTOFF22 2836@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2837@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2838@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2839@deffnx {} BFD_RELOC_IA64_FPTR64I 2840@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2841@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2842@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2843@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2844@deffnx {} BFD_RELOC_IA64_PCREL21B 2845@deffnx {} BFD_RELOC_IA64_PCREL21BI 2846@deffnx {} BFD_RELOC_IA64_PCREL21M 2847@deffnx {} BFD_RELOC_IA64_PCREL21F 2848@deffnx {} BFD_RELOC_IA64_PCREL22 2849@deffnx {} BFD_RELOC_IA64_PCREL60B 2850@deffnx {} BFD_RELOC_IA64_PCREL64I 2851@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2852@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2853@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2854@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2855@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2856@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2857@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2858@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2859@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2860@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2861@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2862@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2863@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2864@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2865@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2866@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2867@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2868@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2869@deffnx {} BFD_RELOC_IA64_REL32MSB 2870@deffnx {} BFD_RELOC_IA64_REL32LSB 2871@deffnx {} BFD_RELOC_IA64_REL64MSB 2872@deffnx {} BFD_RELOC_IA64_REL64LSB 2873@deffnx {} BFD_RELOC_IA64_LTV32MSB 2874@deffnx {} BFD_RELOC_IA64_LTV32LSB 2875@deffnx {} BFD_RELOC_IA64_LTV64MSB 2876@deffnx {} BFD_RELOC_IA64_LTV64LSB 2877@deffnx {} BFD_RELOC_IA64_IPLTMSB 2878@deffnx {} BFD_RELOC_IA64_IPLTLSB 2879@deffnx {} BFD_RELOC_IA64_COPY 2880@deffnx {} BFD_RELOC_IA64_LTOFF22X 2881@deffnx {} BFD_RELOC_IA64_LDXMOV 2882@deffnx {} BFD_RELOC_IA64_TPREL14 2883@deffnx {} BFD_RELOC_IA64_TPREL22 2884@deffnx {} BFD_RELOC_IA64_TPREL64I 2885@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2886@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2887@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2888@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2889@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2890@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2891@deffnx {} BFD_RELOC_IA64_DTPREL14 2892@deffnx {} BFD_RELOC_IA64_DTPREL22 2893@deffnx {} BFD_RELOC_IA64_DTPREL64I 2894@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2895@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2896@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2897@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2898@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2899Intel IA64 Relocations. 2900@end deffn 2901@deffn {} BFD_RELOC_M68HC11_HI8 2902Motorola 68HC11 reloc. 2903This is the 8 bit high part of an absolute address. 2904@end deffn 2905@deffn {} BFD_RELOC_M68HC11_LO8 2906Motorola 68HC11 reloc. 2907This is the 8 bit low part of an absolute address. 2908@end deffn 2909@deffn {} BFD_RELOC_M68HC11_3B 2910Motorola 68HC11 reloc. 2911This is the 3 bit of a value. 2912@end deffn 2913@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2914Motorola 68HC11 reloc. 2915This reloc marks the beginning of a jump/call instruction. 2916It is used for linker relaxation to correctly identify beginning 2917of instruction and change some branches to use PC-relative 2918addressing mode. 2919@end deffn 2920@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2921Motorola 68HC11 reloc. 2922This reloc marks a group of several instructions that gcc generates 2923and for which the linker relaxation pass can modify and/or remove 2924some of them. 2925@end deffn 2926@deffn {} BFD_RELOC_M68HC11_LO16 2927Motorola 68HC11 reloc. 2928This is the 16-bit lower part of an address. It is used for 'call' 2929instruction to specify the symbol address without any special 2930transformation (due to memory bank window). 2931@end deffn 2932@deffn {} BFD_RELOC_M68HC11_PAGE 2933Motorola 68HC11 reloc. 2934This is a 8-bit reloc that specifies the page number of an address. 2935It is used by 'call' instruction to specify the page number of 2936the symbol. 2937@end deffn 2938@deffn {} BFD_RELOC_M68HC11_24 2939Motorola 68HC11 reloc. 2940This is a 24-bit reloc that represents the address with a 16-bit 2941value and a 8-bit page number. The symbol address is transformed 2942to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 2943@end deffn 2944@deffn {} BFD_RELOC_M68HC12_5B 2945Motorola 68HC12 reloc. 2946This is the 5 bits of a value. 2947@end deffn 2948@deffn {} BFD_RELOC_XGATE_RL_JUMP 2949Freescale XGATE reloc. 2950This reloc marks the beginning of a bra/jal instruction. 2951@end deffn 2952@deffn {} BFD_RELOC_XGATE_RL_GROUP 2953Freescale XGATE reloc. 2954This reloc marks a group of several instructions that gcc generates 2955and for which the linker relaxation pass can modify and/or remove 2956some of them. 2957@end deffn 2958@deffn {} BFD_RELOC_XGATE_LO16 2959Freescale XGATE reloc. 2960This is the 16-bit lower part of an address. It is used for the '16-bit' 2961instructions. 2962@end deffn 2963@deffn {} BFD_RELOC_XGATE_GPAGE 2964Freescale XGATE reloc. 2965@end deffn 2966@deffn {} BFD_RELOC_XGATE_24 2967Freescale XGATE reloc. 2968@end deffn 2969@deffn {} BFD_RELOC_XGATE_PCREL_9 2970Freescale XGATE reloc. 2971This is a 9-bit pc-relative reloc. 2972@end deffn 2973@deffn {} BFD_RELOC_XGATE_PCREL_10 2974Freescale XGATE reloc. 2975This is a 10-bit pc-relative reloc. 2976@end deffn 2977@deffn {} BFD_RELOC_XGATE_IMM8_LO 2978Freescale XGATE reloc. 2979This is the 16-bit lower part of an address. It is used for the '16-bit' 2980instructions. 2981@end deffn 2982@deffn {} BFD_RELOC_XGATE_IMM8_HI 2983Freescale XGATE reloc. 2984This is the 16-bit higher part of an address. It is used for the '16-bit' 2985instructions. 2986@end deffn 2987@deffn {} BFD_RELOC_XGATE_IMM3 2988Freescale XGATE reloc. 2989This is a 3-bit pc-relative reloc. 2990@end deffn 2991@deffn {} BFD_RELOC_XGATE_IMM4 2992Freescale XGATE reloc. 2993This is a 4-bit pc-relative reloc. 2994@end deffn 2995@deffn {} BFD_RELOC_XGATE_IMM5 2996Freescale XGATE reloc. 2997This is a 5-bit pc-relative reloc. 2998@end deffn 2999@deffn {} BFD_RELOC_M68HC12_9B 3000Motorola 68HC12 reloc. 3001This is the 9 bits of a value. 3002@end deffn 3003@deffn {} BFD_RELOC_M68HC12_16B 3004Motorola 68HC12 reloc. 3005This is the 16 bits of a value. 3006@end deffn 3007@deffn {} BFD_RELOC_M68HC12_9_PCREL 3008Motorola 68HC12/XGATE reloc. 3009This is a PCREL9 branch. 3010@end deffn 3011@deffn {} BFD_RELOC_M68HC12_10_PCREL 3012Motorola 68HC12/XGATE reloc. 3013This is a PCREL10 branch. 3014@end deffn 3015@deffn {} BFD_RELOC_M68HC12_LO8XG 3016Motorola 68HC12/XGATE reloc. 3017This is the 8 bit low part of an absolute address and immediately precedes 3018a matching HI8XG part. 3019@end deffn 3020@deffn {} BFD_RELOC_M68HC12_HI8XG 3021Motorola 68HC12/XGATE reloc. 3022This is the 8 bit high part of an absolute address and immediately follows 3023a matching LO8XG part. 3024@end deffn 3025@deffn {} BFD_RELOC_16C_NUM08 3026@deffnx {} BFD_RELOC_16C_NUM08_C 3027@deffnx {} BFD_RELOC_16C_NUM16 3028@deffnx {} BFD_RELOC_16C_NUM16_C 3029@deffnx {} BFD_RELOC_16C_NUM32 3030@deffnx {} BFD_RELOC_16C_NUM32_C 3031@deffnx {} BFD_RELOC_16C_DISP04 3032@deffnx {} BFD_RELOC_16C_DISP04_C 3033@deffnx {} BFD_RELOC_16C_DISP08 3034@deffnx {} BFD_RELOC_16C_DISP08_C 3035@deffnx {} BFD_RELOC_16C_DISP16 3036@deffnx {} BFD_RELOC_16C_DISP16_C 3037@deffnx {} BFD_RELOC_16C_DISP24 3038@deffnx {} BFD_RELOC_16C_DISP24_C 3039@deffnx {} BFD_RELOC_16C_DISP24a 3040@deffnx {} BFD_RELOC_16C_DISP24a_C 3041@deffnx {} BFD_RELOC_16C_REG04 3042@deffnx {} BFD_RELOC_16C_REG04_C 3043@deffnx {} BFD_RELOC_16C_REG04a 3044@deffnx {} BFD_RELOC_16C_REG04a_C 3045@deffnx {} BFD_RELOC_16C_REG14 3046@deffnx {} BFD_RELOC_16C_REG14_C 3047@deffnx {} BFD_RELOC_16C_REG16 3048@deffnx {} BFD_RELOC_16C_REG16_C 3049@deffnx {} BFD_RELOC_16C_REG20 3050@deffnx {} BFD_RELOC_16C_REG20_C 3051@deffnx {} BFD_RELOC_16C_ABS20 3052@deffnx {} BFD_RELOC_16C_ABS20_C 3053@deffnx {} BFD_RELOC_16C_ABS24 3054@deffnx {} BFD_RELOC_16C_ABS24_C 3055@deffnx {} BFD_RELOC_16C_IMM04 3056@deffnx {} BFD_RELOC_16C_IMM04_C 3057@deffnx {} BFD_RELOC_16C_IMM16 3058@deffnx {} BFD_RELOC_16C_IMM16_C 3059@deffnx {} BFD_RELOC_16C_IMM20 3060@deffnx {} BFD_RELOC_16C_IMM20_C 3061@deffnx {} BFD_RELOC_16C_IMM24 3062@deffnx {} BFD_RELOC_16C_IMM24_C 3063@deffnx {} BFD_RELOC_16C_IMM32 3064@deffnx {} BFD_RELOC_16C_IMM32_C 3065NS CR16C Relocations. 3066@end deffn 3067@deffn {} BFD_RELOC_CR16_NUM8 3068@deffnx {} BFD_RELOC_CR16_NUM16 3069@deffnx {} BFD_RELOC_CR16_NUM32 3070@deffnx {} BFD_RELOC_CR16_NUM32a 3071@deffnx {} BFD_RELOC_CR16_REGREL0 3072@deffnx {} BFD_RELOC_CR16_REGREL4 3073@deffnx {} BFD_RELOC_CR16_REGREL4a 3074@deffnx {} BFD_RELOC_CR16_REGREL14 3075@deffnx {} BFD_RELOC_CR16_REGREL14a 3076@deffnx {} BFD_RELOC_CR16_REGREL16 3077@deffnx {} BFD_RELOC_CR16_REGREL20 3078@deffnx {} BFD_RELOC_CR16_REGREL20a 3079@deffnx {} BFD_RELOC_CR16_ABS20 3080@deffnx {} BFD_RELOC_CR16_ABS24 3081@deffnx {} BFD_RELOC_CR16_IMM4 3082@deffnx {} BFD_RELOC_CR16_IMM8 3083@deffnx {} BFD_RELOC_CR16_IMM16 3084@deffnx {} BFD_RELOC_CR16_IMM20 3085@deffnx {} BFD_RELOC_CR16_IMM24 3086@deffnx {} BFD_RELOC_CR16_IMM32 3087@deffnx {} BFD_RELOC_CR16_IMM32a 3088@deffnx {} BFD_RELOC_CR16_DISP4 3089@deffnx {} BFD_RELOC_CR16_DISP8 3090@deffnx {} BFD_RELOC_CR16_DISP16 3091@deffnx {} BFD_RELOC_CR16_DISP20 3092@deffnx {} BFD_RELOC_CR16_DISP24 3093@deffnx {} BFD_RELOC_CR16_DISP24a 3094@deffnx {} BFD_RELOC_CR16_SWITCH8 3095@deffnx {} BFD_RELOC_CR16_SWITCH16 3096@deffnx {} BFD_RELOC_CR16_SWITCH32 3097@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3098@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3099@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3100NS CR16 Relocations. 3101@end deffn 3102@deffn {} BFD_RELOC_CRX_REL4 3103@deffnx {} BFD_RELOC_CRX_REL8 3104@deffnx {} BFD_RELOC_CRX_REL8_CMP 3105@deffnx {} BFD_RELOC_CRX_REL16 3106@deffnx {} BFD_RELOC_CRX_REL24 3107@deffnx {} BFD_RELOC_CRX_REL32 3108@deffnx {} BFD_RELOC_CRX_REGREL12 3109@deffnx {} BFD_RELOC_CRX_REGREL22 3110@deffnx {} BFD_RELOC_CRX_REGREL28 3111@deffnx {} BFD_RELOC_CRX_REGREL32 3112@deffnx {} BFD_RELOC_CRX_ABS16 3113@deffnx {} BFD_RELOC_CRX_ABS32 3114@deffnx {} BFD_RELOC_CRX_NUM8 3115@deffnx {} BFD_RELOC_CRX_NUM16 3116@deffnx {} BFD_RELOC_CRX_NUM32 3117@deffnx {} BFD_RELOC_CRX_IMM16 3118@deffnx {} BFD_RELOC_CRX_IMM32 3119@deffnx {} BFD_RELOC_CRX_SWITCH8 3120@deffnx {} BFD_RELOC_CRX_SWITCH16 3121@deffnx {} BFD_RELOC_CRX_SWITCH32 3122NS CRX Relocations. 3123@end deffn 3124@deffn {} BFD_RELOC_CRIS_BDISP8 3125@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3126@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3127@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3128@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3129@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3130@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3131@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3132@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3133@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3134These relocs are only used within the CRIS assembler. They are not 3135(at present) written to any object files. 3136@end deffn 3137@deffn {} BFD_RELOC_CRIS_COPY 3138@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3139@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3140@deffnx {} BFD_RELOC_CRIS_RELATIVE 3141Relocs used in ELF shared libraries for CRIS. 3142@end deffn 3143@deffn {} BFD_RELOC_CRIS_32_GOT 314432-bit offset to symbol-entry within GOT. 3145@end deffn 3146@deffn {} BFD_RELOC_CRIS_16_GOT 314716-bit offset to symbol-entry within GOT. 3148@end deffn 3149@deffn {} BFD_RELOC_CRIS_32_GOTPLT 315032-bit offset to symbol-entry within GOT, with PLT handling. 3151@end deffn 3152@deffn {} BFD_RELOC_CRIS_16_GOTPLT 315316-bit offset to symbol-entry within GOT, with PLT handling. 3154@end deffn 3155@deffn {} BFD_RELOC_CRIS_32_GOTREL 315632-bit offset to symbol, relative to GOT. 3157@end deffn 3158@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 315932-bit offset to symbol with PLT entry, relative to GOT. 3160@end deffn 3161@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 316232-bit offset to symbol with PLT entry, relative to this relocation. 3163@end deffn 3164@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3165@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3166@deffnx {} BFD_RELOC_CRIS_32_GD 3167@deffnx {} BFD_RELOC_CRIS_DTP 3168@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3169@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3170@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3171@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3172@deffnx {} BFD_RELOC_CRIS_32_TPREL 3173@deffnx {} BFD_RELOC_CRIS_16_TPREL 3174@deffnx {} BFD_RELOC_CRIS_DTPMOD 3175@deffnx {} BFD_RELOC_CRIS_32_IE 3176Relocs used in TLS code for CRIS. 3177@end deffn 3178@deffn {} BFD_RELOC_860_COPY 3179@deffnx {} BFD_RELOC_860_GLOB_DAT 3180@deffnx {} BFD_RELOC_860_JUMP_SLOT 3181@deffnx {} BFD_RELOC_860_RELATIVE 3182@deffnx {} BFD_RELOC_860_PC26 3183@deffnx {} BFD_RELOC_860_PLT26 3184@deffnx {} BFD_RELOC_860_PC16 3185@deffnx {} BFD_RELOC_860_LOW0 3186@deffnx {} BFD_RELOC_860_SPLIT0 3187@deffnx {} BFD_RELOC_860_LOW1 3188@deffnx {} BFD_RELOC_860_SPLIT1 3189@deffnx {} BFD_RELOC_860_LOW2 3190@deffnx {} BFD_RELOC_860_SPLIT2 3191@deffnx {} BFD_RELOC_860_LOW3 3192@deffnx {} BFD_RELOC_860_LOGOT0 3193@deffnx {} BFD_RELOC_860_SPGOT0 3194@deffnx {} BFD_RELOC_860_LOGOT1 3195@deffnx {} BFD_RELOC_860_SPGOT1 3196@deffnx {} BFD_RELOC_860_LOGOTOFF0 3197@deffnx {} BFD_RELOC_860_SPGOTOFF0 3198@deffnx {} BFD_RELOC_860_LOGOTOFF1 3199@deffnx {} BFD_RELOC_860_SPGOTOFF1 3200@deffnx {} BFD_RELOC_860_LOGOTOFF2 3201@deffnx {} BFD_RELOC_860_LOGOTOFF3 3202@deffnx {} BFD_RELOC_860_LOPC 3203@deffnx {} BFD_RELOC_860_HIGHADJ 3204@deffnx {} BFD_RELOC_860_HAGOT 3205@deffnx {} BFD_RELOC_860_HAGOTOFF 3206@deffnx {} BFD_RELOC_860_HAPC 3207@deffnx {} BFD_RELOC_860_HIGH 3208@deffnx {} BFD_RELOC_860_HIGOT 3209@deffnx {} BFD_RELOC_860_HIGOTOFF 3210Intel i860 Relocations. 3211@end deffn 3212@deffn {} BFD_RELOC_OR1K_REL_26 3213@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3214@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3215@deffnx {} BFD_RELOC_OR1K_GOT16 3216@deffnx {} BFD_RELOC_OR1K_PLT26 3217@deffnx {} BFD_RELOC_OR1K_GOTOFF_HI16 3218@deffnx {} BFD_RELOC_OR1K_GOTOFF_LO16 3219@deffnx {} BFD_RELOC_OR1K_COPY 3220@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3221@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3222@deffnx {} BFD_RELOC_OR1K_RELATIVE 3223@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3224@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3225@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3226@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3227@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3228@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3229@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3230@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3231@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3232@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3233@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3234@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3235@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3236OpenRISC 1000 Relocations. 3237@end deffn 3238@deffn {} BFD_RELOC_H8_DIR16A8 3239@deffnx {} BFD_RELOC_H8_DIR16R8 3240@deffnx {} BFD_RELOC_H8_DIR24A8 3241@deffnx {} BFD_RELOC_H8_DIR24R8 3242@deffnx {} BFD_RELOC_H8_DIR32A16 3243@deffnx {} BFD_RELOC_H8_DISP32A16 3244H8 elf Relocations. 3245@end deffn 3246@deffn {} BFD_RELOC_XSTORMY16_REL_12 3247@deffnx {} BFD_RELOC_XSTORMY16_12 3248@deffnx {} BFD_RELOC_XSTORMY16_24 3249@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3250Sony Xstormy16 Relocations. 3251@end deffn 3252@deffn {} BFD_RELOC_RELC 3253Self-describing complex relocations. 3254@end deffn 3255@deffn {} BFD_RELOC_XC16X_PAG 3256@deffnx {} BFD_RELOC_XC16X_POF 3257@deffnx {} BFD_RELOC_XC16X_SEG 3258@deffnx {} BFD_RELOC_XC16X_SOF 3259Infineon Relocations. 3260@end deffn 3261@deffn {} BFD_RELOC_VAX_GLOB_DAT 3262@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3263@deffnx {} BFD_RELOC_VAX_RELATIVE 3264Relocations used by VAX ELF. 3265@end deffn 3266@deffn {} BFD_RELOC_MT_PC16 3267Morpho MT - 16 bit immediate relocation. 3268@end deffn 3269@deffn {} BFD_RELOC_MT_HI16 3270Morpho MT - Hi 16 bits of an address. 3271@end deffn 3272@deffn {} BFD_RELOC_MT_LO16 3273Morpho MT - Low 16 bits of an address. 3274@end deffn 3275@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3276Morpho MT - Used to tell the linker which vtable entries are used. 3277@end deffn 3278@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3279Morpho MT - Used to tell the linker which vtable entries are used. 3280@end deffn 3281@deffn {} BFD_RELOC_MT_PCINSN8 3282Morpho MT - 8 bit immediate relocation. 3283@end deffn 3284@deffn {} BFD_RELOC_MSP430_10_PCREL 3285@deffnx {} BFD_RELOC_MSP430_16_PCREL 3286@deffnx {} BFD_RELOC_MSP430_16 3287@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3288@deffnx {} BFD_RELOC_MSP430_16_BYTE 3289@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3290@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3291@deffnx {} BFD_RELOC_MSP430_ABS8 3292@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3293@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3294@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3295@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3296@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3297@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3298@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3299@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3300@deffnx {} BFD_RELOC_MSP430X_PCR16 3301@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3302@deffnx {} BFD_RELOC_MSP430X_ABS16 3303@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3304@deffnx {} BFD_RELOC_MSP430_PREL31 3305@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3306msp430 specific relocation codes 3307@end deffn 3308@deffn {} BFD_RELOC_NIOS2_S16 3309@deffnx {} BFD_RELOC_NIOS2_U16 3310@deffnx {} BFD_RELOC_NIOS2_CALL26 3311@deffnx {} BFD_RELOC_NIOS2_IMM5 3312@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3313@deffnx {} BFD_RELOC_NIOS2_IMM6 3314@deffnx {} BFD_RELOC_NIOS2_IMM8 3315@deffnx {} BFD_RELOC_NIOS2_HI16 3316@deffnx {} BFD_RELOC_NIOS2_LO16 3317@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3318@deffnx {} BFD_RELOC_NIOS2_GPREL 3319@deffnx {} BFD_RELOC_NIOS2_UJMP 3320@deffnx {} BFD_RELOC_NIOS2_CJMP 3321@deffnx {} BFD_RELOC_NIOS2_CALLR 3322@deffnx {} BFD_RELOC_NIOS2_ALIGN 3323@deffnx {} BFD_RELOC_NIOS2_GOT16 3324@deffnx {} BFD_RELOC_NIOS2_CALL16 3325@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3326@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3327@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3328@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3329@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3330@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3331@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3332@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3333@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3334@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3335@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3336@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3337@deffnx {} BFD_RELOC_NIOS2_COPY 3338@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3339@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3340@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3341@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3342@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3343@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3344@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3345@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3346@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3347@deffnx {} BFD_RELOC_NIOS2_R2_S12 3348@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3349@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3350@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3351@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3352@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3353@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3354@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3355@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3356@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3357@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3358@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3359@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3360Relocations used by the Altera Nios II core. 3361@end deffn 3362@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3363@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3364@deffnx {} BFD_RELOC_IQ2000_UHI16 3365IQ2000 Relocations. 3366@end deffn 3367@deffn {} BFD_RELOC_XTENSA_RTLD 3368Special Xtensa relocation used only by PLT entries in ELF shared 3369objects to indicate that the runtime linker should set the value 3370to one of its own internal functions or data structures. 3371@end deffn 3372@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3373@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3374@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3375Xtensa relocations for ELF shared objects. 3376@end deffn 3377@deffn {} BFD_RELOC_XTENSA_PLT 3378Xtensa relocation used in ELF object files for symbols that may require 3379PLT entries. Otherwise, this is just a generic 32-bit relocation. 3380@end deffn 3381@deffn {} BFD_RELOC_XTENSA_DIFF8 3382@deffnx {} BFD_RELOC_XTENSA_DIFF16 3383@deffnx {} BFD_RELOC_XTENSA_DIFF32 3384Xtensa relocations to mark the difference of two local symbols. 3385These are only needed to support linker relaxation and can be ignored 3386when not relaxing. The field is set to the value of the difference 3387assuming no relaxation. The relocation encodes the position of the 3388first symbol so the linker can determine whether to adjust the field 3389value. 3390@end deffn 3391@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3392@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3393@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3394@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3395@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3396@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3397@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3398@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3399@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3400@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3401@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3402@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3403@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3404@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3405@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3406Generic Xtensa relocations for instruction operands. Only the slot 3407number is encoded in the relocation. The relocation applies to the 3408last PC-relative immediate operand, or if there are no PC-relative 3409immediates, to the last immediate operand. 3410@end deffn 3411@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3412@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3413@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3414@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3415@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3416@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3417@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3418@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3419@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3420@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3421@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3422@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3423@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3424@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3425@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3426Alternate Xtensa relocations. Only the slot is encoded in the 3427relocation. The meaning of these relocations is opcode-specific. 3428@end deffn 3429@deffn {} BFD_RELOC_XTENSA_OP0 3430@deffnx {} BFD_RELOC_XTENSA_OP1 3431@deffnx {} BFD_RELOC_XTENSA_OP2 3432Xtensa relocations for backward compatibility. These have all been 3433replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3434@end deffn 3435@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3436Xtensa relocation to mark that the assembler expanded the 3437instructions from an original target. The expansion size is 3438encoded in the reloc size. 3439@end deffn 3440@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3441Xtensa relocation to mark that the linker should simplify 3442assembler-expanded instructions. This is commonly used 3443internally by the linker after analysis of a 3444BFD_RELOC_XTENSA_ASM_EXPAND. 3445@end deffn 3446@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3447@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3448@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3449@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3450@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3451@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3452@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3453Xtensa TLS relocations. 3454@end deffn 3455@deffn {} BFD_RELOC_Z80_DISP8 34568 bit signed offset in (ix+d) or (iy+d). 3457@end deffn 3458@deffn {} BFD_RELOC_Z8K_DISP7 3459DJNZ offset. 3460@end deffn 3461@deffn {} BFD_RELOC_Z8K_CALLR 3462CALR offset. 3463@end deffn 3464@deffn {} BFD_RELOC_Z8K_IMM4L 34654 bit value. 3466@end deffn 3467@deffn {} BFD_RELOC_LM32_CALL 3468@deffnx {} BFD_RELOC_LM32_BRANCH 3469@deffnx {} BFD_RELOC_LM32_16_GOT 3470@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3471@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3472@deffnx {} BFD_RELOC_LM32_COPY 3473@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3474@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3475@deffnx {} BFD_RELOC_LM32_RELATIVE 3476Lattice Mico32 relocations. 3477@end deffn 3478@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3479Difference between two section addreses. Must be followed by a 3480BFD_RELOC_MACH_O_PAIR. 3481@end deffn 3482@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3483Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3484@end deffn 3485@deffn {} BFD_RELOC_MACH_O_PAIR 3486Pair of relocation. Contains the first symbol. 3487@end deffn 3488@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3489Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3490@end deffn 3491@deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3492Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3493@end deffn 3494@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3495@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3496PCREL relocations. They are marked as branch to create PLT entry if 3497required. 3498@end deffn 3499@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3500Used when referencing a GOT entry. 3501@end deffn 3502@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3503Used when loading a GOT entry with movq. It is specially marked so that 3504the linker could optimize the movq to a leaq if possible. 3505@end deffn 3506@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3507Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3508@end deffn 3509@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3510Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3511@end deffn 3512@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3513Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3514@end deffn 3515@deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3516Addend for PAGE or PAGEOFF. 3517@end deffn 3518@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3519Relative offset to page of GOT slot. 3520@end deffn 3521@deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3522Relative offset within page of GOT slot. 3523@end deffn 3524@deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3525Address of a GOT entry. 3526@end deffn 3527@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3528This is a 32 bit reloc for the microblaze that stores the 3529low 16 bits of a value 3530@end deffn 3531@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3532This is a 32 bit pc-relative reloc for the microblaze that 3533stores the low 16 bits of a value 3534@end deffn 3535@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3536This is a 32 bit reloc for the microblaze that stores a 3537value relative to the read-only small data area anchor 3538@end deffn 3539@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3540This is a 32 bit reloc for the microblaze that stores a 3541value relative to the read-write small data area anchor 3542@end deffn 3543@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3544This is a 32 bit reloc for the microblaze to handle 3545expressions of the form "Symbol Op Symbol" 3546@end deffn 3547@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3548This is a 64 bit reloc that stores the 32 bit pc relative 3549value in two words (with an imm instruction). No relocation is 3550done here - only used for relaxing 3551@end deffn 3552@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3553This is a 64 bit reloc that stores the 32 bit pc relative 3554value in two words (with an imm instruction). The relocation is 3555PC-relative GOT offset 3556@end deffn 3557@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3558This is a 64 bit reloc that stores the 32 bit pc relative 3559value in two words (with an imm instruction). The relocation is 3560GOT offset 3561@end deffn 3562@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3563This is a 64 bit reloc that stores the 32 bit pc relative 3564value in two words (with an imm instruction). The relocation is 3565PC-relative offset into PLT 3566@end deffn 3567@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3568This is a 64 bit reloc that stores the 32 bit GOT relative 3569value in two words (with an imm instruction). The relocation is 3570relative offset from _GLOBAL_OFFSET_TABLE_ 3571@end deffn 3572@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3573This is a 32 bit reloc that stores the 32 bit GOT relative 3574value in a word. The relocation is relative offset from 3575@end deffn 3576@deffn {} BFD_RELOC_MICROBLAZE_COPY 3577This is used to tell the dynamic linker to copy the value out of 3578the dynamic object into the runtime process image. 3579@end deffn 3580@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3581Unused Reloc 3582@end deffn 3583@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3584This is a 64 bit reloc that stores the 32 bit GOT relative value 3585of the GOT TLS GD info entry in two words (with an imm instruction). The 3586relocation is GOT offset. 3587@end deffn 3588@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3589This is a 64 bit reloc that stores the 32 bit GOT relative value 3590of the GOT TLS LD info entry in two words (with an imm instruction). The 3591relocation is GOT offset. 3592@end deffn 3593@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3594This is a 32 bit reloc that stores the Module ID to GOT(n). 3595@end deffn 3596@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3597This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3598@end deffn 3599@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3600This is a 32 bit reloc for storing TLS offset to two words (uses imm 3601instruction) 3602@end deffn 3603@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3604This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3605to two words (uses imm instruction). 3606@end deffn 3607@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3608This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3609to two words (uses imm instruction). 3610@end deffn 3611@deffn {} BFD_RELOC_AARCH64_RELOC_START 3612AArch64 pseudo relocation code to mark the start of the AArch64 3613relocation enumerators. N.B. the order of the enumerators is 3614important as several tables in the AArch64 bfd backend are indexed 3615by these enumerators; make sure they are all synced. 3616@end deffn 3617@deffn {} BFD_RELOC_AARCH64_NULL 3618Deprecated AArch64 null relocation code. 3619@end deffn 3620@deffn {} BFD_RELOC_AARCH64_NONE 3621AArch64 null relocation code. 3622@end deffn 3623@deffn {} BFD_RELOC_AARCH64_64 3624@deffnx {} BFD_RELOC_AARCH64_32 3625@deffnx {} BFD_RELOC_AARCH64_16 3626Basic absolute relocations of N bits. These are equivalent to 3627BFD_RELOC_N and they were added to assist the indexing of the howto 3628table. 3629@end deffn 3630@deffn {} BFD_RELOC_AARCH64_64_PCREL 3631@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3632@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3633PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3634and they were added to assist the indexing of the howto table. 3635@end deffn 3636@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3637AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3638of an unsigned address/value. 3639@end deffn 3640@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3641AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3642an address/value. No overflow checking. 3643@end deffn 3644@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3645AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3646of an unsigned address/value. 3647@end deffn 3648@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3649AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3650of an address/value. No overflow checking. 3651@end deffn 3652@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3653AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3654of an unsigned address/value. 3655@end deffn 3656@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3657AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3658of an address/value. No overflow checking. 3659@end deffn 3660@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3661AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3662of a signed or unsigned address/value. 3663@end deffn 3664@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3665AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3666of a signed value. Changes instruction to MOVZ or MOVN depending on the 3667value's sign. 3668@end deffn 3669@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3670AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3671of a signed value. Changes instruction to MOVZ or MOVN depending on the 3672value's sign. 3673@end deffn 3674@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3675AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3676of a signed value. Changes instruction to MOVZ or MOVN depending on the 3677value's sign. 3678@end deffn 3679@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3680AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3681offset. The lowest two bits must be zero and are not stored in the 3682instruction, giving a 21 bit signed byte offset. 3683@end deffn 3684@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3685AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3686@end deffn 3687@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3688AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3689offset, giving a 4KB aligned page base address. 3690@end deffn 3691@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3692AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3693offset, giving a 4KB aligned page base address, but with no overflow 3694checking. 3695@end deffn 3696@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3697AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3698Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3699@end deffn 3700@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3701AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3702address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3703@end deffn 3704@deffn {} BFD_RELOC_AARCH64_TSTBR14 3705AArch64 14 bit pc-relative test bit and branch. 3706The lowest two bits must be zero and are not stored in the instruction, 3707giving a 16 bit signed byte offset. 3708@end deffn 3709@deffn {} BFD_RELOC_AARCH64_BRANCH19 3710AArch64 19 bit pc-relative conditional branch and compare & branch. 3711The lowest two bits must be zero and are not stored in the instruction, 3712giving a 21 bit signed byte offset. 3713@end deffn 3714@deffn {} BFD_RELOC_AARCH64_JUMP26 3715AArch64 26 bit pc-relative unconditional branch. 3716The lowest two bits must be zero and are not stored in the instruction, 3717giving a 28 bit signed byte offset. 3718@end deffn 3719@deffn {} BFD_RELOC_AARCH64_CALL26 3720AArch64 26 bit pc-relative unconditional branch and link. 3721The lowest two bits must be zero and are not stored in the instruction, 3722giving a 28 bit signed byte offset. 3723@end deffn 3724@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3725AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3726address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3727@end deffn 3728@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3729AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3730address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3731@end deffn 3732@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3733AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3734address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3735@end deffn 3736@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3737AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3738address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3739@end deffn 3740@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3741AArch64 Load Literal instruction, holding a 19 bit PC relative word 3742offset of the global offset table entry for a symbol. The lowest two 3743bits must be zero and are not stored in the instruction, giving a 21 3744bit signed byte offset. This relocation type requires signed overflow 3745checking. 3746@end deffn 3747@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3748Get to the page base of the global offset table entry for a symbol as 3749part of an ADRP instruction using a 21 bit PC relative value.Used in 3750conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3751@end deffn 3752@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3753Unsigned 12 bit byte offset for 64 bit load/store from the page of 3754the GOT entry for this symbol. Used in conjunction with 3755BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only. 3756@end deffn 3757@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3758Unsigned 12 bit byte offset for 32 bit load/store from the page of 3759the GOT entry for this symbol. Used in conjunction with 3760BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only. 3761@end deffn 3762@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3763Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3764for this symbol. Valid in LP64 ABI only. 3765@end deffn 3766@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3767Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3768for this symbol. Valid in LP64 ABI only. 3769@end deffn 3770@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3771Unsigned 15 bit byte offset for 64 bit load/store from the page of 3772the GOT entry for this symbol. Valid in LP64 ABI only. 3773@end deffn 3774@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3775Scaled 14 bit byte offset to the page base of the global offset table. 3776@end deffn 3777@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3778Scaled 15 bit byte offset to the page base of the global offset table. 3779@end deffn 3780@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3781Get to the page base of the global offset table entry for a symbols 3782tls_index structure as part of an adrp instruction using a 21 bit PC 3783relative value. Used in conjunction with 3784BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3785@end deffn 3786@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3787AArch64 TLS General Dynamic 3788@end deffn 3789@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3790Unsigned 12 bit byte offset to global offset table entry for a symbols 3791tls_index structure. Used in conjunction with 3792BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3793@end deffn 3794@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3795AArch64 TLS General Dynamic relocation. 3796@end deffn 3797@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3798AArch64 TLS General Dynamic relocation. 3799@end deffn 3800@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3801AArch64 TLS INITIAL EXEC relocation. 3802@end deffn 3803@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3804AArch64 TLS INITIAL EXEC relocation. 3805@end deffn 3806@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3807AArch64 TLS INITIAL EXEC relocation. 3808@end deffn 3809@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3810AArch64 TLS INITIAL EXEC relocation. 3811@end deffn 3812@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3813AArch64 TLS INITIAL EXEC relocation. 3814@end deffn 3815@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3816AArch64 TLS INITIAL EXEC relocation. 3817@end deffn 3818@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3819bit[23:12] of byte offset to module TLS base address. 3820@end deffn 3821@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3822Unsigned 12 bit byte offset to module TLS base address. 3823@end deffn 3824@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3825No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3826@end deffn 3827@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3828Unsigned 12 bit byte offset to global offset table entry for a symbols 3829tls_index structure. Used in conjunction with 3830BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3831@end deffn 3832@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3833GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3834instruction. 3835@end deffn 3836@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3837GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 3838@end deffn 3839@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 3840bit[11:1] of byte offset to module TLS base address, encoded in ldst 3841instructions. 3842@end deffn 3843@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 3844Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 3845@end deffn 3846@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 3847bit[11:2] of byte offset to module TLS base address, encoded in ldst 3848instructions. 3849@end deffn 3850@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 3851Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 3852@end deffn 3853@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 3854bit[11:3] of byte offset to module TLS base address, encoded in ldst 3855instructions. 3856@end deffn 3857@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 3858Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 3859@end deffn 3860@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 3861bit[11:0] of byte offset to module TLS base address, encoded in ldst 3862instructions. 3863@end deffn 3864@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 3865Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 3866@end deffn 3867@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3868bit[15:0] of byte offset to module TLS base address. 3869@end deffn 3870@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 3871No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3872@end deffn 3873@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3874bit[31:16] of byte offset to module TLS base address. 3875@end deffn 3876@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 3877No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3878@end deffn 3879@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 3880bit[47:32] of byte offset to module TLS base address. 3881@end deffn 3882@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 3883AArch64 TLS LOCAL EXEC relocation. 3884@end deffn 3885@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 3886AArch64 TLS LOCAL EXEC relocation. 3887@end deffn 3888@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 3889AArch64 TLS LOCAL EXEC relocation. 3890@end deffn 3891@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 3892AArch64 TLS LOCAL EXEC relocation. 3893@end deffn 3894@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 3895AArch64 TLS LOCAL EXEC relocation. 3896@end deffn 3897@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 3898AArch64 TLS LOCAL EXEC relocation. 3899@end deffn 3900@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 3901AArch64 TLS LOCAL EXEC relocation. 3902@end deffn 3903@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 3904AArch64 TLS LOCAL EXEC relocation. 3905@end deffn 3906@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 3907AArch64 TLS DESC relocation. 3908@end deffn 3909@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 3910AArch64 TLS DESC relocation. 3911@end deffn 3912@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 3913AArch64 TLS DESC relocation. 3914@end deffn 3915@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC 3916AArch64 TLS DESC relocation. 3917@end deffn 3918@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 3919AArch64 TLS DESC relocation. 3920@end deffn 3921@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC 3922AArch64 TLS DESC relocation. 3923@end deffn 3924@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 3925AArch64 TLS DESC relocation. 3926@end deffn 3927@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 3928AArch64 TLS DESC relocation. 3929@end deffn 3930@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 3931AArch64 TLS DESC relocation. 3932@end deffn 3933@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 3934AArch64 TLS DESC relocation. 3935@end deffn 3936@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 3937AArch64 TLS DESC relocation. 3938@end deffn 3939@deffn {} BFD_RELOC_AARCH64_COPY 3940AArch64 TLS relocation. 3941@end deffn 3942@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 3943AArch64 TLS relocation. 3944@end deffn 3945@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 3946AArch64 TLS relocation. 3947@end deffn 3948@deffn {} BFD_RELOC_AARCH64_RELATIVE 3949AArch64 TLS relocation. 3950@end deffn 3951@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 3952AArch64 TLS relocation. 3953@end deffn 3954@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 3955AArch64 TLS relocation. 3956@end deffn 3957@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 3958AArch64 TLS relocation. 3959@end deffn 3960@deffn {} BFD_RELOC_AARCH64_TLSDESC 3961AArch64 TLS relocation. 3962@end deffn 3963@deffn {} BFD_RELOC_AARCH64_IRELATIVE 3964AArch64 support for STT_GNU_IFUNC. 3965@end deffn 3966@deffn {} BFD_RELOC_AARCH64_RELOC_END 3967AArch64 pseudo relocation code to mark the end of the AArch64 3968relocation enumerators that have direct mapping to ELF reloc codes. 3969There are a few more enumerators after this one; those are mainly 3970used by the AArch64 assembler for the internal fixup or to select 3971one of the above enumerators. 3972@end deffn 3973@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 3974AArch64 pseudo relocation code to be used internally by the AArch64 3975assembler and not (currently) written to any object files. 3976@end deffn 3977@deffn {} BFD_RELOC_AARCH64_LDST_LO12 3978AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 3979address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3980@end deffn 3981@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 3982AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 3983used internally by the AArch64 assembler and not (currently) written to 3984any object files. 3985@end deffn 3986@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 3987Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 3988@end deffn 3989@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 3990AArch64 pseudo relocation code to be used internally by the AArch64 3991assembler and not (currently) written to any object files. 3992@end deffn 3993@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 3994AArch64 pseudo relocation code to be used internally by the AArch64 3995assembler and not (currently) written to any object files. 3996@end deffn 3997@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 3998AArch64 pseudo relocation code to be used internally by the AArch64 3999assembler and not (currently) written to any object files. 4000@end deffn 4001@deffn {} BFD_RELOC_TILEPRO_COPY 4002@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4003@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4004@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4005@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4006@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4007@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4008@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4009@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4010@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4011@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4012@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4013@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4014@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4015@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4016@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4017@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4018@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4019@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4020@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4021@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4022@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4023@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4024@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4025@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4026@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4027@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4028@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4029@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4030@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4031@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4032@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4033@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4034@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4035@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4036@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4037@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4038@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4039@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4040@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4041@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4042@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4043@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4044@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4045@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4046@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4047@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4048@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4049@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4050@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4051@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4052@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4053@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4054@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4055@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4056@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4057@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4058@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4059@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4060@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4061@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4062@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4063@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4064@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4065@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4066@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4067@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4068@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4069@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4070@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4071@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4072@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4073@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4074@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4075@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4076@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4077@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4078@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4079@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4080Tilera TILEPro Relocations. 4081@end deffn 4082@deffn {} BFD_RELOC_TILEGX_HW0 4083@deffnx {} BFD_RELOC_TILEGX_HW1 4084@deffnx {} BFD_RELOC_TILEGX_HW2 4085@deffnx {} BFD_RELOC_TILEGX_HW3 4086@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4087@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4088@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4089@deffnx {} BFD_RELOC_TILEGX_COPY 4090@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4091@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4092@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4093@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4094@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4095@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4096@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4097@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4098@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4099@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4100@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4101@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4102@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4103@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4104@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4105@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4106@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4107@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4108@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4109@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4110@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4111@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4112@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4113@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4114@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4115@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4116@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4117@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4118@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4119@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4120@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4121@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4122@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4123@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4124@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4125@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4126@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4127@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4128@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4129@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4130@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4131@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4132@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4133@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4134@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4135@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4136@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4137@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4138@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4139@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4140@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4141@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4142@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4143@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4144@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4145@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4146@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4147@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4148@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4149@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4150@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4151@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4152@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4153@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4154@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4155@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4156@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4157@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4158@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4159@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4160@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4161@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4162@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4163@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4164@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4165@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4166@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4167@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4168@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4169@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4170@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4171@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4172@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4173@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4174@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4175@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4176@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4177@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4178@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4179@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4180@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4181@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4182@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4183@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4184@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4185@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4186@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4187@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4188@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4189@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4190@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4191Tilera TILE-Gx Relocations. 4192@end deffn 4193@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4194Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4195@end deffn 4196@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4197Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4198@end deffn 4199@deffn {} BFD_RELOC_EPIPHANY_HIGH 4200Adapteva EPIPHANY - 16 most-significant bits of absolute address 4201@end deffn 4202@deffn {} BFD_RELOC_EPIPHANY_LOW 4203Adapteva EPIPHANY - 16 least-significant bits of absolute address 4204@end deffn 4205@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4206Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4207@end deffn 4208@deffn {} BFD_RELOC_EPIPHANY_IMM11 4209Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4210@end deffn 4211@deffn {} BFD_RELOC_EPIPHANY_IMM8 4212Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4213@end deffn 4214@deffn {} BFD_RELOC_VISIUM_HI16 4215@deffnx {} BFD_RELOC_VISIUM_LO16 4216@deffnx {} BFD_RELOC_VISIUM_IM16 4217@deffnx {} BFD_RELOC_VISIUM_REL16 4218@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4219@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4220@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4221Visium Relocations. 4222@end deffn 4223 4224@example 4225 4226typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4227@end example 4228@findex bfd_reloc_type_lookup 4229@subsubsection @code{bfd_reloc_type_lookup} 4230@strong{Synopsis} 4231@example 4232reloc_howto_type *bfd_reloc_type_lookup 4233 (bfd *abfd, bfd_reloc_code_real_type code); 4234reloc_howto_type *bfd_reloc_name_lookup 4235 (bfd *abfd, const char *reloc_name); 4236@end example 4237@strong{Description}@* 4238Return a pointer to a howto structure which, when 4239invoked, will perform the relocation @var{code} on data from the 4240architecture noted. 4241 4242@findex bfd_default_reloc_type_lookup 4243@subsubsection @code{bfd_default_reloc_type_lookup} 4244@strong{Synopsis} 4245@example 4246reloc_howto_type *bfd_default_reloc_type_lookup 4247 (bfd *abfd, bfd_reloc_code_real_type code); 4248@end example 4249@strong{Description}@* 4250Provides a default relocation lookup routine for any architecture. 4251 4252@findex bfd_get_reloc_code_name 4253@subsubsection @code{bfd_get_reloc_code_name} 4254@strong{Synopsis} 4255@example 4256const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4257@end example 4258@strong{Description}@* 4259Provides a printable name for the supplied relocation code. 4260Useful mainly for printing error messages. 4261 4262@findex bfd_generic_relax_section 4263@subsubsection @code{bfd_generic_relax_section} 4264@strong{Synopsis} 4265@example 4266bfd_boolean bfd_generic_relax_section 4267 (bfd *abfd, 4268 asection *section, 4269 struct bfd_link_info *, 4270 bfd_boolean *); 4271@end example 4272@strong{Description}@* 4273Provides default handling for relaxing for back ends which 4274don't do relaxing. 4275 4276@findex bfd_generic_gc_sections 4277@subsubsection @code{bfd_generic_gc_sections} 4278@strong{Synopsis} 4279@example 4280bfd_boolean bfd_generic_gc_sections 4281 (bfd *, struct bfd_link_info *); 4282@end example 4283@strong{Description}@* 4284Provides default handling for relaxing for back ends which 4285don't do section gc -- i.e., does nothing. 4286 4287@findex bfd_generic_lookup_section_flags 4288@subsubsection @code{bfd_generic_lookup_section_flags} 4289@strong{Synopsis} 4290@example 4291bfd_boolean bfd_generic_lookup_section_flags 4292 (struct bfd_link_info *, struct flag_info *, asection *); 4293@end example 4294@strong{Description}@* 4295Provides default handling for section flags lookup 4296-- i.e., does nothing. 4297Returns FALSE if the section should be omitted, otherwise TRUE. 4298 4299@findex bfd_generic_merge_sections 4300@subsubsection @code{bfd_generic_merge_sections} 4301@strong{Synopsis} 4302@example 4303bfd_boolean bfd_generic_merge_sections 4304 (bfd *, struct bfd_link_info *); 4305@end example 4306@strong{Description}@* 4307Provides default handling for SEC_MERGE section merging for back ends 4308which don't have SEC_MERGE support -- i.e., does nothing. 4309 4310@findex bfd_generic_get_relocated_section_contents 4311@subsubsection @code{bfd_generic_get_relocated_section_contents} 4312@strong{Synopsis} 4313@example 4314bfd_byte *bfd_generic_get_relocated_section_contents 4315 (bfd *abfd, 4316 struct bfd_link_info *link_info, 4317 struct bfd_link_order *link_order, 4318 bfd_byte *data, 4319 bfd_boolean relocatable, 4320 asymbol **symbols); 4321@end example 4322@strong{Description}@* 4323Provides default handling of relocation effort for back ends 4324which can't be bothered to do it efficiently. 4325 4326