reloc.texi revision 1.3
1@section Relocations 2BFD maintains relocations in much the same way it maintains 3symbols: they are left alone until required, then read in 4en-masse and translated into an internal form. A common 5routine @code{bfd_perform_relocation} acts upon the 6canonical form to do the fixup. 7 8Relocations are maintained on a per section basis, 9while symbols are maintained on a per BFD basis. 10 11All that a back end has to do to fit the BFD interface is to create 12a @code{struct reloc_cache_entry} for each relocation 13in a particular section, and fill in the right bits of the structures. 14 15@menu 16* typedef arelent:: 17* howto manager:: 18@end menu 19 20 21@node typedef arelent, howto manager, Relocations, Relocations 22@subsection typedef arelent 23This is the structure of a relocation entry: 24 25 26@example 27 28typedef enum bfd_reloc_status 29@{ 30 /* No errors detected. */ 31 bfd_reloc_ok, 32 33 /* The relocation was performed, but there was an overflow. */ 34 bfd_reloc_overflow, 35 36 /* The address to relocate was not within the section supplied. */ 37 bfd_reloc_outofrange, 38 39 /* Used by special functions. */ 40 bfd_reloc_continue, 41 42 /* Unsupported relocation size requested. */ 43 bfd_reloc_notsupported, 44 45 /* Unused. */ 46 bfd_reloc_other, 47 48 /* The symbol to relocate against was undefined. */ 49 bfd_reloc_undefined, 50 51 /* The relocation was performed, but may not be ok - presently 52 generated only when linking i960 coff files with i960 b.out 53 symbols. If this type is returned, the error_message argument 54 to bfd_perform_relocation will be set. */ 55 bfd_reloc_dangerous 56 @} 57 bfd_reloc_status_type; 58 59 60typedef struct reloc_cache_entry 61@{ 62 /* A pointer into the canonical table of pointers. */ 63 struct bfd_symbol **sym_ptr_ptr; 64 65 /* offset in section. */ 66 bfd_size_type address; 67 68 /* addend for relocation value. */ 69 bfd_vma addend; 70 71 /* Pointer to how to perform the required relocation. */ 72 reloc_howto_type *howto; 73 74@} 75arelent; 76 77@end example 78@strong{Description}@* 79Here is a description of each of the fields within an @code{arelent}: 80 81@itemize @bullet 82 83@item 84@code{sym_ptr_ptr} 85@end itemize 86The symbol table pointer points to a pointer to the symbol 87associated with the relocation request. It is the pointer 88into the table returned by the back end's 89@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 90referenced through a pointer to a pointer so that tools like 91the linker can fix up all the symbols of the same name by 92modifying only one pointer. The relocation routine looks in 93the symbol and uses the base of the section the symbol is 94attached to and the value of the symbol as the initial 95relocation offset. If the symbol pointer is zero, then the 96section provided is looked up. 97 98@itemize @bullet 99 100@item 101@code{address} 102@end itemize 103The @code{address} field gives the offset in bytes from the base of 104the section data which owns the relocation record to the first 105byte of relocatable information. The actual data relocated 106will be relative to this point; for example, a relocation 107type which modifies the bottom two bytes of a four byte word 108would not touch the first byte pointed to in a big endian 109world. 110 111@itemize @bullet 112 113@item 114@code{addend} 115@end itemize 116The @code{addend} is a value provided by the back end to be added (!) 117to the relocation offset. Its interpretation is dependent upon 118the howto. For example, on the 68k the code: 119 120@example 121 char foo[]; 122 main() 123 @{ 124 return foo[0x12345678]; 125 @} 126@end example 127 128Could be compiled into: 129 130@example 131 linkw fp,#-4 132 moveb @@#12345678,d0 133 extbl d0 134 unlk fp 135 rts 136@end example 137 138This could create a reloc pointing to @code{foo}, but leave the 139offset in the data, something like: 140 141@example 142RELOCATION RECORDS FOR [.text]: 143offset type value 14400000006 32 _foo 145 14600000000 4e56 fffc ; linkw fp,#-4 14700000004 1039 1234 5678 ; moveb @@#12345678,d0 1480000000a 49c0 ; extbl d0 1490000000c 4e5e ; unlk fp 1500000000e 4e75 ; rts 151@end example 152 153Using coff and an 88k, some instructions don't have enough 154space in them to represent the full address range, and 155pointers have to be loaded in two parts. So you'd get something like: 156 157@example 158 or.u r13,r0,hi16(_foo+0x12345678) 159 ld.b r2,r13,lo16(_foo+0x12345678) 160 jmp r1 161@end example 162 163This should create two relocs, both pointing to @code{_foo}, and with 1640x12340000 in their addend field. The data would consist of: 165 166@example 167RELOCATION RECORDS FOR [.text]: 168offset type value 16900000002 HVRT16 _foo+0x12340000 17000000006 LVRT16 _foo+0x12340000 171 17200000000 5da05678 ; or.u r13,r0,0x5678 17300000004 1c4d5678 ; ld.b r2,r13,0x5678 17400000008 f400c001 ; jmp r1 175@end example 176 177The relocation routine digs out the value from the data, adds 178it to the addend to get the original offset, and then adds the 179value of @code{_foo}. Note that all 32 bits have to be kept around 180somewhere, to cope with carry from bit 15 to bit 16. 181 182One further example is the sparc and the a.out format. The 183sparc has a similar problem to the 88k, in that some 184instructions don't have room for an entire offset, but on the 185sparc the parts are created in odd sized lumps. The designers of 186the a.out format chose to not use the data within the section 187for storing part of the offset; all the offset is kept within 188the reloc. Anything in the data should be ignored. 189 190@example 191 save %sp,-112,%sp 192 sethi %hi(_foo+0x12345678),%g2 193 ldsb [%g2+%lo(_foo+0x12345678)],%i0 194 ret 195 restore 196@end example 197 198Both relocs contain a pointer to @code{foo}, and the offsets 199contain junk. 200 201@example 202RELOCATION RECORDS FOR [.text]: 203offset type value 20400000004 HI22 _foo+0x12345678 20500000008 LO10 _foo+0x12345678 206 20700000000 9de3bf90 ; save %sp,-112,%sp 20800000004 05000000 ; sethi %hi(_foo+0),%g2 20900000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 2100000000c 81c7e008 ; ret 21100000010 81e80000 ; restore 212@end example 213 214@itemize @bullet 215 216@item 217@code{howto} 218@end itemize 219The @code{howto} field can be imagined as a 220relocation instruction. It is a pointer to a structure which 221contains information on what to do with all of the other 222information in the reloc record and data section. A back end 223would normally have a relocation instruction set and turn 224relocations into pointers to the correct structure on input - 225but it would be possible to create each howto field on demand. 226 227@subsubsection @code{enum complain_overflow} 228Indicates what sort of overflow checking should be done when 229performing a relocation. 230 231 232@example 233 234enum complain_overflow 235@{ 236 /* Do not complain on overflow. */ 237 complain_overflow_dont, 238 239 /* Complain if the value overflows when considered as a signed 240 number one bit larger than the field. ie. A bitfield of N bits 241 is allowed to represent -2**n to 2**n-1. */ 242 complain_overflow_bitfield, 243 244 /* Complain if the value overflows when considered as a signed 245 number. */ 246 complain_overflow_signed, 247 248 /* Complain if the value overflows when considered as an 249 unsigned number. */ 250 complain_overflow_unsigned 251@}; 252@end example 253@subsubsection @code{reloc_howto_type} 254The @code{reloc_howto_type} is a structure which contains all the 255information that libbfd needs to know to tie up a back end's data. 256 257 258@example 259struct bfd_symbol; /* Forward declaration. */ 260 261struct reloc_howto_struct 262@{ 263 /* The type field has mainly a documentary use - the back end can 264 do what it wants with it, though normally the back end's 265 external idea of what a reloc number is stored 266 in this field. For example, a PC relative word relocation 267 in a coff environment has the type 023 - because that's 268 what the outside world calls a R_PCRWORD reloc. */ 269 unsigned int type; 270 271 /* The value the final relocation is shifted right by. This drops 272 unwanted data from the relocation. */ 273 unsigned int rightshift; 274 275 /* The size of the item to be relocated. This is *not* a 276 power-of-two measure. To get the number of bytes operated 277 on by a type of relocation, use bfd_get_reloc_size. */ 278 int size; 279 280 /* The number of bits in the item to be relocated. This is used 281 when doing overflow checking. */ 282 unsigned int bitsize; 283 284 /* The relocation is relative to the field being relocated. */ 285 bfd_boolean pc_relative; 286 287 /* The bit position of the reloc value in the destination. 288 The relocated value is left shifted by this amount. */ 289 unsigned int bitpos; 290 291 /* What type of overflow error should be checked for when 292 relocating. */ 293 enum complain_overflow complain_on_overflow; 294 295 /* If this field is non null, then the supplied function is 296 called rather than the normal function. This allows really 297 strange relocation methods to be accommodated (e.g., i960 callj 298 instructions). */ 299 bfd_reloc_status_type (*special_function) 300 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 301 bfd *, char **); 302 303 /* The textual name of the relocation type. */ 304 char *name; 305 306 /* Some formats record a relocation addend in the section contents 307 rather than with the relocation. For ELF formats this is the 308 distinction between USE_REL and USE_RELA (though the code checks 309 for USE_REL == 1/0). The value of this field is TRUE if the 310 addend is recorded with the section contents; when performing a 311 partial link (ld -r) the section contents (the data) will be 312 modified. The value of this field is FALSE if addends are 313 recorded with the relocation (in arelent.addend); when performing 314 a partial link the relocation will be modified. 315 All relocations for all ELF USE_RELA targets should set this field 316 to FALSE (values of TRUE should be looked on with suspicion). 317 However, the converse is not true: not all relocations of all ELF 318 USE_REL targets set this field to TRUE. Why this is so is peculiar 319 to each particular target. For relocs that aren't used in partial 320 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 321 bfd_boolean partial_inplace; 322 323 /* src_mask selects the part of the instruction (or data) to be used 324 in the relocation sum. If the target relocations don't have an 325 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 326 dst_mask to extract the addend from the section contents. If 327 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 328 field should be zero. Non-zero values for ELF USE_RELA targets are 329 bogus as in those cases the value in the dst_mask part of the 330 section contents should be treated as garbage. */ 331 bfd_vma src_mask; 332 333 /* dst_mask selects which parts of the instruction (or data) are 334 replaced with a relocated value. */ 335 bfd_vma dst_mask; 336 337 /* When some formats create PC relative instructions, they leave 338 the value of the pc of the place being relocated in the offset 339 slot of the instruction, so that a PC relative relocation can 340 be made just by adding in an ordinary offset (e.g., sun3 a.out). 341 Some formats leave the displacement part of an instruction 342 empty (e.g., m88k bcs); this flag signals the fact. */ 343 bfd_boolean pcrel_offset; 344@}; 345 346@end example 347@findex The HOWTO Macro 348@subsubsection @code{The HOWTO Macro} 349@strong{Description}@* 350The HOWTO define is horrible and will go away. 351@example 352#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \ 353 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @} 354@end example 355 356@strong{Description}@* 357And will be replaced with the totally magic way. But for the 358moment, we are compatible, so do it this way. 359@example 360#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ 361 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ 362 NAME, FALSE, 0, 0, IN) 363 364@end example 365 366@strong{Description}@* 367This is used to fill in an empty howto entry in an array. 368@example 369#define EMPTY_HOWTO(C) \ 370 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ 371 NULL, FALSE, 0, 0, FALSE) 372 373@end example 374 375@strong{Description}@* 376Helper routine to turn a symbol into a relocation value. 377@example 378#define HOWTO_PREPARE(relocation, symbol) \ 379 @{ \ 380 if (symbol != NULL) \ 381 @{ \ 382 if (bfd_is_com_section (symbol->section)) \ 383 @{ \ 384 relocation = 0; \ 385 @} \ 386 else \ 387 @{ \ 388 relocation = symbol->value; \ 389 @} \ 390 @} \ 391 @} 392 393@end example 394 395@findex bfd_get_reloc_size 396@subsubsection @code{bfd_get_reloc_size} 397@strong{Synopsis} 398@example 399unsigned int bfd_get_reloc_size (reloc_howto_type *); 400@end example 401@strong{Description}@* 402For a reloc_howto_type that operates on a fixed number of bytes, 403this returns the number of bytes operated on. 404 405@findex arelent_chain 406@subsubsection @code{arelent_chain} 407@strong{Description}@* 408How relocs are tied together in an @code{asection}: 409@example 410typedef struct relent_chain 411@{ 412 arelent relent; 413 struct relent_chain *next; 414@} 415arelent_chain; 416 417@end example 418 419@findex bfd_check_overflow 420@subsubsection @code{bfd_check_overflow} 421@strong{Synopsis} 422@example 423bfd_reloc_status_type bfd_check_overflow 424 (enum complain_overflow how, 425 unsigned int bitsize, 426 unsigned int rightshift, 427 unsigned int addrsize, 428 bfd_vma relocation); 429@end example 430@strong{Description}@* 431Perform overflow checking on @var{relocation} which has 432@var{bitsize} significant bits and will be shifted right by 433@var{rightshift} bits, on a machine with addresses containing 434@var{addrsize} significant bits. The result is either of 435@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 436 437@findex bfd_perform_relocation 438@subsubsection @code{bfd_perform_relocation} 439@strong{Synopsis} 440@example 441bfd_reloc_status_type bfd_perform_relocation 442 (bfd *abfd, 443 arelent *reloc_entry, 444 void *data, 445 asection *input_section, 446 bfd *output_bfd, 447 char **error_message); 448@end example 449@strong{Description}@* 450If @var{output_bfd} is supplied to this function, the 451generated image will be relocatable; the relocations are 452copied to the output file after they have been changed to 453reflect the new state of the world. There are two ways of 454reflecting the results of partial linkage in an output file: 455by modifying the output data in place, and by modifying the 456relocation record. Some native formats (e.g., basic a.out and 457basic coff) have no way of specifying an addend in the 458relocation type, so the addend has to go in the output data. 459This is no big deal since in these formats the output data 460slot will always be big enough for the addend. Complex reloc 461types with addends were invented to solve just this problem. 462The @var{error_message} argument is set to an error message if 463this return @code{bfd_reloc_dangerous}. 464 465@findex bfd_install_relocation 466@subsubsection @code{bfd_install_relocation} 467@strong{Synopsis} 468@example 469bfd_reloc_status_type bfd_install_relocation 470 (bfd *abfd, 471 arelent *reloc_entry, 472 void *data, bfd_vma data_start, 473 asection *input_section, 474 char **error_message); 475@end example 476@strong{Description}@* 477This looks remarkably like @code{bfd_perform_relocation}, except it 478does not expect that the section contents have been filled in. 479I.e., it's suitable for use when creating, rather than applying 480a relocation. 481 482For now, this function should be considered reserved for the 483assembler. 484 485 486@node howto manager, , typedef arelent, Relocations 487@subsection The howto manager 488When an application wants to create a relocation, but doesn't 489know what the target machine might call it, it can find out by 490using this bit of code. 491 492@findex bfd_reloc_code_type 493@subsubsection @code{bfd_reloc_code_type} 494@strong{Description}@* 495The insides of a reloc code. The idea is that, eventually, there 496will be one enumerator for every type of relocation we ever do. 497Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 498return a howto pointer. 499 500This does mean that the application must determine the correct 501enumerator value; you can't get a howto pointer from a random set 502of attributes. 503 504Here are the possible values for @code{enum bfd_reloc_code_real}: 505 506@deffn {} BFD_RELOC_64 507@deffnx {} BFD_RELOC_32 508@deffnx {} BFD_RELOC_26 509@deffnx {} BFD_RELOC_24 510@deffnx {} BFD_RELOC_16 511@deffnx {} BFD_RELOC_14 512@deffnx {} BFD_RELOC_8 513Basic absolute relocations of N bits. 514@end deffn 515@deffn {} BFD_RELOC_64_PCREL 516@deffnx {} BFD_RELOC_32_PCREL 517@deffnx {} BFD_RELOC_24_PCREL 518@deffnx {} BFD_RELOC_16_PCREL 519@deffnx {} BFD_RELOC_12_PCREL 520@deffnx {} BFD_RELOC_8_PCREL 521PC-relative relocations. Sometimes these are relative to the address 522of the relocation itself; sometimes they are relative to the start of 523the section containing the relocation. It depends on the specific target. 524 525The 24-bit relocation is used in some Intel 960 configurations. 526@end deffn 527@deffn {} BFD_RELOC_32_SECREL 528Section relative relocations. Some targets need this for DWARF2. 529@end deffn 530@deffn {} BFD_RELOC_32_GOT_PCREL 531@deffnx {} BFD_RELOC_16_GOT_PCREL 532@deffnx {} BFD_RELOC_8_GOT_PCREL 533@deffnx {} BFD_RELOC_32_GOTOFF 534@deffnx {} BFD_RELOC_16_GOTOFF 535@deffnx {} BFD_RELOC_LO16_GOTOFF 536@deffnx {} BFD_RELOC_HI16_GOTOFF 537@deffnx {} BFD_RELOC_HI16_S_GOTOFF 538@deffnx {} BFD_RELOC_8_GOTOFF 539@deffnx {} BFD_RELOC_64_PLT_PCREL 540@deffnx {} BFD_RELOC_32_PLT_PCREL 541@deffnx {} BFD_RELOC_24_PLT_PCREL 542@deffnx {} BFD_RELOC_16_PLT_PCREL 543@deffnx {} BFD_RELOC_8_PLT_PCREL 544@deffnx {} BFD_RELOC_64_PLTOFF 545@deffnx {} BFD_RELOC_32_PLTOFF 546@deffnx {} BFD_RELOC_16_PLTOFF 547@deffnx {} BFD_RELOC_LO16_PLTOFF 548@deffnx {} BFD_RELOC_HI16_PLTOFF 549@deffnx {} BFD_RELOC_HI16_S_PLTOFF 550@deffnx {} BFD_RELOC_8_PLTOFF 551For ELF. 552@end deffn 553@deffn {} BFD_RELOC_SIZE32 554@deffnx {} BFD_RELOC_SIZE64 555Size relocations. 556@end deffn 557@deffn {} BFD_RELOC_68K_GLOB_DAT 558@deffnx {} BFD_RELOC_68K_JMP_SLOT 559@deffnx {} BFD_RELOC_68K_RELATIVE 560@deffnx {} BFD_RELOC_68K_TLS_GD32 561@deffnx {} BFD_RELOC_68K_TLS_GD16 562@deffnx {} BFD_RELOC_68K_TLS_GD8 563@deffnx {} BFD_RELOC_68K_TLS_LDM32 564@deffnx {} BFD_RELOC_68K_TLS_LDM16 565@deffnx {} BFD_RELOC_68K_TLS_LDM8 566@deffnx {} BFD_RELOC_68K_TLS_LDO32 567@deffnx {} BFD_RELOC_68K_TLS_LDO16 568@deffnx {} BFD_RELOC_68K_TLS_LDO8 569@deffnx {} BFD_RELOC_68K_TLS_IE32 570@deffnx {} BFD_RELOC_68K_TLS_IE16 571@deffnx {} BFD_RELOC_68K_TLS_IE8 572@deffnx {} BFD_RELOC_68K_TLS_LE32 573@deffnx {} BFD_RELOC_68K_TLS_LE16 574@deffnx {} BFD_RELOC_68K_TLS_LE8 575Relocations used by 68K ELF. 576@end deffn 577@deffn {} BFD_RELOC_VAX_GLOB_DAT 578@deffnx {} BFD_RELOC_VAX_GLOB_REF 579@deffnx {} BFD_RELOC_VAX_JMP_SLOT 580@deffnx {} BFD_RELOC_VAX_RELATIVE 581Relocations used by VAX ELF. 582@end deffn 583@deffn {} BFD_RELOC_32_BASEREL 584@deffnx {} BFD_RELOC_16_BASEREL 585@deffnx {} BFD_RELOC_LO16_BASEREL 586@deffnx {} BFD_RELOC_HI16_BASEREL 587@deffnx {} BFD_RELOC_HI16_S_BASEREL 588@deffnx {} BFD_RELOC_8_BASEREL 589@deffnx {} BFD_RELOC_RVA 590Linkage-table relative. 591@end deffn 592@deffn {} BFD_RELOC_8_FFnn 593Absolute 8-bit relocation, but used to form an address like 0xFFnn. 594@end deffn 595@deffn {} BFD_RELOC_32_PCREL_S2 596@deffnx {} BFD_RELOC_16_PCREL_S2 597@deffnx {} BFD_RELOC_23_PCREL_S2 598These PC-relative relocations are stored as word displacements -- 599i.e., byte displacements shifted right two bits. The 30-bit word 600displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 601SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 602signed 16-bit displacement is used on the MIPS, and the 23-bit 603displacement is used on the Alpha. 604@end deffn 605@deffn {} BFD_RELOC_HI22 606@deffnx {} BFD_RELOC_LO10 607High 22 bits and low 10 bits of 32-bit value, placed into lower bits of 608the target word. These are used on the SPARC. 609@end deffn 610@deffn {} BFD_RELOC_GPREL16 611@deffnx {} BFD_RELOC_GPREL32 612For systems that allocate a Global Pointer register, these are 613displacements off that register. These relocation types are 614handled specially, because the value the register will have is 615decided relatively late. 616@end deffn 617@deffn {} BFD_RELOC_I960_CALLJ 618Reloc types used for i960/b.out. 619@end deffn 620@deffn {} BFD_RELOC_NONE 621@deffnx {} BFD_RELOC_SPARC_WDISP22 622@deffnx {} BFD_RELOC_SPARC22 623@deffnx {} BFD_RELOC_SPARC13 624@deffnx {} BFD_RELOC_SPARC_GOT10 625@deffnx {} BFD_RELOC_SPARC_GOT13 626@deffnx {} BFD_RELOC_SPARC_GOT22 627@deffnx {} BFD_RELOC_SPARC_PC10 628@deffnx {} BFD_RELOC_SPARC_PC22 629@deffnx {} BFD_RELOC_SPARC_WPLT30 630@deffnx {} BFD_RELOC_SPARC_COPY 631@deffnx {} BFD_RELOC_SPARC_GLOB_DAT 632@deffnx {} BFD_RELOC_SPARC_JMP_SLOT 633@deffnx {} BFD_RELOC_SPARC_RELATIVE 634@deffnx {} BFD_RELOC_SPARC_UA16 635@deffnx {} BFD_RELOC_SPARC_UA32 636@deffnx {} BFD_RELOC_SPARC_UA64 637@deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 638@deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 639@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 640@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 641@deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 642@deffnx {} BFD_RELOC_SPARC_JMP_IREL 643@deffnx {} BFD_RELOC_SPARC_IRELATIVE 644SPARC ELF relocations. There is probably some overlap with other 645relocation types already defined. 646@end deffn 647@deffn {} BFD_RELOC_SPARC_BASE13 648@deffnx {} BFD_RELOC_SPARC_BASE22 649I think these are specific to SPARC a.out (e.g., Sun 4). 650@end deffn 651@deffn {} BFD_RELOC_SPARC_64 652@deffnx {} BFD_RELOC_SPARC_10 653@deffnx {} BFD_RELOC_SPARC_11 654@deffnx {} BFD_RELOC_SPARC_OLO10 655@deffnx {} BFD_RELOC_SPARC_HH22 656@deffnx {} BFD_RELOC_SPARC_HM10 657@deffnx {} BFD_RELOC_SPARC_LM22 658@deffnx {} BFD_RELOC_SPARC_PC_HH22 659@deffnx {} BFD_RELOC_SPARC_PC_HM10 660@deffnx {} BFD_RELOC_SPARC_PC_LM22 661@deffnx {} BFD_RELOC_SPARC_WDISP16 662@deffnx {} BFD_RELOC_SPARC_WDISP19 663@deffnx {} BFD_RELOC_SPARC_7 664@deffnx {} BFD_RELOC_SPARC_6 665@deffnx {} BFD_RELOC_SPARC_5 666@deffnx {} BFD_RELOC_SPARC_DISP64 667@deffnx {} BFD_RELOC_SPARC_PLT32 668@deffnx {} BFD_RELOC_SPARC_PLT64 669@deffnx {} BFD_RELOC_SPARC_HIX22 670@deffnx {} BFD_RELOC_SPARC_LOX10 671@deffnx {} BFD_RELOC_SPARC_H44 672@deffnx {} BFD_RELOC_SPARC_M44 673@deffnx {} BFD_RELOC_SPARC_L44 674@deffnx {} BFD_RELOC_SPARC_REGISTER 675@deffnx {} BFD_RELOC_SPARC_H34 676@deffnx {} BFD_RELOC_SPARC_SIZE32 677@deffnx {} BFD_RELOC_SPARC_SIZE64 678@deffnx {} BFD_RELOC_SPARC_WDISP10 679SPARC64 relocations 680@end deffn 681@deffn {} BFD_RELOC_SPARC_REV32 682SPARC little endian relocation 683@end deffn 684@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 685@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 686@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 687@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 688@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 689@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 690@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 691@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 692@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 693@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 694@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 695@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 696@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 697@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 698@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 699@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 700@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 701@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 702@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 703@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 704@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 705@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 706@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 707@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 708SPARC TLS relocations 709@end deffn 710@deffn {} BFD_RELOC_SPU_IMM7 711@deffnx {} BFD_RELOC_SPU_IMM8 712@deffnx {} BFD_RELOC_SPU_IMM10 713@deffnx {} BFD_RELOC_SPU_IMM10W 714@deffnx {} BFD_RELOC_SPU_IMM16 715@deffnx {} BFD_RELOC_SPU_IMM16W 716@deffnx {} BFD_RELOC_SPU_IMM18 717@deffnx {} BFD_RELOC_SPU_PCREL9a 718@deffnx {} BFD_RELOC_SPU_PCREL9b 719@deffnx {} BFD_RELOC_SPU_PCREL16 720@deffnx {} BFD_RELOC_SPU_LO16 721@deffnx {} BFD_RELOC_SPU_HI16 722@deffnx {} BFD_RELOC_SPU_PPU32 723@deffnx {} BFD_RELOC_SPU_PPU64 724@deffnx {} BFD_RELOC_SPU_ADD_PIC 725SPU Relocations. 726@end deffn 727@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 728Alpha ECOFF and ELF relocations. Some of these treat the symbol or 729"addend" in some special way. 730For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 731writing; when reading, it will be the absolute section symbol. The 732addend is the displacement in bytes of the "lda" instruction from 733the "ldah" instruction (which is at the address of this reloc). 734@end deffn 735@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 736For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 737with GPDISP_HI16 relocs. The addend is ignored when writing the 738relocations out, and is filled in with the file's GP value on 739reading, for convenience. 740@end deffn 741@deffn {} BFD_RELOC_ALPHA_GPDISP 742The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 743relocation except that there is no accompanying GPDISP_LO16 744relocation. 745@end deffn 746@deffn {} BFD_RELOC_ALPHA_LITERAL 747@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 748@deffnx {} BFD_RELOC_ALPHA_LITUSE 749The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 750the assembler turns it into a LDQ instruction to load the address of 751the symbol, and then fills in a register in the real instruction. 752 753The LITERAL reloc, at the LDQ instruction, refers to the .lita 754section symbol. The addend is ignored when writing, but is filled 755in with the file's GP value on reading, for convenience, as with the 756GPDISP_LO16 reloc. 757 758The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 759It should refer to the symbol to be referenced, as with 16_GOTOFF, 760but it generates output not based on the position within the .got 761section, but relative to the GP value chosen for the file during the 762final link stage. 763 764The LITUSE reloc, on the instruction using the loaded address, gives 765information to the linker that it might be able to use to optimize 766away some literal section references. The symbol is ignored (read 767as the absolute section symbol), and the "addend" indicates the type 768of instruction using the register: 7691 - "memory" fmt insn 7702 - byte-manipulation (byte offset reg) 7713 - jsr (target of branch) 772@end deffn 773@deffn {} BFD_RELOC_ALPHA_HINT 774The HINT relocation indicates a value that should be filled into the 775"hint" field of a jmp/jsr/ret instruction, for possible branch- 776prediction logic which may be provided on some processors. 777@end deffn 778@deffn {} BFD_RELOC_ALPHA_LINKAGE 779The LINKAGE relocation outputs a linkage pair in the object file, 780which is filled by the linker. 781@end deffn 782@deffn {} BFD_RELOC_ALPHA_CODEADDR 783The CODEADDR relocation outputs a STO_CA in the object file, 784which is filled by the linker. 785@end deffn 786@deffn {} BFD_RELOC_ALPHA_GPREL_HI16 787@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 788The GPREL_HI/LO relocations together form a 32-bit offset from the 789GP register. 790@end deffn 791@deffn {} BFD_RELOC_ALPHA_BRSGP 792Like BFD_RELOC_23_PCREL_S2, except that the source and target must 793share a common GP, and the target address is adjusted for 794STO_ALPHA_STD_GPLOAD. 795@end deffn 796@deffn {} BFD_RELOC_ALPHA_NOP 797The NOP relocation outputs a NOP if the longword displacement 798between two procedure entry points is < 2^21. 799@end deffn 800@deffn {} BFD_RELOC_ALPHA_BSR 801The BSR relocation outputs a BSR if the longword displacement 802between two procedure entry points is < 2^21. 803@end deffn 804@deffn {} BFD_RELOC_ALPHA_LDA 805The LDA relocation outputs a LDA if the longword displacement 806between two procedure entry points is < 2^16. 807@end deffn 808@deffn {} BFD_RELOC_ALPHA_BOH 809The BOH relocation outputs a BSR if the longword displacement 810between two procedure entry points is < 2^21, or else a hint. 811@end deffn 812@deffn {} BFD_RELOC_ALPHA_TLSGD 813@deffnx {} BFD_RELOC_ALPHA_TLSLDM 814@deffnx {} BFD_RELOC_ALPHA_DTPMOD64 815@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 816@deffnx {} BFD_RELOC_ALPHA_DTPREL64 817@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 818@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 819@deffnx {} BFD_RELOC_ALPHA_DTPREL16 820@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 821@deffnx {} BFD_RELOC_ALPHA_TPREL64 822@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 823@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 824@deffnx {} BFD_RELOC_ALPHA_TPREL16 825Alpha thread-local storage relocations. 826@end deffn 827@deffn {} BFD_RELOC_MIPS_JMP 828@deffnx {} BFD_RELOC_MICROMIPS_JMP 829The MIPS jump instruction. 830@end deffn 831@deffn {} BFD_RELOC_MIPS16_JMP 832The MIPS16 jump instruction. 833@end deffn 834@deffn {} BFD_RELOC_MIPS16_GPREL 835MIPS16 GP relative reloc. 836@end deffn 837@deffn {} BFD_RELOC_HI16 838High 16 bits of 32-bit value; simple reloc. 839@end deffn 840@deffn {} BFD_RELOC_HI16_S 841High 16 bits of 32-bit value but the low 16 bits will be sign 842extended and added to form the final result. If the low 16 843bits form a negative number, we need to add one to the high value 844to compensate for the borrow when the low bits are added. 845@end deffn 846@deffn {} BFD_RELOC_LO16 847Low 16 bits. 848@end deffn 849@deffn {} BFD_RELOC_HI16_PCREL 850High 16 bits of 32-bit pc-relative value 851@end deffn 852@deffn {} BFD_RELOC_HI16_S_PCREL 853High 16 bits of 32-bit pc-relative value, adjusted 854@end deffn 855@deffn {} BFD_RELOC_LO16_PCREL 856Low 16 bits of pc-relative value 857@end deffn 858@deffn {} BFD_RELOC_MIPS16_GOT16 859@deffnx {} BFD_RELOC_MIPS16_CALL16 860Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 86116-bit immediate fields 862@end deffn 863@deffn {} BFD_RELOC_MIPS16_HI16 864MIPS16 high 16 bits of 32-bit value. 865@end deffn 866@deffn {} BFD_RELOC_MIPS16_HI16_S 867MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 868extended and added to form the final result. If the low 16 869bits form a negative number, we need to add one to the high value 870to compensate for the borrow when the low bits are added. 871@end deffn 872@deffn {} BFD_RELOC_MIPS16_LO16 873MIPS16 low 16 bits. 874@end deffn 875@deffn {} BFD_RELOC_MIPS16_TLS_GD 876@deffnx {} BFD_RELOC_MIPS16_TLS_LDM 877@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 878@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 879@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 880@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 881@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 882MIPS16 TLS relocations 883@end deffn 884@deffn {} BFD_RELOC_MIPS_LITERAL 885@deffnx {} BFD_RELOC_MICROMIPS_LITERAL 886Relocation against a MIPS literal section. 887@end deffn 888@deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 889@deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 890@deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 891microMIPS PC-relative relocations. 892@end deffn 893@deffn {} BFD_RELOC_MIPS_21_PCREL_S2 894@deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 895@deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 896@deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 897MIPS PC-relative relocations. 898@end deffn 899@deffn {} BFD_RELOC_MICROMIPS_GPREL16 900@deffnx {} BFD_RELOC_MICROMIPS_HI16 901@deffnx {} BFD_RELOC_MICROMIPS_HI16_S 902@deffnx {} BFD_RELOC_MICROMIPS_LO16 903microMIPS versions of generic BFD relocs. 904@end deffn 905@deffn {} BFD_RELOC_MIPS_GOT16 906@deffnx {} BFD_RELOC_MICROMIPS_GOT16 907@deffnx {} BFD_RELOC_MIPS_CALL16 908@deffnx {} BFD_RELOC_MICROMIPS_CALL16 909@deffnx {} BFD_RELOC_MIPS_GOT_HI16 910@deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 911@deffnx {} BFD_RELOC_MIPS_GOT_LO16 912@deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 913@deffnx {} BFD_RELOC_MIPS_CALL_HI16 914@deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 915@deffnx {} BFD_RELOC_MIPS_CALL_LO16 916@deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 917@deffnx {} BFD_RELOC_MIPS_SUB 918@deffnx {} BFD_RELOC_MICROMIPS_SUB 919@deffnx {} BFD_RELOC_MIPS_GOT_PAGE 920@deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 921@deffnx {} BFD_RELOC_MIPS_GOT_OFST 922@deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 923@deffnx {} BFD_RELOC_MIPS_GOT_DISP 924@deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 925@deffnx {} BFD_RELOC_MIPS_SHIFT5 926@deffnx {} BFD_RELOC_MIPS_SHIFT6 927@deffnx {} BFD_RELOC_MIPS_INSERT_A 928@deffnx {} BFD_RELOC_MIPS_INSERT_B 929@deffnx {} BFD_RELOC_MIPS_DELETE 930@deffnx {} BFD_RELOC_MIPS_HIGHEST 931@deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 932@deffnx {} BFD_RELOC_MIPS_HIGHER 933@deffnx {} BFD_RELOC_MICROMIPS_HIGHER 934@deffnx {} BFD_RELOC_MIPS_SCN_DISP 935@deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 936@deffnx {} BFD_RELOC_MIPS_REL16 937@deffnx {} BFD_RELOC_MIPS_RELGOT 938@deffnx {} BFD_RELOC_MIPS_JALR 939@deffnx {} BFD_RELOC_MICROMIPS_JALR 940@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 941@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 942@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 943@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 944@deffnx {} BFD_RELOC_MIPS_TLS_GD 945@deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 946@deffnx {} BFD_RELOC_MIPS_TLS_LDM 947@deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 948@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 949@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 950@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 951@deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 952@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 953@deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 954@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 955@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 956@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 957@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 958@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 959@deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 960@deffnx {} BFD_RELOC_MIPS_EH 961MIPS ELF relocations. 962@end deffn 963@deffn {} BFD_RELOC_MIPS_COPY 964@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 965MIPS ELF relocations (VxWorks and PLT extensions). 966@end deffn 967@deffn {} BFD_RELOC_MOXIE_10_PCREL 968Moxie ELF relocations. 969@end deffn 970@deffn {} BFD_RELOC_FT32_10 971@deffnx {} BFD_RELOC_FT32_20 972@deffnx {} BFD_RELOC_FT32_17 973@deffnx {} BFD_RELOC_FT32_18 974FT32 ELF relocations. 975@end deffn 976@deffn {} BFD_RELOC_FRV_LABEL16 977@deffnx {} BFD_RELOC_FRV_LABEL24 978@deffnx {} BFD_RELOC_FRV_LO16 979@deffnx {} BFD_RELOC_FRV_HI16 980@deffnx {} BFD_RELOC_FRV_GPREL12 981@deffnx {} BFD_RELOC_FRV_GPRELU12 982@deffnx {} BFD_RELOC_FRV_GPREL32 983@deffnx {} BFD_RELOC_FRV_GPRELHI 984@deffnx {} BFD_RELOC_FRV_GPRELLO 985@deffnx {} BFD_RELOC_FRV_GOT12 986@deffnx {} BFD_RELOC_FRV_GOTHI 987@deffnx {} BFD_RELOC_FRV_GOTLO 988@deffnx {} BFD_RELOC_FRV_FUNCDESC 989@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 990@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 991@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 992@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 993@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 994@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 995@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 996@deffnx {} BFD_RELOC_FRV_GOTOFF12 997@deffnx {} BFD_RELOC_FRV_GOTOFFHI 998@deffnx {} BFD_RELOC_FRV_GOTOFFLO 999@deffnx {} BFD_RELOC_FRV_GETTLSOFF 1000@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 1001@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 1002@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 1003@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 1004@deffnx {} BFD_RELOC_FRV_TLSMOFF12 1005@deffnx {} BFD_RELOC_FRV_TLSMOFFHI 1006@deffnx {} BFD_RELOC_FRV_TLSMOFFLO 1007@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 1008@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 1009@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 1010@deffnx {} BFD_RELOC_FRV_TLSOFF 1011@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 1012@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 1013@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 1014@deffnx {} BFD_RELOC_FRV_TLSMOFF 1015Fujitsu Frv Relocations. 1016@end deffn 1017@deffn {} BFD_RELOC_MN10300_GOTOFF24 1018This is a 24bit GOT-relative reloc for the mn10300. 1019@end deffn 1020@deffn {} BFD_RELOC_MN10300_GOT32 1021This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes 1022in the instruction. 1023@end deffn 1024@deffn {} BFD_RELOC_MN10300_GOT24 1025This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes 1026in the instruction. 1027@end deffn 1028@deffn {} BFD_RELOC_MN10300_GOT16 1029This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes 1030in the instruction. 1031@end deffn 1032@deffn {} BFD_RELOC_MN10300_COPY 1033Copy symbol at runtime. 1034@end deffn 1035@deffn {} BFD_RELOC_MN10300_GLOB_DAT 1036Create GOT entry. 1037@end deffn 1038@deffn {} BFD_RELOC_MN10300_JMP_SLOT 1039Create PLT entry. 1040@end deffn 1041@deffn {} BFD_RELOC_MN10300_RELATIVE 1042Adjust by program base. 1043@end deffn 1044@deffn {} BFD_RELOC_MN10300_SYM_DIFF 1045Together with another reloc targeted at the same location, 1046allows for a value that is the difference of two symbols 1047in the same section. 1048@end deffn 1049@deffn {} BFD_RELOC_MN10300_ALIGN 1050The addend of this reloc is an alignment power that must 1051be honoured at the offset's location, regardless of linker 1052relaxation. 1053@end deffn 1054@deffn {} BFD_RELOC_MN10300_TLS_GD 1055@deffnx {} BFD_RELOC_MN10300_TLS_LD 1056@deffnx {} BFD_RELOC_MN10300_TLS_LDO 1057@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 1058@deffnx {} BFD_RELOC_MN10300_TLS_IE 1059@deffnx {} BFD_RELOC_MN10300_TLS_LE 1060@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 1061@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 1062@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 1063Various TLS-related relocations. 1064@end deffn 1065@deffn {} BFD_RELOC_MN10300_32_PCREL 1066This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the 1067instruction. 1068@end deffn 1069@deffn {} BFD_RELOC_MN10300_16_PCREL 1070This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the 1071instruction. 1072@end deffn 1073@deffn {} BFD_RELOC_386_GOT32 1074@deffnx {} BFD_RELOC_386_PLT32 1075@deffnx {} BFD_RELOC_386_COPY 1076@deffnx {} BFD_RELOC_386_GLOB_DAT 1077@deffnx {} BFD_RELOC_386_JUMP_SLOT 1078@deffnx {} BFD_RELOC_386_RELATIVE 1079@deffnx {} BFD_RELOC_386_GOTOFF 1080@deffnx {} BFD_RELOC_386_GOTPC 1081@deffnx {} BFD_RELOC_386_TLS_TPOFF 1082@deffnx {} BFD_RELOC_386_TLS_IE 1083@deffnx {} BFD_RELOC_386_TLS_GOTIE 1084@deffnx {} BFD_RELOC_386_TLS_LE 1085@deffnx {} BFD_RELOC_386_TLS_GD 1086@deffnx {} BFD_RELOC_386_TLS_LDM 1087@deffnx {} BFD_RELOC_386_TLS_LDO_32 1088@deffnx {} BFD_RELOC_386_TLS_IE_32 1089@deffnx {} BFD_RELOC_386_TLS_LE_32 1090@deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1091@deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1092@deffnx {} BFD_RELOC_386_TLS_TPOFF32 1093@deffnx {} BFD_RELOC_386_TLS_GOTDESC 1094@deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1095@deffnx {} BFD_RELOC_386_TLS_DESC 1096@deffnx {} BFD_RELOC_386_IRELATIVE 1097@deffnx {} BFD_RELOC_386_GOT32X 1098i386/elf relocations 1099@end deffn 1100@deffn {} BFD_RELOC_X86_64_GOT32 1101@deffnx {} BFD_RELOC_X86_64_PLT32 1102@deffnx {} BFD_RELOC_X86_64_COPY 1103@deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1104@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1105@deffnx {} BFD_RELOC_X86_64_RELATIVE 1106@deffnx {} BFD_RELOC_X86_64_GOTPCREL 1107@deffnx {} BFD_RELOC_X86_64_32S 1108@deffnx {} BFD_RELOC_X86_64_DTPMOD64 1109@deffnx {} BFD_RELOC_X86_64_DTPOFF64 1110@deffnx {} BFD_RELOC_X86_64_TPOFF64 1111@deffnx {} BFD_RELOC_X86_64_TLSGD 1112@deffnx {} BFD_RELOC_X86_64_TLSLD 1113@deffnx {} BFD_RELOC_X86_64_DTPOFF32 1114@deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1115@deffnx {} BFD_RELOC_X86_64_TPOFF32 1116@deffnx {} BFD_RELOC_X86_64_GOTOFF64 1117@deffnx {} BFD_RELOC_X86_64_GOTPC32 1118@deffnx {} BFD_RELOC_X86_64_GOT64 1119@deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1120@deffnx {} BFD_RELOC_X86_64_GOTPC64 1121@deffnx {} BFD_RELOC_X86_64_GOTPLT64 1122@deffnx {} BFD_RELOC_X86_64_PLTOFF64 1123@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1124@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1125@deffnx {} BFD_RELOC_X86_64_TLSDESC 1126@deffnx {} BFD_RELOC_X86_64_IRELATIVE 1127@deffnx {} BFD_RELOC_X86_64_PC32_BND 1128@deffnx {} BFD_RELOC_X86_64_PLT32_BND 1129@deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1130@deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1131x86-64/elf relocations 1132@end deffn 1133@deffn {} BFD_RELOC_NS32K_IMM_8 1134@deffnx {} BFD_RELOC_NS32K_IMM_16 1135@deffnx {} BFD_RELOC_NS32K_IMM_32 1136@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1137@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1138@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1139@deffnx {} BFD_RELOC_NS32K_DISP_8 1140@deffnx {} BFD_RELOC_NS32K_DISP_16 1141@deffnx {} BFD_RELOC_NS32K_DISP_32 1142@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1143@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1144@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1145ns32k relocations 1146@end deffn 1147@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1148@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1149PDP11 relocations 1150@end deffn 1151@deffn {} BFD_RELOC_PJ_CODE_HI16 1152@deffnx {} BFD_RELOC_PJ_CODE_LO16 1153@deffnx {} BFD_RELOC_PJ_CODE_DIR16 1154@deffnx {} BFD_RELOC_PJ_CODE_DIR32 1155@deffnx {} BFD_RELOC_PJ_CODE_REL16 1156@deffnx {} BFD_RELOC_PJ_CODE_REL32 1157Picojava relocs. Not all of these appear in object files. 1158@end deffn 1159@deffn {} BFD_RELOC_PPC_B26 1160@deffnx {} BFD_RELOC_PPC_BA26 1161@deffnx {} BFD_RELOC_PPC_TOC16 1162@deffnx {} BFD_RELOC_PPC_B16 1163@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1164@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1165@deffnx {} BFD_RELOC_PPC_BA16 1166@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1167@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1168@deffnx {} BFD_RELOC_PPC_COPY 1169@deffnx {} BFD_RELOC_PPC_GLOB_DAT 1170@deffnx {} BFD_RELOC_PPC_JMP_SLOT 1171@deffnx {} BFD_RELOC_PPC_RELATIVE 1172@deffnx {} BFD_RELOC_PPC_LOCAL24PC 1173@deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1174@deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1175@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1176@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1177@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1178@deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1179@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1180@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1181@deffnx {} BFD_RELOC_PPC_EMB_SDA21 1182@deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1183@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1184@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1185@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1186@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1187@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1188@deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1189@deffnx {} BFD_RELOC_PPC_VLE_REL8 1190@deffnx {} BFD_RELOC_PPC_VLE_REL15 1191@deffnx {} BFD_RELOC_PPC_VLE_REL24 1192@deffnx {} BFD_RELOC_PPC_VLE_LO16A 1193@deffnx {} BFD_RELOC_PPC_VLE_LO16D 1194@deffnx {} BFD_RELOC_PPC_VLE_HI16A 1195@deffnx {} BFD_RELOC_PPC_VLE_HI16D 1196@deffnx {} BFD_RELOC_PPC_VLE_HA16A 1197@deffnx {} BFD_RELOC_PPC_VLE_HA16D 1198@deffnx {} BFD_RELOC_PPC_VLE_SDA21 1199@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1200@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1201@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1202@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1203@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1204@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1205@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1206@deffnx {} BFD_RELOC_PPC_REL16DX_HA 1207@deffnx {} BFD_RELOC_PPC64_HIGHER 1208@deffnx {} BFD_RELOC_PPC64_HIGHER_S 1209@deffnx {} BFD_RELOC_PPC64_HIGHEST 1210@deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1211@deffnx {} BFD_RELOC_PPC64_TOC16_LO 1212@deffnx {} BFD_RELOC_PPC64_TOC16_HI 1213@deffnx {} BFD_RELOC_PPC64_TOC16_HA 1214@deffnx {} BFD_RELOC_PPC64_TOC 1215@deffnx {} BFD_RELOC_PPC64_PLTGOT16 1216@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1217@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1218@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1219@deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1220@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1221@deffnx {} BFD_RELOC_PPC64_GOT16_DS 1222@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1223@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1224@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1225@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1226@deffnx {} BFD_RELOC_PPC64_TOC16_DS 1227@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1228@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1229@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1230@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1231@deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1232@deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1233@deffnx {} BFD_RELOC_PPC64_ENTRY 1234Power(rs6000) and PowerPC relocations. 1235@end deffn 1236@deffn {} BFD_RELOC_PPC_TLS 1237@deffnx {} BFD_RELOC_PPC_TLSGD 1238@deffnx {} BFD_RELOC_PPC_TLSLD 1239@deffnx {} BFD_RELOC_PPC_DTPMOD 1240@deffnx {} BFD_RELOC_PPC_TPREL16 1241@deffnx {} BFD_RELOC_PPC_TPREL16_LO 1242@deffnx {} BFD_RELOC_PPC_TPREL16_HI 1243@deffnx {} BFD_RELOC_PPC_TPREL16_HA 1244@deffnx {} BFD_RELOC_PPC_TPREL 1245@deffnx {} BFD_RELOC_PPC_DTPREL16 1246@deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1247@deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1248@deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1249@deffnx {} BFD_RELOC_PPC_DTPREL 1250@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1251@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1252@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1253@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1254@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1255@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1256@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1257@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1258@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1259@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1260@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1261@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1262@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1263@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1264@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1265@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1266@deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1267@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1268@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1269@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1270@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1271@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1272@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1273@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1274@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1275@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1276@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1277@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1278@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1279@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1280@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1281@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1282PowerPC and PowerPC64 thread-local storage relocations. 1283@end deffn 1284@deffn {} BFD_RELOC_I370_D12 1285IBM 370/390 relocations 1286@end deffn 1287@deffn {} BFD_RELOC_CTOR 1288The type of reloc used to build a constructor table - at the moment 1289probably a 32 bit wide absolute relocation, but the target can choose. 1290It generally does map to one of the other relocation types. 1291@end deffn 1292@deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1293ARM 26 bit pc-relative branch. The lowest two bits must be zero and are 1294not stored in the instruction. 1295@end deffn 1296@deffn {} BFD_RELOC_ARM_PCREL_BLX 1297ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1298not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1299field in the instruction. 1300@end deffn 1301@deffn {} BFD_RELOC_THUMB_PCREL_BLX 1302Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1303not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1304field in the instruction. 1305@end deffn 1306@deffn {} BFD_RELOC_ARM_PCREL_CALL 1307ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. 1308@end deffn 1309@deffn {} BFD_RELOC_ARM_PCREL_JUMP 1310ARM 26-bit pc-relative branch for B or conditional BL instruction. 1311@end deffn 1312@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1313@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1314@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1315@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1316@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1317@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1318Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1319The lowest bit must be zero and is not stored in the instruction. 1320Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1321"nn" one smaller in all cases. Note further that BRANCH23 1322corresponds to R_ARM_THM_CALL. 1323@end deffn 1324@deffn {} BFD_RELOC_ARM_OFFSET_IMM 132512-bit immediate offset, used in ARM-format ldr and str instructions. 1326@end deffn 1327@deffn {} BFD_RELOC_ARM_THUMB_OFFSET 13285-bit immediate offset, used in Thumb-format ldr and str instructions. 1329@end deffn 1330@deffn {} BFD_RELOC_ARM_TARGET1 1331Pc-relative or absolute relocation depending on target. Used for 1332entries in .init_array sections. 1333@end deffn 1334@deffn {} BFD_RELOC_ARM_ROSEGREL32 1335Read-only segment base relative address. 1336@end deffn 1337@deffn {} BFD_RELOC_ARM_SBREL32 1338Data segment base relative address. 1339@end deffn 1340@deffn {} BFD_RELOC_ARM_TARGET2 1341This reloc is used for references to RTTI data from exception handling 1342tables. The actual definition depends on the target. It may be a 1343pc-relative or some form of GOT-indirect relocation. 1344@end deffn 1345@deffn {} BFD_RELOC_ARM_PREL31 134631-bit PC relative address. 1347@end deffn 1348@deffn {} BFD_RELOC_ARM_MOVW 1349@deffnx {} BFD_RELOC_ARM_MOVT 1350@deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1351@deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1352@deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1353@deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1354@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1355@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1356Low and High halfword relocations for MOVW and MOVT instructions. 1357@end deffn 1358@deffn {} BFD_RELOC_ARM_JUMP_SLOT 1359@deffnx {} BFD_RELOC_ARM_GLOB_DAT 1360@deffnx {} BFD_RELOC_ARM_GOT32 1361@deffnx {} BFD_RELOC_ARM_PLT32 1362@deffnx {} BFD_RELOC_ARM_RELATIVE 1363@deffnx {} BFD_RELOC_ARM_GOTOFF 1364@deffnx {} BFD_RELOC_ARM_GOTPC 1365@deffnx {} BFD_RELOC_ARM_GOT_PREL 1366Relocations for setting up GOTs and PLTs for shared libraries. 1367@end deffn 1368@deffn {} BFD_RELOC_ARM_TLS_GD32 1369@deffnx {} BFD_RELOC_ARM_TLS_LDO32 1370@deffnx {} BFD_RELOC_ARM_TLS_LDM32 1371@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1372@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1373@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1374@deffnx {} BFD_RELOC_ARM_TLS_IE32 1375@deffnx {} BFD_RELOC_ARM_TLS_LE32 1376@deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1377@deffnx {} BFD_RELOC_ARM_TLS_CALL 1378@deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1379@deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1380@deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1381@deffnx {} BFD_RELOC_ARM_TLS_DESC 1382ARM thread-local storage relocations. 1383@end deffn 1384@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1385@deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1386@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1387@deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1388@deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1389@deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1390@deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1391@deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1392@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1393@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1394@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1395@deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1396@deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1397@deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1398@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1399@deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1400@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1401@deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1402@deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1403@deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1404@deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1405@deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1406@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1407@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1408@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1409@deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1410@deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1411@deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1412ARM group relocations. 1413@end deffn 1414@deffn {} BFD_RELOC_ARM_V4BX 1415Annotation of BX instructions. 1416@end deffn 1417@deffn {} BFD_RELOC_ARM_IRELATIVE 1418ARM support for STT_GNU_IFUNC. 1419@end deffn 1420@deffn {} BFD_RELOC_ARM_IMMEDIATE 1421@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1422@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1423@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1424@deffnx {} BFD_RELOC_ARM_T32_IMM12 1425@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1426@deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1427@deffnx {} BFD_RELOC_ARM_SMC 1428@deffnx {} BFD_RELOC_ARM_HVC 1429@deffnx {} BFD_RELOC_ARM_SWI 1430@deffnx {} BFD_RELOC_ARM_MULTI 1431@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1432@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1433@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1434@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1435@deffnx {} BFD_RELOC_ARM_ADR_IMM 1436@deffnx {} BFD_RELOC_ARM_LDR_IMM 1437@deffnx {} BFD_RELOC_ARM_LITERAL 1438@deffnx {} BFD_RELOC_ARM_IN_POOL 1439@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1440@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1441@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1442@deffnx {} BFD_RELOC_ARM_HWLITERAL 1443@deffnx {} BFD_RELOC_ARM_THUMB_ADD 1444@deffnx {} BFD_RELOC_ARM_THUMB_IMM 1445@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1446These relocs are only used within the ARM assembler. They are not 1447(at present) written to any object files. 1448@end deffn 1449@deffn {} BFD_RELOC_SH_PCDISP8BY2 1450@deffnx {} BFD_RELOC_SH_PCDISP12BY2 1451@deffnx {} BFD_RELOC_SH_IMM3 1452@deffnx {} BFD_RELOC_SH_IMM3U 1453@deffnx {} BFD_RELOC_SH_DISP12 1454@deffnx {} BFD_RELOC_SH_DISP12BY2 1455@deffnx {} BFD_RELOC_SH_DISP12BY4 1456@deffnx {} BFD_RELOC_SH_DISP12BY8 1457@deffnx {} BFD_RELOC_SH_DISP20 1458@deffnx {} BFD_RELOC_SH_DISP20BY8 1459@deffnx {} BFD_RELOC_SH_IMM4 1460@deffnx {} BFD_RELOC_SH_IMM4BY2 1461@deffnx {} BFD_RELOC_SH_IMM4BY4 1462@deffnx {} BFD_RELOC_SH_IMM8 1463@deffnx {} BFD_RELOC_SH_IMM8BY2 1464@deffnx {} BFD_RELOC_SH_IMM8BY4 1465@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1466@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1467@deffnx {} BFD_RELOC_SH_SWITCH16 1468@deffnx {} BFD_RELOC_SH_SWITCH32 1469@deffnx {} BFD_RELOC_SH_USES 1470@deffnx {} BFD_RELOC_SH_COUNT 1471@deffnx {} BFD_RELOC_SH_ALIGN 1472@deffnx {} BFD_RELOC_SH_CODE 1473@deffnx {} BFD_RELOC_SH_DATA 1474@deffnx {} BFD_RELOC_SH_LABEL 1475@deffnx {} BFD_RELOC_SH_LOOP_START 1476@deffnx {} BFD_RELOC_SH_LOOP_END 1477@deffnx {} BFD_RELOC_SH_COPY 1478@deffnx {} BFD_RELOC_SH_GLOB_DAT 1479@deffnx {} BFD_RELOC_SH_JMP_SLOT 1480@deffnx {} BFD_RELOC_SH_RELATIVE 1481@deffnx {} BFD_RELOC_SH_GOTPC 1482@deffnx {} BFD_RELOC_SH_GOT_LOW16 1483@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1484@deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1485@deffnx {} BFD_RELOC_SH_GOT_HI16 1486@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1487@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1488@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1489@deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1490@deffnx {} BFD_RELOC_SH_PLT_LOW16 1491@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1492@deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1493@deffnx {} BFD_RELOC_SH_PLT_HI16 1494@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1495@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1496@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1497@deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1498@deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1499@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1500@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1501@deffnx {} BFD_RELOC_SH_GOTPC_HI16 1502@deffnx {} BFD_RELOC_SH_COPY64 1503@deffnx {} BFD_RELOC_SH_GLOB_DAT64 1504@deffnx {} BFD_RELOC_SH_JMP_SLOT64 1505@deffnx {} BFD_RELOC_SH_RELATIVE64 1506@deffnx {} BFD_RELOC_SH_GOT10BY4 1507@deffnx {} BFD_RELOC_SH_GOT10BY8 1508@deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1509@deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1510@deffnx {} BFD_RELOC_SH_GOTPLT32 1511@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1512@deffnx {} BFD_RELOC_SH_IMMU5 1513@deffnx {} BFD_RELOC_SH_IMMS6 1514@deffnx {} BFD_RELOC_SH_IMMS6BY32 1515@deffnx {} BFD_RELOC_SH_IMMU6 1516@deffnx {} BFD_RELOC_SH_IMMS10 1517@deffnx {} BFD_RELOC_SH_IMMS10BY2 1518@deffnx {} BFD_RELOC_SH_IMMS10BY4 1519@deffnx {} BFD_RELOC_SH_IMMS10BY8 1520@deffnx {} BFD_RELOC_SH_IMMS16 1521@deffnx {} BFD_RELOC_SH_IMMU16 1522@deffnx {} BFD_RELOC_SH_IMM_LOW16 1523@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1524@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1525@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1526@deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1527@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1528@deffnx {} BFD_RELOC_SH_IMM_HI16 1529@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1530@deffnx {} BFD_RELOC_SH_PT_16 1531@deffnx {} BFD_RELOC_SH_TLS_GD_32 1532@deffnx {} BFD_RELOC_SH_TLS_LD_32 1533@deffnx {} BFD_RELOC_SH_TLS_LDO_32 1534@deffnx {} BFD_RELOC_SH_TLS_IE_32 1535@deffnx {} BFD_RELOC_SH_TLS_LE_32 1536@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1537@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1538@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1539@deffnx {} BFD_RELOC_SH_GOT20 1540@deffnx {} BFD_RELOC_SH_GOTOFF20 1541@deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1542@deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1543@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1544@deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1545@deffnx {} BFD_RELOC_SH_FUNCDESC 1546Renesas / SuperH SH relocs. Not all of these appear in object files. 1547@end deffn 1548@deffn {} BFD_RELOC_ARC_NONE 1549@deffnx {} BFD_RELOC_ARC_8 1550@deffnx {} BFD_RELOC_ARC_16 1551@deffnx {} BFD_RELOC_ARC_24 1552@deffnx {} BFD_RELOC_ARC_32 1553@deffnx {} BFD_RELOC_ARC_N8 1554@deffnx {} BFD_RELOC_ARC_N16 1555@deffnx {} BFD_RELOC_ARC_N24 1556@deffnx {} BFD_RELOC_ARC_N32 1557@deffnx {} BFD_RELOC_ARC_SDA 1558@deffnx {} BFD_RELOC_ARC_SECTOFF 1559@deffnx {} BFD_RELOC_ARC_S21H_PCREL 1560@deffnx {} BFD_RELOC_ARC_S21W_PCREL 1561@deffnx {} BFD_RELOC_ARC_S25H_PCREL 1562@deffnx {} BFD_RELOC_ARC_S25W_PCREL 1563@deffnx {} BFD_RELOC_ARC_SDA32 1564@deffnx {} BFD_RELOC_ARC_SDA_LDST 1565@deffnx {} BFD_RELOC_ARC_SDA_LDST1 1566@deffnx {} BFD_RELOC_ARC_SDA_LDST2 1567@deffnx {} BFD_RELOC_ARC_SDA16_LD 1568@deffnx {} BFD_RELOC_ARC_SDA16_LD1 1569@deffnx {} BFD_RELOC_ARC_SDA16_LD2 1570@deffnx {} BFD_RELOC_ARC_S13_PCREL 1571@deffnx {} BFD_RELOC_ARC_W 1572@deffnx {} BFD_RELOC_ARC_32_ME 1573@deffnx {} BFD_RELOC_ARC_32_ME_S 1574@deffnx {} BFD_RELOC_ARC_N32_ME 1575@deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1576@deffnx {} BFD_RELOC_ARC_SDA32_ME 1577@deffnx {} BFD_RELOC_ARC_W_ME 1578@deffnx {} BFD_RELOC_AC_SECTOFF_U8 1579@deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1580@deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1581@deffnx {} BFD_RELOC_AC_SECTFOFF_S9 1582@deffnx {} BFD_RELOC_AC_SECTFOFF_S9_1 1583@deffnx {} BFD_RELOC_AC_SECTFOFF_S9_2 1584@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1585@deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1586@deffnx {} BFD_RELOC_ARC_SECTOFF_1 1587@deffnx {} BFD_RELOC_ARC_SECTOFF_2 1588@deffnx {} BFD_RELOC_ARC_SDA16_ST2 1589@deffnx {} BFD_RELOC_ARC_32_PCREL 1590@deffnx {} BFD_RELOC_ARC_PC32 1591@deffnx {} BFD_RELOC_ARC_GOT32 1592@deffnx {} BFD_RELOC_ARC_GOTPC32 1593@deffnx {} BFD_RELOC_ARC_PLT32 1594@deffnx {} BFD_RELOC_ARC_COPY 1595@deffnx {} BFD_RELOC_ARC_GLOB_DAT 1596@deffnx {} BFD_RELOC_ARC_JMP_SLOT 1597@deffnx {} BFD_RELOC_ARC_RELATIVE 1598@deffnx {} BFD_RELOC_ARC_GOTOFF 1599@deffnx {} BFD_RELOC_ARC_GOTPC 1600@deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1601@deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1602@deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1603@deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1604@deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1605@deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1606@deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1607@deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1608@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1609@deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1610@deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1611@deffnx {} BFD_RELOC_ARC_TLS_LE_32 1612@deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1613@deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1614ARC relocs. 1615@end deffn 1616@deffn {} BFD_RELOC_BFIN_16_IMM 1617ADI Blackfin 16 bit immediate absolute reloc. 1618@end deffn 1619@deffn {} BFD_RELOC_BFIN_16_HIGH 1620ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1621@end deffn 1622@deffn {} BFD_RELOC_BFIN_4_PCREL 1623ADI Blackfin 'a' part of LSETUP. 1624@end deffn 1625@deffn {} BFD_RELOC_BFIN_5_PCREL 1626ADI Blackfin. 1627@end deffn 1628@deffn {} BFD_RELOC_BFIN_16_LOW 1629ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1630@end deffn 1631@deffn {} BFD_RELOC_BFIN_10_PCREL 1632ADI Blackfin. 1633@end deffn 1634@deffn {} BFD_RELOC_BFIN_11_PCREL 1635ADI Blackfin 'b' part of LSETUP. 1636@end deffn 1637@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1638ADI Blackfin. 1639@end deffn 1640@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1641ADI Blackfin Short jump, pcrel. 1642@end deffn 1643@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1644ADI Blackfin Call.x not implemented. 1645@end deffn 1646@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1647ADI Blackfin Long Jump pcrel. 1648@end deffn 1649@deffn {} BFD_RELOC_BFIN_GOT17M4 1650@deffnx {} BFD_RELOC_BFIN_GOTHI 1651@deffnx {} BFD_RELOC_BFIN_GOTLO 1652@deffnx {} BFD_RELOC_BFIN_FUNCDESC 1653@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1654@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1655@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1656@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1657@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1658@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1659@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1660@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1661@deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1662@deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1663ADI Blackfin FD-PIC relocations. 1664@end deffn 1665@deffn {} BFD_RELOC_BFIN_GOT 1666ADI Blackfin GOT relocation. 1667@end deffn 1668@deffn {} BFD_RELOC_BFIN_PLTPC 1669ADI Blackfin PLTPC relocation. 1670@end deffn 1671@deffn {} BFD_ARELOC_BFIN_PUSH 1672ADI Blackfin arithmetic relocation. 1673@end deffn 1674@deffn {} BFD_ARELOC_BFIN_CONST 1675ADI Blackfin arithmetic relocation. 1676@end deffn 1677@deffn {} BFD_ARELOC_BFIN_ADD 1678ADI Blackfin arithmetic relocation. 1679@end deffn 1680@deffn {} BFD_ARELOC_BFIN_SUB 1681ADI Blackfin arithmetic relocation. 1682@end deffn 1683@deffn {} BFD_ARELOC_BFIN_MULT 1684ADI Blackfin arithmetic relocation. 1685@end deffn 1686@deffn {} BFD_ARELOC_BFIN_DIV 1687ADI Blackfin arithmetic relocation. 1688@end deffn 1689@deffn {} BFD_ARELOC_BFIN_MOD 1690ADI Blackfin arithmetic relocation. 1691@end deffn 1692@deffn {} BFD_ARELOC_BFIN_LSHIFT 1693ADI Blackfin arithmetic relocation. 1694@end deffn 1695@deffn {} BFD_ARELOC_BFIN_RSHIFT 1696ADI Blackfin arithmetic relocation. 1697@end deffn 1698@deffn {} BFD_ARELOC_BFIN_AND 1699ADI Blackfin arithmetic relocation. 1700@end deffn 1701@deffn {} BFD_ARELOC_BFIN_OR 1702ADI Blackfin arithmetic relocation. 1703@end deffn 1704@deffn {} BFD_ARELOC_BFIN_XOR 1705ADI Blackfin arithmetic relocation. 1706@end deffn 1707@deffn {} BFD_ARELOC_BFIN_LAND 1708ADI Blackfin arithmetic relocation. 1709@end deffn 1710@deffn {} BFD_ARELOC_BFIN_LOR 1711ADI Blackfin arithmetic relocation. 1712@end deffn 1713@deffn {} BFD_ARELOC_BFIN_LEN 1714ADI Blackfin arithmetic relocation. 1715@end deffn 1716@deffn {} BFD_ARELOC_BFIN_NEG 1717ADI Blackfin arithmetic relocation. 1718@end deffn 1719@deffn {} BFD_ARELOC_BFIN_COMP 1720ADI Blackfin arithmetic relocation. 1721@end deffn 1722@deffn {} BFD_ARELOC_BFIN_PAGE 1723ADI Blackfin arithmetic relocation. 1724@end deffn 1725@deffn {} BFD_ARELOC_BFIN_HWPAGE 1726ADI Blackfin arithmetic relocation. 1727@end deffn 1728@deffn {} BFD_ARELOC_BFIN_ADDR 1729ADI Blackfin arithmetic relocation. 1730@end deffn 1731@deffn {} BFD_RELOC_D10V_10_PCREL_R 1732Mitsubishi D10V relocs. 1733This is a 10-bit reloc with the right 2 bits 1734assumed to be 0. 1735@end deffn 1736@deffn {} BFD_RELOC_D10V_10_PCREL_L 1737Mitsubishi D10V relocs. 1738This is a 10-bit reloc with the right 2 bits 1739assumed to be 0. This is the same as the previous reloc 1740except it is in the left container, i.e., 1741shifted left 15 bits. 1742@end deffn 1743@deffn {} BFD_RELOC_D10V_18 1744This is an 18-bit reloc with the right 2 bits 1745assumed to be 0. 1746@end deffn 1747@deffn {} BFD_RELOC_D10V_18_PCREL 1748This is an 18-bit reloc with the right 2 bits 1749assumed to be 0. 1750@end deffn 1751@deffn {} BFD_RELOC_D30V_6 1752Mitsubishi D30V relocs. 1753This is a 6-bit absolute reloc. 1754@end deffn 1755@deffn {} BFD_RELOC_D30V_9_PCREL 1756This is a 6-bit pc-relative reloc with 1757the right 3 bits assumed to be 0. 1758@end deffn 1759@deffn {} BFD_RELOC_D30V_9_PCREL_R 1760This is a 6-bit pc-relative reloc with 1761the right 3 bits assumed to be 0. Same 1762as the previous reloc but on the right side 1763of the container. 1764@end deffn 1765@deffn {} BFD_RELOC_D30V_15 1766This is a 12-bit absolute reloc with the 1767right 3 bitsassumed to be 0. 1768@end deffn 1769@deffn {} BFD_RELOC_D30V_15_PCREL 1770This is a 12-bit pc-relative reloc with 1771the right 3 bits assumed to be 0. 1772@end deffn 1773@deffn {} BFD_RELOC_D30V_15_PCREL_R 1774This is a 12-bit pc-relative reloc with 1775the right 3 bits assumed to be 0. Same 1776as the previous reloc but on the right side 1777of the container. 1778@end deffn 1779@deffn {} BFD_RELOC_D30V_21 1780This is an 18-bit absolute reloc with 1781the right 3 bits assumed to be 0. 1782@end deffn 1783@deffn {} BFD_RELOC_D30V_21_PCREL 1784This is an 18-bit pc-relative reloc with 1785the right 3 bits assumed to be 0. 1786@end deffn 1787@deffn {} BFD_RELOC_D30V_21_PCREL_R 1788This is an 18-bit pc-relative reloc with 1789the right 3 bits assumed to be 0. Same 1790as the previous reloc but on the right side 1791of the container. 1792@end deffn 1793@deffn {} BFD_RELOC_D30V_32 1794This is a 32-bit absolute reloc. 1795@end deffn 1796@deffn {} BFD_RELOC_D30V_32_PCREL 1797This is a 32-bit pc-relative reloc. 1798@end deffn 1799@deffn {} BFD_RELOC_DLX_HI16_S 1800DLX relocs 1801@end deffn 1802@deffn {} BFD_RELOC_DLX_LO16 1803DLX relocs 1804@end deffn 1805@deffn {} BFD_RELOC_DLX_JMP26 1806DLX relocs 1807@end deffn 1808@deffn {} BFD_RELOC_M32C_HI8 1809@deffnx {} BFD_RELOC_M32C_RL_JUMP 1810@deffnx {} BFD_RELOC_M32C_RL_1ADDR 1811@deffnx {} BFD_RELOC_M32C_RL_2ADDR 1812Renesas M16C/M32C Relocations. 1813@end deffn 1814@deffn {} BFD_RELOC_M32R_24 1815Renesas M32R (formerly Mitsubishi M32R) relocs. 1816This is a 24 bit absolute address. 1817@end deffn 1818@deffn {} BFD_RELOC_M32R_10_PCREL 1819This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0. 1820@end deffn 1821@deffn {} BFD_RELOC_M32R_18_PCREL 1822This is an 18-bit reloc with the right 2 bits assumed to be 0. 1823@end deffn 1824@deffn {} BFD_RELOC_M32R_26_PCREL 1825This is a 26-bit reloc with the right 2 bits assumed to be 0. 1826@end deffn 1827@deffn {} BFD_RELOC_M32R_HI16_ULO 1828This is a 16-bit reloc containing the high 16 bits of an address 1829used when the lower 16 bits are treated as unsigned. 1830@end deffn 1831@deffn {} BFD_RELOC_M32R_HI16_SLO 1832This is a 16-bit reloc containing the high 16 bits of an address 1833used when the lower 16 bits are treated as signed. 1834@end deffn 1835@deffn {} BFD_RELOC_M32R_LO16 1836This is a 16-bit reloc containing the lower 16 bits of an address. 1837@end deffn 1838@deffn {} BFD_RELOC_M32R_SDA16 1839This is a 16-bit reloc containing the small data area offset for use in 1840add3, load, and store instructions. 1841@end deffn 1842@deffn {} BFD_RELOC_M32R_GOT24 1843@deffnx {} BFD_RELOC_M32R_26_PLTREL 1844@deffnx {} BFD_RELOC_M32R_COPY 1845@deffnx {} BFD_RELOC_M32R_GLOB_DAT 1846@deffnx {} BFD_RELOC_M32R_JMP_SLOT 1847@deffnx {} BFD_RELOC_M32R_RELATIVE 1848@deffnx {} BFD_RELOC_M32R_GOTOFF 1849@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1850@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1851@deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1852@deffnx {} BFD_RELOC_M32R_GOTPC24 1853@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1854@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1855@deffnx {} BFD_RELOC_M32R_GOT16_LO 1856@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1857@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1858@deffnx {} BFD_RELOC_M32R_GOTPC_LO 1859For PIC. 1860@end deffn 1861@deffn {} BFD_RELOC_NDS32_20 1862NDS32 relocs. 1863This is a 20 bit absolute address. 1864@end deffn 1865@deffn {} BFD_RELOC_NDS32_9_PCREL 1866This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1867@end deffn 1868@deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1869This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0. 1870@end deffn 1871@deffn {} BFD_RELOC_NDS32_15_PCREL 1872This is an 15-bit reloc with the right 1 bit assumed to be 0. 1873@end deffn 1874@deffn {} BFD_RELOC_NDS32_17_PCREL 1875This is an 17-bit reloc with the right 1 bit assumed to be 0. 1876@end deffn 1877@deffn {} BFD_RELOC_NDS32_25_PCREL 1878This is a 25-bit reloc with the right 1 bit assumed to be 0. 1879@end deffn 1880@deffn {} BFD_RELOC_NDS32_HI20 1881This is a 20-bit reloc containing the high 20 bits of an address 1882used with the lower 12 bits 1883@end deffn 1884@deffn {} BFD_RELOC_NDS32_LO12S3 1885This is a 12-bit reloc containing the lower 12 bits of an address 1886then shift right by 3. This is used with ldi,sdi... 1887@end deffn 1888@deffn {} BFD_RELOC_NDS32_LO12S2 1889This is a 12-bit reloc containing the lower 12 bits of an address 1890then shift left by 2. This is used with lwi,swi... 1891@end deffn 1892@deffn {} BFD_RELOC_NDS32_LO12S1 1893This is a 12-bit reloc containing the lower 12 bits of an address 1894then shift left by 1. This is used with lhi,shi... 1895@end deffn 1896@deffn {} BFD_RELOC_NDS32_LO12S0 1897This is a 12-bit reloc containing the lower 12 bits of an address 1898then shift left by 0. This is used with lbisbi... 1899@end deffn 1900@deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1901This is a 12-bit reloc containing the lower 12 bits of an address 1902then shift left by 0. This is only used with branch relaxations 1903@end deffn 1904@deffn {} BFD_RELOC_NDS32_SDA15S3 1905This is a 15-bit reloc containing the small data area 18-bit signed offset 1906and shift left by 3 for use in ldi, sdi... 1907@end deffn 1908@deffn {} BFD_RELOC_NDS32_SDA15S2 1909This is a 15-bit reloc containing the small data area 17-bit signed offset 1910and shift left by 2 for use in lwi, swi... 1911@end deffn 1912@deffn {} BFD_RELOC_NDS32_SDA15S1 1913This is a 15-bit reloc containing the small data area 16-bit signed offset 1914and shift left by 1 for use in lhi, shi... 1915@end deffn 1916@deffn {} BFD_RELOC_NDS32_SDA15S0 1917This is a 15-bit reloc containing the small data area 15-bit signed offset 1918and shift left by 0 for use in lbi, sbi... 1919@end deffn 1920@deffn {} BFD_RELOC_NDS32_SDA16S3 1921This is a 16-bit reloc containing the small data area 16-bit signed offset 1922and shift left by 3 1923@end deffn 1924@deffn {} BFD_RELOC_NDS32_SDA17S2 1925This is a 17-bit reloc containing the small data area 17-bit signed offset 1926and shift left by 2 for use in lwi.gp, swi.gp... 1927@end deffn 1928@deffn {} BFD_RELOC_NDS32_SDA18S1 1929This is a 18-bit reloc containing the small data area 18-bit signed offset 1930and shift left by 1 for use in lhi.gp, shi.gp... 1931@end deffn 1932@deffn {} BFD_RELOC_NDS32_SDA19S0 1933This is a 19-bit reloc containing the small data area 19-bit signed offset 1934and shift left by 0 for use in lbi.gp, sbi.gp... 1935@end deffn 1936@deffn {} BFD_RELOC_NDS32_GOT20 1937@deffnx {} BFD_RELOC_NDS32_9_PLTREL 1938@deffnx {} BFD_RELOC_NDS32_25_PLTREL 1939@deffnx {} BFD_RELOC_NDS32_COPY 1940@deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1941@deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1942@deffnx {} BFD_RELOC_NDS32_RELATIVE 1943@deffnx {} BFD_RELOC_NDS32_GOTOFF 1944@deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1945@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1946@deffnx {} BFD_RELOC_NDS32_GOTPC20 1947@deffnx {} BFD_RELOC_NDS32_GOT_HI20 1948@deffnx {} BFD_RELOC_NDS32_GOT_LO12 1949@deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1950@deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1951for PIC 1952@end deffn 1953@deffn {} BFD_RELOC_NDS32_INSN16 1954@deffnx {} BFD_RELOC_NDS32_LABEL 1955@deffnx {} BFD_RELOC_NDS32_LONGCALL1 1956@deffnx {} BFD_RELOC_NDS32_LONGCALL2 1957@deffnx {} BFD_RELOC_NDS32_LONGCALL3 1958@deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1959@deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1960@deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1961@deffnx {} BFD_RELOC_NDS32_LOADSTORE 1962@deffnx {} BFD_RELOC_NDS32_9_FIXED 1963@deffnx {} BFD_RELOC_NDS32_15_FIXED 1964@deffnx {} BFD_RELOC_NDS32_17_FIXED 1965@deffnx {} BFD_RELOC_NDS32_25_FIXED 1966@deffnx {} BFD_RELOC_NDS32_LONGCALL4 1967@deffnx {} BFD_RELOC_NDS32_LONGCALL5 1968@deffnx {} BFD_RELOC_NDS32_LONGCALL6 1969@deffnx {} BFD_RELOC_NDS32_LONGJUMP4 1970@deffnx {} BFD_RELOC_NDS32_LONGJUMP5 1971@deffnx {} BFD_RELOC_NDS32_LONGJUMP6 1972@deffnx {} BFD_RELOC_NDS32_LONGJUMP7 1973for relax 1974@end deffn 1975@deffn {} BFD_RELOC_NDS32_PLTREL_HI20 1976@deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 1977@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 1978@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 1979for PIC 1980@end deffn 1981@deffn {} BFD_RELOC_NDS32_SDA12S2_DP 1982@deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 1983@deffnx {} BFD_RELOC_NDS32_LO12S2_DP 1984@deffnx {} BFD_RELOC_NDS32_LO12S2_SP 1985for floating point 1986@end deffn 1987@deffn {} BFD_RELOC_NDS32_DWARF2_OP1 1988@deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 1989@deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 1990for dwarf2 debug_line. 1991@end deffn 1992@deffn {} BFD_RELOC_NDS32_UPDATE_TA 1993for eliminate 16-bit instructions 1994@end deffn 1995@deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 1996@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 1997@deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 1998@deffnx {} BFD_RELOC_NDS32_GOT_LO15 1999@deffnx {} BFD_RELOC_NDS32_GOT_LO19 2000@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2001@deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2002@deffnx {} BFD_RELOC_NDS32_GOT15S2 2003@deffnx {} BFD_RELOC_NDS32_GOT17S2 2004for PIC object relaxation 2005@end deffn 2006@deffn {} BFD_RELOC_NDS32_5 2007NDS32 relocs. 2008This is a 5 bit absolute address. 2009@end deffn 2010@deffn {} BFD_RELOC_NDS32_10_UPCREL 2011This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0. 2012@end deffn 2013@deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2014If fp were omitted, fp can used as another gp. 2015@end deffn 2016@deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2017@deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2018@deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2019@deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2020@deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2021@deffnx {} BFD_RELOC_NDS32_PTR 2022@deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2023@deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2024@deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2025@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2026@deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2027@deffnx {} BFD_RELOC_NDS32_MINUEND 2028@deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2029@deffnx {} BFD_RELOC_NDS32_DIFF8 2030@deffnx {} BFD_RELOC_NDS32_DIFF16 2031@deffnx {} BFD_RELOC_NDS32_DIFF32 2032@deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2033@deffnx {} BFD_RELOC_NDS32_EMPTY 2034relaxation relative relocation types 2035@end deffn 2036@deffn {} BFD_RELOC_NDS32_25_ABS 2037This is a 25 bit absolute address. 2038@end deffn 2039@deffn {} BFD_RELOC_NDS32_DATA 2040@deffnx {} BFD_RELOC_NDS32_TRAN 2041@deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2042@deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2043For ex9 and ifc using. 2044@end deffn 2045@deffn {} BFD_RELOC_NDS32_TPOFF 2046@deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2047@deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2048@deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2049@deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2050@deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2051@deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2052@deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2053@deffnx {} BFD_RELOC_NDS32_TLS_TPOFF 2054@deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2055@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2056@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2057@deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2058For TLS. 2059@end deffn 2060@deffn {} BFD_RELOC_V850_9_PCREL 2061This is a 9-bit reloc 2062@end deffn 2063@deffn {} BFD_RELOC_V850_22_PCREL 2064This is a 22-bit reloc 2065@end deffn 2066@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2067This is a 16 bit offset from the short data area pointer. 2068@end deffn 2069@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2070This is a 16 bit offset (of which only 15 bits are used) from the 2071short data area pointer. 2072@end deffn 2073@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2074This is a 16 bit offset from the zero data area pointer. 2075@end deffn 2076@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2077This is a 16 bit offset (of which only 15 bits are used) from the 2078zero data area pointer. 2079@end deffn 2080@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2081This is an 8 bit offset (of which only 6 bits are used) from the 2082tiny data area pointer. 2083@end deffn 2084@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2085This is an 8bit offset (of which only 7 bits are used) from the tiny 2086data area pointer. 2087@end deffn 2088@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2089This is a 7 bit offset from the tiny data area pointer. 2090@end deffn 2091@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2092This is a 16 bit offset from the tiny data area pointer. 2093@end deffn 2094@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2095This is a 5 bit offset (of which only 4 bits are used) from the tiny 2096data area pointer. 2097@end deffn 2098@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2099This is a 4 bit offset from the tiny data area pointer. 2100@end deffn 2101@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2102This is a 16 bit offset from the short data area pointer, with the 2103bits placed non-contiguously in the instruction. 2104@end deffn 2105@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2106This is a 16 bit offset from the zero data area pointer, with the 2107bits placed non-contiguously in the instruction. 2108@end deffn 2109@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2110This is a 6 bit offset from the call table base pointer. 2111@end deffn 2112@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2113This is a 16 bit offset from the call table base pointer. 2114@end deffn 2115@deffn {} BFD_RELOC_V850_LONGCALL 2116Used for relaxing indirect function calls. 2117@end deffn 2118@deffn {} BFD_RELOC_V850_LONGJUMP 2119Used for relaxing indirect jumps. 2120@end deffn 2121@deffn {} BFD_RELOC_V850_ALIGN 2122Used to maintain alignment whilst relaxing. 2123@end deffn 2124@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2125This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu 2126instructions. 2127@end deffn 2128@deffn {} BFD_RELOC_V850_16_PCREL 2129This is a 16-bit reloc. 2130@end deffn 2131@deffn {} BFD_RELOC_V850_17_PCREL 2132This is a 17-bit reloc. 2133@end deffn 2134@deffn {} BFD_RELOC_V850_23 2135This is a 23-bit reloc. 2136@end deffn 2137@deffn {} BFD_RELOC_V850_32_PCREL 2138This is a 32-bit reloc. 2139@end deffn 2140@deffn {} BFD_RELOC_V850_32_ABS 2141This is a 32-bit reloc. 2142@end deffn 2143@deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2144This is a 16-bit reloc. 2145@end deffn 2146@deffn {} BFD_RELOC_V850_16_S1 2147This is a 16-bit reloc. 2148@end deffn 2149@deffn {} BFD_RELOC_V850_LO16_S1 2150Low 16 bits. 16 bit shifted by 1. 2151@end deffn 2152@deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2153This is a 16 bit offset from the call table base pointer. 2154@end deffn 2155@deffn {} BFD_RELOC_V850_32_GOTPCREL 2156DSO relocations. 2157@end deffn 2158@deffn {} BFD_RELOC_V850_16_GOT 2159DSO relocations. 2160@end deffn 2161@deffn {} BFD_RELOC_V850_32_GOT 2162DSO relocations. 2163@end deffn 2164@deffn {} BFD_RELOC_V850_22_PLT_PCREL 2165DSO relocations. 2166@end deffn 2167@deffn {} BFD_RELOC_V850_32_PLT_PCREL 2168DSO relocations. 2169@end deffn 2170@deffn {} BFD_RELOC_V850_COPY 2171DSO relocations. 2172@end deffn 2173@deffn {} BFD_RELOC_V850_GLOB_DAT 2174DSO relocations. 2175@end deffn 2176@deffn {} BFD_RELOC_V850_JMP_SLOT 2177DSO relocations. 2178@end deffn 2179@deffn {} BFD_RELOC_V850_RELATIVE 2180DSO relocations. 2181@end deffn 2182@deffn {} BFD_RELOC_V850_16_GOTOFF 2183DSO relocations. 2184@end deffn 2185@deffn {} BFD_RELOC_V850_32_GOTOFF 2186DSO relocations. 2187@end deffn 2188@deffn {} BFD_RELOC_V850_CODE 2189start code. 2190@end deffn 2191@deffn {} BFD_RELOC_V850_DATA 2192start data in text. 2193@end deffn 2194@deffn {} BFD_RELOC_TIC30_LDP 2195This is a 8bit DP reloc for the tms320c30, where the most 2196significant 8 bits of a 24 bit word are placed into the least 2197significant 8 bits of the opcode. 2198@end deffn 2199@deffn {} BFD_RELOC_TIC54X_PARTLS7 2200This is a 7bit reloc for the tms320c54x, where the least 2201significant 7 bits of a 16 bit word are placed into the least 2202significant 7 bits of the opcode. 2203@end deffn 2204@deffn {} BFD_RELOC_TIC54X_PARTMS9 2205This is a 9bit DP reloc for the tms320c54x, where the most 2206significant 9 bits of a 16 bit word are placed into the least 2207significant 9 bits of the opcode. 2208@end deffn 2209@deffn {} BFD_RELOC_TIC54X_23 2210This is an extended address 23-bit reloc for the tms320c54x. 2211@end deffn 2212@deffn {} BFD_RELOC_TIC54X_16_OF_23 2213This is a 16-bit reloc for the tms320c54x, where the least 2214significant 16 bits of a 23-bit extended address are placed into 2215the opcode. 2216@end deffn 2217@deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2218This is a reloc for the tms320c54x, where the most 2219significant 7 bits of a 23-bit extended address are placed into 2220the opcode. 2221@end deffn 2222@deffn {} BFD_RELOC_C6000_PCR_S21 2223@deffnx {} BFD_RELOC_C6000_PCR_S12 2224@deffnx {} BFD_RELOC_C6000_PCR_S10 2225@deffnx {} BFD_RELOC_C6000_PCR_S7 2226@deffnx {} BFD_RELOC_C6000_ABS_S16 2227@deffnx {} BFD_RELOC_C6000_ABS_L16 2228@deffnx {} BFD_RELOC_C6000_ABS_H16 2229@deffnx {} BFD_RELOC_C6000_SBR_U15_B 2230@deffnx {} BFD_RELOC_C6000_SBR_U15_H 2231@deffnx {} BFD_RELOC_C6000_SBR_U15_W 2232@deffnx {} BFD_RELOC_C6000_SBR_S16 2233@deffnx {} BFD_RELOC_C6000_SBR_L16_B 2234@deffnx {} BFD_RELOC_C6000_SBR_L16_H 2235@deffnx {} BFD_RELOC_C6000_SBR_L16_W 2236@deffnx {} BFD_RELOC_C6000_SBR_H16_B 2237@deffnx {} BFD_RELOC_C6000_SBR_H16_H 2238@deffnx {} BFD_RELOC_C6000_SBR_H16_W 2239@deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2240@deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2241@deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2242@deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2243@deffnx {} BFD_RELOC_C6000_PREL31 2244@deffnx {} BFD_RELOC_C6000_COPY 2245@deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2246@deffnx {} BFD_RELOC_C6000_EHTYPE 2247@deffnx {} BFD_RELOC_C6000_PCR_H16 2248@deffnx {} BFD_RELOC_C6000_PCR_L16 2249@deffnx {} BFD_RELOC_C6000_ALIGN 2250@deffnx {} BFD_RELOC_C6000_FPHEAD 2251@deffnx {} BFD_RELOC_C6000_NOCMP 2252TMS320C6000 relocations. 2253@end deffn 2254@deffn {} BFD_RELOC_FR30_48 2255This is a 48 bit reloc for the FR30 that stores 32 bits. 2256@end deffn 2257@deffn {} BFD_RELOC_FR30_20 2258This is a 32 bit reloc for the FR30 that stores 20 bits split up into 2259two sections. 2260@end deffn 2261@deffn {} BFD_RELOC_FR30_6_IN_4 2262This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in 22634 bits. 2264@end deffn 2265@deffn {} BFD_RELOC_FR30_8_IN_8 2266This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2267into 8 bits. 2268@end deffn 2269@deffn {} BFD_RELOC_FR30_9_IN_8 2270This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2271into 8 bits. 2272@end deffn 2273@deffn {} BFD_RELOC_FR30_10_IN_8 2274This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2275into 8 bits. 2276@end deffn 2277@deffn {} BFD_RELOC_FR30_9_PCREL 2278This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2279short offset into 8 bits. 2280@end deffn 2281@deffn {} BFD_RELOC_FR30_12_PCREL 2282This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2283short offset into 11 bits. 2284@end deffn 2285@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2286@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2287@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2288@deffnx {} BFD_RELOC_MCORE_PCREL_32 2289@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2290@deffnx {} BFD_RELOC_MCORE_RVA 2291Motorola Mcore relocations. 2292@end deffn 2293@deffn {} BFD_RELOC_MEP_8 2294@deffnx {} BFD_RELOC_MEP_16 2295@deffnx {} BFD_RELOC_MEP_32 2296@deffnx {} BFD_RELOC_MEP_PCREL8A2 2297@deffnx {} BFD_RELOC_MEP_PCREL12A2 2298@deffnx {} BFD_RELOC_MEP_PCREL17A2 2299@deffnx {} BFD_RELOC_MEP_PCREL24A2 2300@deffnx {} BFD_RELOC_MEP_PCABS24A2 2301@deffnx {} BFD_RELOC_MEP_LOW16 2302@deffnx {} BFD_RELOC_MEP_HI16U 2303@deffnx {} BFD_RELOC_MEP_HI16S 2304@deffnx {} BFD_RELOC_MEP_GPREL 2305@deffnx {} BFD_RELOC_MEP_TPREL 2306@deffnx {} BFD_RELOC_MEP_TPREL7 2307@deffnx {} BFD_RELOC_MEP_TPREL7A2 2308@deffnx {} BFD_RELOC_MEP_TPREL7A4 2309@deffnx {} BFD_RELOC_MEP_UIMM24 2310@deffnx {} BFD_RELOC_MEP_ADDR24A4 2311@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2312@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2313Toshiba Media Processor Relocations. 2314@end deffn 2315@deffn {} BFD_RELOC_METAG_HIADDR16 2316@deffnx {} BFD_RELOC_METAG_LOADDR16 2317@deffnx {} BFD_RELOC_METAG_RELBRANCH 2318@deffnx {} BFD_RELOC_METAG_GETSETOFF 2319@deffnx {} BFD_RELOC_METAG_HIOG 2320@deffnx {} BFD_RELOC_METAG_LOOG 2321@deffnx {} BFD_RELOC_METAG_REL8 2322@deffnx {} BFD_RELOC_METAG_REL16 2323@deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2324@deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2325@deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2326@deffnx {} BFD_RELOC_METAG_GETSET_GOT 2327@deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2328@deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2329@deffnx {} BFD_RELOC_METAG_HI16_PLT 2330@deffnx {} BFD_RELOC_METAG_LO16_PLT 2331@deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2332@deffnx {} BFD_RELOC_METAG_GOTOFF 2333@deffnx {} BFD_RELOC_METAG_PLT 2334@deffnx {} BFD_RELOC_METAG_COPY 2335@deffnx {} BFD_RELOC_METAG_JMP_SLOT 2336@deffnx {} BFD_RELOC_METAG_RELATIVE 2337@deffnx {} BFD_RELOC_METAG_GLOB_DAT 2338@deffnx {} BFD_RELOC_METAG_TLS_GD 2339@deffnx {} BFD_RELOC_METAG_TLS_LDM 2340@deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2341@deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2342@deffnx {} BFD_RELOC_METAG_TLS_LDO 2343@deffnx {} BFD_RELOC_METAG_TLS_IE 2344@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2345@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2346@deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2347@deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2348@deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2349@deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2350@deffnx {} BFD_RELOC_METAG_TLS_LE 2351@deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2352@deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2353Imagination Technologies Meta relocations. 2354@end deffn 2355@deffn {} BFD_RELOC_MMIX_GETA 2356@deffnx {} BFD_RELOC_MMIX_GETA_1 2357@deffnx {} BFD_RELOC_MMIX_GETA_2 2358@deffnx {} BFD_RELOC_MMIX_GETA_3 2359These are relocations for the GETA instruction. 2360@end deffn 2361@deffn {} BFD_RELOC_MMIX_CBRANCH 2362@deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2363@deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2364@deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2365@deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2366These are relocations for a conditional branch instruction. 2367@end deffn 2368@deffn {} BFD_RELOC_MMIX_PUSHJ 2369@deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2370@deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2371@deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2372@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2373These are relocations for the PUSHJ instruction. 2374@end deffn 2375@deffn {} BFD_RELOC_MMIX_JMP 2376@deffnx {} BFD_RELOC_MMIX_JMP_1 2377@deffnx {} BFD_RELOC_MMIX_JMP_2 2378@deffnx {} BFD_RELOC_MMIX_JMP_3 2379These are relocations for the JMP instruction. 2380@end deffn 2381@deffn {} BFD_RELOC_MMIX_ADDR19 2382This is a relocation for a relative address as in a GETA instruction or 2383a branch. 2384@end deffn 2385@deffn {} BFD_RELOC_MMIX_ADDR27 2386This is a relocation for a relative address as in a JMP instruction. 2387@end deffn 2388@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2389This is a relocation for an instruction field that may be a general 2390register or a value 0..255. 2391@end deffn 2392@deffn {} BFD_RELOC_MMIX_REG 2393This is a relocation for an instruction field that may be a general 2394register. 2395@end deffn 2396@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2397This is a relocation for two instruction fields holding a register and 2398an offset, the equivalent of the relocation. 2399@end deffn 2400@deffn {} BFD_RELOC_MMIX_LOCAL 2401This relocation is an assertion that the expression is not allocated as 2402a global register. It does not modify contents. 2403@end deffn 2404@deffn {} BFD_RELOC_AVR_7_PCREL 2405This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2406short offset into 7 bits. 2407@end deffn 2408@deffn {} BFD_RELOC_AVR_13_PCREL 2409This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2410short offset into 12 bits. 2411@end deffn 2412@deffn {} BFD_RELOC_AVR_16_PM 2413This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2414program memory address) into 16 bits. 2415@end deffn 2416@deffn {} BFD_RELOC_AVR_LO8_LDI 2417This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2418data memory address) into 8 bit immediate value of LDI insn. 2419@end deffn 2420@deffn {} BFD_RELOC_AVR_HI8_LDI 2421This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2422of data memory address) into 8 bit immediate value of LDI insn. 2423@end deffn 2424@deffn {} BFD_RELOC_AVR_HH8_LDI 2425This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2426of program memory address) into 8 bit immediate value of LDI insn. 2427@end deffn 2428@deffn {} BFD_RELOC_AVR_MS8_LDI 2429This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2430of 32 bit value) into 8 bit immediate value of LDI insn. 2431@end deffn 2432@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2433This is a 16 bit reloc for the AVR that stores negated 8 bit value 2434(usually data memory address) into 8 bit immediate value of SUBI insn. 2435@end deffn 2436@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2437This is a 16 bit reloc for the AVR that stores negated 8 bit value 2438(high 8 bit of data memory address) into 8 bit immediate value of 2439SUBI insn. 2440@end deffn 2441@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2442This is a 16 bit reloc for the AVR that stores negated 8 bit value 2443(most high 8 bit of program memory address) into 8 bit immediate value 2444of LDI or SUBI insn. 2445@end deffn 2446@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2447This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb 2448of 32 bit value) into 8 bit immediate value of LDI insn. 2449@end deffn 2450@deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2451This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2452command address) into 8 bit immediate value of LDI insn. 2453@end deffn 2454@deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2455This is a 16 bit reloc for the AVR that stores 8 bit value 2456(command address) into 8 bit immediate value of LDI insn. If the address 2457is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2458in the lower 128k. 2459@end deffn 2460@deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2461This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2462of command address) into 8 bit immediate value of LDI insn. 2463@end deffn 2464@deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2465This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2466of command address) into 8 bit immediate value of LDI insn. If the address 2467is beyond the 128k boundary, the linker inserts a jump stub for this reloc 2468below 128k. 2469@end deffn 2470@deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2471This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit 2472of command address) into 8 bit immediate value of LDI insn. 2473@end deffn 2474@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2475This is a 16 bit reloc for the AVR that stores negated 8 bit value 2476(usually command address) into 8 bit immediate value of SUBI insn. 2477@end deffn 2478@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2479This is a 16 bit reloc for the AVR that stores negated 8 bit value 2480(high 8 bit of 16 bit command address) into 8 bit immediate value 2481of SUBI insn. 2482@end deffn 2483@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2484This is a 16 bit reloc for the AVR that stores negated 8 bit value 2485(high 6 bit of 22 bit command address) into 8 bit immediate 2486value of SUBI insn. 2487@end deffn 2488@deffn {} BFD_RELOC_AVR_CALL 2489This is a 32 bit reloc for the AVR that stores 23 bit value 2490into 22 bits. 2491@end deffn 2492@deffn {} BFD_RELOC_AVR_LDI 2493This is a 16 bit reloc for the AVR that stores all needed bits 2494for absolute addressing with ldi with overflow check to linktime 2495@end deffn 2496@deffn {} BFD_RELOC_AVR_6 2497This is a 6 bit reloc for the AVR that stores offset for ldd/std 2498instructions 2499@end deffn 2500@deffn {} BFD_RELOC_AVR_6_ADIW 2501This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2502instructions 2503@end deffn 2504@deffn {} BFD_RELOC_AVR_8_LO 2505This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2506in .byte lo8(symbol) 2507@end deffn 2508@deffn {} BFD_RELOC_AVR_8_HI 2509This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2510in .byte hi8(symbol) 2511@end deffn 2512@deffn {} BFD_RELOC_AVR_8_HLO 2513This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2514in .byte hlo8(symbol) 2515@end deffn 2516@deffn {} BFD_RELOC_AVR_DIFF8 2517@deffnx {} BFD_RELOC_AVR_DIFF16 2518@deffnx {} BFD_RELOC_AVR_DIFF32 2519AVR relocations to mark the difference of two local symbols. 2520These are only needed to support linker relaxation and can be ignored 2521when not relaxing. The field is set to the value of the difference 2522assuming no relaxation. The relocation encodes the position of the 2523second symbol so the linker can determine whether to adjust the field 2524value. 2525@end deffn 2526@deffn {} BFD_RELOC_AVR_LDS_STS_16 2527This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2528lds and sts instructions supported only tiny core. 2529@end deffn 2530@deffn {} BFD_RELOC_AVR_PORT6 2531This is a 6 bit reloc for the AVR that stores an I/O register 2532number for the IN and OUT instructions 2533@end deffn 2534@deffn {} BFD_RELOC_AVR_PORT5 2535This is a 5 bit reloc for the AVR that stores an I/O register 2536number for the SBIC, SBIS, SBI and CBI instructions 2537@end deffn 2538@deffn {} BFD_RELOC_RL78_NEG8 2539@deffnx {} BFD_RELOC_RL78_NEG16 2540@deffnx {} BFD_RELOC_RL78_NEG24 2541@deffnx {} BFD_RELOC_RL78_NEG32 2542@deffnx {} BFD_RELOC_RL78_16_OP 2543@deffnx {} BFD_RELOC_RL78_24_OP 2544@deffnx {} BFD_RELOC_RL78_32_OP 2545@deffnx {} BFD_RELOC_RL78_8U 2546@deffnx {} BFD_RELOC_RL78_16U 2547@deffnx {} BFD_RELOC_RL78_24U 2548@deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2549@deffnx {} BFD_RELOC_RL78_DIFF 2550@deffnx {} BFD_RELOC_RL78_GPRELB 2551@deffnx {} BFD_RELOC_RL78_GPRELW 2552@deffnx {} BFD_RELOC_RL78_GPRELL 2553@deffnx {} BFD_RELOC_RL78_SYM 2554@deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2555@deffnx {} BFD_RELOC_RL78_OP_NEG 2556@deffnx {} BFD_RELOC_RL78_OP_AND 2557@deffnx {} BFD_RELOC_RL78_OP_SHRA 2558@deffnx {} BFD_RELOC_RL78_ABS8 2559@deffnx {} BFD_RELOC_RL78_ABS16 2560@deffnx {} BFD_RELOC_RL78_ABS16_REV 2561@deffnx {} BFD_RELOC_RL78_ABS32 2562@deffnx {} BFD_RELOC_RL78_ABS32_REV 2563@deffnx {} BFD_RELOC_RL78_ABS16U 2564@deffnx {} BFD_RELOC_RL78_ABS16UW 2565@deffnx {} BFD_RELOC_RL78_ABS16UL 2566@deffnx {} BFD_RELOC_RL78_RELAX 2567@deffnx {} BFD_RELOC_RL78_HI16 2568@deffnx {} BFD_RELOC_RL78_HI8 2569@deffnx {} BFD_RELOC_RL78_LO16 2570@deffnx {} BFD_RELOC_RL78_CODE 2571@deffnx {} BFD_RELOC_RL78_SADDR 2572Renesas RL78 Relocations. 2573@end deffn 2574@deffn {} BFD_RELOC_RX_NEG8 2575@deffnx {} BFD_RELOC_RX_NEG16 2576@deffnx {} BFD_RELOC_RX_NEG24 2577@deffnx {} BFD_RELOC_RX_NEG32 2578@deffnx {} BFD_RELOC_RX_16_OP 2579@deffnx {} BFD_RELOC_RX_24_OP 2580@deffnx {} BFD_RELOC_RX_32_OP 2581@deffnx {} BFD_RELOC_RX_8U 2582@deffnx {} BFD_RELOC_RX_16U 2583@deffnx {} BFD_RELOC_RX_24U 2584@deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2585@deffnx {} BFD_RELOC_RX_DIFF 2586@deffnx {} BFD_RELOC_RX_GPRELB 2587@deffnx {} BFD_RELOC_RX_GPRELW 2588@deffnx {} BFD_RELOC_RX_GPRELL 2589@deffnx {} BFD_RELOC_RX_SYM 2590@deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2591@deffnx {} BFD_RELOC_RX_OP_NEG 2592@deffnx {} BFD_RELOC_RX_ABS8 2593@deffnx {} BFD_RELOC_RX_ABS16 2594@deffnx {} BFD_RELOC_RX_ABS16_REV 2595@deffnx {} BFD_RELOC_RX_ABS32 2596@deffnx {} BFD_RELOC_RX_ABS32_REV 2597@deffnx {} BFD_RELOC_RX_ABS16U 2598@deffnx {} BFD_RELOC_RX_ABS16UW 2599@deffnx {} BFD_RELOC_RX_ABS16UL 2600@deffnx {} BFD_RELOC_RX_RELAX 2601Renesas RX Relocations. 2602@end deffn 2603@deffn {} BFD_RELOC_390_12 2604Direct 12 bit. 2605@end deffn 2606@deffn {} BFD_RELOC_390_GOT12 260712 bit GOT offset. 2608@end deffn 2609@deffn {} BFD_RELOC_390_PLT32 261032 bit PC relative PLT address. 2611@end deffn 2612@deffn {} BFD_RELOC_390_COPY 2613Copy symbol at runtime. 2614@end deffn 2615@deffn {} BFD_RELOC_390_GLOB_DAT 2616Create GOT entry. 2617@end deffn 2618@deffn {} BFD_RELOC_390_JMP_SLOT 2619Create PLT entry. 2620@end deffn 2621@deffn {} BFD_RELOC_390_RELATIVE 2622Adjust by program base. 2623@end deffn 2624@deffn {} BFD_RELOC_390_GOTPC 262532 bit PC relative offset to GOT. 2626@end deffn 2627@deffn {} BFD_RELOC_390_GOT16 262816 bit GOT offset. 2629@end deffn 2630@deffn {} BFD_RELOC_390_PC12DBL 2631PC relative 12 bit shifted by 1. 2632@end deffn 2633@deffn {} BFD_RELOC_390_PLT12DBL 263412 bit PC rel. PLT shifted by 1. 2635@end deffn 2636@deffn {} BFD_RELOC_390_PC16DBL 2637PC relative 16 bit shifted by 1. 2638@end deffn 2639@deffn {} BFD_RELOC_390_PLT16DBL 264016 bit PC rel. PLT shifted by 1. 2641@end deffn 2642@deffn {} BFD_RELOC_390_PC24DBL 2643PC relative 24 bit shifted by 1. 2644@end deffn 2645@deffn {} BFD_RELOC_390_PLT24DBL 264624 bit PC rel. PLT shifted by 1. 2647@end deffn 2648@deffn {} BFD_RELOC_390_PC32DBL 2649PC relative 32 bit shifted by 1. 2650@end deffn 2651@deffn {} BFD_RELOC_390_PLT32DBL 265232 bit PC rel. PLT shifted by 1. 2653@end deffn 2654@deffn {} BFD_RELOC_390_GOTPCDBL 265532 bit PC rel. GOT shifted by 1. 2656@end deffn 2657@deffn {} BFD_RELOC_390_GOT64 265864 bit GOT offset. 2659@end deffn 2660@deffn {} BFD_RELOC_390_PLT64 266164 bit PC relative PLT address. 2662@end deffn 2663@deffn {} BFD_RELOC_390_GOTENT 266432 bit rel. offset to GOT entry. 2665@end deffn 2666@deffn {} BFD_RELOC_390_GOTOFF64 266764 bit offset to GOT. 2668@end deffn 2669@deffn {} BFD_RELOC_390_GOTPLT12 267012-bit offset to symbol-entry within GOT, with PLT handling. 2671@end deffn 2672@deffn {} BFD_RELOC_390_GOTPLT16 267316-bit offset to symbol-entry within GOT, with PLT handling. 2674@end deffn 2675@deffn {} BFD_RELOC_390_GOTPLT32 267632-bit offset to symbol-entry within GOT, with PLT handling. 2677@end deffn 2678@deffn {} BFD_RELOC_390_GOTPLT64 267964-bit offset to symbol-entry within GOT, with PLT handling. 2680@end deffn 2681@deffn {} BFD_RELOC_390_GOTPLTENT 268232-bit rel. offset to symbol-entry within GOT, with PLT handling. 2683@end deffn 2684@deffn {} BFD_RELOC_390_PLTOFF16 268516-bit rel. offset from the GOT to a PLT entry. 2686@end deffn 2687@deffn {} BFD_RELOC_390_PLTOFF32 268832-bit rel. offset from the GOT to a PLT entry. 2689@end deffn 2690@deffn {} BFD_RELOC_390_PLTOFF64 269164-bit rel. offset from the GOT to a PLT entry. 2692@end deffn 2693@deffn {} BFD_RELOC_390_TLS_LOAD 2694@deffnx {} BFD_RELOC_390_TLS_GDCALL 2695@deffnx {} BFD_RELOC_390_TLS_LDCALL 2696@deffnx {} BFD_RELOC_390_TLS_GD32 2697@deffnx {} BFD_RELOC_390_TLS_GD64 2698@deffnx {} BFD_RELOC_390_TLS_GOTIE12 2699@deffnx {} BFD_RELOC_390_TLS_GOTIE32 2700@deffnx {} BFD_RELOC_390_TLS_GOTIE64 2701@deffnx {} BFD_RELOC_390_TLS_LDM32 2702@deffnx {} BFD_RELOC_390_TLS_LDM64 2703@deffnx {} BFD_RELOC_390_TLS_IE32 2704@deffnx {} BFD_RELOC_390_TLS_IE64 2705@deffnx {} BFD_RELOC_390_TLS_IEENT 2706@deffnx {} BFD_RELOC_390_TLS_LE32 2707@deffnx {} BFD_RELOC_390_TLS_LE64 2708@deffnx {} BFD_RELOC_390_TLS_LDO32 2709@deffnx {} BFD_RELOC_390_TLS_LDO64 2710@deffnx {} BFD_RELOC_390_TLS_DTPMOD 2711@deffnx {} BFD_RELOC_390_TLS_DTPOFF 2712@deffnx {} BFD_RELOC_390_TLS_TPOFF 2713s390 tls relocations. 2714@end deffn 2715@deffn {} BFD_RELOC_390_20 2716@deffnx {} BFD_RELOC_390_GOT20 2717@deffnx {} BFD_RELOC_390_GOTPLT20 2718@deffnx {} BFD_RELOC_390_TLS_GOTIE20 2719Long displacement extension. 2720@end deffn 2721@deffn {} BFD_RELOC_390_IRELATIVE 2722STT_GNU_IFUNC relocation. 2723@end deffn 2724@deffn {} BFD_RELOC_SCORE_GPREL15 2725Score relocations 2726Low 16 bit for load/store 2727@end deffn 2728@deffn {} BFD_RELOC_SCORE_DUMMY2 2729@deffnx {} BFD_RELOC_SCORE_JMP 2730This is a 24-bit reloc with the right 1 bit assumed to be 0 2731@end deffn 2732@deffn {} BFD_RELOC_SCORE_BRANCH 2733This is a 19-bit reloc with the right 1 bit assumed to be 0 2734@end deffn 2735@deffn {} BFD_RELOC_SCORE_IMM30 2736This is a 32-bit reloc for 48-bit instructions. 2737@end deffn 2738@deffn {} BFD_RELOC_SCORE_IMM32 2739This is a 32-bit reloc for 48-bit instructions. 2740@end deffn 2741@deffn {} BFD_RELOC_SCORE16_JMP 2742This is a 11-bit reloc with the right 1 bit assumed to be 0 2743@end deffn 2744@deffn {} BFD_RELOC_SCORE16_BRANCH 2745This is a 8-bit reloc with the right 1 bit assumed to be 0 2746@end deffn 2747@deffn {} BFD_RELOC_SCORE_BCMP 2748This is a 9-bit reloc with the right 1 bit assumed to be 0 2749@end deffn 2750@deffn {} BFD_RELOC_SCORE_GOT15 2751@deffnx {} BFD_RELOC_SCORE_GOT_LO16 2752@deffnx {} BFD_RELOC_SCORE_CALL15 2753@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2754Undocumented Score relocs 2755@end deffn 2756@deffn {} BFD_RELOC_IP2K_FR9 2757Scenix IP2K - 9-bit register number / data address 2758@end deffn 2759@deffn {} BFD_RELOC_IP2K_BANK 2760Scenix IP2K - 4-bit register/data bank number 2761@end deffn 2762@deffn {} BFD_RELOC_IP2K_ADDR16CJP 2763Scenix IP2K - low 13 bits of instruction word address 2764@end deffn 2765@deffn {} BFD_RELOC_IP2K_PAGE3 2766Scenix IP2K - high 3 bits of instruction word address 2767@end deffn 2768@deffn {} BFD_RELOC_IP2K_LO8DATA 2769@deffnx {} BFD_RELOC_IP2K_HI8DATA 2770@deffnx {} BFD_RELOC_IP2K_EX8DATA 2771Scenix IP2K - ext/low/high 8 bits of data address 2772@end deffn 2773@deffn {} BFD_RELOC_IP2K_LO8INSN 2774@deffnx {} BFD_RELOC_IP2K_HI8INSN 2775Scenix IP2K - low/high 8 bits of instruction word address 2776@end deffn 2777@deffn {} BFD_RELOC_IP2K_PC_SKIP 2778Scenix IP2K - even/odd PC modifier to modify snb pcl.0 2779@end deffn 2780@deffn {} BFD_RELOC_IP2K_TEXT 2781Scenix IP2K - 16 bit word address in text section. 2782@end deffn 2783@deffn {} BFD_RELOC_IP2K_FR_OFFSET 2784Scenix IP2K - 7-bit sp or dp offset 2785@end deffn 2786@deffn {} BFD_RELOC_VPE4KMATH_DATA 2787@deffnx {} BFD_RELOC_VPE4KMATH_INSN 2788Scenix VPE4K coprocessor - data/insn-space addressing 2789@end deffn 2790@deffn {} BFD_RELOC_VTABLE_INHERIT 2791@deffnx {} BFD_RELOC_VTABLE_ENTRY 2792These two relocations are used by the linker to determine which of 2793the entries in a C++ virtual function table are actually used. When 2794the --gc-sections option is given, the linker will zero out the entries 2795that are not used, so that the code for those functions need not be 2796included in the output. 2797 2798VTABLE_INHERIT is a zero-space relocation used to describe to the 2799linker the inheritance tree of a C++ virtual function table. The 2800relocation's symbol should be the parent class' vtable, and the 2801relocation should be located at the child vtable. 2802 2803VTABLE_ENTRY is a zero-space relocation that describes the use of a 2804virtual function table entry. The reloc's symbol should refer to the 2805table of the class mentioned in the code. Off of that base, an offset 2806describes the entry that is being used. For Rela hosts, this offset 2807is stored in the reloc's addend. For Rel hosts, we are forced to put 2808this offset in the reloc's section offset. 2809@end deffn 2810@deffn {} BFD_RELOC_IA64_IMM14 2811@deffnx {} BFD_RELOC_IA64_IMM22 2812@deffnx {} BFD_RELOC_IA64_IMM64 2813@deffnx {} BFD_RELOC_IA64_DIR32MSB 2814@deffnx {} BFD_RELOC_IA64_DIR32LSB 2815@deffnx {} BFD_RELOC_IA64_DIR64MSB 2816@deffnx {} BFD_RELOC_IA64_DIR64LSB 2817@deffnx {} BFD_RELOC_IA64_GPREL22 2818@deffnx {} BFD_RELOC_IA64_GPREL64I 2819@deffnx {} BFD_RELOC_IA64_GPREL32MSB 2820@deffnx {} BFD_RELOC_IA64_GPREL32LSB 2821@deffnx {} BFD_RELOC_IA64_GPREL64MSB 2822@deffnx {} BFD_RELOC_IA64_GPREL64LSB 2823@deffnx {} BFD_RELOC_IA64_LTOFF22 2824@deffnx {} BFD_RELOC_IA64_LTOFF64I 2825@deffnx {} BFD_RELOC_IA64_PLTOFF22 2826@deffnx {} BFD_RELOC_IA64_PLTOFF64I 2827@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2828@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2829@deffnx {} BFD_RELOC_IA64_FPTR64I 2830@deffnx {} BFD_RELOC_IA64_FPTR32MSB 2831@deffnx {} BFD_RELOC_IA64_FPTR32LSB 2832@deffnx {} BFD_RELOC_IA64_FPTR64MSB 2833@deffnx {} BFD_RELOC_IA64_FPTR64LSB 2834@deffnx {} BFD_RELOC_IA64_PCREL21B 2835@deffnx {} BFD_RELOC_IA64_PCREL21BI 2836@deffnx {} BFD_RELOC_IA64_PCREL21M 2837@deffnx {} BFD_RELOC_IA64_PCREL21F 2838@deffnx {} BFD_RELOC_IA64_PCREL22 2839@deffnx {} BFD_RELOC_IA64_PCREL60B 2840@deffnx {} BFD_RELOC_IA64_PCREL64I 2841@deffnx {} BFD_RELOC_IA64_PCREL32MSB 2842@deffnx {} BFD_RELOC_IA64_PCREL32LSB 2843@deffnx {} BFD_RELOC_IA64_PCREL64MSB 2844@deffnx {} BFD_RELOC_IA64_PCREL64LSB 2845@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2846@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2847@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2848@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2849@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2850@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2851@deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2852@deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2853@deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2854@deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2855@deffnx {} BFD_RELOC_IA64_SECREL32MSB 2856@deffnx {} BFD_RELOC_IA64_SECREL32LSB 2857@deffnx {} BFD_RELOC_IA64_SECREL64MSB 2858@deffnx {} BFD_RELOC_IA64_SECREL64LSB 2859@deffnx {} BFD_RELOC_IA64_REL32MSB 2860@deffnx {} BFD_RELOC_IA64_REL32LSB 2861@deffnx {} BFD_RELOC_IA64_REL64MSB 2862@deffnx {} BFD_RELOC_IA64_REL64LSB 2863@deffnx {} BFD_RELOC_IA64_LTV32MSB 2864@deffnx {} BFD_RELOC_IA64_LTV32LSB 2865@deffnx {} BFD_RELOC_IA64_LTV64MSB 2866@deffnx {} BFD_RELOC_IA64_LTV64LSB 2867@deffnx {} BFD_RELOC_IA64_IPLTMSB 2868@deffnx {} BFD_RELOC_IA64_IPLTLSB 2869@deffnx {} BFD_RELOC_IA64_COPY 2870@deffnx {} BFD_RELOC_IA64_LTOFF22X 2871@deffnx {} BFD_RELOC_IA64_LDXMOV 2872@deffnx {} BFD_RELOC_IA64_TPREL14 2873@deffnx {} BFD_RELOC_IA64_TPREL22 2874@deffnx {} BFD_RELOC_IA64_TPREL64I 2875@deffnx {} BFD_RELOC_IA64_TPREL64MSB 2876@deffnx {} BFD_RELOC_IA64_TPREL64LSB 2877@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2878@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2879@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2880@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2881@deffnx {} BFD_RELOC_IA64_DTPREL14 2882@deffnx {} BFD_RELOC_IA64_DTPREL22 2883@deffnx {} BFD_RELOC_IA64_DTPREL64I 2884@deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2885@deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2886@deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2887@deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2888@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2889Intel IA64 Relocations. 2890@end deffn 2891@deffn {} BFD_RELOC_M68HC11_HI8 2892Motorola 68HC11 reloc. 2893This is the 8 bit high part of an absolute address. 2894@end deffn 2895@deffn {} BFD_RELOC_M68HC11_LO8 2896Motorola 68HC11 reloc. 2897This is the 8 bit low part of an absolute address. 2898@end deffn 2899@deffn {} BFD_RELOC_M68HC11_3B 2900Motorola 68HC11 reloc. 2901This is the 3 bit of a value. 2902@end deffn 2903@deffn {} BFD_RELOC_M68HC11_RL_JUMP 2904Motorola 68HC11 reloc. 2905This reloc marks the beginning of a jump/call instruction. 2906It is used for linker relaxation to correctly identify beginning 2907of instruction and change some branches to use PC-relative 2908addressing mode. 2909@end deffn 2910@deffn {} BFD_RELOC_M68HC11_RL_GROUP 2911Motorola 68HC11 reloc. 2912This reloc marks a group of several instructions that gcc generates 2913and for which the linker relaxation pass can modify and/or remove 2914some of them. 2915@end deffn 2916@deffn {} BFD_RELOC_M68HC11_LO16 2917Motorola 68HC11 reloc. 2918This is the 16-bit lower part of an address. It is used for 'call' 2919instruction to specify the symbol address without any special 2920transformation (due to memory bank window). 2921@end deffn 2922@deffn {} BFD_RELOC_M68HC11_PAGE 2923Motorola 68HC11 reloc. 2924This is a 8-bit reloc that specifies the page number of an address. 2925It is used by 'call' instruction to specify the page number of 2926the symbol. 2927@end deffn 2928@deffn {} BFD_RELOC_M68HC11_24 2929Motorola 68HC11 reloc. 2930This is a 24-bit reloc that represents the address with a 16-bit 2931value and a 8-bit page number. The symbol address is transformed 2932to follow the 16K memory bank of 68HC12 (seen as mapped in the window). 2933@end deffn 2934@deffn {} BFD_RELOC_M68HC12_5B 2935Motorola 68HC12 reloc. 2936This is the 5 bits of a value. 2937@end deffn 2938@deffn {} BFD_RELOC_XGATE_RL_JUMP 2939Freescale XGATE reloc. 2940This reloc marks the beginning of a bra/jal instruction. 2941@end deffn 2942@deffn {} BFD_RELOC_XGATE_RL_GROUP 2943Freescale XGATE reloc. 2944This reloc marks a group of several instructions that gcc generates 2945and for which the linker relaxation pass can modify and/or remove 2946some of them. 2947@end deffn 2948@deffn {} BFD_RELOC_XGATE_LO16 2949Freescale XGATE reloc. 2950This is the 16-bit lower part of an address. It is used for the '16-bit' 2951instructions. 2952@end deffn 2953@deffn {} BFD_RELOC_XGATE_GPAGE 2954Freescale XGATE reloc. 2955@end deffn 2956@deffn {} BFD_RELOC_XGATE_24 2957Freescale XGATE reloc. 2958@end deffn 2959@deffn {} BFD_RELOC_XGATE_PCREL_9 2960Freescale XGATE reloc. 2961This is a 9-bit pc-relative reloc. 2962@end deffn 2963@deffn {} BFD_RELOC_XGATE_PCREL_10 2964Freescale XGATE reloc. 2965This is a 10-bit pc-relative reloc. 2966@end deffn 2967@deffn {} BFD_RELOC_XGATE_IMM8_LO 2968Freescale XGATE reloc. 2969This is the 16-bit lower part of an address. It is used for the '16-bit' 2970instructions. 2971@end deffn 2972@deffn {} BFD_RELOC_XGATE_IMM8_HI 2973Freescale XGATE reloc. 2974This is the 16-bit higher part of an address. It is used for the '16-bit' 2975instructions. 2976@end deffn 2977@deffn {} BFD_RELOC_XGATE_IMM3 2978Freescale XGATE reloc. 2979This is a 3-bit pc-relative reloc. 2980@end deffn 2981@deffn {} BFD_RELOC_XGATE_IMM4 2982Freescale XGATE reloc. 2983This is a 4-bit pc-relative reloc. 2984@end deffn 2985@deffn {} BFD_RELOC_XGATE_IMM5 2986Freescale XGATE reloc. 2987This is a 5-bit pc-relative reloc. 2988@end deffn 2989@deffn {} BFD_RELOC_M68HC12_9B 2990Motorola 68HC12 reloc. 2991This is the 9 bits of a value. 2992@end deffn 2993@deffn {} BFD_RELOC_M68HC12_16B 2994Motorola 68HC12 reloc. 2995This is the 16 bits of a value. 2996@end deffn 2997@deffn {} BFD_RELOC_M68HC12_9_PCREL 2998Motorola 68HC12/XGATE reloc. 2999This is a PCREL9 branch. 3000@end deffn 3001@deffn {} BFD_RELOC_M68HC12_10_PCREL 3002Motorola 68HC12/XGATE reloc. 3003This is a PCREL10 branch. 3004@end deffn 3005@deffn {} BFD_RELOC_M68HC12_LO8XG 3006Motorola 68HC12/XGATE reloc. 3007This is the 8 bit low part of an absolute address and immediately precedes 3008a matching HI8XG part. 3009@end deffn 3010@deffn {} BFD_RELOC_M68HC12_HI8XG 3011Motorola 68HC12/XGATE reloc. 3012This is the 8 bit high part of an absolute address and immediately follows 3013a matching LO8XG part. 3014@end deffn 3015@deffn {} BFD_RELOC_16C_NUM08 3016@deffnx {} BFD_RELOC_16C_NUM08_C 3017@deffnx {} BFD_RELOC_16C_NUM16 3018@deffnx {} BFD_RELOC_16C_NUM16_C 3019@deffnx {} BFD_RELOC_16C_NUM32 3020@deffnx {} BFD_RELOC_16C_NUM32_C 3021@deffnx {} BFD_RELOC_16C_DISP04 3022@deffnx {} BFD_RELOC_16C_DISP04_C 3023@deffnx {} BFD_RELOC_16C_DISP08 3024@deffnx {} BFD_RELOC_16C_DISP08_C 3025@deffnx {} BFD_RELOC_16C_DISP16 3026@deffnx {} BFD_RELOC_16C_DISP16_C 3027@deffnx {} BFD_RELOC_16C_DISP24 3028@deffnx {} BFD_RELOC_16C_DISP24_C 3029@deffnx {} BFD_RELOC_16C_DISP24a 3030@deffnx {} BFD_RELOC_16C_DISP24a_C 3031@deffnx {} BFD_RELOC_16C_REG04 3032@deffnx {} BFD_RELOC_16C_REG04_C 3033@deffnx {} BFD_RELOC_16C_REG04a 3034@deffnx {} BFD_RELOC_16C_REG04a_C 3035@deffnx {} BFD_RELOC_16C_REG14 3036@deffnx {} BFD_RELOC_16C_REG14_C 3037@deffnx {} BFD_RELOC_16C_REG16 3038@deffnx {} BFD_RELOC_16C_REG16_C 3039@deffnx {} BFD_RELOC_16C_REG20 3040@deffnx {} BFD_RELOC_16C_REG20_C 3041@deffnx {} BFD_RELOC_16C_ABS20 3042@deffnx {} BFD_RELOC_16C_ABS20_C 3043@deffnx {} BFD_RELOC_16C_ABS24 3044@deffnx {} BFD_RELOC_16C_ABS24_C 3045@deffnx {} BFD_RELOC_16C_IMM04 3046@deffnx {} BFD_RELOC_16C_IMM04_C 3047@deffnx {} BFD_RELOC_16C_IMM16 3048@deffnx {} BFD_RELOC_16C_IMM16_C 3049@deffnx {} BFD_RELOC_16C_IMM20 3050@deffnx {} BFD_RELOC_16C_IMM20_C 3051@deffnx {} BFD_RELOC_16C_IMM24 3052@deffnx {} BFD_RELOC_16C_IMM24_C 3053@deffnx {} BFD_RELOC_16C_IMM32 3054@deffnx {} BFD_RELOC_16C_IMM32_C 3055NS CR16C Relocations. 3056@end deffn 3057@deffn {} BFD_RELOC_CR16_NUM8 3058@deffnx {} BFD_RELOC_CR16_NUM16 3059@deffnx {} BFD_RELOC_CR16_NUM32 3060@deffnx {} BFD_RELOC_CR16_NUM32a 3061@deffnx {} BFD_RELOC_CR16_REGREL0 3062@deffnx {} BFD_RELOC_CR16_REGREL4 3063@deffnx {} BFD_RELOC_CR16_REGREL4a 3064@deffnx {} BFD_RELOC_CR16_REGREL14 3065@deffnx {} BFD_RELOC_CR16_REGREL14a 3066@deffnx {} BFD_RELOC_CR16_REGREL16 3067@deffnx {} BFD_RELOC_CR16_REGREL20 3068@deffnx {} BFD_RELOC_CR16_REGREL20a 3069@deffnx {} BFD_RELOC_CR16_ABS20 3070@deffnx {} BFD_RELOC_CR16_ABS24 3071@deffnx {} BFD_RELOC_CR16_IMM4 3072@deffnx {} BFD_RELOC_CR16_IMM8 3073@deffnx {} BFD_RELOC_CR16_IMM16 3074@deffnx {} BFD_RELOC_CR16_IMM20 3075@deffnx {} BFD_RELOC_CR16_IMM24 3076@deffnx {} BFD_RELOC_CR16_IMM32 3077@deffnx {} BFD_RELOC_CR16_IMM32a 3078@deffnx {} BFD_RELOC_CR16_DISP4 3079@deffnx {} BFD_RELOC_CR16_DISP8 3080@deffnx {} BFD_RELOC_CR16_DISP16 3081@deffnx {} BFD_RELOC_CR16_DISP20 3082@deffnx {} BFD_RELOC_CR16_DISP24 3083@deffnx {} BFD_RELOC_CR16_DISP24a 3084@deffnx {} BFD_RELOC_CR16_SWITCH8 3085@deffnx {} BFD_RELOC_CR16_SWITCH16 3086@deffnx {} BFD_RELOC_CR16_SWITCH32 3087@deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3088@deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3089@deffnx {} BFD_RELOC_CR16_GLOB_DAT 3090NS CR16 Relocations. 3091@end deffn 3092@deffn {} BFD_RELOC_CRX_REL4 3093@deffnx {} BFD_RELOC_CRX_REL8 3094@deffnx {} BFD_RELOC_CRX_REL8_CMP 3095@deffnx {} BFD_RELOC_CRX_REL16 3096@deffnx {} BFD_RELOC_CRX_REL24 3097@deffnx {} BFD_RELOC_CRX_REL32 3098@deffnx {} BFD_RELOC_CRX_REGREL12 3099@deffnx {} BFD_RELOC_CRX_REGREL22 3100@deffnx {} BFD_RELOC_CRX_REGREL28 3101@deffnx {} BFD_RELOC_CRX_REGREL32 3102@deffnx {} BFD_RELOC_CRX_ABS16 3103@deffnx {} BFD_RELOC_CRX_ABS32 3104@deffnx {} BFD_RELOC_CRX_NUM8 3105@deffnx {} BFD_RELOC_CRX_NUM16 3106@deffnx {} BFD_RELOC_CRX_NUM32 3107@deffnx {} BFD_RELOC_CRX_IMM16 3108@deffnx {} BFD_RELOC_CRX_IMM32 3109@deffnx {} BFD_RELOC_CRX_SWITCH8 3110@deffnx {} BFD_RELOC_CRX_SWITCH16 3111@deffnx {} BFD_RELOC_CRX_SWITCH32 3112NS CRX Relocations. 3113@end deffn 3114@deffn {} BFD_RELOC_CRIS_BDISP8 3115@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3116@deffnx {} BFD_RELOC_CRIS_SIGNED_6 3117@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3118@deffnx {} BFD_RELOC_CRIS_SIGNED_8 3119@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3120@deffnx {} BFD_RELOC_CRIS_SIGNED_16 3121@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3122@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3123@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3124These relocs are only used within the CRIS assembler. They are not 3125(at present) written to any object files. 3126@end deffn 3127@deffn {} BFD_RELOC_CRIS_COPY 3128@deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3129@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3130@deffnx {} BFD_RELOC_CRIS_RELATIVE 3131Relocs used in ELF shared libraries for CRIS. 3132@end deffn 3133@deffn {} BFD_RELOC_CRIS_32_GOT 313432-bit offset to symbol-entry within GOT. 3135@end deffn 3136@deffn {} BFD_RELOC_CRIS_16_GOT 313716-bit offset to symbol-entry within GOT. 3138@end deffn 3139@deffn {} BFD_RELOC_CRIS_32_GOTPLT 314032-bit offset to symbol-entry within GOT, with PLT handling. 3141@end deffn 3142@deffn {} BFD_RELOC_CRIS_16_GOTPLT 314316-bit offset to symbol-entry within GOT, with PLT handling. 3144@end deffn 3145@deffn {} BFD_RELOC_CRIS_32_GOTREL 314632-bit offset to symbol, relative to GOT. 3147@end deffn 3148@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 314932-bit offset to symbol with PLT entry, relative to GOT. 3150@end deffn 3151@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 315232-bit offset to symbol with PLT entry, relative to this relocation. 3153@end deffn 3154@deffn {} BFD_RELOC_CRIS_32_GOT_GD 3155@deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3156@deffnx {} BFD_RELOC_CRIS_32_GD 3157@deffnx {} BFD_RELOC_CRIS_DTP 3158@deffnx {} BFD_RELOC_CRIS_32_DTPREL 3159@deffnx {} BFD_RELOC_CRIS_16_DTPREL 3160@deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3161@deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3162@deffnx {} BFD_RELOC_CRIS_32_TPREL 3163@deffnx {} BFD_RELOC_CRIS_16_TPREL 3164@deffnx {} BFD_RELOC_CRIS_DTPMOD 3165@deffnx {} BFD_RELOC_CRIS_32_IE 3166Relocs used in TLS code for CRIS. 3167@end deffn 3168@deffn {} BFD_RELOC_860_COPY 3169@deffnx {} BFD_RELOC_860_GLOB_DAT 3170@deffnx {} BFD_RELOC_860_JUMP_SLOT 3171@deffnx {} BFD_RELOC_860_RELATIVE 3172@deffnx {} BFD_RELOC_860_PC26 3173@deffnx {} BFD_RELOC_860_PLT26 3174@deffnx {} BFD_RELOC_860_PC16 3175@deffnx {} BFD_RELOC_860_LOW0 3176@deffnx {} BFD_RELOC_860_SPLIT0 3177@deffnx {} BFD_RELOC_860_LOW1 3178@deffnx {} BFD_RELOC_860_SPLIT1 3179@deffnx {} BFD_RELOC_860_LOW2 3180@deffnx {} BFD_RELOC_860_SPLIT2 3181@deffnx {} BFD_RELOC_860_LOW3 3182@deffnx {} BFD_RELOC_860_LOGOT0 3183@deffnx {} BFD_RELOC_860_SPGOT0 3184@deffnx {} BFD_RELOC_860_LOGOT1 3185@deffnx {} BFD_RELOC_860_SPGOT1 3186@deffnx {} BFD_RELOC_860_LOGOTOFF0 3187@deffnx {} BFD_RELOC_860_SPGOTOFF0 3188@deffnx {} BFD_RELOC_860_LOGOTOFF1 3189@deffnx {} BFD_RELOC_860_SPGOTOFF1 3190@deffnx {} BFD_RELOC_860_LOGOTOFF2 3191@deffnx {} BFD_RELOC_860_LOGOTOFF3 3192@deffnx {} BFD_RELOC_860_LOPC 3193@deffnx {} BFD_RELOC_860_HIGHADJ 3194@deffnx {} BFD_RELOC_860_HAGOT 3195@deffnx {} BFD_RELOC_860_HAGOTOFF 3196@deffnx {} BFD_RELOC_860_HAPC 3197@deffnx {} BFD_RELOC_860_HIGH 3198@deffnx {} BFD_RELOC_860_HIGOT 3199@deffnx {} BFD_RELOC_860_HIGOTOFF 3200Intel i860 Relocations. 3201@end deffn 3202@deffn {} BFD_RELOC_OR1K_REL_26 3203@deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3204@deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3205@deffnx {} BFD_RELOC_OR1K_GOT16 3206@deffnx {} BFD_RELOC_OR1K_PLT26 3207@deffnx {} BFD_RELOC_OR1K_GOTOFF_HI16 3208@deffnx {} BFD_RELOC_OR1K_GOTOFF_LO16 3209@deffnx {} BFD_RELOC_OR1K_COPY 3210@deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3211@deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3212@deffnx {} BFD_RELOC_OR1K_RELATIVE 3213@deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3214@deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3215@deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3216@deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3217@deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3218@deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3219@deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3220@deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3221@deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3222@deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3223@deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3224@deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3225@deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3226OpenRISC 1000 Relocations. 3227@end deffn 3228@deffn {} BFD_RELOC_H8_DIR16A8 3229@deffnx {} BFD_RELOC_H8_DIR16R8 3230@deffnx {} BFD_RELOC_H8_DIR24A8 3231@deffnx {} BFD_RELOC_H8_DIR24R8 3232@deffnx {} BFD_RELOC_H8_DIR32A16 3233@deffnx {} BFD_RELOC_H8_DISP32A16 3234H8 elf Relocations. 3235@end deffn 3236@deffn {} BFD_RELOC_XSTORMY16_REL_12 3237@deffnx {} BFD_RELOC_XSTORMY16_12 3238@deffnx {} BFD_RELOC_XSTORMY16_24 3239@deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3240Sony Xstormy16 Relocations. 3241@end deffn 3242@deffn {} BFD_RELOC_RELC 3243Self-describing complex relocations. 3244@end deffn 3245@deffn {} BFD_RELOC_XC16X_PAG 3246@deffnx {} BFD_RELOC_XC16X_POF 3247@deffnx {} BFD_RELOC_XC16X_SEG 3248@deffnx {} BFD_RELOC_XC16X_SOF 3249Infineon Relocations. 3250@end deffn 3251@deffn {} BFD_RELOC_VAX_GLOB_DAT 3252@deffnx {} BFD_RELOC_VAX_JMP_SLOT 3253@deffnx {} BFD_RELOC_VAX_RELATIVE 3254Relocations used by VAX ELF. 3255@end deffn 3256@deffn {} BFD_RELOC_MT_PC16 3257Morpho MT - 16 bit immediate relocation. 3258@end deffn 3259@deffn {} BFD_RELOC_MT_HI16 3260Morpho MT - Hi 16 bits of an address. 3261@end deffn 3262@deffn {} BFD_RELOC_MT_LO16 3263Morpho MT - Low 16 bits of an address. 3264@end deffn 3265@deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3266Morpho MT - Used to tell the linker which vtable entries are used. 3267@end deffn 3268@deffn {} BFD_RELOC_MT_GNU_VTENTRY 3269Morpho MT - Used to tell the linker which vtable entries are used. 3270@end deffn 3271@deffn {} BFD_RELOC_MT_PCINSN8 3272Morpho MT - 8 bit immediate relocation. 3273@end deffn 3274@deffn {} BFD_RELOC_MSP430_10_PCREL 3275@deffnx {} BFD_RELOC_MSP430_16_PCREL 3276@deffnx {} BFD_RELOC_MSP430_16 3277@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3278@deffnx {} BFD_RELOC_MSP430_16_BYTE 3279@deffnx {} BFD_RELOC_MSP430_2X_PCREL 3280@deffnx {} BFD_RELOC_MSP430_RL_PCREL 3281@deffnx {} BFD_RELOC_MSP430_ABS8 3282@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3283@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3284@deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3285@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3286@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3287@deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3288@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3289@deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3290@deffnx {} BFD_RELOC_MSP430X_PCR16 3291@deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3292@deffnx {} BFD_RELOC_MSP430X_ABS16 3293@deffnx {} BFD_RELOC_MSP430_ABS_HI16 3294@deffnx {} BFD_RELOC_MSP430_PREL31 3295@deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3296msp430 specific relocation codes 3297@end deffn 3298@deffn {} BFD_RELOC_NIOS2_S16 3299@deffnx {} BFD_RELOC_NIOS2_U16 3300@deffnx {} BFD_RELOC_NIOS2_CALL26 3301@deffnx {} BFD_RELOC_NIOS2_IMM5 3302@deffnx {} BFD_RELOC_NIOS2_CACHE_OPX 3303@deffnx {} BFD_RELOC_NIOS2_IMM6 3304@deffnx {} BFD_RELOC_NIOS2_IMM8 3305@deffnx {} BFD_RELOC_NIOS2_HI16 3306@deffnx {} BFD_RELOC_NIOS2_LO16 3307@deffnx {} BFD_RELOC_NIOS2_HIADJ16 3308@deffnx {} BFD_RELOC_NIOS2_GPREL 3309@deffnx {} BFD_RELOC_NIOS2_UJMP 3310@deffnx {} BFD_RELOC_NIOS2_CJMP 3311@deffnx {} BFD_RELOC_NIOS2_CALLR 3312@deffnx {} BFD_RELOC_NIOS2_ALIGN 3313@deffnx {} BFD_RELOC_NIOS2_GOT16 3314@deffnx {} BFD_RELOC_NIOS2_CALL16 3315@deffnx {} BFD_RELOC_NIOS2_GOTOFF_LO 3316@deffnx {} BFD_RELOC_NIOS2_GOTOFF_HA 3317@deffnx {} BFD_RELOC_NIOS2_PCREL_LO 3318@deffnx {} BFD_RELOC_NIOS2_PCREL_HA 3319@deffnx {} BFD_RELOC_NIOS2_TLS_GD16 3320@deffnx {} BFD_RELOC_NIOS2_TLS_LDM16 3321@deffnx {} BFD_RELOC_NIOS2_TLS_LDO16 3322@deffnx {} BFD_RELOC_NIOS2_TLS_IE16 3323@deffnx {} BFD_RELOC_NIOS2_TLS_LE16 3324@deffnx {} BFD_RELOC_NIOS2_TLS_DTPMOD 3325@deffnx {} BFD_RELOC_NIOS2_TLS_DTPREL 3326@deffnx {} BFD_RELOC_NIOS2_TLS_TPREL 3327@deffnx {} BFD_RELOC_NIOS2_COPY 3328@deffnx {} BFD_RELOC_NIOS2_GLOB_DAT 3329@deffnx {} BFD_RELOC_NIOS2_JUMP_SLOT 3330@deffnx {} BFD_RELOC_NIOS2_RELATIVE 3331@deffnx {} BFD_RELOC_NIOS2_GOTOFF 3332@deffnx {} BFD_RELOC_NIOS2_CALL26_NOAT 3333@deffnx {} BFD_RELOC_NIOS2_GOT_LO 3334@deffnx {} BFD_RELOC_NIOS2_GOT_HA 3335@deffnx {} BFD_RELOC_NIOS2_CALL_LO 3336@deffnx {} BFD_RELOC_NIOS2_CALL_HA 3337@deffnx {} BFD_RELOC_NIOS2_R2_S12 3338@deffnx {} BFD_RELOC_NIOS2_R2_I10_1_PCREL 3339@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_1_PCREL 3340@deffnx {} BFD_RELOC_NIOS2_R2_T1I7_2 3341@deffnx {} BFD_RELOC_NIOS2_R2_T2I4 3342@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_1 3343@deffnx {} BFD_RELOC_NIOS2_R2_T2I4_2 3344@deffnx {} BFD_RELOC_NIOS2_R2_X1I7_2 3345@deffnx {} BFD_RELOC_NIOS2_R2_X2L5 3346@deffnx {} BFD_RELOC_NIOS2_R2_F1I5_2 3347@deffnx {} BFD_RELOC_NIOS2_R2_L5I4X1 3348@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6 3349@deffnx {} BFD_RELOC_NIOS2_R2_T1X1I6_2 3350Relocations used by the Altera Nios II core. 3351@end deffn 3352@deffn {} BFD_RELOC_IQ2000_OFFSET_16 3353@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3354@deffnx {} BFD_RELOC_IQ2000_UHI16 3355IQ2000 Relocations. 3356@end deffn 3357@deffn {} BFD_RELOC_XTENSA_RTLD 3358Special Xtensa relocation used only by PLT entries in ELF shared 3359objects to indicate that the runtime linker should set the value 3360to one of its own internal functions or data structures. 3361@end deffn 3362@deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3363@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3364@deffnx {} BFD_RELOC_XTENSA_RELATIVE 3365Xtensa relocations for ELF shared objects. 3366@end deffn 3367@deffn {} BFD_RELOC_XTENSA_PLT 3368Xtensa relocation used in ELF object files for symbols that may require 3369PLT entries. Otherwise, this is just a generic 32-bit relocation. 3370@end deffn 3371@deffn {} BFD_RELOC_XTENSA_DIFF8 3372@deffnx {} BFD_RELOC_XTENSA_DIFF16 3373@deffnx {} BFD_RELOC_XTENSA_DIFF32 3374Xtensa relocations to mark the difference of two local symbols. 3375These are only needed to support linker relaxation and can be ignored 3376when not relaxing. The field is set to the value of the difference 3377assuming no relaxation. The relocation encodes the position of the 3378first symbol so the linker can determine whether to adjust the field 3379value. 3380@end deffn 3381@deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3382@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3383@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3384@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3385@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3386@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3387@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3388@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3389@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3390@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3391@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3392@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3393@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3394@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3395@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3396Generic Xtensa relocations for instruction operands. Only the slot 3397number is encoded in the relocation. The relocation applies to the 3398last PC-relative immediate operand, or if there are no PC-relative 3399immediates, to the last immediate operand. 3400@end deffn 3401@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3402@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3403@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3404@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3405@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3406@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3407@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3408@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3409@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3410@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3411@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3412@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3413@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3414@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3415@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3416Alternate Xtensa relocations. Only the slot is encoded in the 3417relocation. The meaning of these relocations is opcode-specific. 3418@end deffn 3419@deffn {} BFD_RELOC_XTENSA_OP0 3420@deffnx {} BFD_RELOC_XTENSA_OP1 3421@deffnx {} BFD_RELOC_XTENSA_OP2 3422Xtensa relocations for backward compatibility. These have all been 3423replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3424@end deffn 3425@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3426Xtensa relocation to mark that the assembler expanded the 3427instructions from an original target. The expansion size is 3428encoded in the reloc size. 3429@end deffn 3430@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3431Xtensa relocation to mark that the linker should simplify 3432assembler-expanded instructions. This is commonly used 3433internally by the linker after analysis of a 3434BFD_RELOC_XTENSA_ASM_EXPAND. 3435@end deffn 3436@deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3437@deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3438@deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3439@deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3440@deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3441@deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3442@deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3443Xtensa TLS relocations. 3444@end deffn 3445@deffn {} BFD_RELOC_Z80_DISP8 34468 bit signed offset in (ix+d) or (iy+d). 3447@end deffn 3448@deffn {} BFD_RELOC_Z8K_DISP7 3449DJNZ offset. 3450@end deffn 3451@deffn {} BFD_RELOC_Z8K_CALLR 3452CALR offset. 3453@end deffn 3454@deffn {} BFD_RELOC_Z8K_IMM4L 34554 bit value. 3456@end deffn 3457@deffn {} BFD_RELOC_LM32_CALL 3458@deffnx {} BFD_RELOC_LM32_BRANCH 3459@deffnx {} BFD_RELOC_LM32_16_GOT 3460@deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3461@deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3462@deffnx {} BFD_RELOC_LM32_COPY 3463@deffnx {} BFD_RELOC_LM32_GLOB_DAT 3464@deffnx {} BFD_RELOC_LM32_JMP_SLOT 3465@deffnx {} BFD_RELOC_LM32_RELATIVE 3466Lattice Mico32 relocations. 3467@end deffn 3468@deffn {} BFD_RELOC_MACH_O_SECTDIFF 3469Difference between two section addreses. Must be followed by a 3470BFD_RELOC_MACH_O_PAIR. 3471@end deffn 3472@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3473Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3474@end deffn 3475@deffn {} BFD_RELOC_MACH_O_PAIR 3476Pair of relocation. Contains the first symbol. 3477@end deffn 3478@deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3479@deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3480PCREL relocations. They are marked as branch to create PLT entry if 3481required. 3482@end deffn 3483@deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3484Used when referencing a GOT entry. 3485@end deffn 3486@deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3487Used when loading a GOT entry with movq. It is specially marked so that 3488the linker could optimize the movq to a leaq if possible. 3489@end deffn 3490@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32 3491Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3492@end deffn 3493@deffn {} BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64 3494Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3495@end deffn 3496@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3497Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3498@end deffn 3499@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3500Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3501@end deffn 3502@deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3503Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3504@end deffn 3505@deffn {} BFD_RELOC_MICROBLAZE_32_LO 3506This is a 32 bit reloc for the microblaze that stores the 3507low 16 bits of a value 3508@end deffn 3509@deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3510This is a 32 bit pc-relative reloc for the microblaze that 3511stores the low 16 bits of a value 3512@end deffn 3513@deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3514This is a 32 bit reloc for the microblaze that stores a 3515value relative to the read-only small data area anchor 3516@end deffn 3517@deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3518This is a 32 bit reloc for the microblaze that stores a 3519value relative to the read-write small data area anchor 3520@end deffn 3521@deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3522This is a 32 bit reloc for the microblaze to handle 3523expressions of the form "Symbol Op Symbol" 3524@end deffn 3525@deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3526This is a 64 bit reloc that stores the 32 bit pc relative 3527value in two words (with an imm instruction). No relocation is 3528done here - only used for relaxing 3529@end deffn 3530@deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3531This is a 64 bit reloc that stores the 32 bit pc relative 3532value in two words (with an imm instruction). The relocation is 3533PC-relative GOT offset 3534@end deffn 3535@deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3536This is a 64 bit reloc that stores the 32 bit pc relative 3537value in two words (with an imm instruction). The relocation is 3538GOT offset 3539@end deffn 3540@deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3541This is a 64 bit reloc that stores the 32 bit pc relative 3542value in two words (with an imm instruction). The relocation is 3543PC-relative offset into PLT 3544@end deffn 3545@deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3546This is a 64 bit reloc that stores the 32 bit GOT relative 3547value in two words (with an imm instruction). The relocation is 3548relative offset from _GLOBAL_OFFSET_TABLE_ 3549@end deffn 3550@deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3551This is a 32 bit reloc that stores the 32 bit GOT relative 3552value in a word. The relocation is relative offset from 3553@end deffn 3554@deffn {} BFD_RELOC_MICROBLAZE_COPY 3555This is used to tell the dynamic linker to copy the value out of 3556the dynamic object into the runtime process image. 3557@end deffn 3558@deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3559Unused Reloc 3560@end deffn 3561@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3562This is a 64 bit reloc that stores the 32 bit GOT relative value 3563of the GOT TLS GD info entry in two words (with an imm instruction). The 3564relocation is GOT offset. 3565@end deffn 3566@deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3567This is a 64 bit reloc that stores the 32 bit GOT relative value 3568of the GOT TLS LD info entry in two words (with an imm instruction). The 3569relocation is GOT offset. 3570@end deffn 3571@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3572This is a 32 bit reloc that stores the Module ID to GOT(n). 3573@end deffn 3574@deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3575This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3576@end deffn 3577@deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3578This is a 32 bit reloc for storing TLS offset to two words (uses imm 3579instruction) 3580@end deffn 3581@deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3582This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3583to two words (uses imm instruction). 3584@end deffn 3585@deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3586This is a 64 bit reloc that stores 32-bit thread pointer relative offset 3587to two words (uses imm instruction). 3588@end deffn 3589@deffn {} BFD_RELOC_AARCH64_RELOC_START 3590AArch64 pseudo relocation code to mark the start of the AArch64 3591relocation enumerators. N.B. the order of the enumerators is 3592important as several tables in the AArch64 bfd backend are indexed 3593by these enumerators; make sure they are all synced. 3594@end deffn 3595@deffn {} BFD_RELOC_AARCH64_NONE 3596AArch64 null relocation code. 3597@end deffn 3598@deffn {} BFD_RELOC_AARCH64_64 3599@deffnx {} BFD_RELOC_AARCH64_32 3600@deffnx {} BFD_RELOC_AARCH64_16 3601Basic absolute relocations of N bits. These are equivalent to 3602BFD_RELOC_N and they were added to assist the indexing of the howto 3603table. 3604@end deffn 3605@deffn {} BFD_RELOC_AARCH64_64_PCREL 3606@deffnx {} BFD_RELOC_AARCH64_32_PCREL 3607@deffnx {} BFD_RELOC_AARCH64_16_PCREL 3608PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3609and they were added to assist the indexing of the howto table. 3610@end deffn 3611@deffn {} BFD_RELOC_AARCH64_MOVW_G0 3612AArch64 MOV[NZK] instruction with most significant bits 0 to 15 3613of an unsigned address/value. 3614@end deffn 3615@deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3616AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3617an address/value. No overflow checking. 3618@end deffn 3619@deffn {} BFD_RELOC_AARCH64_MOVW_G1 3620AArch64 MOV[NZK] instruction with most significant bits 16 to 31 3621of an unsigned address/value. 3622@end deffn 3623@deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3624AArch64 MOV[NZK] instruction with less significant bits 16 to 31 3625of an address/value. No overflow checking. 3626@end deffn 3627@deffn {} BFD_RELOC_AARCH64_MOVW_G2 3628AArch64 MOV[NZK] instruction with most significant bits 32 to 47 3629of an unsigned address/value. 3630@end deffn 3631@deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3632AArch64 MOV[NZK] instruction with less significant bits 32 to 47 3633of an address/value. No overflow checking. 3634@end deffn 3635@deffn {} BFD_RELOC_AARCH64_MOVW_G3 3636AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 3637of a signed or unsigned address/value. 3638@end deffn 3639@deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3640AArch64 MOV[NZ] instruction with most significant bits 0 to 15 3641of a signed value. Changes instruction to MOVZ or MOVN depending on the 3642value's sign. 3643@end deffn 3644@deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3645AArch64 MOV[NZ] instruction with most significant bits 16 to 31 3646of a signed value. Changes instruction to MOVZ or MOVN depending on the 3647value's sign. 3648@end deffn 3649@deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3650AArch64 MOV[NZ] instruction with most significant bits 32 to 47 3651of a signed value. Changes instruction to MOVZ or MOVN depending on the 3652value's sign. 3653@end deffn 3654@deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3655AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3656offset. The lowest two bits must be zero and are not stored in the 3657instruction, giving a 21 bit signed byte offset. 3658@end deffn 3659@deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3660AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. 3661@end deffn 3662@deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3663AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3664offset, giving a 4KB aligned page base address. 3665@end deffn 3666@deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3667AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3668offset, giving a 4KB aligned page base address, but with no overflow 3669checking. 3670@end deffn 3671@deffn {} BFD_RELOC_AARCH64_ADD_LO12 3672AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. 3673Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3674@end deffn 3675@deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3676AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3677address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3678@end deffn 3679@deffn {} BFD_RELOC_AARCH64_TSTBR14 3680AArch64 14 bit pc-relative test bit and branch. 3681The lowest two bits must be zero and are not stored in the instruction, 3682giving a 16 bit signed byte offset. 3683@end deffn 3684@deffn {} BFD_RELOC_AARCH64_BRANCH19 3685AArch64 19 bit pc-relative conditional branch and compare & branch. 3686The lowest two bits must be zero and are not stored in the instruction, 3687giving a 21 bit signed byte offset. 3688@end deffn 3689@deffn {} BFD_RELOC_AARCH64_JUMP26 3690AArch64 26 bit pc-relative unconditional branch. 3691The lowest two bits must be zero and are not stored in the instruction, 3692giving a 28 bit signed byte offset. 3693@end deffn 3694@deffn {} BFD_RELOC_AARCH64_CALL26 3695AArch64 26 bit pc-relative unconditional branch and link. 3696The lowest two bits must be zero and are not stored in the instruction, 3697giving a 28 bit signed byte offset. 3698@end deffn 3699@deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3700AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3701address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3702@end deffn 3703@deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3704AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3705address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3706@end deffn 3707@deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3708AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3709address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3710@end deffn 3711@deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3712AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3713address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3714@end deffn 3715@deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3716AArch64 Load Literal instruction, holding a 19 bit PC relative word 3717offset of the global offset table entry for a symbol. The lowest two 3718bits must be zero and are not stored in the instruction, giving a 21 3719bit signed byte offset. This relocation type requires signed overflow 3720checking. 3721@end deffn 3722@deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3723Get to the page base of the global offset table entry for a symbol as 3724part of an ADRP instruction using a 21 bit PC relative value.Used in 3725conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3726@end deffn 3727@deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3728Unsigned 12 bit byte offset for 64 bit load/store from the page of 3729the GOT entry for this symbol. Used in conjunction with 3730BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only. 3731@end deffn 3732@deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3733Unsigned 12 bit byte offset for 32 bit load/store from the page of 3734the GOT entry for this symbol. Used in conjunction with 3735BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only. 3736@end deffn 3737@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3738Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3739for this symbol. Valid in LP64 ABI only. 3740@end deffn 3741@deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3742Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry 3743for this symbol. Valid in LP64 ABI only. 3744@end deffn 3745@deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3746Unsigned 15 bit byte offset for 64 bit load/store from the page of 3747the GOT entry for this symbol. Valid in LP64 ABI only. 3748@end deffn 3749@deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3750Scaled 14 bit byte offset to the page base of the global offset table. 3751@end deffn 3752@deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3753Scaled 15 bit byte offset to the page base of the global offset table. 3754@end deffn 3755@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3756Get to the page base of the global offset table entry for a symbols 3757tls_index structure as part of an adrp instruction using a 21 bit PC 3758relative value. Used in conjunction with 3759BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3760@end deffn 3761@deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3762AArch64 TLS General Dynamic 3763@end deffn 3764@deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3765Unsigned 12 bit byte offset to global offset table entry for a symbols 3766tls_index structure. Used in conjunction with 3767BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3768@end deffn 3769@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3770AArch64 TLS General Dynamic relocation. 3771@end deffn 3772@deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3773AArch64 TLS General Dynamic relocation. 3774@end deffn 3775@deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3776AArch64 TLS INITIAL EXEC relocation. 3777@end deffn 3778@deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3779AArch64 TLS INITIAL EXEC relocation. 3780@end deffn 3781@deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3782AArch64 TLS INITIAL EXEC relocation. 3783@end deffn 3784@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3785AArch64 TLS INITIAL EXEC relocation. 3786@end deffn 3787@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3788AArch64 TLS INITIAL EXEC relocation. 3789@end deffn 3790@deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3791AArch64 TLS INITIAL EXEC relocation. 3792@end deffn 3793@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3794bit[23:12] of byte offset to module TLS base address. 3795@end deffn 3796@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3797Unsigned 12 bit byte offset to module TLS base address. 3798@end deffn 3799@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3800No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3801@end deffn 3802@deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3803Unsigned 12 bit byte offset to global offset table entry for a symbols 3804tls_index structure. Used in conjunction with 3805BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3806@end deffn 3807@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3808GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3809instruction. 3810@end deffn 3811@deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3812GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction. 3813@end deffn 3814@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 3815bit[11:1] of byte offset to module TLS base address, encoded in ldst 3816instructions. 3817@end deffn 3818@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 3819Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check. 3820@end deffn 3821@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 3822bit[11:2] of byte offset to module TLS base address, encoded in ldst 3823instructions. 3824@end deffn 3825@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 3826Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check. 3827@end deffn 3828@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 3829bit[11:3] of byte offset to module TLS base address, encoded in ldst 3830instructions. 3831@end deffn 3832@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 3833Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check. 3834@end deffn 3835@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 3836bit[11:0] of byte offset to module TLS base address, encoded in ldst 3837instructions. 3838@end deffn 3839@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 3840Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check. 3841@end deffn 3842@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3843bit[15:0] of byte offset to module TLS base address. 3844@end deffn 3845@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 3846No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 3847@end deffn 3848@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3849bit[31:16] of byte offset to module TLS base address. 3850@end deffn 3851@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 3852No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 3853@end deffn 3854@deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 3855bit[47:32] of byte offset to module TLS base address. 3856@end deffn 3857@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 3858AArch64 TLS LOCAL EXEC relocation. 3859@end deffn 3860@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 3861AArch64 TLS LOCAL EXEC relocation. 3862@end deffn 3863@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 3864AArch64 TLS LOCAL EXEC relocation. 3865@end deffn 3866@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 3867AArch64 TLS LOCAL EXEC relocation. 3868@end deffn 3869@deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 3870AArch64 TLS LOCAL EXEC relocation. 3871@end deffn 3872@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 3873AArch64 TLS LOCAL EXEC relocation. 3874@end deffn 3875@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 3876AArch64 TLS LOCAL EXEC relocation. 3877@end deffn 3878@deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 3879AArch64 TLS LOCAL EXEC relocation. 3880@end deffn 3881@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 3882AArch64 TLS DESC relocation. 3883@end deffn 3884@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 3885AArch64 TLS DESC relocation. 3886@end deffn 3887@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 3888AArch64 TLS DESC relocation. 3889@end deffn 3890@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC 3891AArch64 TLS DESC relocation. 3892@end deffn 3893@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 3894AArch64 TLS DESC relocation. 3895@end deffn 3896@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC 3897AArch64 TLS DESC relocation. 3898@end deffn 3899@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 3900AArch64 TLS DESC relocation. 3901@end deffn 3902@deffn {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 3903AArch64 TLS DESC relocation. 3904@end deffn 3905@deffn {} BFD_RELOC_AARCH64_TLSDESC_LDR 3906AArch64 TLS DESC relocation. 3907@end deffn 3908@deffn {} BFD_RELOC_AARCH64_TLSDESC_ADD 3909AArch64 TLS DESC relocation. 3910@end deffn 3911@deffn {} BFD_RELOC_AARCH64_TLSDESC_CALL 3912AArch64 TLS DESC relocation. 3913@end deffn 3914@deffn {} BFD_RELOC_AARCH64_COPY 3915AArch64 TLS relocation. 3916@end deffn 3917@deffn {} BFD_RELOC_AARCH64_GLOB_DAT 3918AArch64 TLS relocation. 3919@end deffn 3920@deffn {} BFD_RELOC_AARCH64_JUMP_SLOT 3921AArch64 TLS relocation. 3922@end deffn 3923@deffn {} BFD_RELOC_AARCH64_RELATIVE 3924AArch64 TLS relocation. 3925@end deffn 3926@deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 3927AArch64 TLS relocation. 3928@end deffn 3929@deffn {} BFD_RELOC_AARCH64_TLS_DTPREL 3930AArch64 TLS relocation. 3931@end deffn 3932@deffn {} BFD_RELOC_AARCH64_TLS_TPREL 3933AArch64 TLS relocation. 3934@end deffn 3935@deffn {} BFD_RELOC_AARCH64_TLSDESC 3936AArch64 TLS relocation. 3937@end deffn 3938@deffn {} BFD_RELOC_AARCH64_IRELATIVE 3939AArch64 support for STT_GNU_IFUNC. 3940@end deffn 3941@deffn {} BFD_RELOC_AARCH64_RELOC_END 3942AArch64 pseudo relocation code to mark the end of the AArch64 3943relocation enumerators that have direct mapping to ELF reloc codes. 3944There are a few more enumerators after this one; those are mainly 3945used by the AArch64 assembler for the internal fixup or to select 3946one of the above enumerators. 3947@end deffn 3948@deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 3949AArch64 pseudo relocation code to be used internally by the AArch64 3950assembler and not (currently) written to any object files. 3951@end deffn 3952@deffn {} BFD_RELOC_AARCH64_LDST_LO12 3953AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 3954address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3955@end deffn 3956@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 3957AArch64 pseudo relocation code for TLS local dynamic mode. It's to be 3958used internally by the AArch64 assembler and not (currently) written to 3959any object files. 3960@end deffn 3961@deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 3962Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. 3963@end deffn 3964@deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 3965AArch64 pseudo relocation code to be used internally by the AArch64 3966assembler and not (currently) written to any object files. 3967@end deffn 3968@deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 3969AArch64 pseudo relocation code to be used internally by the AArch64 3970assembler and not (currently) written to any object files. 3971@end deffn 3972@deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 3973AArch64 pseudo relocation code to be used internally by the AArch64 3974assembler and not (currently) written to any object files. 3975@end deffn 3976@deffn {} BFD_RELOC_TILEPRO_COPY 3977@deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 3978@deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 3979@deffnx {} BFD_RELOC_TILEPRO_RELATIVE 3980@deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 3981@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 3982@deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 3983@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 3984@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 3985@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 3986@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 3987@deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 3988@deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 3989@deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 3990@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 3991@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 3992@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 3993@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 3994@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 3995@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 3996@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 3997@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 3998@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 3999@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4000@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4001@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4002@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4003@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4004@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4005@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4006@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4007@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4008@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4009@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4010@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4011@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4012@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4013@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4014@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4015@deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4016@deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4017@deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4018@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4019@deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4020@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4021@deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4022@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4023@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4024@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4025@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4026@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4027@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4028@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4029@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4030@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4031@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4032@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4033@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4034@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4035@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4036@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4037@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4038@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4039@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4040@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4041@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4042@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4043@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4044@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4045@deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4046@deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4047@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4048@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4049@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4050@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4051@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4052@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4053@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4054@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4055Tilera TILEPro Relocations. 4056@end deffn 4057@deffn {} BFD_RELOC_TILEGX_HW0 4058@deffnx {} BFD_RELOC_TILEGX_HW1 4059@deffnx {} BFD_RELOC_TILEGX_HW2 4060@deffnx {} BFD_RELOC_TILEGX_HW3 4061@deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4062@deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4063@deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4064@deffnx {} BFD_RELOC_TILEGX_COPY 4065@deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4066@deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4067@deffnx {} BFD_RELOC_TILEGX_RELATIVE 4068@deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4069@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4070@deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4071@deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4072@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4073@deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4074@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4075@deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4076@deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4077@deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4078@deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4079@deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4080@deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4081@deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4082@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4083@deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4084@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4085@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4086@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4087@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4088@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4089@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4090@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4091@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4092@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4093@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4094@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4095@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4096@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4097@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4098@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4099@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4100@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4101@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4102@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4103@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4104@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4105@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4106@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4107@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4108@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4109@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4110@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4111@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4112@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4113@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4114@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4115@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4116@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4117@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4118@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4119@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4120@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4121@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4122@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4123@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4124@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4125@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4126@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4127@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4128@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4129@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4130@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4131@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4132@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4133@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4134@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4135@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4136@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4137@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4138@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4139@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4140@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4141@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4142@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4143@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4144@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4145@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4146@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4147@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4148@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4149@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4150@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4151@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4152@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4153@deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4154@deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4155@deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4156@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4157@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4158@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4159@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4160@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4161@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4162@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4163@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4164@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4165@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4166Tilera TILE-Gx Relocations. 4167@end deffn 4168@deffn {} BFD_RELOC_EPIPHANY_SIMM8 4169Adapteva EPIPHANY - 8 bit signed pc-relative displacement 4170@end deffn 4171@deffn {} BFD_RELOC_EPIPHANY_SIMM24 4172Adapteva EPIPHANY - 24 bit signed pc-relative displacement 4173@end deffn 4174@deffn {} BFD_RELOC_EPIPHANY_HIGH 4175Adapteva EPIPHANY - 16 most-significant bits of absolute address 4176@end deffn 4177@deffn {} BFD_RELOC_EPIPHANY_LOW 4178Adapteva EPIPHANY - 16 least-significant bits of absolute address 4179@end deffn 4180@deffn {} BFD_RELOC_EPIPHANY_SIMM11 4181Adapteva EPIPHANY - 11 bit signed number - add/sub immediate 4182@end deffn 4183@deffn {} BFD_RELOC_EPIPHANY_IMM11 4184Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) 4185@end deffn 4186@deffn {} BFD_RELOC_EPIPHANY_IMM8 4187Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4188@end deffn 4189@deffn {} BFD_RELOC_VISIUM_HI16 4190@deffnx {} BFD_RELOC_VISIUM_LO16 4191@deffnx {} BFD_RELOC_VISIUM_IM16 4192@deffnx {} BFD_RELOC_VISIUM_REL16 4193@deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4194@deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4195@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4196Visium Relocations. 4197@end deffn 4198 4199@example 4200 4201typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4202@end example 4203@findex bfd_reloc_type_lookup 4204@subsubsection @code{bfd_reloc_type_lookup} 4205@strong{Synopsis} 4206@example 4207reloc_howto_type *bfd_reloc_type_lookup 4208 (bfd *abfd, bfd_reloc_code_real_type code); 4209reloc_howto_type *bfd_reloc_name_lookup 4210 (bfd *abfd, const char *reloc_name); 4211@end example 4212@strong{Description}@* 4213Return a pointer to a howto structure which, when 4214invoked, will perform the relocation @var{code} on data from the 4215architecture noted. 4216 4217@findex bfd_default_reloc_type_lookup 4218@subsubsection @code{bfd_default_reloc_type_lookup} 4219@strong{Synopsis} 4220@example 4221reloc_howto_type *bfd_default_reloc_type_lookup 4222 (bfd *abfd, bfd_reloc_code_real_type code); 4223@end example 4224@strong{Description}@* 4225Provides a default relocation lookup routine for any architecture. 4226 4227@findex bfd_get_reloc_code_name 4228@subsubsection @code{bfd_get_reloc_code_name} 4229@strong{Synopsis} 4230@example 4231const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4232@end example 4233@strong{Description}@* 4234Provides a printable name for the supplied relocation code. 4235Useful mainly for printing error messages. 4236 4237@findex bfd_generic_relax_section 4238@subsubsection @code{bfd_generic_relax_section} 4239@strong{Synopsis} 4240@example 4241bfd_boolean bfd_generic_relax_section 4242 (bfd *abfd, 4243 asection *section, 4244 struct bfd_link_info *, 4245 bfd_boolean *); 4246@end example 4247@strong{Description}@* 4248Provides default handling for relaxing for back ends which 4249don't do relaxing. 4250 4251@findex bfd_generic_gc_sections 4252@subsubsection @code{bfd_generic_gc_sections} 4253@strong{Synopsis} 4254@example 4255bfd_boolean bfd_generic_gc_sections 4256 (bfd *, struct bfd_link_info *); 4257@end example 4258@strong{Description}@* 4259Provides default handling for relaxing for back ends which 4260don't do section gc -- i.e., does nothing. 4261 4262@findex bfd_generic_lookup_section_flags 4263@subsubsection @code{bfd_generic_lookup_section_flags} 4264@strong{Synopsis} 4265@example 4266bfd_boolean bfd_generic_lookup_section_flags 4267 (struct bfd_link_info *, struct flag_info *, asection *); 4268@end example 4269@strong{Description}@* 4270Provides default handling for section flags lookup 4271-- i.e., does nothing. 4272Returns FALSE if the section should be omitted, otherwise TRUE. 4273 4274@findex bfd_generic_merge_sections 4275@subsubsection @code{bfd_generic_merge_sections} 4276@strong{Synopsis} 4277@example 4278bfd_boolean bfd_generic_merge_sections 4279 (bfd *, struct bfd_link_info *); 4280@end example 4281@strong{Description}@* 4282Provides default handling for SEC_MERGE section merging for back ends 4283which don't have SEC_MERGE support -- i.e., does nothing. 4284 4285@findex bfd_generic_get_relocated_section_contents 4286@subsubsection @code{bfd_generic_get_relocated_section_contents} 4287@strong{Synopsis} 4288@example 4289bfd_byte *bfd_generic_get_relocated_section_contents 4290 (bfd *abfd, 4291 struct bfd_link_info *link_info, 4292 struct bfd_link_order *link_order, 4293 bfd_byte *data, 4294 bfd_boolean relocatable, 4295 asymbol **symbols); 4296@end example 4297@strong{Description}@* 4298Provides default handling of relocation effort for back ends 4299which can't be bothered to do it efficiently. 4300 4301