1# $NetBSD: Makefile,v 1.3 2024/07/02 21:56:00 mrg Exp $ 2 3LIB= LLVMAMDGPUCodeGen 4 5.include <bsd.init.mk> 6 7CPPFLAGS+= -I${LLVM_SRCDIR}/lib/Target/AMDGPU 8 9.PATH: ${LLVM_SRCDIR}/lib/Target/AMDGPU 10 11SRCS+= AMDGPUAliasAnalysis.cpp \ 12 AMDGPUAlwaysInlinePass.cpp \ 13 AMDGPUAnnotateKernelFeatures.cpp \ 14 AMDGPUAnnotateUniformValues.cpp \ 15 AMDGPUArgumentUsageInfo.cpp \ 16 AMDGPUAsmPrinter.cpp \ 17 AMDGPUAtomicOptimizer.cpp \ 18 AMDGPUCallLowering.cpp \ 19 AMDGPUCodeGenPrepare.cpp \ 20 AMDGPUExportClustering.cpp \ 21 AMDGPUFixFunctionBitcasts.cpp \ 22 AMDGPUFrameLowering.cpp \ 23 AMDGPUGlobalISelUtils.cpp \ 24 AMDGPUHSAMetadataStreamer.cpp \ 25 AMDGPUInstCombineIntrinsic.cpp \ 26 AMDGPUInstrInfo.cpp \ 27 AMDGPUInstructionSelector.cpp \ 28 AMDGPUISelDAGToDAG.cpp \ 29 AMDGPUISelLowering.cpp \ 30 AMDGPULateCodeGenPrepare.cpp \ 31 AMDGPULegalizerInfo.cpp \ 32 AMDGPULibCalls.cpp \ 33 AMDGPULibFunc.cpp \ 34 AMDGPULowerIntrinsics.cpp \ 35 AMDGPULowerKernelArguments.cpp \ 36 AMDGPULowerKernelAttributes.cpp \ 37 AMDGPULowerModuleLDSPass.cpp \ 38 AMDGPUMachineCFGStructurizer.cpp \ 39 AMDGPUMachineFunction.cpp \ 40 AMDGPUMachineModuleInfo.cpp \ 41 AMDGPUMacroFusion.cpp \ 42 AMDGPUMCInstLower.cpp \ 43 AMDGPUMIRFormatter.cpp \ 44 AMDGPUOpenCLEnqueuedBlockLowering.cpp \ 45 AMDGPUPerfHintAnalysis.cpp \ 46 AMDGPUPostLegalizerCombiner.cpp \ 47 AMDGPUPreLegalizerCombiner.cpp \ 48 AMDGPUPrintfRuntimeBinding.cpp \ 49 AMDGPUPromoteAlloca.cpp \ 50 AMDGPUPropagateAttributes.cpp \ 51 AMDGPURegBankCombiner.cpp \ 52 AMDGPURegisterBankInfo.cpp \ 53 AMDGPURewriteOutArguments.cpp \ 54 AMDGPUSubtarget.cpp \ 55 AMDGPUTargetMachine.cpp \ 56 AMDGPUTargetObjectFile.cpp \ 57 AMDGPUTargetTransformInfo.cpp \ 58 AMDGPUUnifyDivergentExitNodes.cpp \ 59 AMDGPUUnifyMetadata.cpp \ 60 AMDILCFGStructurizer.cpp \ 61 GCNDPPCombine.cpp \ 62 GCNHazardRecognizer.cpp \ 63 GCNILPSched.cpp \ 64 GCNIterativeScheduler.cpp \ 65 GCNMinRegStrategy.cpp \ 66 GCNNSAReassign.cpp \ 67 GCNRegPressure.cpp \ 68 GCNSchedStrategy.cpp \ 69 R600AsmPrinter.cpp \ 70 R600ClauseMergePass.cpp \ 71 R600ControlFlowFinalizer.cpp \ 72 R600EmitClauseMarkers.cpp \ 73 R600ExpandSpecialInstrs.cpp \ 74 R600FrameLowering.cpp \ 75 R600InstrInfo.cpp \ 76 R600ISelLowering.cpp \ 77 R600MachineFunctionInfo.cpp \ 78 R600MachineScheduler.cpp \ 79 R600OpenCLImageTypeLoweringPass.cpp \ 80 R600OptimizeVectorRegisters.cpp \ 81 R600Packetizer.cpp \ 82 R600RegisterInfo.cpp \ 83 SIAnnotateControlFlow.cpp \ 84 SIFixSGPRCopies.cpp \ 85 SIFixVGPRCopies.cpp \ 86 SIFoldOperands.cpp \ 87 SIFormMemoryClauses.cpp \ 88 SIFrameLowering.cpp \ 89 SIInsertHardClauses.cpp \ 90 SIInsertWaitcnts.cpp \ 91 SIInstrInfo.cpp \ 92 SIISelLowering.cpp \ 93 SILateBranchLowering.cpp \ 94 SILoadStoreOptimizer.cpp \ 95 SILowerControlFlow.cpp \ 96 SILowerI1Copies.cpp \ 97 SILowerSGPRSpills.cpp \ 98 SIMachineFunctionInfo.cpp \ 99 SIMachineScheduler.cpp \ 100 SIMemoryLegalizer.cpp \ 101 SIModeRegister.cpp \ 102 SIOptimizeExecMasking.cpp \ 103 SIOptimizeExecMaskingPreRA.cpp \ 104 SIPeepholeSDWA.cpp \ 105 SIPostRABundler.cpp \ 106 SIPreAllocateWWMRegs.cpp \ 107 SIPreEmitPeephole.cpp \ 108 SIProgramInfo.cpp \ 109 SIRegisterInfo.cpp \ 110 SIShrinkInstructions.cpp \ 111 SIWholeQuadMode.cpp 112 113TABLEGEN_SRC= AMDGPU.td AMDGPUGISel.td InstCombineTables.td R600.td 114TABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/AMDGPU 115TABLEGEN_OUTPUT.AMDGPU.td= \ 116 AMDGPUGenAsmMatcher.inc|-gen-asm-matcher \ 117 AMDGPUGenAsmWriter.inc|-gen-asm-writer \ 118 AMDGPUGenCallingConv.inc|-gen-callingconv \ 119 AMDGPUGenDAGISel.inc|-gen-dag-isel \ 120 AMDGPUGenDisassemblerTables.inc|-gen-disassembler \ 121 AMDGPUGenInstrInfo.inc|-gen-instr-info \ 122 AMDGPUGenMCCodeEmitter.inc|-gen-emitter \ 123 AMDGPUGenMCPseudoLowering.inc|-gen-pseudo-lowering \ 124 AMDGPUGenRegisterBank.inc|-gen-register-bank \ 125 AMDGPUGenRegisterInfo.inc|-gen-register-info \ 126 AMDGPUGenSearchableTables.inc|-gen-searchable-tables \ 127 AMDGPUGenSubtargetInfo.inc|-gen-subtarget 128 129TABLEGEN_OUTPUT.InstCombineTables.td= \ 130 InstCombineTables.inc|-gen-searchable-tables 131 132TABLEGEN_OUTPUT.AMDGPUGISel.td= \ 133 AMDGPUGenGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ 134 AMDGPUGenGlobalISel.inc|-gen-global-isel \ 135 AMDGPUGenPostLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPostLegalizerCombinerHelper \ 136 AMDGPUGenPreLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ 137 AMDGPUGenRegBankGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPURegBankCombinerHelper 138 139TABLEGEN_OUTPUT.R600.td= \ 140 R600GenAsmWriter.inc|-gen-asm-writer \ 141 R600GenCallingConv.inc|-gen-callingconv \ 142 R600GenDAGISel.inc|-gen-dag-isel \ 143 R600GenDFAPacketizer.inc|-gen-dfa-packetizer \ 144 R600GenInstrInfo.inc|-gen-instr-info \ 145 R600GenMCCodeEmitter.inc|-gen-emitter \ 146 R600GenRegisterInfo.inc|-gen-register-info \ 147 R600GenSubtargetInfo.inc|-gen-subtarget 148 149.include "${.PARSEDIR}/../../tablegen.mk" 150 151.if defined(HOSTLIB) 152.include <bsd.hostlib.mk> 153.else 154.include <bsd.lib.mk> 155.endif 156 157CWARNFLAGS.gcc+= ${CC_WNO_STRINGOP_OVERREAD} 158