1//===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the pass which lower AMX tile copy instructions. Since
10// there is no tile copy instruction, we need store tile register to stack
11// and load from stack to another tile register. We need extra GR to hold
12// the stride, and we need stack slot to hold the tile data register.
13// We would run this pass after copy propagation, so that we don't miss copy
14// optimization. And we would run this pass before prolog/epilog insertion,
15// so that we can allocate stack slot.
16//
17//===----------------------------------------------------------------------===//
18
19#include "X86.h"
20#include "X86InstrBuilder.h"
21#include "X86InstrInfo.h"
22#include "X86Subtarget.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/IR/DebugLoc.h"
32#include "llvm/InitializePasses.h"
33#include "llvm/Support/Debug.h"
34
35using namespace llvm;
36
37#define DEBUG_TYPE "x86-lower-tile-copy"
38
39namespace {
40
41class X86LowerTileCopy : public MachineFunctionPass {
42public:
43  static char ID;
44
45  X86LowerTileCopy() : MachineFunctionPass(ID) {}
46
47  void getAnalysisUsage(AnalysisUsage &AU) const override;
48
49  bool runOnMachineFunction(MachineFunction &MF) override;
50
51  StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
52};
53
54} // namespace
55
56char X86LowerTileCopy::ID = 0;
57
58INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
59                      false, false)
60INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
61                    false, false)
62
63void X86LowerTileCopy::getAnalysisUsage(AnalysisUsage &AU) const {
64  AU.setPreservesAll();
65  MachineFunctionPass::getAnalysisUsage(AU);
66}
67
68FunctionPass *llvm::createX86LowerTileCopyPass() {
69  return new X86LowerTileCopy();
70}
71
72bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
73  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
74  const X86InstrInfo *TII = ST.getInstrInfo();
75  bool Changed = false;
76
77  for (MachineBasicBlock &MBB : MF) {
78    for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
79         MII != MIE;) {
80      MachineInstr &MI = *MII++;
81      if (!MI.isCopy())
82        continue;
83      MachineOperand &DstMO = MI.getOperand(0);
84      MachineOperand &SrcMO = MI.getOperand(1);
85      Register SrcReg = SrcMO.getReg();
86      Register DstReg = DstMO.getReg();
87      if (!X86::TILERegClass.contains(DstReg, SrcReg))
88        continue;
89
90      const TargetRegisterInfo *TRI = ST.getRegisterInfo();
91      // Allocate stack slot for tile register
92      unsigned Size = TRI->getSpillSize(X86::TILERegClass);
93      Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
94      int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
95      // Allocate stack slot for stride register
96      Size = TRI->getSpillSize(X86::GR64RegClass);
97      Alignment = TRI->getSpillAlign(X86::GR64RegClass);
98      int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
99
100      // TODO: Pick a killed regiter to avoid save/reload. There is problem
101      // to get live interval in this stage.
102      Register GR64Cand = X86::RAX;
103
104      const DebugLoc &DL = MI.getDebugLoc();
105      // mov %rax (%sp)
106      BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
107      addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
108          .addReg(GR64Cand);
109      // mov 64 %rax
110      BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
111      // tilestored %tmm, (%sp, %idx)
112      unsigned Opc = X86::TILESTORED;
113      MachineInstr *NewMI =
114          addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
115              .addReg(SrcReg, getKillRegState(SrcMO.isKill()));
116      MachineOperand &MO = NewMI->getOperand(2);
117      MO.setReg(GR64Cand);
118      MO.setIsKill(true);
119      // tileloadd (%sp, %idx), %tmm
120      Opc = X86::TILELOADD;
121      NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
122                                TileSS);
123      // restore %rax
124      // mov (%sp) %rax
125      addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
126                        StrideSS);
127      MI.eraseFromParent();
128      Changed = true;
129    }
130  }
131  return Changed;
132}
133