1//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
14#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
15
16#include "SparcRegisterInfo.h"
17#include "llvm/CodeGen/TargetInstrInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "SparcGenInstrInfo.inc"
21
22namespace llvm {
23
24class SparcSubtarget;
25
26/// SPII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace SPII {
30  enum {
31    Pseudo = (1<<0),
32    Load = (1<<1),
33    Store = (1<<2),
34    DelaySlot = (1<<3)
35  };
36}
37
38class SparcInstrInfo : public SparcGenInstrInfo {
39  const SparcRegisterInfo RI;
40  const SparcSubtarget& Subtarget;
41  virtual void anchor();
42public:
43  explicit SparcInstrInfo(SparcSubtarget &ST);
44
45  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
46  /// such, whenever a client has an instance of instruction info, it should
47  /// always be able to get register info as well (through this method).
48  ///
49  const SparcRegisterInfo &getRegisterInfo() const { return RI; }
50
51  /// isLoadFromStackSlot - If the specified machine instruction is a direct
52  /// load from a stack slot, return the virtual or physical register number of
53  /// the destination along with the FrameIndex of the loaded stack slot.  If
54  /// not, return 0.  This predicate must return 0 if the instruction has
55  /// any side effects other than loading from the stack slot.
56  unsigned isLoadFromStackSlot(const MachineInstr &MI,
57                               int &FrameIndex) const override;
58
59  /// isStoreToStackSlot - If the specified machine instruction is a direct
60  /// store to a stack slot, return the virtual or physical register number of
61  /// the source reg along with the FrameIndex of the loaded stack slot.  If
62  /// not, return 0.  This predicate must return 0 if the instruction has
63  /// any side effects other than storing to the stack slot.
64  unsigned isStoreToStackSlot(const MachineInstr &MI,
65                              int &FrameIndex) const override;
66
67  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
68                     MachineBasicBlock *&FBB,
69                     SmallVectorImpl<MachineOperand> &Cond,
70                     bool AllowModify = false) const override;
71
72  unsigned removeBranch(MachineBasicBlock &MBB,
73                        int *BytesRemoved = nullptr) const override;
74
75  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
76                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77                        const DebugLoc &DL,
78                        int *BytesAdded = nullptr) const override;
79
80  bool
81  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
82
83  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
85                   bool KillSrc) const override;
86
87  void storeRegToStackSlot(MachineBasicBlock &MBB,
88                           MachineBasicBlock::iterator MBBI,
89                           Register SrcReg, bool isKill, int FrameIndex,
90                           const TargetRegisterClass *RC,
91                           const TargetRegisterInfo *TRI) const override;
92
93  void loadRegFromStackSlot(MachineBasicBlock &MBB,
94                            MachineBasicBlock::iterator MBBI,
95                            Register DestReg, int FrameIndex,
96                            const TargetRegisterClass *RC,
97                            const TargetRegisterInfo *TRI) const override;
98
99  Register getGlobalBaseReg(MachineFunction *MF) const;
100
101  // Lower pseudo instructions after register allocation.
102  bool expandPostRAPseudo(MachineInstr &MI) const override;
103};
104
105}
106
107#endif
108