1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#ifndef __RADEON_DRV_H__ 32#define __RADEON_DRV_H__ 33 34/* General customization: 35 */ 36 37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 38 39#define DRIVER_NAME "radeon" 40#define DRIVER_DESC "ATI Radeon" 41#define DRIVER_DATE "20080613" 42 43/* Interface history: 44 * 45 * 1.1 - ?? 46 * 1.2 - Add vertex2 ioctl (keith) 47 * - Add stencil capability to clear ioctl (gareth, keith) 48 * - Increase MAX_TEXTURE_LEVELS (brian) 49 * 1.3 - Add cmdbuf ioctl (keith) 50 * - Add support for new radeon packets (keith) 51 * - Add getparam ioctl (keith) 52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 53 * 1.4 - Add scratch registers to get_param ioctl. 54 * 1.5 - Add r200 packets to cmdbuf ioctl 55 * - Add r200 function to init ioctl 56 * - Add 'scalar2' instruction to cmdbuf 57 * 1.6 - Add static GART memory manager 58 * Add irq handler (won't be turned on unless X server knows to) 59 * Add irq ioctls and irq_active getparam. 60 * Add wait command for cmdbuf ioctl 61 * Add GART offset query for getparam 62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 63 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 67 * Add 'GET' queries for starting additional clients on different VT's. 68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 69 * Add texture rectangle support for r100. 70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 71 * clients use to tell the DRM where they think the framebuffer is 72 * located in the card's address space 73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 74 * and GL_EXT_blend_[func|equation]_separate on r200 75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 76 * (No 3D support yet - just microcode loading). 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 78 * - Add hyperz support, add hyperz flags to clear ioctl. 79 * 1.14- Add support for color tiling 80 * - Add R100/R200 surface allocation/free support 81 * 1.15- Add support for texture micro tiling 82 * - Add support for r100 cube maps 83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 84 * texture filtering on r200 85 * 1.17- Add initial support for R300 (3D). 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets 87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 90 * 1.19- Add support for gart table in FB memory and PCIE r300 91 * 1.20- Add support for r300 texrect 92 * 1.21- Add support for card type getparam 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 94 * 1.23- Add new radeon memory map work from benh 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 97 * new packet type) 98 * 1.26- Add support for variable size PCI(E) gart aperture 99 * 1.27- Add support for IGP GART 100 * 1.28- Add support for VBL on CRTC2 101 * 1.29- R500 3D cmd buffer support 102 * 1.30- Add support for occlusion queries 103 * 1.31- Add support for num Z pipes from GET_PARAM 104 */ 105 106#define DRIVER_MAJOR 1 107#define DRIVER_MINOR 29 108#define DRIVER_PATCHLEVEL 0 109 110/* 111 * Radeon chip families 112 */ 113enum radeon_family { 114 CHIP_R100, 115 CHIP_RV100, 116 CHIP_RS100, 117 CHIP_RV200, 118 CHIP_RS200, 119 CHIP_R200, 120 CHIP_RV250, 121 CHIP_RS300, 122 CHIP_RV280, 123 CHIP_R300, 124 CHIP_R350, 125 CHIP_RV350, 126 CHIP_RV380, 127 CHIP_R420, 128 CHIP_R423, 129 CHIP_RV410, 130 CHIP_RS400, 131 CHIP_RS480, 132 CHIP_RS600, 133 CHIP_RS690, 134 CHIP_RS740, 135 CHIP_RV515, 136 CHIP_R520, 137 CHIP_RV530, 138 CHIP_RV560, 139 CHIP_RV570, 140 CHIP_R580, 141 CHIP_R600, 142 CHIP_RV610, 143 CHIP_RV630, 144 CHIP_RV670, 145 CHIP_RV620, 146 CHIP_RV635, 147 CHIP_RS780, 148 CHIP_RS880, 149 CHIP_RV770, 150 CHIP_RV730, 151 CHIP_RV710, 152 CHIP_RV740, 153 CHIP_CEDAR, 154 CHIP_REDWOOD, 155 CHIP_JUNIPER, 156 CHIP_CYPRESS, 157 CHIP_HEMLOCK, 158 CHIP_LAST, 159}; 160 161/* 162 * Chip flags 163 */ 164enum radeon_chip_flags { 165 RADEON_FAMILY_MASK = 0x0000ffffUL, 166 RADEON_FLAGS_MASK = 0xffff0000UL, 167 RADEON_IS_MOBILITY = 0x00010000UL, 168 RADEON_IS_IGP = 0x00020000UL, 169 RADEON_SINGLE_CRTC = 0x00040000UL, 170 RADEON_IS_AGP = 0x00080000UL, 171 RADEON_HAS_HIERZ = 0x00100000UL, 172 RADEON_IS_PCIE = 0x00200000UL, 173 RADEON_NEW_MEMMAP = 0x00400000UL, 174 RADEON_IS_PCI = 0x00800000UL, 175 RADEON_IS_IGPGART = 0x01000000UL, 176}; 177 178#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 179 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 180#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 181 182#define R600_GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 183 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(R600_CP_RB_RPTR)) 184 185typedef struct drm_radeon_freelist { 186 unsigned int age; 187 struct drm_buf *buf; 188 struct drm_radeon_freelist *next; 189 struct drm_radeon_freelist *prev; 190} drm_radeon_freelist_t; 191 192typedef struct drm_radeon_ring_buffer { 193 u32 *start; 194 u32 *end; 195 int size; /* Double Words */ 196 int size_l2qw; /* log2 Quad Words */ 197 198 int rptr_update; /* Double Words */ 199 int rptr_update_l2qw; /* log2 Quad Words */ 200 201 int fetch_size; /* Double Words */ 202 int fetch_size_l2ow; /* log2 Oct Words */ 203 204 u32 tail; 205 u32 tail_mask; 206 int space; 207 208 int high_mark; 209} drm_radeon_ring_buffer_t; 210 211typedef struct drm_radeon_depth_clear_t { 212 u32 rb3d_cntl; 213 u32 rb3d_zstencilcntl; 214 u32 se_cntl; 215} drm_radeon_depth_clear_t; 216 217struct drm_radeon_driver_file_fields { 218 int64_t radeon_fb_delta; 219}; 220 221struct mem_block { 222 struct mem_block *next; 223 struct mem_block *prev; 224 int start; 225 int size; 226 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 227}; 228 229struct radeon_surface { 230 int refcount; 231 u32 lower; 232 u32 upper; 233 u32 flags; 234}; 235 236struct radeon_virt_surface { 237 int surface_index; 238 u32 lower; 239 u32 upper; 240 u32 flags; 241 struct drm_file *file_priv; 242}; 243 244struct drm_radeon_kernel_chunk { 245 uint32_t chunk_id; 246 uint32_t length_dw; 247 uint32_t __user *chunk_data; 248 uint32_t *kdata; 249}; 250 251struct drm_radeon_cs_parser { 252 struct drm_device *dev; 253 struct drm_file *file_priv; 254 uint32_t num_chunks; 255 struct drm_radeon_kernel_chunk *chunks; 256 int ib_index; 257 int reloc_index; 258 uint32_t card_offset; 259 void *ib; 260}; 261 262/* command submission struct */ 263struct drm_radeon_cs_priv { 264 DRM_SPINTYPE cs_mutex; 265 uint32_t id_wcnt; 266 uint32_t id_scnt; 267 uint32_t id_last_wcnt; 268 uint32_t id_last_scnt; 269 270 int (*parse)(struct drm_radeon_cs_parser *parser); 271 void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id); 272 uint32_t (*id_last_get)(struct drm_device *dev); 273 /* this ib handling callback are for hidding memory manager drm 274 * from memory manager less drm, free have to emit ib discard 275 * sequence into the ring */ 276 int (*ib_get)(struct drm_radeon_cs_parser *parser); 277 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib); 278 void (*ib_free)(struct drm_radeon_cs_parser *parser, int error); 279 /* do a relocation either MM or non-MM */ 280 int (*relocate)(struct drm_radeon_cs_parser *parser, 281 uint32_t *reloc, uint64_t *offset); 282}; 283 284#define RADEON_FLUSH_EMITED (1 < 0) 285#define RADEON_PURGE_EMITED (1 < 1) 286 287typedef struct drm_radeon_private { 288 289 drm_radeon_ring_buffer_t ring; 290 drm_radeon_sarea_t *sarea_priv; 291 292 u32 fb_location; 293 u32 fb_size; 294 int new_memmap; 295 296 int gart_size; 297 u32 gart_vm_start; 298 unsigned long gart_buffers_offset; 299 300 int cp_mode; 301 int cp_running; 302 303 drm_radeon_freelist_t *head; 304 drm_radeon_freelist_t *tail; 305 int last_buf; 306 volatile u32 *scratch; 307 int writeback_works; 308 309 int usec_timeout; 310 311 struct { 312 u32 boxes; 313 int freelist_timeouts; 314 int freelist_loops; 315 int requested_bufs; 316 int last_frame_reads; 317 int last_clear_reads; 318 int clears; 319 int texture_uploads; 320 } stats; 321 322 int do_boxes; 323 int page_flipping; 324 325 u32 color_fmt; 326 unsigned int front_offset; 327 unsigned int front_pitch; 328 unsigned int back_offset; 329 unsigned int back_pitch; 330 331 u32 depth_fmt; 332 unsigned int depth_offset; 333 unsigned int depth_pitch; 334 335 u32 front_pitch_offset; 336 u32 back_pitch_offset; 337 u32 depth_pitch_offset; 338 339 drm_radeon_depth_clear_t depth_clear; 340 341 unsigned long ring_offset; 342 unsigned long ring_rptr_offset; 343 unsigned long buffers_offset; 344 unsigned long gart_textures_offset; 345 346 drm_local_map_t *sarea; 347 drm_local_map_t *mmio; 348 drm_local_map_t *fb_map; 349 drm_local_map_t *cp_ring; 350 drm_local_map_t *ring_rptr; 351 drm_local_map_t *gart_textures; 352 353 struct mem_block *gart_heap; 354 struct mem_block *fb_heap; 355 356 /* SW interrupt */ 357 wait_queue_head_t swi_queue; 358 atomic_t swi_emitted; 359 int vblank_crtc; 360 uint32_t irq_enable_reg; 361 int irq_enabled; 362 uint32_t r500_disp_irq_reg; 363 364 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 365 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 366 367 unsigned long pcigart_offset; 368 unsigned int pcigart_offset_set; 369 struct drm_ati_pcigart_info gart_info; 370 371 u32 scratch_ages[5]; 372 373 unsigned int crtc_last_cnt; 374 unsigned int crtc2_last_cnt; 375 376 /* starting from here on, data is preserved accross an open */ 377 uint32_t flags; /* see radeon_chip_flags */ 378 unsigned long fb_aper_offset; 379 380 int num_gb_pipes; 381 int num_z_pipes; 382 int track_flush; 383 uint32_t chip_family; /* extract from flags */ 384 385 /* r6xx/r7xx pipe/shader config */ 386 int r600_max_pipes; 387 int r600_max_tile_pipes; 388 int r600_max_simds; 389 int r600_max_backends; 390 int r600_max_gprs; 391 int r600_max_threads; 392 int r600_max_stack_entries; 393 int r600_max_hw_contexts; 394 int r600_max_gs_threads; 395 int r600_sx_max_export_size; 396 int r600_sx_max_export_pos_size; 397 int r600_sx_max_export_smx_size; 398 int r600_sq_num_cf_insts; 399 int r700_sx_num_of_sets; 400 int r700_sc_prim_fifo_size; 401 int r700_sc_hiz_tile_fifo_size; 402 int r700_sc_earlyz_tile_fifo_fize; 403 /* r6xx/r7xx drm blit vertex buffer */ 404 struct drm_buf *blit_vb; 405 406 /* CS */ 407 struct drm_radeon_cs_priv cs; 408 struct drm_buf *cs_buf; 409 410} drm_radeon_private_t; 411 412typedef struct drm_radeon_buf_priv { 413 u32 age; 414} drm_radeon_buf_priv_t; 415 416typedef struct drm_radeon_kcmd_buffer { 417 int bufsz; 418 char *buf; 419 int nbox; 420 struct drm_clip_rect __user *boxes; 421} drm_radeon_kcmd_buffer_t; 422 423extern int radeon_no_wb; 424extern struct drm_ioctl_desc radeon_ioctls[]; 425extern int radeon_max_ioctl; 426 427/* Check whether the given hardware address is inside the framebuffer or the 428 * GART area. 429 */ 430static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 431 u64 off) 432{ 433 u64 fb_start = dev_priv->fb_location; 434 u64 fb_end = fb_start + dev_priv->fb_size - 1; 435 u64 gart_start = dev_priv->gart_vm_start; 436 u64 gart_end = gart_start + dev_priv->gart_size - 1; 437 438 return ((off >= fb_start && off <= fb_end) || 439 (off >= gart_start && off <= gart_end)); 440} 441 442 /* radeon_cp.c */ 443extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 444extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 445extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 446extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 447extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 448extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 449extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 450extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 451extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 452extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 453extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); 454 455extern void radeon_freelist_reset(struct drm_device * dev); 456extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 457 458extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 459extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 460 461extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 462 463extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 464extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 465extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 466extern void radeon_mem_takedown(struct mem_block **heap); 467extern void radeon_mem_release(struct drm_file *file_priv, 468 struct mem_block *heap); 469 470 /* radeon_irq.c */ 471extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 472extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 473extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 474 475extern void radeon_do_release(struct drm_device * dev); 476extern u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int crtc); 477extern int radeon_enable_vblank(struct drm_device *dev, unsigned int crtc); 478extern void radeon_disable_vblank(struct drm_device *dev, unsigned int crtc); 479extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 480extern void radeon_driver_irq_preinstall(struct drm_device * dev); 481extern int radeon_driver_irq_postinstall(struct drm_device * dev); 482extern void radeon_driver_irq_uninstall(struct drm_device * dev); 483extern int radeon_vblank_crtc_get(struct drm_device *dev); 484extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 485 486extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 487extern int radeon_driver_unload(struct drm_device *dev); 488extern int radeon_driver_firstopen(struct drm_device *dev); 489extern void radeon_driver_preclose(struct drm_device * dev, 490 struct drm_file *file_priv); 491extern void radeon_driver_postclose(struct drm_device * dev, 492 struct drm_file *file_priv); 493extern void radeon_driver_lastclose(struct drm_device * dev); 494extern int radeon_driver_open(struct drm_device * dev, 495 struct drm_file * file_priv); 496extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 497 unsigned long arg); 498 499void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 500void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc); 501void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 502 503/* r300_cmdbuf.c */ 504extern void r300_init_reg_flags(struct drm_device *dev); 505 506extern int r300_do_cp_cmdbuf(struct drm_device *dev, 507 struct drm_file *file_priv, 508 drm_radeon_kcmd_buffer_t *cmdbuf); 509 510/* r600 cp */ 511extern int r600_do_engine_reset(struct drm_device *dev); 512extern int r600_do_cleanup_cp(struct drm_device *dev); 513extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init); 514extern int r600_do_resume_cp(struct drm_device *dev); 515extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 516extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 517extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 518extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 519extern int r600_cp_dispatch_indirect(struct drm_device *dev, 520 struct drm_buf *buf, int start, int end); 521extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 522extern int r600_page_table_init(struct drm_device *dev); 523extern void r600_cp_dispatch_swap(struct drm_device * dev); 524extern int r600_cp_dispatch_texture(struct drm_device * dev, 525 struct drm_file *file_priv, 526 drm_radeon_texture_t * tex, 527 drm_radeon_tex_image_t * image); 528 529/* r600_blit.c */ 530extern int 531r600_prepare_blit_copy(struct drm_device *dev); 532extern void 533r600_done_blit_copy(struct drm_device *dev); 534extern void 535r600_blit_copy(struct drm_device *dev, 536 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 537 int size_bytes); 538extern void 539r600_blit_swap(struct drm_device *dev, 540 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 541 int sx, int sy, int dx, int dy, 542 int w, int h, int src_pitch, int dst_pitch, int cpp); 543 544/* radeon_state.c */ 545extern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf); 546 547/* radeon_cs.c */ 548extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 549extern int r600_cs_init(struct drm_device *dev); 550 551/* part of platform code, usually radeon_drv.c */ 552int radeon_load_a_microcode(const char *fmt, const char *chip_name, void **codep, size_t *sizep); 553void radeon_free_a_microcode(void *code, size_t size); 554 555/* Flags for stats.boxes 556 */ 557#define RADEON_BOX_DMA_IDLE 0x1 558#define RADEON_BOX_RING_FULL 0x2 559#define RADEON_BOX_FLIP 0x4 560#define RADEON_BOX_WAIT_IDLE 0x8 561#define RADEON_BOX_TEXTURE_LOAD 0x10 562 563/* Register definitions, register access macros and drmAddMap constants 564 * for Radeon kernel driver. 565 */ 566#define RADEON_MM_INDEX 0x0000 567#define RADEON_MM_DATA 0x0004 568 569#define RADEON_AGP_COMMAND 0x0f60 570#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 571# define RADEON_AGP_ENABLE (1<<8) 572#define RADEON_AUX_SCISSOR_CNTL 0x26f0 573# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 574# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 575# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 576# define RADEON_SCISSOR_0_ENABLE (1 << 28) 577# define RADEON_SCISSOR_1_ENABLE (1 << 29) 578# define RADEON_SCISSOR_2_ENABLE (1 << 30) 579 580/* 581 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 582 * don't have an explicit bus mastering disable bit. It's handled 583 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 584 * handling, not bus mastering itself. 585 */ 586#define RADEON_BUS_CNTL 0x0030 587/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 588# define RADEON_BUS_MASTER_DIS (1 << 6) 589/* rs600/rs690/rs740 */ 590# define RS600_BUS_MASTER_DIS (1 << 14) 591# define RS600_MSI_REARM (1 << 20) 592/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ 593 594#define RADEON_BUS_CNTL1 0x0034 595# define RADEON_PMI_BM_DIS (1 << 2) 596# define RADEON_PMI_INT_DIS (1 << 3) 597 598#define RV370_BUS_CNTL 0x004c 599# define RV370_PMI_BM_DIS (1 << 5) 600# define RV370_PMI_INT_DIS (1 << 6) 601 602#define RADEON_MSI_REARM_EN 0x0160 603/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 604# define RV370_MSI_REARM_EN (1 << 0) 605 606#define RADEON_CLOCK_CNTL_DATA 0x000c 607# define RADEON_PLL_WR_EN (1 << 7) 608#define RADEON_CLOCK_CNTL_INDEX 0x0008 609#define RADEON_CONFIG_APER_SIZE 0x0108 610#define RADEON_CONFIG_MEMSIZE 0x00f8 611#define RADEON_CRTC_OFFSET 0x0224 612#define RADEON_CRTC_OFFSET_CNTL 0x0228 613# define RADEON_CRTC_TILE_EN (1 << 15) 614# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 615#define RADEON_CRTC2_OFFSET 0x0324 616#define RADEON_CRTC2_OFFSET_CNTL 0x0328 617 618#define RADEON_PCIE_INDEX 0x0030 619#define RADEON_PCIE_DATA 0x0034 620#define RADEON_PCIE_TX_GART_CNTL 0x10 621# define RADEON_PCIE_TX_GART_EN (1 << 0) 622# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 623# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 624# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 625# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 626# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 627# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 628# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 629#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 630#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 631#define RADEON_PCIE_TX_GART_BASE 0x13 632#define RADEON_PCIE_TX_GART_START_LO 0x14 633#define RADEON_PCIE_TX_GART_START_HI 0x15 634#define RADEON_PCIE_TX_GART_END_LO 0x16 635#define RADEON_PCIE_TX_GART_END_HI 0x17 636 637#define RS480_NB_MC_INDEX 0x168 638# define RS480_NB_MC_IND_WR_EN (1 << 8) 639#define RS480_NB_MC_DATA 0x16c 640 641#define RS690_MC_INDEX 0x78 642# define RS690_MC_INDEX_MASK 0x1ff 643# define RS690_MC_INDEX_WR_EN (1 << 9) 644# define RS690_MC_INDEX_WR_ACK 0x7f 645#define RS690_MC_DATA 0x7c 646 647/* MC indirect registers */ 648#define RS480_MC_MISC_CNTL 0x18 649# define RS480_DISABLE_GTW (1 << 1) 650/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 651# define RS480_GART_INDEX_REG_EN (1 << 12) 652# define RS690_BLOCK_GFX_D3_EN (1 << 14) 653#define RS480_K8_FB_LOCATION 0x1e 654#define RS480_GART_FEATURE_ID 0x2b 655# define RS480_HANG_EN (1 << 11) 656# define RS480_TLB_ENABLE (1 << 18) 657# define RS480_P2P_ENABLE (1 << 19) 658# define RS480_GTW_LAC_EN (1 << 25) 659# define RS480_2LEVEL_GART (0 << 30) 660# define RS480_1LEVEL_GART (1 << 30) 661# define RS480_PDC_EN (1 << 31) 662#define RS480_GART_BASE 0x2c 663#define RS480_GART_CACHE_CNTRL 0x2e 664# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 665#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 666# define RS480_GART_EN (1 << 0) 667# define RS480_VA_SIZE_32MB (0 << 1) 668# define RS480_VA_SIZE_64MB (1 << 1) 669# define RS480_VA_SIZE_128MB (2 << 1) 670# define RS480_VA_SIZE_256MB (3 << 1) 671# define RS480_VA_SIZE_512MB (4 << 1) 672# define RS480_VA_SIZE_1GB (5 << 1) 673# define RS480_VA_SIZE_2GB (6 << 1) 674#define RS480_AGP_MODE_CNTL 0x39 675# define RS480_POST_GART_Q_SIZE (1 << 18) 676# define RS480_NONGART_SNOOP (1 << 19) 677# define RS480_AGP_RD_BUF_SIZE (1 << 20) 678# define RS480_REQ_TYPE_SNOOP_SHIFT 22 679# define RS480_REQ_TYPE_SNOOP_MASK 0x3 680# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 681#define RS480_MC_MISC_UMA_CNTL 0x5f 682#define RS480_MC_MCLK_CNTL 0x7a 683#define RS480_MC_UMA_DUALCH_CNTL 0x86 684 685#define RS690_MC_FB_LOCATION 0x100 686#define RS690_MC_AGP_LOCATION 0x101 687#define RS690_MC_AGP_BASE 0x102 688#define RS690_MC_AGP_BASE_2 0x103 689 690#define RS600_MC_INDEX 0x70 691# define RS600_MC_ADDR_MASK 0xffff 692# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 693# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 694# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 695# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 696# define RS600_MC_IND_AIC_RBS (1 << 20) 697# define RS600_MC_IND_CITF_ARB0 (1 << 21) 698# define RS600_MC_IND_CITF_ARB1 (1 << 22) 699# define RS600_MC_IND_WR_EN (1 << 23) 700#define RS600_MC_DATA 0x74 701 702#define RS600_MC_STATUS 0x0 703# define RS600_MC_IDLE (1 << 1) 704#define RS600_MC_FB_LOCATION 0x4 705#define RS600_MC_AGP_LOCATION 0x5 706#define RS600_AGP_BASE 0x6 707#define RS600_AGP_BASE_2 0x7 708#define RS600_MC_CNTL1 0x9 709# define RS600_ENABLE_PAGE_TABLES (1 << 26) 710#define RS600_MC_PT0_CNTL 0x100 711# define RS600_ENABLE_PT (1 << 0) 712# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 713# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 714# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 715# define RS600_INVALIDATE_L2_CACHE (1 << 29) 716#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 717# define RS600_ENABLE_PAGE_TABLE (1 << 0) 718# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 719#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 720#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 721#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 722#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 723#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 724#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 725#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 726# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 727# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 728# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 729# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 730# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 731# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 732# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 733# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 734# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 735# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 736# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 737# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 738# define RS600_INVALIDATE_L1_TLB (1 << 20) 739 740#define R520_MC_IND_INDEX 0x70 741#define R520_MC_IND_WR_EN (1 << 24) 742#define R520_MC_IND_DATA 0x74 743 744#define RV515_MC_FB_LOCATION 0x01 745#define RV515_MC_AGP_LOCATION 0x02 746#define RV515_MC_AGP_BASE 0x03 747#define RV515_MC_AGP_BASE_2 0x04 748 749#define R520_MC_FB_LOCATION 0x04 750#define R520_MC_AGP_LOCATION 0x05 751#define R520_MC_AGP_BASE 0x06 752#define R520_MC_AGP_BASE_2 0x07 753 754#define RADEON_MPP_TB_CONFIG 0x01c0 755#define RADEON_MEM_CNTL 0x0140 756#define RADEON_MEM_SDRAM_MODE_REG 0x0158 757#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 758#define RS480_AGP_BASE_2 0x0164 759#define RADEON_AGP_BASE 0x0170 760 761/* pipe config regs */ 762#define R400_GB_PIPE_SELECT 0x402c 763#define RV530_GB_PIPE_SELECT2 0x4124 764#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 765#define R500_SU_REG_DEST 0x42c8 766#define R300_GB_TILE_CONFIG 0x4018 767# define R300_ENABLE_TILING (1 << 0) 768# define R300_PIPE_COUNT_RV350 (0 << 1) 769# define R300_PIPE_COUNT_R300 (3 << 1) 770# define R300_PIPE_COUNT_R420_3P (6 << 1) 771# define R300_PIPE_COUNT_R420 (7 << 1) 772# define R300_TILE_SIZE_8 (0 << 4) 773# define R300_TILE_SIZE_16 (1 << 4) 774# define R300_TILE_SIZE_32 (2 << 4) 775# define R300_SUBPIXEL_1_12 (0 << 16) 776# define R300_SUBPIXEL_1_16 (1 << 16) 777#define R300_DST_PIPE_CONFIG 0x170c 778# define R300_PIPE_AUTO_CONFIG (1 << 31) 779#define R300_RB2D_DSTCACHE_MODE 0x3428 780# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 781# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 782 783#define RADEON_RB3D_COLOROFFSET 0x1c40 784#define RADEON_RB3D_COLORPITCH 0x1c48 785 786#define RADEON_SRC_X_Y 0x1590 787 788#define RADEON_DP_GUI_MASTER_CNTL 0x146c 789# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 790# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 791# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 792# define RADEON_GMC_BRUSH_NONE (15 << 4) 793# define RADEON_GMC_DST_16BPP (4 << 8) 794# define RADEON_GMC_DST_24BPP (5 << 8) 795# define RADEON_GMC_DST_32BPP (6 << 8) 796# define RADEON_GMC_DST_DATATYPE_SHIFT 8 797# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 798# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 799# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 800# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 801# define RADEON_GMC_WR_MSK_DIS (1 << 30) 802# define RADEON_ROP3_S 0x00cc0000 803# define RADEON_ROP3_P 0x00f00000 804#define RADEON_DP_WRITE_MASK 0x16cc 805#define RADEON_SRC_PITCH_OFFSET 0x1428 806#define RADEON_DST_PITCH_OFFSET 0x142c 807#define RADEON_DST_PITCH_OFFSET_C 0x1c80 808# define RADEON_DST_TILE_LINEAR (0 << 30) 809# define RADEON_DST_TILE_MACRO (1 << 30) 810# define RADEON_DST_TILE_MICRO (2 << 30) 811# define RADEON_DST_TILE_BOTH (3 << 30) 812 813#define RADEON_SCRATCH_REG0 0x15e0 814#define RADEON_SCRATCH_REG1 0x15e4 815#define RADEON_SCRATCH_REG2 0x15e8 816#define RADEON_SCRATCH_REG3 0x15ec 817#define RADEON_SCRATCH_REG4 0x15f0 818#define RADEON_SCRATCH_REG5 0x15f4 819#define RADEON_SCRATCH_UMSK 0x0770 820#define RADEON_SCRATCH_ADDR 0x0774 821 822#define R600_SCRATCH_REG0 0x8500 823#define R600_SCRATCH_REG1 0x8504 824#define R600_SCRATCH_REG2 0x8508 825#define R600_SCRATCH_REG3 0x850c 826#define R600_SCRATCH_REG4 0x8510 827#define R600_SCRATCH_REG5 0x8514 828#define R600_SCRATCH_REG6 0x8518 829#define R600_SCRATCH_REG7 0x851c 830#define R600_SCRATCH_UMSK 0x8540 831#define R600_SCRATCH_ADDR 0x8544 832 833#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 834 835#define R600_SCRATCHOFF( x ) (R600_SCRATCH_REG_OFFSET + 4*(x)) 836 837#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 838 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 839 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 840 841#define GET_R600_SCRATCH( x ) (dev_priv->writeback_works \ 842 ? DRM_READ32( dev_priv->ring_rptr, R600_SCRATCHOFF(x) ) \ 843 : RADEON_READ( R600_SCRATCH_REG0 + 4*(x) ) ) 844 845#define RADEON_CRTC_CRNT_FRAME 0x0214 846#define RADEON_CRTC2_CRNT_FRAME 0x0314 847 848#define RADEON_CRTC_STATUS 0x005c 849#define RADEON_CRTC2_STATUS 0x03fc 850 851#define RADEON_GEN_INT_CNTL 0x0040 852# define RADEON_CRTC_VBLANK_MASK (1 << 0) 853# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 854# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 855# define RADEON_SW_INT_ENABLE (1 << 25) 856 857#define RADEON_GEN_INT_STATUS 0x0044 858# define RADEON_CRTC_VBLANK_STAT (1 << 0) 859# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 860# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 861# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 862# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 863# define RADEON_SW_INT_TEST (1 << 25) 864# define RADEON_SW_INT_TEST_ACK (1 << 25) 865# define RADEON_SW_INT_FIRE (1 << 26) 866# define R500_DISPLAY_INT_STATUS (1 << 0) 867 868 869#define RADEON_HOST_PATH_CNTL 0x0130 870# define RADEON_HDP_SOFT_RESET (1 << 26) 871# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 872# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 873 874#define RADEON_ISYNC_CNTL 0x1724 875# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 876# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 877# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 878# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 879# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 880# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 881 882#define RADEON_RBBM_GUICNTL 0x172c 883# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 884# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 885# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 886# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 887 888#define RADEON_MC_AGP_LOCATION 0x014c 889#define RADEON_MC_FB_LOCATION 0x0148 890#define RADEON_MCLK_CNTL 0x0012 891# define RADEON_FORCEON_MCLKA (1 << 16) 892# define RADEON_FORCEON_MCLKB (1 << 17) 893# define RADEON_FORCEON_YCLKA (1 << 18) 894# define RADEON_FORCEON_YCLKB (1 << 19) 895# define RADEON_FORCEON_MC (1 << 20) 896# define RADEON_FORCEON_AIC (1 << 21) 897 898#define RADEON_PP_BORDER_COLOR_0 0x1d40 899#define RADEON_PP_BORDER_COLOR_1 0x1d44 900#define RADEON_PP_BORDER_COLOR_2 0x1d48 901#define RADEON_PP_CNTL 0x1c38 902# define RADEON_SCISSOR_ENABLE (1 << 1) 903#define RADEON_PP_LUM_MATRIX 0x1d00 904#define RADEON_PP_MISC 0x1c14 905#define RADEON_PP_ROT_MATRIX_0 0x1d58 906#define RADEON_PP_TXFILTER_0 0x1c54 907#define RADEON_PP_TXOFFSET_0 0x1c5c 908#define RADEON_PP_TXFILTER_1 0x1c6c 909#define RADEON_PP_TXFILTER_2 0x1c84 910 911#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 912#define R300_DSTCACHE_CTLSTAT 0x1714 913# define R300_RB2D_DC_FLUSH (3 << 0) 914# define R300_RB2D_DC_FREE (3 << 2) 915# define R300_RB2D_DC_FLUSH_ALL 0xf 916# define R300_RB2D_DC_BUSY (1 << 31) 917#define RADEON_RB3D_CNTL 0x1c3c 918# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 919# define RADEON_PLANE_MASK_ENABLE (1 << 1) 920# define RADEON_DITHER_ENABLE (1 << 2) 921# define RADEON_ROUND_ENABLE (1 << 3) 922# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 923# define RADEON_DITHER_INIT (1 << 5) 924# define RADEON_ROP_ENABLE (1 << 6) 925# define RADEON_STENCIL_ENABLE (1 << 7) 926# define RADEON_Z_ENABLE (1 << 8) 927# define RADEON_ZBLOCK16 (1 << 15) 928#define RADEON_RB3D_DEPTHOFFSET 0x1c24 929#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 930#define RADEON_RB3D_DEPTHPITCH 0x1c28 931#define RADEON_RB3D_PLANEMASK 0x1d84 932#define RADEON_RB3D_STENCILREFMASK 0x1d7c 933#define RADEON_RB3D_ZCACHE_MODE 0x3250 934#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 935# define RADEON_RB3D_ZC_FLUSH (1 << 0) 936# define RADEON_RB3D_ZC_FREE (1 << 2) 937# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 938# define RADEON_RB3D_ZC_BUSY (1 << 31) 939#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 940# define R300_ZC_FLUSH (1 << 0) 941# define R300_ZC_FREE (1 << 1) 942# define R300_ZC_BUSY (1 << 31) 943#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 944# define RADEON_RB3D_DC_FLUSH (3 << 0) 945# define RADEON_RB3D_DC_FREE (3 << 2) 946# define RADEON_RB3D_DC_FLUSH_ALL 0xf 947# define RADEON_RB3D_DC_BUSY (1 << 31) 948#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 949# define R300_RB3D_DC_FLUSH (2 << 0) 950# define R300_RB3D_DC_FREE (2 << 2) 951# define R300_RB3D_DC_FINISH (1 << 4) 952#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 953# define RADEON_Z_TEST_MASK (7 << 4) 954# define RADEON_Z_TEST_ALWAYS (7 << 4) 955# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 956# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 957# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 958# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 959# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 960# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 961# define RADEON_FORCE_Z_DIRTY (1 << 29) 962# define RADEON_Z_WRITE_ENABLE (1 << 30) 963# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 964#define RADEON_RBBM_SOFT_RESET 0x00f0 965# define RADEON_SOFT_RESET_CP (1 << 0) 966# define RADEON_SOFT_RESET_HI (1 << 1) 967# define RADEON_SOFT_RESET_SE (1 << 2) 968# define RADEON_SOFT_RESET_RE (1 << 3) 969# define RADEON_SOFT_RESET_PP (1 << 4) 970# define RADEON_SOFT_RESET_E2 (1 << 5) 971# define RADEON_SOFT_RESET_RB (1 << 6) 972# define RADEON_SOFT_RESET_HDP (1 << 7) 973/* 974 * 6:0 Available slots in the FIFO 975 * 8 Host Interface active 976 * 9 CP request active 977 * 10 FIFO request active 978 * 11 Host Interface retry active 979 * 12 CP retry active 980 * 13 FIFO retry active 981 * 14 FIFO pipeline busy 982 * 15 Event engine busy 983 * 16 CP command stream busy 984 * 17 2D engine busy 985 * 18 2D portion of render backend busy 986 * 20 3D setup engine busy 987 * 26 GA engine busy 988 * 27 CBA 2D engine busy 989 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 990 * command stream queue not empty or Ring Buffer not empty 991 */ 992#define RADEON_RBBM_STATUS 0x0e40 993/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 994/* #define RADEON_RBBM_STATUS 0x1740 */ 995/* bits 6:0 are dword slots available in the cmd fifo */ 996# define RADEON_RBBM_FIFOCNT_MASK 0x007f 997# define RADEON_HIRQ_ON_RBB (1 << 8) 998# define RADEON_CPRQ_ON_RBB (1 << 9) 999# define RADEON_CFRQ_ON_RBB (1 << 10) 1000# define RADEON_HIRQ_IN_RTBUF (1 << 11) 1001# define RADEON_CPRQ_IN_RTBUF (1 << 12) 1002# define RADEON_CFRQ_IN_RTBUF (1 << 13) 1003# define RADEON_PIPE_BUSY (1 << 14) 1004# define RADEON_ENG_EV_BUSY (1 << 15) 1005# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 1006# define RADEON_E2_BUSY (1 << 17) 1007# define RADEON_RB2D_BUSY (1 << 18) 1008# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 1009# define RADEON_VAP_BUSY (1 << 20) 1010# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 1011# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 1012# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 1013# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 1014# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 1015# define RADEON_GA_BUSY (1 << 26) 1016# define RADEON_CBA2D_BUSY (1 << 27) 1017# define RADEON_RBBM_ACTIVE (1 << 31) 1018#define RADEON_RE_LINE_PATTERN 0x1cd0 1019#define RADEON_RE_MISC 0x26c4 1020#define RADEON_RE_TOP_LEFT 0x26c0 1021#define RADEON_RE_WIDTH_HEIGHT 0x1c44 1022#define RADEON_RE_STIPPLE_ADDR 0x1cc8 1023#define RADEON_RE_STIPPLE_DATA 0x1ccc 1024 1025#define RADEON_SCISSOR_TL_0 0x1cd8 1026#define RADEON_SCISSOR_BR_0 0x1cdc 1027#define RADEON_SCISSOR_TL_1 0x1ce0 1028#define RADEON_SCISSOR_BR_1 0x1ce4 1029#define RADEON_SCISSOR_TL_2 0x1ce8 1030#define RADEON_SCISSOR_BR_2 0x1cec 1031#define RADEON_SE_COORD_FMT 0x1c50 1032#define RADEON_SE_CNTL 0x1c4c 1033# define RADEON_FFACE_CULL_CW (0 << 0) 1034# define RADEON_BFACE_SOLID (3 << 1) 1035# define RADEON_FFACE_SOLID (3 << 3) 1036# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 1037# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 1038# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 1039# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 1040# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 1041# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 1042# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 1043# define RADEON_FOG_SHADE_FLAT (1 << 14) 1044# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 1045# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 1046# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 1047# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 1048# define RADEON_ROUND_MODE_TRUNC (0 << 28) 1049# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 1050#define RADEON_SE_CNTL_STATUS 0x2140 1051#define RADEON_SE_LINE_WIDTH 0x1db8 1052#define RADEON_SE_VPORT_XSCALE 0x1d98 1053#define RADEON_SE_ZBIAS_FACTOR 0x1db0 1054#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1055#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1056#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 1057# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 1058# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 1059#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 1060#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 1061# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 1062#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 1063#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 1064#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 1065#define RADEON_SURFACE_CNTL 0x0b00 1066# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1067# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 1068# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 1069# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 1070# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 1071# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 1072# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 1073# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 1074# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 1075#define RADEON_SURFACE0_INFO 0x0b0c 1076# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 1077# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 1078# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 1079# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 1080# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 1081# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 1082#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1083#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1084# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 1085#define RADEON_SURFACE1_INFO 0x0b1c 1086#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1087#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1088#define RADEON_SURFACE2_INFO 0x0b2c 1089#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1090#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1091#define RADEON_SURFACE3_INFO 0x0b3c 1092#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1093#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1094#define RADEON_SURFACE4_INFO 0x0b4c 1095#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1096#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1097#define RADEON_SURFACE5_INFO 0x0b5c 1098#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1099#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1100#define RADEON_SURFACE6_INFO 0x0b6c 1101#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1102#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1103#define RADEON_SURFACE7_INFO 0x0b7c 1104#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1105#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1106#define RADEON_SW_SEMAPHORE 0x013c 1107 1108#define RADEON_WAIT_UNTIL 0x1720 1109#define R600_WAIT_UNTIL 0x8040 1110# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1111# define RADEON_WAIT_2D_IDLE (1 << 14) 1112# define RADEON_WAIT_3D_IDLE (1 << 15) 1113# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1114# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1115# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1116 1117#define RADEON_RB3D_ZMASKOFFSET 0x3234 1118#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1119# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1120# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1121 1122/* CP registers */ 1123#define RADEON_CP_ME_RAM_ADDR 0x07d4 1124#define RADEON_CP_ME_RAM_RADDR 0x07d8 1125#define RADEON_CP_ME_RAM_DATAH 0x07dc 1126#define RADEON_CP_ME_RAM_DATAL 0x07e0 1127 1128#define RADEON_CP_RB_BASE 0x0700 1129#define RADEON_CP_RB_CNTL 0x0704 1130# define RADEON_BUF_SWAP_32BIT (2 << 16) 1131# define RADEON_RB_NO_UPDATE (1 << 27) 1132# define RADEON_RB_RPTR_WR_ENA (1 << 31) 1133#define RADEON_CP_RB_RPTR_ADDR 0x070c 1134#define RADEON_CP_RB_RPTR 0x0710 1135#define RADEON_CP_RB_WPTR 0x0714 1136 1137#define RADEON_CP_RB_WPTR_DELAY 0x0718 1138# define RADEON_PRE_WRITE_TIMER_SHIFT 0 1139# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1140 1141#define RADEON_CP_IB_BASE 0x0738 1142 1143#define RADEON_CP_CSQ_CNTL 0x0740 1144# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1145# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1146# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1147# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1148# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1149# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1150# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1151 1152#define RADEON_AIC_CNTL 0x01d0 1153# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1154# define RS400_MSI_REARM (1 << 3) 1155#define RADEON_AIC_STAT 0x01d4 1156#define RADEON_AIC_PT_BASE 0x01d8 1157#define RADEON_AIC_LO_ADDR 0x01dc 1158#define RADEON_AIC_HI_ADDR 0x01e0 1159#define RADEON_AIC_TLB_ADDR 0x01e4 1160#define RADEON_AIC_TLB_DATA 0x01e8 1161 1162/* CP command packets */ 1163#define RADEON_CP_PACKET0 0x00000000 1164# define RADEON_ONE_REG_WR (1 << 15) 1165#define RADEON_CP_PACKET1 0x40000000 1166#define RADEON_CP_PACKET2 0x80000000 1167#define RADEON_CP_PACKET3 0xC0000000 1168# define RADEON_CP_NOP 0x00001000 1169# define RADEON_CP_NEXT_CHAR 0x00001900 1170# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1171# define RADEON_CP_SET_SCISSORS 0x00001E00 1172 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1173# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1174# define RADEON_WAIT_FOR_IDLE 0x00002600 1175# define RADEON_3D_DRAW_VBUF 0x00002800 1176# define RADEON_3D_DRAW_IMMD 0x00002900 1177# define RADEON_3D_DRAW_INDX 0x00002A00 1178# define RADEON_CP_LOAD_PALETTE 0x00002C00 1179# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1180# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1181# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1182# define RADEON_3D_CLEAR_ZMASK 0x00003200 1183# define RADEON_CP_INDX_BUFFER 0x00003300 1184# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1185# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1186# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1187# define RADEON_3D_CLEAR_HIZ 0x00003700 1188# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1189# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1190# define RADEON_CNTL_PAINT_MULTI 0x00009A00 1191# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1192# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1193 1194# define R600_IT_INDIRECT_BUFFER 0x00003200 1195# define R600_IT_ME_INITIALIZE 0x00004400 1196# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1197# define R600_IT_EVENT_WRITE 0x00004600 1198# define R600_IT_SET_CONFIG_REG 0x00006800 1199# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1200 1201#define RADEON_CP_PACKET_MASK 0xC0000000 1202#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1203#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1204#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1205#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1206 1207#define RADEON_VTX_Z_PRESENT (1 << 31) 1208#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1209 1210#define RADEON_PRIM_TYPE_NONE (0 << 0) 1211#define RADEON_PRIM_TYPE_POINT (1 << 0) 1212#define RADEON_PRIM_TYPE_LINE (2 << 0) 1213#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1214#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1215#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1216#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1217#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1218#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1219#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1220#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1221#define RADEON_PRIM_TYPE_MASK 0xf 1222#define RADEON_PRIM_WALK_IND (1 << 4) 1223#define RADEON_PRIM_WALK_LIST (2 << 4) 1224#define RADEON_PRIM_WALK_RING (3 << 4) 1225#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1226#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1227#define RADEON_MAOS_ENABLE (1 << 7) 1228#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1229#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1230#define RADEON_NUM_VERTICES_SHIFT 16 1231 1232#define RADEON_COLOR_FORMAT_CI8 2 1233#define RADEON_COLOR_FORMAT_ARGB1555 3 1234#define RADEON_COLOR_FORMAT_RGB565 4 1235#define RADEON_COLOR_FORMAT_ARGB8888 6 1236#define RADEON_COLOR_FORMAT_RGB332 7 1237#define RADEON_COLOR_FORMAT_RGB8 9 1238#define RADEON_COLOR_FORMAT_ARGB4444 15 1239 1240#define RADEON_TXFORMAT_I8 0 1241#define RADEON_TXFORMAT_AI88 1 1242#define RADEON_TXFORMAT_RGB332 2 1243#define RADEON_TXFORMAT_ARGB1555 3 1244#define RADEON_TXFORMAT_RGB565 4 1245#define RADEON_TXFORMAT_ARGB4444 5 1246#define RADEON_TXFORMAT_ARGB8888 6 1247#define RADEON_TXFORMAT_RGBA8888 7 1248#define RADEON_TXFORMAT_Y8 8 1249#define RADEON_TXFORMAT_VYUY422 10 1250#define RADEON_TXFORMAT_YVYU422 11 1251#define RADEON_TXFORMAT_DXT1 12 1252#define RADEON_TXFORMAT_DXT23 14 1253#define RADEON_TXFORMAT_DXT45 15 1254 1255#define R200_PP_TXCBLEND_0 0x2f00 1256#define R200_PP_TXCBLEND_1 0x2f10 1257#define R200_PP_TXCBLEND_2 0x2f20 1258#define R200_PP_TXCBLEND_3 0x2f30 1259#define R200_PP_TXCBLEND_4 0x2f40 1260#define R200_PP_TXCBLEND_5 0x2f50 1261#define R200_PP_TXCBLEND_6 0x2f60 1262#define R200_PP_TXCBLEND_7 0x2f70 1263#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1264#define R200_PP_TFACTOR_0 0x2ee0 1265#define R200_SE_VTX_FMT_0 0x2088 1266#define R200_SE_VAP_CNTL 0x2080 1267#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1268#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1269#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1270#define R200_PP_TXFILTER_5 0x2ca0 1271#define R200_PP_TXFILTER_4 0x2c80 1272#define R200_PP_TXFILTER_3 0x2c60 1273#define R200_PP_TXFILTER_2 0x2c40 1274#define R200_PP_TXFILTER_1 0x2c20 1275#define R200_PP_TXFILTER_0 0x2c00 1276#define R200_PP_TXOFFSET_5 0x2d78 1277#define R200_PP_TXOFFSET_4 0x2d60 1278#define R200_PP_TXOFFSET_3 0x2d48 1279#define R200_PP_TXOFFSET_2 0x2d30 1280#define R200_PP_TXOFFSET_1 0x2d18 1281#define R200_PP_TXOFFSET_0 0x2d00 1282 1283#define R200_PP_CUBIC_FACES_0 0x2c18 1284#define R200_PP_CUBIC_FACES_1 0x2c38 1285#define R200_PP_CUBIC_FACES_2 0x2c58 1286#define R200_PP_CUBIC_FACES_3 0x2c78 1287#define R200_PP_CUBIC_FACES_4 0x2c98 1288#define R200_PP_CUBIC_FACES_5 0x2cb8 1289#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1290#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1291#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1292#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1293#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1294#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1295#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1296#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1297#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1298#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1299#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1300#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1301#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1302#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1303#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1304#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1305#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1306#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1307#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1308#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1309#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1310#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1311#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1312#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1313#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1314#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1315#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1316#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1317#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1318#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1319 1320#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1321#define R200_SE_VTE_CNTL 0x20b0 1322#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1323#define R200_PP_TAM_DEBUG3 0x2d9c 1324#define R200_PP_CNTL_X 0x2cc4 1325#define R200_SE_VAP_CNTL_STATUS 0x2140 1326#define R200_RE_SCISSOR_TL_0 0x1cd8 1327#define R200_RE_SCISSOR_TL_1 0x1ce0 1328#define R200_RE_SCISSOR_TL_2 0x1ce8 1329#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1330#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1331#define R200_SE_VTX_STATE_CNTL 0x2180 1332#define R200_RE_POINTSIZE 0x2648 1333#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1334 1335#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1336#define RADEON_PP_TEX_SIZE_1 0x1d0c 1337#define RADEON_PP_TEX_SIZE_2 0x1d14 1338 1339#define RADEON_PP_CUBIC_FACES_0 0x1d24 1340#define RADEON_PP_CUBIC_FACES_1 0x1d28 1341#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1342#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1343#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1344#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1345 1346#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1347 1348#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1349#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1350#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1351#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1352#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1353#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1354#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1355#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1356#define R200_3D_DRAW_IMMD_2 0xC0003500 1357#define R200_SE_VTX_FMT_1 0x208c 1358#define R200_RE_CNTL 0x1c50 1359 1360#define R200_RB3D_BLENDCOLOR 0x3218 1361 1362#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1363 1364#define R200_PP_TRI_PERF 0x2cf8 1365 1366#define R200_PP_AFS_0 0x2f80 1367#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1368 1369#define R200_VAP_PVS_CNTL_1 0x22D0 1370 1371/* MPEG settings from VHA code */ 1372#define RADEON_VHA_SETTO16_1 0x2694 1373#define RADEON_VHA_SETTO16_2 0x2680 1374#define RADEON_VHA_SETTO0_1 0x1840 1375#define RADEON_VHA_FB_OFFSET 0x19e4 1376#define RADEON_VHA_SETTO1AND70S 0x19d8 1377#define RADEON_VHA_DST_PITCH 0x1408 1378 1379// set as reference header 1380#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 1381#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 1382#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 1383#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 1384#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 1385#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 1386#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 1387#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 1388#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 1389#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 1390#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 1391#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 1392#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 1393#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 1394#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 1395#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 1396#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 1397#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 1398 1399#define R500_D1CRTC_STATUS 0x609c 1400#define R500_D2CRTC_STATUS 0x689c 1401#define R500_CRTC_V_BLANK (1<<0) 1402 1403#define R500_D1CRTC_FRAME_COUNT 0x60a4 1404#define R500_D2CRTC_FRAME_COUNT 0x68a4 1405 1406#define R500_D1MODE_V_COUNTER 0x6530 1407#define R500_D2MODE_V_COUNTER 0x6d30 1408 1409#define R500_D1MODE_VBLANK_STATUS 0x6534 1410#define R500_D2MODE_VBLANK_STATUS 0x6d34 1411#define R500_VBLANK_OCCURED (1<<0) 1412#define R500_VBLANK_ACK (1<<4) 1413#define R500_VBLANK_STAT (1<<12) 1414#define R500_VBLANK_INT (1<<16) 1415 1416#define R500_DxMODE_INT_MASK 0x6540 1417#define R500_D1MODE_INT_MASK (1<<0) 1418#define R500_D2MODE_INT_MASK (1<<8) 1419 1420#define R500_DISP_INTERRUPT_STATUS 0x7edc 1421#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1422#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1423 1424/* R6xx/R7xx registers */ 1425#define R600_MC_VM_FB_LOCATION 0x2180 1426#define R600_MC_VM_AGP_TOP 0x2184 1427#define R600_MC_VM_AGP_BOT 0x2188 1428#define R600_MC_VM_AGP_BASE 0x218c 1429#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1430#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1431#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1432 1433#define R700_MC_VM_FB_LOCATION 0x2024 1434#define R700_MC_VM_AGP_TOP 0x2028 1435#define R700_MC_VM_AGP_BOT 0x202c 1436#define R700_MC_VM_AGP_BASE 0x2030 1437#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1438#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1439#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1440 1441#define R600_MCD_RD_A_CNTL 0x219c 1442#define R600_MCD_RD_B_CNTL 0x21a0 1443 1444#define R600_MCD_WR_A_CNTL 0x21a4 1445#define R600_MCD_WR_B_CNTL 0x21a8 1446 1447#define R600_MCD_RD_SYS_CNTL 0x2200 1448#define R600_MCD_WR_SYS_CNTL 0x2214 1449 1450#define R600_MCD_RD_GFX_CNTL 0x21fc 1451#define R600_MCD_RD_HDP_CNTL 0x2204 1452#define R600_MCD_RD_PDMA_CNTL 0x2208 1453#define R600_MCD_RD_SEM_CNTL 0x220c 1454#define R600_MCD_WR_GFX_CNTL 0x2210 1455#define R600_MCD_WR_HDP_CNTL 0x2218 1456#define R600_MCD_WR_PDMA_CNTL 0x221c 1457#define R600_MCD_WR_SEM_CNTL 0x2220 1458 1459# define R600_MCD_L1_TLB (1 << 0) 1460# define R600_MCD_L1_FRAG_PROC (1 << 1) 1461# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1462 1463# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1464# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1465# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1466# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1467# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1468 1469# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1470# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1471 1472# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1473# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1474# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1475# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1476 1477#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1478#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1479#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1480 1481#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1482#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1483#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1484#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1485 1486# define R700_ENABLE_L1_TLB (1 << 0) 1487# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1488# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1489# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1490# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1491# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1492 1493#define R700_MC_ARB_RAMCFG 0x2760 1494# define R700_NOOFBANK_SHIFT 0 1495# define R700_NOOFBANK_MASK 0x3 1496# define R700_NOOFRANK_SHIFT 2 1497# define R700_NOOFRANK_MASK 0x1 1498# define R700_NOOFROWS_SHIFT 3 1499# define R700_NOOFROWS_MASK 0x7 1500# define R700_NOOFCOLS_SHIFT 6 1501# define R700_NOOFCOLS_MASK 0x3 1502# define R700_CHANSIZE_SHIFT 8 1503# define R700_CHANSIZE_MASK 0x1 1504# define R700_BURSTLENGTH_SHIFT 9 1505# define R700_BURSTLENGTH_MASK 0x1 1506#define R600_RAMCFG 0x2408 1507# define R600_NOOFBANK_SHIFT 0 1508# define R600_NOOFBANK_MASK 0x1 1509# define R600_NOOFRANK_SHIFT 1 1510# define R600_NOOFRANK_MASK 0x1 1511# define R600_NOOFROWS_SHIFT 2 1512# define R600_NOOFROWS_MASK 0x7 1513# define R600_NOOFCOLS_SHIFT 5 1514# define R600_NOOFCOLS_MASK 0x3 1515# define R600_CHANSIZE_SHIFT 7 1516# define R600_CHANSIZE_MASK 0x1 1517# define R600_BURSTLENGTH_SHIFT 8 1518# define R600_BURSTLENGTH_MASK 0x1 1519 1520#define R600_VM_L2_CNTL 0x1400 1521# define R600_VM_L2_CACHE_EN (1 << 0) 1522# define R600_VM_L2_FRAG_PROC (1 << 1) 1523# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1524# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1525# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1526 1527#define R600_VM_L2_CNTL2 0x1404 1528# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1529# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1530#define R600_VM_L2_CNTL3 0x1408 1531# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1532# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1533# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1534# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1535# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1536 1537#define R600_VM_L2_STATUS 0x140c 1538 1539#define R600_VM_CONTEXT0_CNTL 0x1410 1540# define R600_VM_ENABLE_CONTEXT (1 << 0) 1541# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1542 1543#define R600_VM_CONTEXT0_CNTL2 0x1430 1544#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1545#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1546#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1547#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1548#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1549#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1550 1551#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1552#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1553#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1554 1555#define R600_HDP_HOST_PATH_CNTL 0x2c00 1556 1557#define R600_GRBM_CNTL 0x8000 1558# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1559 1560#define R600_GRBM_STATUS 0x8010 1561# define R600_CMDFIFO_AVAIL_MASK 0x1f 1562# define R700_CMDFIFO_AVAIL_MASK 0xf 1563# define R600_GUI_ACTIVE (1 << 31) 1564#define R600_GRBM_STATUS2 0x8014 1565#define R600_GRBM_SOFT_RESET 0x8020 1566# define R600_SOFT_RESET_CP (1 << 0) 1567#define R600_WAIT_UNTIL 0x8040 1568 1569#define R600_CP_SEM_WAIT_TIMER 0x85bc 1570#define R600_CP_ME_CNTL 0x86d8 1571# define R600_CP_ME_HALT (1 << 28) 1572#define R600_CP_QUEUE_THRESHOLDS 0x8760 1573# define R600_ROQ_IB1_START(x) ((x) << 0) 1574# define R600_ROQ_IB2_START(x) ((x) << 8) 1575#define R600_CP_MEQ_THRESHOLDS 0x8764 1576# define R700_STQ_SPLIT(x) ((x) << 0) 1577# define R600_MEQ_END(x) ((x) << 16) 1578# define R600_ROQ_END(x) ((x) << 24) 1579#define R600_CP_PERFMON_CNTL 0x87fc 1580#define R600_CP_RB_BASE 0xc100 1581#define R600_CP_RB_CNTL 0xc104 1582# define R600_RB_BUFSZ(x) ((x) << 0) 1583# define R600_RB_BLKSZ(x) ((x) << 8) 1584# define R600_RB_NO_UPDATE (1 << 27) 1585# define R600_RB_RPTR_WR_ENA (1 << 31) 1586#define R600_CP_RB_RPTR_WR 0xc108 1587#define R600_CP_RB_RPTR_ADDR 0xc10c 1588#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1589#define R600_CP_RB_WPTR 0xc114 1590#define R600_CP_RB_WPTR_ADDR 0xc118 1591#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1592#define R600_CP_RB_RPTR 0x8700 1593#define R600_CP_RB_WPTR_DELAY 0x8704 1594#define R600_CP_PFP_UCODE_ADDR 0xc150 1595#define R600_CP_PFP_UCODE_DATA 0xc154 1596#define R600_CP_ME_RAM_RADDR 0xc158 1597#define R600_CP_ME_RAM_WADDR 0xc15c 1598#define R600_CP_ME_RAM_DATA 0xc160 1599#define R600_CP_DEBUG 0xc1fc 1600 1601#define R600_PA_CL_ENHANCE 0x8a14 1602# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1603# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1604#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1605#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1606#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1607# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1608# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1609#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1610#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1611#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1612#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1613# define R600_S0_X(x) ((x) << 0) 1614# define R600_S0_Y(x) ((x) << 4) 1615# define R600_S1_X(x) ((x) << 8) 1616# define R600_S1_Y(x) ((x) << 12) 1617# define R600_S2_X(x) ((x) << 16) 1618# define R600_S2_Y(x) ((x) << 20) 1619# define R600_S3_X(x) ((x) << 24) 1620# define R600_S3_Y(x) ((x) << 28) 1621# define R600_S4_X(x) ((x) << 0) 1622# define R600_S4_Y(x) ((x) << 4) 1623# define R600_S5_X(x) ((x) << 8) 1624# define R600_S5_Y(x) ((x) << 12) 1625# define R600_S6_X(x) ((x) << 16) 1626# define R600_S6_Y(x) ((x) << 20) 1627# define R600_S7_X(x) ((x) << 24) 1628# define R600_S7_Y(x) ((x) << 28) 1629#define R600_PA_SC_FIFO_SIZE 0x8bd0 1630# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1631# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1632# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1633#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1634# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1635# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1636# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1637#define R600_PA_SC_ENHANCE 0x8bf0 1638# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1639# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1640#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1641#define R700_PA_SC_EDGERULE 0x28230 1642#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1643#define R600_PA_SC_MODE_CNTL 0x28a4c 1644#define R600_PA_SC_AA_CONFIG 0x28c04 1645 1646#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1647# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1648# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1649# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1650#define R600_SX_DEBUG_1 0x9054 1651# define R600_SMX_EVENT_RELEASE (1 << 0) 1652# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1653#define R700_SX_DEBUG_1 0x9058 1654# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1655#define R600_SX_MISC 0x28350 1656 1657#define R600_DB_DEBUG 0x9830 1658# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1659#define R600_DB_WATERMARKS 0x9838 1660# define R600_DEPTH_FREE(x) ((x) << 0) 1661# define R600_DEPTH_FLUSH(x) ((x) << 5) 1662# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1663# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1664#define R700_DB_DEBUG3 0x98b0 1665# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1666#define RV700_DB_DEBUG4 0x9b8c 1667# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1668 1669#define R600_VGT_CACHE_INVALIDATION 0x88c4 1670# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1671# define R600_VC_ONLY 0 1672# define R600_TC_ONLY 1 1673# define R600_VC_AND_TC 2 1674# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1675# define R700_NO_AUTO 0 1676# define R700_ES_AUTO 1 1677# define R700_GS_AUTO 2 1678# define R700_ES_AND_GS_AUTO 3 1679#define R600_VGT_GS_PER_ES 0x88c8 1680#define R600_VGT_ES_PER_GS 0x88cc 1681#define R600_VGT_GS_PER_VS 0x88e8 1682#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1683#define R600_VGT_NUM_INSTANCES 0x8974 1684#define R600_VGT_STRMOUT_EN 0x28ab0 1685#define R600_VGT_EVENT_INITIATOR 0x28a90 1686# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1687#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1688# define R600_VTX_REUSE_DEPTH_MASK 0xff 1689#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1690# define R600_DEALLOC_DIST_MASK 0x7f 1691 1692#define R600_CB_COLOR0_BASE 0x28040 1693#define R600_CB_COLOR1_BASE 0x28044 1694#define R600_CB_COLOR2_BASE 0x28048 1695#define R600_CB_COLOR3_BASE 0x2804c 1696#define R600_CB_COLOR4_BASE 0x28050 1697#define R600_CB_COLOR5_BASE 0x28054 1698#define R600_CB_COLOR6_BASE 0x28058 1699#define R600_CB_COLOR7_BASE 0x2805c 1700#define R600_CB_COLOR7_FRAG 0x280fc 1701 1702#define R600_TC_CNTL 0x9608 1703# define R600_TC_L2_SIZE(x) ((x) << 5) 1704# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1705 1706#define R600_ARB_POP 0x2418 1707# define R600_ENABLE_TC128 (1 << 30) 1708#define R600_ARB_GDEC_RD_CNTL 0x246c 1709 1710#define R600_TA_CNTL_AUX 0x9508 1711# define R600_DISABLE_CUBE_WRAP (1 << 0) 1712# define R600_DISABLE_CUBE_ANISO (1 << 1) 1713# define R700_GETLOD_SELECT(x) ((x) << 2) 1714# define R600_SYNC_GRADIENT (1 << 24) 1715# define R600_SYNC_WALKER (1 << 25) 1716# define R600_SYNC_ALIGNER (1 << 26) 1717# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1718# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1719 1720#define R700_TCP_CNTL 0x9610 1721 1722#define R600_SMX_DC_CTL0 0xa020 1723# define R700_USE_HASH_FUNCTION (1 << 0) 1724# define R700_CACHE_DEPTH(x) ((x) << 1) 1725# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1726# define R700_STALL_ON_EVENT (1 << 11) 1727#define R700_SMX_EVENT_CTL 0xa02c 1728# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1729# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1730# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1731# define R700_SYNC_FLUSH_CTL (1 << 8) 1732 1733#define R600_SQ_CONFIG 0x8c00 1734# define R600_VC_ENABLE (1 << 0) 1735# define R600_EXPORT_SRC_C (1 << 1) 1736# define R600_DX9_CONSTS (1 << 2) 1737# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1738# define R600_DX10_CLAMP (1 << 4) 1739# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1740# define R600_PS_PRIO(x) ((x) << 24) 1741# define R600_VS_PRIO(x) ((x) << 26) 1742# define R600_GS_PRIO(x) ((x) << 28) 1743# define R600_ES_PRIO(x) ((x) << 30) 1744#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1745# define R600_NUM_PS_GPRS(x) ((x) << 0) 1746# define R600_NUM_VS_GPRS(x) ((x) << 16) 1747# define R700_DYN_GPR_ENABLE (1 << 27) 1748# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1749#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1750# define R600_NUM_GS_GPRS(x) ((x) << 0) 1751# define R600_NUM_ES_GPRS(x) ((x) << 16) 1752#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1753# define R600_NUM_PS_THREADS(x) ((x) << 0) 1754# define R600_NUM_VS_THREADS(x) ((x) << 8) 1755# define R600_NUM_GS_THREADS(x) ((x) << 16) 1756# define R600_NUM_ES_THREADS(x) ((x) << 24) 1757#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1758# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1759# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1760#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1761# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1762# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1763#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1764# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1765# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1766# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1767# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1768#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1769# define R700_SIMDA_RING0(x) ((x) << 0) 1770# define R700_SIMDA_RING1(x) ((x) << 8) 1771# define R700_SIMDB_RING0(x) ((x) << 16) 1772# define R700_SIMDB_RING1(x) ((x) << 24) 1773#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1774#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1775#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1776#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1777#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1778#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1779#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1780 1781#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1782# define R600_NUM_INTERP(x) ((x) << 0) 1783# define R600_POSITION_ENA (1 << 8) 1784# define R600_POSITION_CENTROID (1 << 9) 1785# define R600_POSITION_ADDR(x) ((x) << 10) 1786# define R600_PARAM_GEN(x) ((x) << 15) 1787# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1788# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1789# define R600_PERSP_GRADIENT_ENA (1 << 28) 1790# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1791# define R600_POSITION_SAMPLE (1 << 30) 1792# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1793#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1794# define R600_GEN_INDEX_PIX (1 << 0) 1795# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1796# define R600_FRONT_FACE_ENA (1 << 8) 1797# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1798# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1799# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1800# define R600_FOG_ADDR(x) ((x) << 17) 1801# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1802# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1803# define R700_POSITION_ULC (1 << 30) 1804#define R600_SPI_INPUT_Z 0x286d8 1805 1806#define R600_SPI_CONFIG_CNTL 0x9100 1807# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1808# define R600_DISABLE_INTERP_1 (1 << 5) 1809#define R600_SPI_CONFIG_CNTL_1 0x913c 1810# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1811# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1812 1813#define R600_GB_TILING_CONFIG 0x98f0 1814# define R600_PIPE_TILING(x) ((x) << 1) 1815# define R600_BANK_TILING(x) ((x) << 4) 1816# define R600_GROUP_SIZE(x) ((x) << 6) 1817# define R600_ROW_TILING(x) ((x) << 8) 1818# define R600_BANK_SWAPS(x) ((x) << 11) 1819# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1820# define R600_BACKEND_MAP(x) ((x) << 16) 1821#define R600_DCP_TILING_CONFIG 0x6ca0 1822#define R600_HDP_TILING_CONFIG 0x2f3c 1823 1824#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1825#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1826# define R600_BACKEND_DISABLE(x) ((x) << 16) 1827 1828#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1829#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1830# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1831# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1832# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1833# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1834 1835#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1836#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1837#define R700_CGTS_TCC_DISABLE 0x9148 1838#define R700_CGTS_USER_TCC_DISABLE 0x914c 1839 1840/* Constants */ 1841#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1842 1843#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1844#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1845#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1846#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1847#define RADEON_LAST_DISPATCH 1 1848 1849 1850#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1851#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1852#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1853#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1854 1855#define RADEON_MAX_VB_AGE 0x7fffffff 1856#define RADEON_MAX_VB_VERTS (0xffff) 1857 1858#define RADEON_RING_HIGH_MARK 128 1859 1860#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1861 1862#define RADEON_READ(reg) RADEON_READ_MM(dev_priv, reg) 1863#define RADEON_WRITE(reg,val) \ 1864do { \ 1865 if (reg < 0x10000) { \ 1866 DRM_WRITE32( dev_priv->mmio, (reg), (val) ); \ 1867 } else { \ 1868 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, (reg) ); \ 1869 DRM_WRITE32( dev_priv->mmio, RADEON_MM_DATA, (val) ); \ 1870 } \ 1871} while (0) 1872#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1873#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1874 1875#define RADEON_WRITE_PLL( addr, val ) \ 1876do { \ 1877 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1878 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1879 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1880} while (0) 1881 1882#define RADEON_WRITE_PCIE( addr, val ) \ 1883do { \ 1884 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1885 ((addr) & 0xff)); \ 1886 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1887} while (0) 1888 1889#define R500_WRITE_MCIND( addr, val ) \ 1890do { \ 1891 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1892 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1893 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1894} while (0) 1895 1896#define RS480_WRITE_MCIND( addr, val ) \ 1897do { \ 1898 RADEON_WRITE( RS480_NB_MC_INDEX, \ 1899 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1900 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ 1901 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ 1902} while (0) 1903 1904#define RS690_WRITE_MCIND( addr, val ) \ 1905do { \ 1906 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1907 RADEON_WRITE(RS690_MC_DATA, val); \ 1908 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1909} while (0) 1910 1911#define RS600_WRITE_MCIND( addr, val ) \ 1912do { \ 1913 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1914 RADEON_WRITE(RS600_MC_DATA, val); \ 1915} while (0) 1916 1917#define IGP_WRITE_MCIND( addr, val ) \ 1918do { \ 1919 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1921 RS690_WRITE_MCIND( addr, val ); \ 1922 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1923 RS600_WRITE_MCIND( addr, val ); \ 1924 else \ 1925 RS480_WRITE_MCIND( addr, val ); \ 1926} while (0) 1927 1928#define CP_PACKET0( reg, n ) \ 1929 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1930#define CP_PACKET0_TABLE( reg, n ) \ 1931 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1932#define CP_PACKET1( reg0, reg1 ) \ 1933 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1934#define CP_PACKET2() \ 1935 (RADEON_CP_PACKET2) 1936#define CP_PACKET3( pkt, n ) \ 1937 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1938 1939/* ================================================================ 1940 * Engine control helper macros 1941 */ 1942 1943#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1944 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1945 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1946 else \ 1947 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1948 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1949 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1950} while (0) 1951 1952#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1953 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1954 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1955 else \ 1956 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1957 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1958 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1959} while (0) 1960 1961#define RADEON_WAIT_UNTIL_IDLE() do { \ 1962 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1963 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1964 else \ 1965 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1966 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1967 RADEON_WAIT_3D_IDLECLEAN | \ 1968 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1969} while (0) 1970 1971#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1972 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1973 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1974 else \ 1975 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1976 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1977} while (0) 1978 1979#define RADEON_FLUSH_CACHE() do { \ 1980 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1981 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1982 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1983 } else { \ 1984 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1985 OUT_RING(R300_RB3D_DC_FLUSH); \ 1986 } \ 1987} while (0) 1988 1989#define RADEON_PURGE_CACHE() do { \ 1990 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1991 OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1992 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1993 } else { \ 1994 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1995 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ 1996 } \ 1997} while (0) 1998 1999#define RADEON_FLUSH_ZCACHE() do { \ 2000 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 2001 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 2002 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 2003 } else { \ 2004 OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ 2005 OUT_RING( R300_ZC_FLUSH ); \ 2006 } \ 2007} while (0) 2008 2009#define RADEON_PURGE_ZCACHE() do { \ 2010 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 2011 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 2012 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 2013 } else { \ 2014 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 2015 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 2016 } \ 2017} while (0) 2018 2019/* ================================================================ 2020 * Misc helper macros 2021 */ 2022 2023/* Perfbox functionality only. 2024 */ 2025#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 2026do { \ 2027 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 2028 u32 head = GET_RING_HEAD( dev_priv ); \ 2029 if (head == dev_priv->ring.tail) \ 2030 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 2031 } \ 2032} while (0) 2033 2034#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 2035do { \ 2036 drm_radeon_sarea_t *sarea_priv_ = dev_priv->sarea_priv; \ 2037 if ( sarea_priv_->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2038 int __ret = radeon_do_cp_idle( dev_priv ); \ 2039 if ( __ret ) return __ret; \ 2040 sarea_priv_->last_dispatch = 0; \ 2041 radeon_freelist_reset( dev ); \ 2042 } \ 2043} while (0) 2044 2045#define RADEON_DISPATCH_AGE( age ) do { \ 2046 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2047 OUT_RING( age ); \ 2048} while (0) 2049 2050#define RADEON_FRAME_AGE( age ) do { \ 2051 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2052 OUT_RING( age ); \ 2053} while (0) 2054 2055#define RADEON_CLEAR_AGE( age ) do { \ 2056 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2057 OUT_RING( age ); \ 2058} while (0) 2059 2060#define R600_DISPATCH_AGE(age) do { \ 2061 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2062 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2063 OUT_RING(age); \ 2064} while (0) 2065 2066#define R600_FRAME_AGE(age) do { \ 2067 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2068 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2069 OUT_RING(age); \ 2070} while (0) 2071 2072#define R600_CLEAR_AGE(age) do { \ 2073 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2074 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2075 OUT_RING(age); \ 2076} while (0) 2077 2078/* ================================================================ 2079 * Ring control 2080 */ 2081 2082#define RADEON_VERBOSE 0 2083 2084#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2085 2086#define RADEON_RING_ALIGN 16 2087 2088#define BEGIN_RING( n ) do { \ 2089 if ( RADEON_VERBOSE ) { \ 2090 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2091 } \ 2092 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \ 2093 _align_nr += n; \ 2094 if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \ 2095 COMMIT_RING(); \ 2096 radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \ 2097 } \ 2098 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2099 ring = dev_priv->ring.start; \ 2100 write = dev_priv->ring.tail; \ 2101 mask = dev_priv->ring.tail_mask; \ 2102} while (0) 2103 2104#define ADVANCE_RING() do { \ 2105 if ( RADEON_VERBOSE ) { \ 2106 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2107 write, dev_priv->ring.tail ); \ 2108 } \ 2109 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2110 DRM_ERROR( \ 2111 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2112 ((dev_priv->ring.tail + _nr) & mask), \ 2113 write, __LINE__); \ 2114 } else \ 2115 dev_priv->ring.tail = write; \ 2116} while (0) 2117 2118 2119#define COMMIT_RING() radeon_commit_ring(dev_priv) 2120 2121 2122#define OUT_RING( x ) do { \ 2123 if ( RADEON_VERBOSE ) { \ 2124 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2125 (unsigned int)(x), write ); \ 2126 } \ 2127 ring[write++] = (x); \ 2128 write &= mask; \ 2129} while (0) 2130 2131#define OUT_RING_REG( reg, val ) do { \ 2132 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2133 OUT_RING( val ); \ 2134} while (0) 2135 2136#define OUT_RING_TABLE( tab, sz ) do { \ 2137 int _size = (sz); \ 2138 int *_tab = (int *)(tab); \ 2139 \ 2140 if (write + _size > mask) { \ 2141 int _i = (mask+1) - write; \ 2142 _size -= _i; \ 2143 while (_i > 0) { \ 2144 *(int *)(ring + write) = *_tab++; \ 2145 write++; \ 2146 _i--; \ 2147 } \ 2148 write = 0; \ 2149 _tab += _i; \ 2150 } \ 2151 while (_size > 0) { \ 2152 *(ring + write) = *_tab++; \ 2153 write++; \ 2154 _size--; \ 2155 } \ 2156 write &= mask; \ 2157} while (0) 2158 2159#endif /* __RADEON_DRV_H__ */ 2160