1/*	$OpenBSD: if_urtwreg.h,v 1.13 2010/08/27 17:08:01 jsg Exp $	*/
2
3/*-
4 * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org>
5 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define	URTW_CONFIG_NO			1
21#define	URTW_IFACE_INDEX		0
22
23/*
24 * Known hardware revisions.
25 */
26#define	URTW_HWREV_8187			0x01
27#define	URTW_HWREV_8187_B		0x02
28#define	URTW_HWREV_8187_D		0x04
29#define	URTW_HWREV_8187B		0x08
30#define	URTW_HWREV_8187B_B		0x10
31#define	URTW_HWREV_8187B_D		0x20
32#define	URTW_HWREV_8187B_E		0x40
33
34/*
35 * Registers specific to RTL8187 and RTL8187B.
36 */
37#define	URTW_MAC0			0x0000		/* 1 byte */
38#define	URTW_MAC1			0x0001		/* 1 byte */
39#define	URTW_MAC2			0x0002		/* 1 byte */
40#define	URTW_MAC3			0x0003		/* 1 byte */
41#define	URTW_MAC4			0x0004		/* 1 byte */
42#define	URTW_MAC5			0x0005		/* 1 byte */
43#define	URTW_8187_BRSR			0x002c		/* 2 byte */
44#define	URTW_BRSR_MBR_8185		(0x0fff)
45#define	URTW_8187B_EIFS			0x002d		/* 1 byte */
46#define	URTW_BSSID			0x002e		/* 6 byte */
47#define	URTW_RESP_RATE			0x0034		/* 1 byte */
48#define	URTW_8187B_BRSR			0x0034		/* 2 byte */
49#define	URTW_RESP_MAX_RATE_SHIFT	(4)
50#define	URTW_RESP_MIN_RATE_SHIFT	(0)
51#define	URTW_8187_EIFS			0x0035		/* 1 byte */
52#define	URTW_INTR_MASK			0x003c		/* 2 byte */
53#define	URTW_CMD			0x0037		/* 1 byte */
54#define	URTW_CMD_TX_ENABLE		(0x4)
55#define	URTW_CMD_RX_ENABLE		(0x8)
56#define	URTW_CMD_RST			(0x10)
57#define	URTW_TX_CONF			0x0040		/* 4 byte */
58#define	URTW_TX_HWREV_MASK		(7 << 25)
59#define	URTW_TX_HWREV_8187_D		(5 << 25)
60#define	URTW_TX_HWREV_8187B_D		(6 << 25)
61#define	URTW_TX_DURPROCMODE		(1 << 30)
62#define	URTW_TX_DISREQQSIZE		(1 << 28)
63#define	URTW_TX_SHORTRETRY		(7 << 8)
64#define	URTW_TX_LONGRETRY		(7 << 0)
65#define	URTW_TX_LOOPBACK_SHIFT		(17)
66#define	URTW_TX_LOOPBACK_NONE		(0 << URTW_TX_LOOPBACK_SHIFT)
67#define	URTW_TX_LOOPBACK_MAC		(1 << URTW_TX_LOOPBACK_SHIFT)
68#define	URTW_TX_LOOPBACK_BASEBAND	(2 << URTW_TX_LOOPBACK_SHIFT)
69#define	URTW_TX_LOOPBACK_CONTINUE	(3 << URTW_TX_LOOPBACK_SHIFT)
70#define	URTW_TX_LOOPBACK_MASK		(0x60000)
71#define	URTW_TX_DPRETRY_MASK		(0xff00)
72#define	URTW_TX_RTSRETRY_MASK		(0xff)
73#define	URTW_TX_DPRETRY_SHIFT		(0)
74#define	URTW_TX_RTSRETRY_SHIFT		(8)
75#define	URTW_TX_NOCRC			(0x10000)
76#define	URTW_TX_MXDMA_MASK		(0xe00000)
77#define	URTW_TX_MXDMA_1024		(6 << URTW_TX_MXDMA_SHIFT)
78#define	URTW_TX_MXDMA_2048		(7 << URTW_TX_MXDMA_SHIFT)
79#define	URTW_TX_MXDMA_SHIFT		(21)
80#define	URTW_TX_CWMIN			(1 << 31)
81#define	URTW_TX_DISCW			(1 << 20)
82#define	URTW_TX_SWPLCPLEN		(1 << 24)
83#define	URTW_TX_NOICV			(0x80000)
84#define	URTW_RX				0x0044		/* 4 byte */
85#define	URTW_RX_9356SEL			(1 << 6)
86#define	URTW_RX_FILTER_MASK			\
87	(URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \
88	URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \
89	URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG |	\
90	(1 << 21) |							\
91	URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID)
92#define	URTW_RX_FILTER_ALLMAC		(0x00000001)
93#define	URTW_RX_FILTER_NICMAC		(0x00000002)
94#define	URTW_RX_FILTER_MCAST		(0x00000004)
95#define	URTW_RX_FILTER_BCAST		(0x00000008)
96#define	URTW_RX_FILTER_CRCERR		(0x00000020)
97#define	URTW_RX_FILTER_ICVERR		(0x00001000)
98#define	URTW_RX_FILTER_DATA		(0x00040000)
99#define	URTW_RX_FILTER_CTL		(0x00080000)
100#define	URTW_RX_FILTER_MNG		(0x00100000)
101#define	URTW_RX_FILTER_PWR		(0x00400000)
102#define	URTW_RX_CHECK_BSSID		(0x00800000)
103#define	URTW_RX_FIFO_THRESHOLD_MASK	((1 << 13) | (1 << 14) | (1 << 15))
104#define	URTW_RX_FIFO_THRESHOLD_SHIFT	(13)
105#define	URTW_RX_FIFO_THRESHOLD_128	(3)
106#define	URTW_RX_FIFO_THRESHOLD_256	(4)
107#define	URTW_RX_FIFO_THRESHOLD_512	(5)
108#define	URTW_RX_FIFO_THRESHOLD_1024	(6)
109#define	URTW_RX_FIFO_THRESHOLD_NONE	(7 << URTW_RX_FIFO_THRESHOLD_SHIFT)
110#define	URTW_RX_AUTORESETPHY		(1 << URTW_RX_AUTORESETPHY_SHIFT)
111#define	URTW_RX_AUTORESETPHY_SHIFT	(28)
112#define	URTW_MAX_RX_DMA_MASK		((1<<8) | (1<<9) | (1<<10))
113#define	URTW_MAX_RX_DMA_2048		(7 << URTW_MAX_RX_DMA_SHIFT)
114#define	URTW_MAX_RX_DMA_1024		(6)
115#define	URTW_MAX_RX_DMA_SHIFT		(10)
116#define	URTW_RCR_ONLYERLPKT		(1 << 31)
117#define	URTW_INT_TIMEOUT		0x0048		/* 4 byte */
118#define	URTW_EPROM_CMD			0x0050		/* 1 byte */
119#define	URTW_EPROM_CMD_NORMAL		(0x0)
120#define	URTW_EPROM_CMD_NORMAL_MODE				\
121	(URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT)
122#define	URTW_EPROM_CMD_LOAD		(0x1)
123#define	URTW_EPROM_CMD_PROGRAM		(0x2)
124#define	URTW_EPROM_CMD_PROGRAM_MODE				\
125	(URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT)
126#define	URTW_EPROM_CMD_CONFIG		(0x3)
127#define	URTW_EPROM_CMD_SHIFT		(6)
128#define	URTW_EPROM_CMD_MASK		((1 << 7) | (1 << 6))
129#define	URTW_EPROM_READBIT		(0x1)
130#define	URTW_EPROM_WRITEBIT		(0x2)
131#define	URTW_EPROM_CK			(0x4)
132#define	URTW_EPROM_CS			(0x8)
133#define	URTW_CONFIG1			0x0052		/* 1 byte */
134#define	URTW_CONFIG2			0x0053		/* 1 byte */
135#define	URTW_ANAPARAM			0x0054		/* 4 byte */
136#define	URTW_8187_8225_ANAPARAM_ON	(0xa0000a59)
137#define	URTW_8187B_8225_ANAPARAM_ON	(0x45090658)
138#define	URTW_MSR			0x0058		/* 1 byte */
139#define	URTW_MSR_LINK_MASK		((1 << 2) | (1 << 3))
140#define	URTW_MSR_LINK_SHIFT		(2)
141#define	URTW_MSR_LINK_NONE		(0 << URTW_MSR_LINK_SHIFT)
142#define	URTW_MSR_LINK_ADHOC		(1 << URTW_MSR_LINK_SHIFT)
143#define	URTW_MSR_LINK_STA		(2 << URTW_MSR_LINK_SHIFT)
144#define	URTW_MSR_LINK_HOSTAP		(3 << URTW_MSR_LINK_SHIFT)
145#define	URTW_MSR_LINK_ENEDCA		(4 << URTW_MSR_LINK_SHIFT)
146#define	URTW_CONFIG3			0x0059		/* 1 byte */
147#define	URTW_CONFIG3_ANAPARAM_WRITE	(0x40)
148#define	URTW_CONFIG3_ANAPARAM_W_SHIFT	(6)
149#define	URTW_CONFIG3_GNT_SELECT		(0x80)
150#define	URTW_PSR			0x005e		/* 1 byte */
151#define	URTW_ANAPARAM2			0x0060		/* 4 byte */
152#define	URTW_8187_8225_ANAPARAM2_ON	(0x860c7312)
153#define	URTW_8187B_8225_ANAPARAM2_ON	(0x727f3f52)
154#define	URTW_BEACON_INTERVAL		0x0070		/* 2 byte */
155#define	URTW_ATIM_WND			0x0072		/* 2 byte */
156#define	URTW_BEACON_INTERVAL_TIME	0x0074		/* 2 byte */
157#define	URTW_ATIM_TR_ITV		0x0076		/* 2 byte */
158#define	URTW_RF_PINS_OUTPUT		0x0080		/* 2 byte */
159#define	URTW_BB_HOST_BANG_CLK		(1 << 1)
160#define	URTW_BB_HOST_BANG_EN		(1 << 2)
161#define	URTW_BB_HOST_BANG_RW		(1 << 3)
162#define	URTW_RF_PINS_ENABLE		0x0082		/* 2 byte */
163#define	URTW_RF_PINS_SELECT		0x0084		/* 2 byte */
164#define	URTW_RF_PINS_INPUT		0x0086		/* 2 byte */
165#define	URTW_RF_PARA			0x0088		/* 4 byte */
166#define	URTW_RF_TIMING			0x008c		/* 4 byte */
167#define	URTW_GP_ENABLE			0x0090		/* 1 byte */
168#define	URTW_GPIO			0x0091		/* 1 byte */
169#define	URTW_HSSI_PARA			0x0094		/* 4 byte */
170#define	URTW_TX_AGC_CTL			0x009c		/* 1 byte */
171#define	URTW_TX_AGC_CTL_PERPACKET_GAIN	(0x1)
172#define	URTW_TX_AGC_CTL_PERPACKET_ANTSEL	(0x2)
173#define	URTW_TX_AGC_CTL_FEEDBACK_ANT	(0x4)
174#define	URTW_TX_GAIN_CCK		0x009d		/* 1 byte */
175#define	URTW_TX_GAIN_OFDM		0x009e		/* 1 byte */
176#define	URTW_TX_ANTENNA			0x009f		/* 1 byte */
177#define	URTW_WPA_CONFIG			0x00b0		/* 1 byte */
178#define	URTW_SIFS			0x00b4		/* 1 byte */
179#define	URTW_DIFS			0x00b5		/* 1 byte */
180#define	URTW_SLOT			0x00b6		/* 1 byte */
181#define	URTW_CW_CONF			0x00bc		/* 1 byte */
182#define	URTW_CW_CONF_PERPACKET_RETRY	(0x2)
183#define	URTW_CW_CONF_PERPACKET_CW	(0x1)
184#define	URTW_CW_VAL			0x00bd		/* 1 byte */
185#define	URTW_RATE_FALLBACK		0x00be		/* 1 byte */
186#define	URTW_RATE_FALLBACK_ENABLE	(0x80)
187#define	URTW_ACM_CONTROL		0x00bf		/* 1 byte */
188#define	URTW_8187B_HWREV		0x00e1		/* 1 byte */
189#define	URTW_8187B_HWREV_8187B_B	(0x0)
190#define	URTW_8187B_HWREV_8187B_D	(0x1)
191#define	URTW_8187B_HWREV_8187B_E	(0x2)
192#define	URTW_INT_MIG			0x00e2		/* 2 byte */
193#define	URTW_TID_AC_MAP			0x00e8		/* 2 byte */
194#define	URTW_ANAPARAM3			0x00ee		/* 4 byte */
195#define	URTW_8187B_8225_ANAPARAM3_ON	(0x0)
196#define	URTW_TALLY_SEL			0x00fc		/* 1 byte */
197#define	URTW_AC_VO			0x00f0		/* 1 byte */
198#define	URTW_AC_VI			0x00f4		/* 1 byte */
199#define	URTW_AC_BE			0x00f8		/* 1 byte */
200#define	URTW_AC_BK			0x00fc		/* 1 byte */
201#define	URTW_FEMR			0x01d4		/* 2 byte */
202#define	URTW_ARFR			0x01e0		/* 2 byte */
203#define	URTW_RFSW_CTRL			0x0272		/* 2 byte */
204
205/* for EEPROM */
206#define	URTW_EPROM_TXPW_BASE		0x05
207#define	URTW_EPROM_RFCHIPID		0x06
208#define	URTW_EPROM_RFCHIPID_RTL8225U	(5)
209#define	URTW_EPROM_MACADDR		0x07
210#define	URTW_EPROM_TXPW0		0x16
211#define	URTW_EPROM_TXPW2		0x1b
212#define	URTW_EPROM_TXPW1		0x3d
213#define	URTW_EPROM_SWREV		0x3f
214#define	URTW_EPROM_CID_MASK		(0xff)
215#define	URTW_EPROM_CID_RSVD0		(0x00)
216#define	URTW_EPROM_CID_RSVD1		(0xff)
217#define	URTW_EPROM_CID_ALPHA0		(0x01)
218#define	URTW_EPROM_CID_SERCOMM_PS	(0x02)
219#define	URTW_EPROM_CID_HW_LED		(0x03)
220
221/* LED */
222#define	URTW_CID_DEFAULT		0
223#define	URTW_CID_8187_ALPHA0		1
224#define	URTW_CID_8187_SERCOMM_PS	2
225#define	URTW_CID_8187_HW_LED		3
226#define	URTW_SW_LED_MODE0		0
227#define	URTW_SW_LED_MODE1		1
228#define	URTW_SW_LED_MODE2		2
229#define	URTW_SW_LED_MODE3		3
230#define	URTW_HW_LED			4
231#define	URTW_LED_CTL_POWER_ON		0
232#define	URTW_LED_CTL_LINK		2
233#define	URTW_LED_CTL_TX			4
234#define	URTW_LED_PIN_GPIO0		0
235#define	URTW_LED_PIN_LED0		1
236#define	URTW_LED_PIN_LED1		2
237#define	URTW_LED_UNKNOWN		0
238#define	URTW_LED_ON			1
239#define	URTW_LED_OFF			2
240#define	URTW_LED_BLINK_NORMAL		3
241#define	URTW_LED_BLINK_SLOWLY		4
242#define	URTW_LED_POWER_ON_BLINK		5
243#define	URTW_LED_SCAN_BLINK		6
244#define	URTW_LED_NO_LINK_BLINK		7
245#define	URTW_LED_BLINK_CM3		8
246
247/* for extra area */
248#define	URTW_EPROM_DISABLE		0
249#define	URTW_EPROM_ENABLE		1
250#define	URTW_EPROM_DELAY		10
251#define	URTW_8187_GETREGS_REQ		5
252#define	URTW_8187_SETREGS_REQ		5
253#define	URTW_8225_RF_MAX_SENS		6
254#define	URTW_8225_RF_DEF_SENS		4
255#define	URTW_DEFAULT_RTS_RETRY		7
256#define	URTW_DEFAULT_TX_RETRY		7
257#define	URTW_DEFAULT_RTS_THRESHOLD	2342U
258
259#define	URTW_MAX_CHANNELS		15
260
261struct urtw_tx_data {
262	struct urtw_softc	*sc;
263	usbd_xfer_handle	xfer;
264	uint8_t			*buf;
265	struct ieee80211_node	*ni;
266};
267
268struct urtw_rx_data {
269	struct urtw_softc	*sc;
270	usbd_xfer_handle	xfer;
271	uint8_t			*buf;
272	struct mbuf		*m;
273};
274
275/* XXX not correct.. */
276#define	URTW_MIN_RXBUFSZ						\
277	(sizeof(struct ieee80211_frame_min))
278
279#define	URTW_RX_DATA_LIST_COUNT		1
280#define	URTW_TX_DATA_LIST_COUNT		16
281#define	URTW_RX_MAXSIZE			0x9c4
282#define	URTW_TX_MAXSIZE			0x9c4
283
284struct urtw_rx_radiotap_header {
285	struct ieee80211_radiotap_header wr_ihdr;
286	uint8_t		wr_flags;
287	uint16_t	wr_chan_freq;
288	uint16_t	wr_chan_flags;
289	int8_t		wr_dbm_antsignal;
290} __packed;
291
292#define	URTW_RX_RADIOTAP_PRESENT					\
293	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
294	 (1 << IEEE80211_RADIOTAP_CHANNEL) |				\
295	 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL))
296
297struct urtw_tx_radiotap_header {
298	struct ieee80211_radiotap_header wt_ihdr;
299	uint8_t		wt_flags;
300	uint8_t		wt_rate;
301	uint16_t	wt_chan_freq;
302	uint16_t	wt_chan_flags;
303} __packed;
304
305#define	URTW_TX_RADIOTAP_PRESENT					\
306	((1 << IEEE80211_RADIOTAP_FLAGS) |				\
307	 (1 << IEEE80211_RADIOTAP_CHANNEL))
308
309struct urtw_rf {
310	/* RF methods */
311	usbd_status			(*init)(struct urtw_rf *);
312	usbd_status			(*set_chan)(struct urtw_rf *, int);
313	usbd_status			(*set_sens)(struct urtw_rf *);
314
315	/* RF attributes */
316	struct urtw_softc		*rf_sc;
317	uint32_t			max_sens;
318	uint32_t			sens;
319};
320
321struct urtw_softc {
322	device_t			sc_dev;
323	struct ieee80211com		sc_ic;
324	struct ethercom			sc_ec;
325#define sc_if	sc_ec.ec_if
326	int				(*sc_newstate)(struct ieee80211com *,
327					    enum ieee80211_state, int);
328	struct urtw_rf			sc_rf;
329
330	bool				sc_dying;
331
332	struct usb_task			sc_task;
333	usbd_device_handle		sc_udev;
334	usbd_interface_handle		sc_iface;
335
336	enum ieee80211_state		sc_state;
337	int				sc_arg;
338
339	uint8_t				sc_hwrev;
340	int				sc_flags;
341#define	URTW_INIT_ONCE			(1 << 1)
342	int				sc_epromtype;
343#define	URTW_EEPROM_93C46		0
344#define	URTW_EEPROM_93C56		1
345	uint8_t				sc_crcmon;
346	uint8_t				sc_bssid[IEEE80211_ADDR_LEN];
347
348	/* for LED */
349	struct callout			sc_led_ch;
350	struct usb_task			sc_ledtask;
351	uint8_t				sc_psr;
352	uint8_t				sc_strategy;
353#define	URTW_LED_GPIO			1
354	uint8_t				sc_gpio_ledon;
355	uint8_t				sc_gpio_ledinprogress;
356	uint8_t				sc_gpio_ledstate;
357	uint8_t				sc_gpio_ledpin;
358	uint8_t				sc_gpio_blinktime;
359	uint8_t				sc_gpio_blinkstate;
360	/* RX/TX */
361	usbd_pipe_handle		sc_rxpipe;
362	usbd_pipe_handle		sc_txpipe_low;
363	usbd_pipe_handle		sc_txpipe_normal;
364#define	URTW_PRIORITY_LOW		0
365#define	URTW_PRIORITY_NORMAL		1
366#define	URTW_DATA_TIMEOUT		10000		/* 10 sec */
367	struct urtw_rx_data		sc_rx_data[URTW_RX_DATA_LIST_COUNT];
368	struct urtw_tx_data		sc_tx_data[URTW_TX_DATA_LIST_COUNT];
369	uint32_t			sc_tx_low_queued;
370	uint32_t			sc_tx_normal_queued;
371	uint32_t			sc_txidx;
372	uint8_t				sc_rts_retry;
373	uint8_t				sc_tx_retry;
374	uint8_t				sc_preamble_mode;
375	struct callout			scan_to;
376	int				sc_txtimer;
377	int				sc_currate;
378	/* TX power */
379	uint8_t				sc_txpwr_cck[URTW_MAX_CHANNELS];
380	uint8_t				sc_txpwr_cck_base;
381	uint8_t				sc_txpwr_ofdm[URTW_MAX_CHANNELS];
382	uint8_t				sc_txpwr_ofdm_base;
383
384	struct bpf_if *			sc_drvbpf;
385
386	union {
387		struct urtw_rx_radiotap_header th;
388		uint8_t pad[64];
389	}				sc_rxtapu;
390#define	sc_rxtap	sc_rxtapu.th
391	int				sc_rxtap_len;
392
393	union {
394		struct urtw_tx_radiotap_header th;
395		uint8_t pad[64];
396	}				sc_txtapu;
397#define	sc_txtap	sc_txtapu.th
398	int				sc_txtap_len;
399};
400
401