1/* $NetBSD: sdhc.c,v 1.43 2013/01/10 17:19:33 jmcneill Exp $ */ 2/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */ 3 4/* 5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/* 21 * SD Host Controller driver based on the SD Host Controller Standard 22 * Simplified Specification Version 1.00 (www.sdcard.com). 23 */ 24 25#include <sys/cdefs.h> 26__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.10.2.4 2013/01/02 23:34:56 riz Exp $"); 27 28#ifdef _KERNEL_OPT 29#include "opt_sdmmc.h" 30#endif 31 32#include <sys/param.h> 33#include <sys/device.h> 34#include <sys/kernel.h> 35#include <sys/kthread.h> 36#include <sys/malloc.h> 37#include <sys/systm.h> 38#include <sys/mutex.h> 39#include <sys/condvar.h> 40 41#include <dev/sdmmc/sdhcreg.h> 42#include <dev/sdmmc/sdhcvar.h> 43#include <dev/sdmmc/sdmmcchip.h> 44#include <dev/sdmmc/sdmmcreg.h> 45#include <dev/sdmmc/sdmmcvar.h> 46 47#ifdef SDHC_DEBUG 48int sdhcdebug = 1; 49#define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0) 50void sdhc_dump_regs(struct sdhc_host *); 51#else 52#define DPRINTF(n,s) do {} while (0) 53#endif 54 55#define SDHC_COMMAND_TIMEOUT hz 56#define SDHC_BUFFER_TIMEOUT hz 57#define SDHC_TRANSFER_TIMEOUT hz 58#define SDHC_DMA_TIMEOUT hz 59 60struct sdhc_host { 61 struct sdhc_softc *sc; /* host controller device */ 62 63 bus_space_tag_t iot; /* host register set tag */ 64 bus_space_handle_t ioh; /* host register set handle */ 65 bus_dma_tag_t dmat; /* host DMA tag */ 66 67 device_t sdmmc; /* generic SD/MMC device */ 68 69 struct kmutex host_mtx; 70 71 u_int clkbase; /* base clock frequency in KHz */ 72 int maxblklen; /* maximum block length */ 73 uint32_t ocr; /* OCR value from capabilities */ 74 75 uint8_t regs[14]; /* host controller state */ 76 77 uint16_t intr_status; /* soft interrupt status */ 78 uint16_t intr_error_status; /* soft error status */ 79 struct kmutex intr_mtx; 80 struct kcondvar intr_cv; 81 82 int specver; /* spec. version */ 83 84 uint32_t flags; /* flags for this host */ 85#define SHF_USE_DMA 0x0001 86#define SHF_USE_4BIT_MODE 0x0002 87#define SHF_USE_8BIT_MODE 0x0004 88}; 89 90#define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev)) 91 92static uint8_t 93hread1(struct sdhc_host *hp, bus_size_t reg) 94{ 95 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 96 return bus_space_read_1(hp->iot, hp->ioh, reg); 97 98 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3)); 99} 100 101static uint16_t 102hread2(struct sdhc_host *hp, bus_size_t reg) 103{ 104 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) 105 return bus_space_read_2(hp->iot, hp->ioh, reg); 106 107 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2)); 108} 109 110#define HREAD1(hp, reg) hread1(hp, reg) 111#define HREAD2(hp, reg) hread2(hp, reg) 112#define HREAD4(hp, reg) \ 113 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))) 114 115 116static void 117hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val) 118{ 119 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 120 bus_space_write_1(hp->iot, hp->ioh, o, val); 121 } else { 122 const size_t shift = 8 * (o & 3); 123 o &= -4; 124 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 125 tmp = (val << shift) | (tmp & ~(0xff << shift)); 126 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 127 } 128} 129 130static void 131hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val) 132{ 133 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 134 bus_space_write_2(hp->iot, hp->ioh, o, val); 135 } else { 136 const size_t shift = 8 * (o & 2); 137 o &= -4; 138 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o); 139 tmp = (val << shift) | (tmp & ~(0xffff << shift)); 140 bus_space_write_4(hp->iot, hp->ioh, o, tmp); 141 } 142} 143 144#define HWRITE1(hp, reg, val) hwrite1(hp, reg, val) 145#define HWRITE2(hp, reg, val) hwrite2(hp, reg, val) 146#define HWRITE4(hp, reg, val) \ 147 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val)) 148 149#define HCLR1(hp, reg, bits) \ 150 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0) 151#define HCLR2(hp, reg, bits) \ 152 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0) 153#define HCLR4(hp, reg, bits) \ 154 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0) 155#define HSET1(hp, reg, bits) \ 156 do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0) 157#define HSET2(hp, reg, bits) \ 158 do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0) 159#define HSET4(hp, reg, bits) \ 160 do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0) 161 162static int sdhc_host_reset(sdmmc_chipset_handle_t); 163static int sdhc_host_reset1(sdmmc_chipset_handle_t); 164static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t); 165static int sdhc_host_maxblklen(sdmmc_chipset_handle_t); 166static int sdhc_card_detect(sdmmc_chipset_handle_t); 167static int sdhc_write_protect(sdmmc_chipset_handle_t); 168static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t); 169static int sdhc_bus_clock(sdmmc_chipset_handle_t, int); 170static int sdhc_bus_width(sdmmc_chipset_handle_t, int); 171static int sdhc_bus_rod(sdmmc_chipset_handle_t, int); 172static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int); 173static void sdhc_card_intr_ack(sdmmc_chipset_handle_t); 174static void sdhc_exec_command(sdmmc_chipset_handle_t, 175 struct sdmmc_command *); 176static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *); 177static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t); 178static int sdhc_soft_reset(struct sdhc_host *, int); 179static int sdhc_wait_intr(struct sdhc_host *, int, int); 180static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *); 181static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *); 182static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *); 183static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 184static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 185static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int); 186static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int); 187 188 189static struct sdmmc_chip_functions sdhc_functions = { 190 /* host controller reset */ 191 sdhc_host_reset, 192 193 /* host controller capabilities */ 194 sdhc_host_ocr, 195 sdhc_host_maxblklen, 196 197 /* card detection */ 198 sdhc_card_detect, 199 200 /* write protect */ 201 sdhc_write_protect, 202 203 /* bus power, clock frequency and width */ 204 sdhc_bus_power, 205 sdhc_bus_clock, 206 sdhc_bus_width, 207 sdhc_bus_rod, 208 209 /* command execution */ 210 sdhc_exec_command, 211 212 /* card interrupt */ 213 sdhc_card_enable_intr, 214 sdhc_card_intr_ack 215}; 216 217/* 218 * Called by attachment driver. For each SD card slot there is one SD 219 * host controller standard register set. (1.3) 220 */ 221int 222sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, 223 bus_space_handle_t ioh, bus_size_t iosize) 224{ 225 struct sdmmcbus_attach_args saa; 226 struct sdhc_host *hp; 227 uint32_t caps; 228 uint16_t sdhcver; 229 230 /* Allocate one more host structure. */ 231 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO); 232 if (hp == NULL) { 233 aprint_error_dev(sc->sc_dev, 234 "couldn't alloc memory (sdhc host)\n"); 235 goto err1; 236 } 237 sc->sc_host[sc->sc_nhosts++] = hp; 238 239 /* Fill in the new host structure. */ 240 hp->sc = sc; 241 hp->iot = iot; 242 hp->ioh = ioh; 243 hp->dmat = sc->sc_dmat; 244 245 mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC); 246 mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC); 247 cv_init(&hp->intr_cv, "sdhcintr"); 248 249 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION); 250 aprint_normal_dev(sc->sc_dev, "SD Host Specification "); 251 hp->specver = SDHC_SPEC_VERSION(sdhcver); 252 switch (SDHC_SPEC_VERSION(sdhcver)) { 253 case SDHC_SPEC_VERS_100: 254 aprint_normal("1.0"); 255 break; 256 257 case SDHC_SPEC_VERS_200: 258 aprint_normal("2.0"); 259 break; 260 261 case SDHC_SPEC_VERS_300: 262 aprint_normal("3.0"); 263 break; 264 265 default: 266 aprint_normal("unknown version(0x%x)", 267 SDHC_SPEC_VERSION(sdhcver)); 268 break; 269 } 270 aprint_normal(", rev.%u\n", SDHC_VENDOR_VERSION(sdhcver)); 271 272 /* 273 * Reset the host controller and enable interrupts. 274 */ 275 (void)sdhc_host_reset(hp); 276 277 /* Determine host capabilities. */ 278 if (ISSET(sc->sc_flags, SDHC_FLAG_HOSTCAPS)) { 279 caps = sc->sc_caps; 280 } else { 281 mutex_enter(&hp->host_mtx); 282 caps = HREAD4(hp, SDHC_CAPABILITIES); 283 mutex_exit(&hp->host_mtx); 284 } 285 286#if notyet 287 /* Use DMA if the host system and the controller support it. */ 288 if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA) 289 || ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA) 290 && ISSET(caps, SDHC_DMA_SUPPORT)))) { 291 SET(hp->flags, SHF_USE_DMA); 292 aprint_normal_dev(sc->sc_dev, "using DMA transfer\n"); 293 } 294#endif 295 296 /* 297 * Determine the base clock frequency. (2.2.24) 298 */ 299 if (hp->specver == SDHC_SPEC_VERS_300) { 300 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps); 301 } else { 302 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps); 303 } 304 if (hp->clkbase == 0) { 305 if (sc->sc_clkbase == 0) { 306 /* The attachment driver must tell us. */ 307 aprint_error_dev(sc->sc_dev,"unknown base clock frequency\n"); 308 goto err; 309 } 310 hp->clkbase = sc->sc_clkbase; 311 } 312 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) { 313 /* SDHC 1.0 supports only 10-63 MHz. */ 314 aprint_error_dev(sc->sc_dev, 315 "base clock frequency out of range: %u MHz\n", 316 hp->clkbase / 1000); 317 goto err; 318 } 319 DPRINTF(1,("%s: base clock frequency %u MHz\n", 320 device_xname(sc->sc_dev), hp->clkbase / 1000)); 321 322 /* 323 * XXX Set the data timeout counter value according to 324 * capabilities. (2.2.15) 325 */ 326 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 327#if 0 328 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 329 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 330#endif 331 332 /* 333 * Determine SD bus voltage levels supported by the controller. 334 */ 335 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)) { 336 SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V); 337 } 338 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)) { 339 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V); 340 } 341 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)) { 342 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V); 343 } 344 345 /* 346 * Determine the maximum block length supported by the host 347 * controller. (2.2.24) 348 */ 349 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) { 350 case SDHC_MAX_BLK_LEN_512: 351 hp->maxblklen = 512; 352 break; 353 354 case SDHC_MAX_BLK_LEN_1024: 355 hp->maxblklen = 1024; 356 break; 357 358 case SDHC_MAX_BLK_LEN_2048: 359 hp->maxblklen = 2048; 360 break; 361 362 case SDHC_MAX_BLK_LEN_4096: 363 hp->maxblklen = 4096; 364 break; 365 366 default: 367 aprint_error_dev(sc->sc_dev, "max block length unknown\n"); 368 goto err; 369 } 370 DPRINTF(1, ("%s: max block length %u byte%s\n", 371 device_xname(sc->sc_dev), hp->maxblklen, 372 hp->maxblklen > 1 ? "s" : "")); 373 374 /* 375 * Attach the generic SD/MMC bus driver. (The bus driver must 376 * not invoke any chipset functions before it is attached.) 377 */ 378 memset(&saa, 0, sizeof(saa)); 379 saa.saa_busname = "sdmmc"; 380 saa.saa_sct = &sdhc_functions; 381 saa.saa_sch = hp; 382 saa.saa_dmat = hp->dmat; 383 saa.saa_clkmax = hp->clkbase; 384 if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_CGM)) 385 saa.saa_clkmin = hp->clkbase / 256 / 2046; 386 else if (ISSET(sc->sc_flags, SDHC_FLAG_HAVE_DVS)) 387 saa.saa_clkmin = hp->clkbase / 256 / 16; 388 else if (hp->specver == SDHC_SPEC_VERS_300) 389 saa.saa_clkmin = hp->clkbase / 0x3ff; 390 else 391 saa.saa_clkmin = hp->clkbase / 256; 392 393 saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP; 394 if (ISSET(sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 395 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 396 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)) 397 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 398#if notyet 399 if (ISSET(hp->flags, SHF_USE_DMA)) 400 saa.saa_caps |= SMC_CAPS_DMA; 401#endif 402 hp->sdmmc = config_found(sc->sc_dev, &saa, NULL); 403 404 return 0; 405 406err: 407 cv_destroy(&hp->intr_cv); 408 mutex_destroy(&hp->intr_mtx); 409 mutex_destroy(&hp->host_mtx); 410 free(hp, M_DEVBUF); 411 sc->sc_host[--sc->sc_nhosts] = NULL; 412err1: 413 return 1; 414} 415 416int 417sdhc_detach(device_t dev, int flags) 418{ 419 struct sdhc_host *hp = (struct sdhc_host *)dev; 420 struct sdhc_softc *sc = hp->sc; 421 int rv = 0; 422 423 if (hp->sdmmc) 424 rv = config_detach(hp->sdmmc, flags); 425 426 cv_destroy(&hp->intr_cv); 427 mutex_destroy(&hp->intr_mtx); 428 mutex_destroy(&hp->host_mtx); 429 free(hp, M_DEVBUF); 430 sc->sc_host[--sc->sc_nhosts] = NULL; 431 432 return rv; 433} 434 435bool 436sdhc_suspend(device_t dev, const pmf_qual_t *qual) 437{ 438 struct sdhc_softc *sc = device_private(dev); 439 struct sdhc_host *hp; 440 441 /* XXX poll for command completion or suspend command 442 * in progress */ 443 444 /* Save the host controller state. */ 445 for (size_t n = 0; n < sc->sc_nhosts; n++) { 446 hp = sc->sc_host[n]; 447 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 448 for (size_t i = 0; i < sizeof hp->regs; i += 4) { 449 uint32_t v = HREAD4(hp, i); 450 hp->regs[i + 0] = (v >> 0); 451 hp->regs[i + 1] = (v >> 8); 452 if (i + 3 < sizeof hp->regs) { 453 hp->regs[i + 2] = (v >> 16); 454 hp->regs[i + 3] = (v >> 24); 455 } 456 } 457 } else { 458 for (size_t i = 0; i < sizeof hp->regs; i++) { 459 hp->regs[i] = HREAD1(hp, i); 460 } 461 } 462 } 463 return true; 464} 465 466bool 467sdhc_resume(device_t dev, const pmf_qual_t *qual) 468{ 469 struct sdhc_softc *sc = device_private(dev); 470 struct sdhc_host *hp; 471 472 /* Restore the host controller state. */ 473 for (size_t n = 0; n < sc->sc_nhosts; n++) { 474 hp = sc->sc_host[n]; 475 (void)sdhc_host_reset(hp); 476 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 477 for (size_t i = 0; i < sizeof hp->regs; i += 4) { 478 if (i + 3 < sizeof hp->regs) { 479 HWRITE4(hp, i, 480 (hp->regs[i + 0] << 0) 481 | (hp->regs[i + 1] << 8) 482 | (hp->regs[i + 2] << 16) 483 | (hp->regs[i + 3] << 24)); 484 } else { 485 HWRITE4(hp, i, 486 (hp->regs[i + 0] << 0) 487 | (hp->regs[i + 1] << 8)); 488 } 489 } 490 } else { 491 for (size_t i = 0; i < sizeof hp->regs; i++) { 492 HWRITE1(hp, i, hp->regs[i]); 493 } 494 } 495 } 496 return true; 497} 498 499bool 500sdhc_shutdown(device_t dev, int flags) 501{ 502 struct sdhc_softc *sc = device_private(dev); 503 struct sdhc_host *hp; 504 505 /* XXX chip locks up if we don't disable it before reboot. */ 506 for (size_t i = 0; i < sc->sc_nhosts; i++) { 507 hp = sc->sc_host[i]; 508 (void)sdhc_host_reset(hp); 509 } 510 return true; 511} 512 513/* 514 * Reset the host controller. Called during initialization, when 515 * cards are removed, upon resume, and during error recovery. 516 */ 517static int 518sdhc_host_reset1(sdmmc_chipset_handle_t sch) 519{ 520 struct sdhc_host *hp = (struct sdhc_host *)sch; 521 uint32_t sdhcimask; 522 int error; 523 524 /* Don't lock. */ 525 526 /* Disable all interrupts. */ 527 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 528 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0); 529 } else { 530 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0); 531 } 532 533 /* 534 * Reset the entire host controller and wait up to 100ms for 535 * the controller to clear the reset bit. 536 */ 537 error = sdhc_soft_reset(hp, SDHC_RESET_ALL); 538 if (error) 539 goto out; 540 541 /* Set data timeout counter value to max for now. */ 542 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); 543#if 0 544 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 545 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16); 546#endif 547 548 /* Enable interrupts. */ 549 sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION | 550 SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY | 551 SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT | 552 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE; 553 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 554 sdhcimask |= SDHC_EINTR_STATUS_MASK << 16; 555 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 556 sdhcimask ^= 557 (SDHC_EINTR_STATUS_MASK ^ SDHC_EINTR_SIGNAL_MASK) << 16; 558 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 559 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 560 } else { 561 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask); 562 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK); 563 sdhcimask ^= SDHC_BUFFER_READ_READY ^ SDHC_BUFFER_WRITE_READY; 564 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask); 565 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK); 566 } 567 568out: 569 return error; 570} 571 572static int 573sdhc_host_reset(sdmmc_chipset_handle_t sch) 574{ 575 struct sdhc_host *hp = (struct sdhc_host *)sch; 576 int error; 577 578 mutex_enter(&hp->host_mtx); 579 error = sdhc_host_reset1(sch); 580 mutex_exit(&hp->host_mtx); 581 582 return error; 583} 584 585static uint32_t 586sdhc_host_ocr(sdmmc_chipset_handle_t sch) 587{ 588 struct sdhc_host *hp = (struct sdhc_host *)sch; 589 590 return hp->ocr; 591} 592 593static int 594sdhc_host_maxblklen(sdmmc_chipset_handle_t sch) 595{ 596 struct sdhc_host *hp = (struct sdhc_host *)sch; 597 598 return hp->maxblklen; 599} 600 601/* 602 * Return non-zero if the card is currently inserted. 603 */ 604static int 605sdhc_card_detect(sdmmc_chipset_handle_t sch) 606{ 607 struct sdhc_host *hp = (struct sdhc_host *)sch; 608 int r; 609 610 mutex_enter(&hp->host_mtx); 611 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); 612 mutex_exit(&hp->host_mtx); 613 614 return r ? 1 : 0; 615} 616 617/* 618 * Return non-zero if the card is currently write-protected. 619 */ 620static int 621sdhc_write_protect(sdmmc_chipset_handle_t sch) 622{ 623 struct sdhc_host *hp = (struct sdhc_host *)sch; 624 int r; 625 626 mutex_enter(&hp->host_mtx); 627 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); 628 mutex_exit(&hp->host_mtx); 629 630 if (!r) 631 return 1; 632 return 0; 633} 634 635/* 636 * Set or change SD bus voltage and enable or disable SD bus power. 637 * Return zero on success. 638 */ 639static int 640sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 641{ 642 struct sdhc_host *hp = (struct sdhc_host *)sch; 643 uint8_t vdd; 644 int error = 0; 645 646 mutex_enter(&hp->host_mtx); 647 648 /* 649 * Disable bus power before voltage change. 650 */ 651 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS) 652 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) 653 HWRITE1(hp, SDHC_POWER_CTL, 0); 654 655 /* If power is disabled, reset the host and return now. */ 656 if (ocr == 0) { 657 (void)sdhc_host_reset1(hp); 658 goto out; 659 } 660 661 /* 662 * Select the lowest voltage according to capabilities. 663 */ 664 ocr &= hp->ocr; 665 if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V)) { 666 vdd = SDHC_VOLTAGE_1_8V; 667 } else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)) { 668 vdd = SDHC_VOLTAGE_3_0V; 669 } else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)) { 670 vdd = SDHC_VOLTAGE_3_3V; 671 } else { 672 /* Unsupported voltage level requested. */ 673 error = EINVAL; 674 goto out; 675 } 676 677 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 678 /* 679 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus 680 * voltage ramp until power rises. 681 */ 682 HWRITE1(hp, SDHC_POWER_CTL, 683 (vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER); 684 sdmmc_delay(10000); 685 686 /* 687 * The host system may not power the bus due to battery low, 688 * etc. In that case, the host controller should clear the 689 * bus power bit. 690 */ 691 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) { 692 error = ENXIO; 693 goto out; 694 } 695 } 696 697out: 698 mutex_exit(&hp->host_mtx); 699 700 return error; 701} 702 703/* 704 * Return the smallest possible base clock frequency divisor value 705 * for the CLOCK_CTL register to produce `freq' (KHz). 706 */ 707static bool 708sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp) 709{ 710 u_int div; 711 712 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) { 713 for (div = hp->clkbase / freq; div <= 0x3ff; div++) { 714 if ((hp->clkbase / div) <= freq) { 715 *divp = SDHC_SDCLK_CGM 716 | ((div & 0x300) << SDHC_SDCLK_XDIV_SHIFT) 717 | ((div & 0x0ff) << SDHC_SDCLK_DIV_SHIFT); 718 return true; 719 } 720 } 721 /* No divisor found. */ 722 return false; 723 } 724 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) { 725 u_int dvs = (hp->clkbase + freq - 1) / freq; 726 u_int roundup = dvs & 1; 727 for (dvs >>= 1, div = 1; div <= 256; div <<= 1, dvs >>= 1) { 728 if (dvs + roundup <= 16) { 729 dvs += roundup - 1; 730 *divp = (div << SDHC_SDCLK_DIV_SHIFT) 731 | (dvs << SDHC_SDCLK_DVS_SHIFT); 732 DPRINTF(2, 733 ("%s: divisor for freq %u is %u * %u\n", 734 HDEVNAME(hp), freq, div * 2, dvs + 1)); 735 return true; 736 } 737 /* 738 * If we drop bits, we need to round up the divisor. 739 */ 740 roundup |= dvs & 1; 741 } 742 /* No divisor found. */ 743 return false; 744 } 745 if (hp->specver == SDHC_SPEC_VERS_300) { 746 div = howmany(hp->clkbase, freq); 747 if (div > 0x3ff) 748 return false; 749 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK) 750 << SDHC_SDCLK_XDIV_SHIFT) | 751 (((div >> 0) & SDHC_SDCLK_DIV_MASK) 752 << SDHC_SDCLK_DIV_SHIFT); 753 return true; 754 } else { 755 for (div = 1; div <= 256; div *= 2) { 756 if ((hp->clkbase / div) <= freq) { 757 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT; 758 //freq = hp->clkbase / div; 759 return true; 760 } 761 } 762 /* No divisor found. */ 763 return false; 764 } 765 /* No divisor found. */ 766 return false; 767} 768 769/* 770 * Set or change SDCLK frequency or disable the SD clock. 771 * Return zero on success. 772 */ 773static int 774sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 775{ 776 struct sdhc_host *hp = (struct sdhc_host *)sch; 777 u_int div; 778 u_int timo; 779 int error = 0; 780#ifdef DIAGNOSTIC 781 bool ispresent; 782#endif 783 784#ifdef DIAGNOSTIC 785 mutex_enter(&hp->host_mtx); 786 ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK); 787 mutex_exit(&hp->host_mtx); 788 789 /* Must not stop the clock if commands are in progress. */ 790 if (ispresent && sdhc_card_detect(hp)) 791 printf("%s: sdhc_sdclk_frequency_select: command in progress\n", 792 device_xname(hp->sc->sc_dev)); 793#endif 794 795 mutex_enter(&hp->host_mtx); 796 797 /* 798 * Stop SD clock before changing the frequency. 799 */ 800 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 801 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8); 802 if (freq == SDMMC_SDCLK_OFF) { 803 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0); 804 goto out; 805 } 806 } else { 807 HWRITE2(hp, SDHC_CLOCK_CTL, 0); 808 if (freq == SDMMC_SDCLK_OFF) 809 goto out; 810 } 811 812 /* 813 * Set the minimum base clock frequency divisor. 814 */ 815 if (!sdhc_clock_divisor(hp, freq, &div)) { 816 /* Invalid base clock frequency or `freq' value. */ 817 error = EINVAL; 818 goto out; 819 } 820 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 821 HWRITE4(hp, SDHC_CLOCK_CTL, 822 div | (SDHC_TIMEOUT_MAX << 16)); 823 } else { 824 HWRITE2(hp, SDHC_CLOCK_CTL, div); 825 } 826 827 /* 828 * Start internal clock. Wait 10ms for stabilization. 829 */ 830 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 831 sdmmc_delay(10000); 832 HSET4(hp, SDHC_CLOCK_CTL, 8|SDHC_INTCLK_ENABLE|SDHC_INTCLK_STABLE); 833 } else { 834 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE); 835 for (timo = 1000; timo > 0; timo--) { 836 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)) 837 break; 838 sdmmc_delay(10); 839 } 840 if (timo == 0) { 841 error = ETIMEDOUT; 842 goto out; 843 } 844 } 845 846 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 847 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE); 848 /* 849 * Sending 80 clocks at 400kHz takes 200us. 850 * So delay for that time + slop and then 851 * check a few times for completion. 852 */ 853 sdmmc_delay(210); 854 for (timo = 10; timo > 0; timo--) { 855 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), 856 SDHC_INIT_ACTIVE)) 857 break; 858 sdmmc_delay(10); 859 } 860 DPRINTF(2,("%s: %u init spins\n", __func__, 10 - timo)); 861 /* 862 * Enable SD clock. 863 */ 864 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 865 } else { 866 /* 867 * Enable SD clock. 868 */ 869 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE); 870 871 if (freq > 25000 && 872 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT)) 873 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 874 else 875 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED); 876 } 877 878out: 879 mutex_exit(&hp->host_mtx); 880 881 return error; 882} 883 884static int 885sdhc_bus_width(sdmmc_chipset_handle_t sch, int width) 886{ 887 struct sdhc_host *hp = (struct sdhc_host *)sch; 888 int reg; 889 890 switch (width) { 891 case 1: 892 case 4: 893 break; 894 895 case 8: 896 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE)) 897 break; 898 /* FALLTHROUGH */ 899 default: 900 DPRINTF(0,("%s: unsupported bus width (%d)\n", 901 HDEVNAME(hp), width)); 902 return 1; 903 } 904 905 mutex_enter(&hp->host_mtx); 906 reg = HREAD1(hp, SDHC_HOST_CTL); 907 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 908 reg &= ~(SDHC_4BIT_MODE|SDHC_8BIT_MODE); 909 if (width == 4) 910 reg |= SDHC_4BIT_MODE; 911 else if (width == 8) 912 reg |= SDHC_8BIT_MODE; 913 } else { 914 reg &= ~SDHC_4BIT_MODE; 915 if (width == 4) 916 reg |= SDHC_4BIT_MODE; 917 } 918 HWRITE1(hp, SDHC_HOST_CTL, reg); 919 mutex_exit(&hp->host_mtx); 920 921 return 0; 922} 923 924static int 925sdhc_bus_rod(sdmmc_chipset_handle_t sch, int on) 926{ 927 928 /* Nothing ?? */ 929 return 0; 930} 931 932static void 933sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 934{ 935 struct sdhc_host *hp = (struct sdhc_host *)sch; 936 937 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 938 mutex_enter(&hp->host_mtx); 939 if (enable) { 940 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 941 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 942 } else { 943 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT); 944 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 945 } 946 mutex_exit(&hp->host_mtx); 947 } 948} 949 950static void 951sdhc_card_intr_ack(sdmmc_chipset_handle_t sch) 952{ 953 struct sdhc_host *hp = (struct sdhc_host *)sch; 954 955 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 956 mutex_enter(&hp->host_mtx); 957 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 958 mutex_exit(&hp->host_mtx); 959 } 960} 961 962static int 963sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value) 964{ 965 uint32_t state; 966 int timeout; 967 968 for (timeout = 10; timeout > 0; timeout--) { 969 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value) 970 return 0; 971 sdmmc_delay(10000); 972 } 973 DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp), 974 value, state)); 975 return ETIMEDOUT; 976} 977 978static void 979sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 980{ 981 struct sdhc_host *hp = (struct sdhc_host *)sch; 982 int error; 983 984#if 0 985 if (cmd->c_data) { 986 const uint16_t ready = SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY; 987 if (ISSET(hp->flags, SHF_USE_DMA)) { 988 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready); 989 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready); 990 } else { 991 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready); 992 HSET2(hp, SDHC_NINTR_STATUS_EN, ready); 993 } 994 } 995#endif 996 997 /* 998 * Start the MMC command, or mark `cmd' as failed and return. 999 */ 1000 error = sdhc_start_command(hp, cmd); 1001 if (error) { 1002 cmd->c_error = error; 1003 goto out; 1004 } 1005 1006 /* 1007 * Wait until the command phase is done, or until the command 1008 * is marked done for any other reason. 1009 */ 1010 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) { 1011 cmd->c_error = ETIMEDOUT; 1012 goto out; 1013 } 1014 1015 /* 1016 * The host controller removes bits [0:7] from the response 1017 * data (CRC) and we pass the data up unchanged to the bus 1018 * driver (without padding). 1019 */ 1020 mutex_enter(&hp->host_mtx); 1021 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1022 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0); 1023 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1024 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4); 1025 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8); 1026 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12); 1027 } 1028 } 1029 mutex_exit(&hp->host_mtx); 1030 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0])); 1031 1032 /* 1033 * If the command has data to transfer in any direction, 1034 * execute the transfer now. 1035 */ 1036 if (cmd->c_error == 0 && cmd->c_data != NULL) 1037 sdhc_transfer_data(hp, cmd); 1038 1039out: 1040#if 0 1041 if (cmd->c_dmamap != NULL && cmd->c_error == 0 1042 && ISSET(hp->flags, SHF_USE_DMA) 1043 && ISSET(cmd->c_flags, SCF_CMD_READ) { 1044 if (((uintptr_t)cmd->c_data & PAGE_MASK) + cmd->c_datalen > PAGE_SIZE) { 1045 memcpy(cmd->c_data, 1046 (void *)hp->sc->dma_map->dm_segs[0].ds_addr, 1047 cmd->c_datalen); 1048 } 1049 bus_dmamap_unload(hp->sc->dt, hp->sc->dma_map); 1050 } 1051#endif 1052 1053 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED) 1054 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) { 1055 mutex_enter(&hp->host_mtx); 1056 /* Turn off the LED. */ 1057 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1058 mutex_exit(&hp->host_mtx); 1059 } 1060 SET(cmd->c_flags, SCF_ITSDONE); 1061 1062 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp), 1063 cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort", 1064 cmd->c_flags, cmd->c_error)); 1065} 1066 1067static int 1068sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) 1069{ 1070 struct sdhc_softc * const sc = hp->sc; 1071 uint16_t blksize = 0; 1072 uint16_t blkcount = 0; 1073 uint16_t mode; 1074 uint16_t command; 1075 int error; 1076 1077 DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x, status=%#x\n", 1078 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data, 1079 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS))); 1080 1081 /* 1082 * The maximum block length for commands should be the minimum 1083 * of the host buffer size and the card buffer size. (1.7.2) 1084 */ 1085 1086 /* Fragment the data into proper blocks. */ 1087 if (cmd->c_datalen > 0) { 1088 blksize = MIN(cmd->c_datalen, cmd->c_blklen); 1089 blkcount = cmd->c_datalen / blksize; 1090 if (cmd->c_datalen % blksize > 0) { 1091 /* XXX: Split this command. (1.7.4) */ 1092 aprint_error_dev(sc->sc_dev, 1093 "data not a multiple of %u bytes\n", blksize); 1094 return EINVAL; 1095 } 1096 } 1097 1098 /* Check limit imposed by 9-bit block count. (1.7.2) */ 1099 if (blkcount > SDHC_BLOCK_COUNT_MAX) { 1100 aprint_error_dev(sc->sc_dev, "too much data\n"); 1101 return EINVAL; 1102 } 1103 1104 /* Prepare transfer mode register value. (2.2.5) */ 1105 mode = 0; 1106 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1107 mode |= SDHC_READ_MODE; 1108 if (blkcount > 0) { 1109 mode |= SDHC_BLOCK_COUNT_ENABLE; 1110 if (blkcount > 1) { 1111 mode |= SDHC_MULTI_BLOCK_MODE; 1112 /* XXX only for memory commands? */ 1113 mode |= SDHC_AUTO_CMD12_ENABLE; 1114 } 1115 } 1116 if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) { 1117 if (cmd->c_dmamap->dm_nsegs == 1) { 1118 mode |= SDHC_DMA_ENABLE; 1119 } else { 1120 cmd->c_dmamap = NULL; 1121 } 1122 } 1123 1124 /* 1125 * Prepare command register value. (2.2.6) 1126 */ 1127 command = 1128 (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT; 1129 1130 if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 1131 command |= SDHC_CRC_CHECK_ENABLE; 1132 if (ISSET(cmd->c_flags, SCF_RSP_IDX)) 1133 command |= SDHC_INDEX_CHECK_ENABLE; 1134 if (cmd->c_data != NULL) 1135 command |= SDHC_DATA_PRESENT_SELECT; 1136 1137 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 1138 command |= SDHC_NO_RESPONSE; 1139 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 1140 command |= SDHC_RESP_LEN_136; 1141 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 1142 command |= SDHC_RESP_LEN_48_CHK_BUSY; 1143 else 1144 command |= SDHC_RESP_LEN_48; 1145 1146 /* Wait until command and data inhibit bits are clear. (1.5) */ 1147 error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0); 1148 if (error) 1149 return error; 1150 1151 DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n", 1152 HDEVNAME(hp), blksize, blkcount, mode, command)); 1153 1154 mutex_enter(&hp->host_mtx); 1155 1156 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1157 /* Alert the user not to remove the card. */ 1158 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON); 1159 } 1160 1161 /* Set DMA start address. */ 1162 if (ISSET(mode, SDHC_DMA_ENABLE)) 1163 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr); 1164 1165 /* 1166 * Start a CPU data transfer. Writing to the high order byte 1167 * of the SDHC_COMMAND register triggers the SD command. (1.5) 1168 */ 1169 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1170 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16)); 1171 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1172 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16)); 1173 } else { 1174 HWRITE2(hp, SDHC_TRANSFER_MODE, mode); 1175 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize); 1176 if (blkcount > 1) 1177 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount); 1178 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg); 1179 HWRITE2(hp, SDHC_COMMAND, command); 1180 } 1181 1182 mutex_exit(&hp->host_mtx); 1183 1184 return 0; 1185} 1186 1187static void 1188sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd) 1189{ 1190 int error; 1191 1192 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp), 1193 MMC_R1(cmd->c_resp), cmd->c_datalen)); 1194 1195#ifdef SDHC_DEBUG 1196 /* XXX I forgot why I wanted to know when this happens :-( */ 1197 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) && 1198 ISSET(MMC_R1(cmd->c_resp), 0xcb00)) { 1199 aprint_error_dev(hp->sc->sc_dev, 1200 "CMD52/53 error response flags %#x\n", 1201 MMC_R1(cmd->c_resp) & 0xff00); 1202 } 1203#endif 1204 1205 if (cmd->c_dmamap != NULL) 1206 error = sdhc_transfer_data_dma(hp, cmd); 1207 else 1208 error = sdhc_transfer_data_pio(hp, cmd); 1209 if (error) 1210 cmd->c_error = error; 1211 SET(cmd->c_flags, SCF_ITSDONE); 1212 1213 DPRINTF(1,("%s: data transfer done (error=%d)\n", 1214 HDEVNAME(hp), cmd->c_error)); 1215} 1216 1217static int 1218sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd) 1219{ 1220 bus_dmamap_t dmap = cmd->c_dmamap; 1221 uint16_t blklen = cmd->c_blklen; 1222 uint16_t blkcnt = cmd->c_datalen / blklen; 1223 uint16_t remain; 1224 int error = 0; 1225 1226 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT); 1227 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT); 1228 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1229 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1230 1231 for (;;) { 1232 if (!sdhc_wait_intr(hp, 1233 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE, 1234 SDHC_DMA_TIMEOUT)) { 1235 error = ETIMEDOUT; 1236 break; 1237 } 1238 1239 /* single block mode */ 1240 if (blkcnt == 1) 1241 break; 1242 1243 /* multi block mode */ 1244 remain = HREAD2(hp, SDHC_BLOCK_COUNT); 1245 if (remain == 0) 1246 break; 1247 1248 HWRITE4(hp, SDHC_DMA_ADDR, 1249 dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen); 1250 } 1251 1252#if 0 1253 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1254 SDHC_TRANSFER_TIMEOUT)) 1255 error = ETIMEDOUT; 1256#endif 1257 1258 return error; 1259} 1260 1261static int 1262sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd) 1263{ 1264 uint8_t *data = cmd->c_data; 1265 u_int len, datalen; 1266 u_int imask; 1267 u_int pmask; 1268 int error = 0; 1269 void (*pio_func)(struct sdhc_host *, uint8_t *, u_int); 1270 1271 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1272 imask = SDHC_BUFFER_READ_READY; 1273 pmask = SDHC_BUFFER_READ_ENABLE; 1274 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1275 pio_func = esdhc_read_data_pio; 1276 } else { 1277 pio_func = sdhc_read_data_pio; 1278 } 1279 } else { 1280 imask = SDHC_BUFFER_WRITE_READY; 1281 pmask = SDHC_BUFFER_WRITE_ENABLE; 1282 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1283 pio_func = esdhc_write_data_pio; 1284 } else { 1285 pio_func = sdhc_write_data_pio; 1286 } 1287 } 1288 datalen = cmd->c_datalen; 1289 1290 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask); 1291 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE); 1292 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE); 1293 1294 while (datalen > 0) { 1295 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), imask)) { 1296 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1297 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask); 1298 } else { 1299 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask); 1300 } 1301 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT)) { 1302 error = ETIMEDOUT; 1303 break; 1304 } 1305 1306 error = sdhc_wait_state(hp, pmask, pmask); 1307 if (error) 1308 break; 1309 } 1310 1311 len = MIN(datalen, cmd->c_blklen); 1312 (*pio_func)(hp, data, len); 1313 DPRINTF(2,("%s: pio data transfer %u @ %p\n", 1314 HDEVNAME(hp), len, data)); 1315 1316 data += len; 1317 datalen -= len; 1318 } 1319 1320 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, 1321 SDHC_TRANSFER_TIMEOUT)) 1322 error = ETIMEDOUT; 1323 1324 return error; 1325} 1326 1327static void 1328sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1329{ 1330 1331 if (((__uintptr_t)data & 3) == 0) { 1332 while (datalen > 3) { 1333 *(uint32_t *)data = HREAD4(hp, SDHC_DATA); 1334 data += 4; 1335 datalen -= 4; 1336 } 1337 if (datalen > 1) { 1338 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1339 data += 2; 1340 datalen -= 2; 1341 } 1342 if (datalen > 0) { 1343 *data = HREAD1(hp, SDHC_DATA); 1344 data += 1; 1345 datalen -= 1; 1346 } 1347 } else if (((__uintptr_t)data & 1) == 0) { 1348 while (datalen > 1) { 1349 *(uint16_t *)data = HREAD2(hp, SDHC_DATA); 1350 data += 2; 1351 datalen -= 2; 1352 } 1353 if (datalen > 0) { 1354 *data = HREAD1(hp, SDHC_DATA); 1355 data += 1; 1356 datalen -= 1; 1357 } 1358 } else { 1359 while (datalen > 0) { 1360 *data = HREAD1(hp, SDHC_DATA); 1361 data += 1; 1362 datalen -= 1; 1363 } 1364 } 1365} 1366 1367static void 1368sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1369{ 1370 1371 if (((__uintptr_t)data & 3) == 0) { 1372 while (datalen > 3) { 1373 HWRITE4(hp, SDHC_DATA, *(uint32_t *)data); 1374 data += 4; 1375 datalen -= 4; 1376 } 1377 if (datalen > 1) { 1378 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1379 data += 2; 1380 datalen -= 2; 1381 } 1382 if (datalen > 0) { 1383 HWRITE1(hp, SDHC_DATA, *data); 1384 data += 1; 1385 datalen -= 1; 1386 } 1387 } else if (((__uintptr_t)data & 1) == 0) { 1388 while (datalen > 1) { 1389 HWRITE2(hp, SDHC_DATA, *(uint16_t *)data); 1390 data += 2; 1391 datalen -= 2; 1392 } 1393 if (datalen > 0) { 1394 HWRITE1(hp, SDHC_DATA, *data); 1395 data += 1; 1396 datalen -= 1; 1397 } 1398 } else { 1399 while (datalen > 0) { 1400 HWRITE1(hp, SDHC_DATA, *data); 1401 data += 1; 1402 datalen -= 1; 1403 } 1404 } 1405} 1406 1407 1408static void 1409esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1410{ 1411 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1412 uint32_t v; 1413 1414 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK; 1415 size_t count = 0; 1416 1417 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1418 if (count == 0) { 1419 /* 1420 * If we've drained "watermark" words, we need to wait 1421 * a little bit so the read FIFO can refill. 1422 */ 1423 sdmmc_delay(10); 1424 count = watermark; 1425 } 1426 v = HREAD4(hp, SDHC_DATA); 1427 v = le32toh(v); 1428 *(uint32_t *)data = v; 1429 data += 4; 1430 datalen -= 4; 1431 status = HREAD2(hp, SDHC_NINTR_STATUS); 1432 count--; 1433 } 1434 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1435 if (count == 0) { 1436 sdmmc_delay(10); 1437 } 1438 v = HREAD4(hp, SDHC_DATA); 1439 v = le32toh(v); 1440 do { 1441 *data++ = v; 1442 v >>= 8; 1443 } while (--datalen > 0); 1444 } 1445} 1446 1447static void 1448esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen) 1449{ 1450 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS); 1451 uint32_t v; 1452 1453 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK; 1454 size_t count = watermark; 1455 1456 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1457 if (count == 0) { 1458 sdmmc_delay(10); 1459 count = watermark; 1460 } 1461 v = *(uint32_t *)data; 1462 v = htole32(v); 1463 HWRITE4(hp, SDHC_DATA, v); 1464 data += 4; 1465 datalen -= 4; 1466 status = HREAD2(hp, SDHC_NINTR_STATUS); 1467 count--; 1468 } 1469 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) { 1470 if (count == 0) { 1471 sdmmc_delay(10); 1472 } 1473 v = *(uint32_t *)data; 1474 v = htole32(v); 1475 HWRITE4(hp, SDHC_DATA, v); 1476 } 1477} 1478 1479/* Prepare for another command. */ 1480static int 1481sdhc_soft_reset(struct sdhc_host *hp, int mask) 1482{ 1483 int timo; 1484 1485 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask)); 1486 1487 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask); 1488 for (timo = 10; timo > 0; timo--) { 1489 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)) 1490 break; 1491 sdmmc_delay(10000); 1492 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1493 } 1494 if (timo == 0) { 1495 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp), 1496 HREAD1(hp, SDHC_SOFTWARE_RESET))); 1497 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0); 1498 return ETIMEDOUT; 1499 } 1500 1501 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1502 HWRITE4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP); 1503 } 1504 1505 return 0; 1506} 1507 1508static int 1509sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo) 1510{ 1511 int status; 1512 1513 mask |= SDHC_ERROR_INTERRUPT; 1514 1515 mutex_enter(&hp->intr_mtx); 1516 status = hp->intr_status & mask; 1517 while (status == 0) { 1518 if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo) 1519 == EWOULDBLOCK) { 1520 status |= SDHC_ERROR_INTERRUPT; 1521 break; 1522 } 1523 status = hp->intr_status & mask; 1524 } 1525 hp->intr_status &= ~status; 1526 1527 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status, 1528 hp->intr_error_status)); 1529 1530 /* Command timeout has higher priority than command complete. */ 1531 if (ISSET(status, SDHC_ERROR_INTERRUPT) || hp->intr_error_status) { 1532 hp->intr_error_status = 0; 1533 hp->intr_status &= ~SDHC_ERROR_INTERRUPT; 1534 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1535 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD); 1536 } 1537 status = 0; 1538 } 1539 mutex_exit(&hp->intr_mtx); 1540 1541 return status; 1542} 1543 1544/* 1545 * Established by attachment driver at interrupt priority IPL_SDMMC. 1546 */ 1547int 1548sdhc_intr(void *arg) 1549{ 1550 struct sdhc_softc *sc = (struct sdhc_softc *)arg; 1551 struct sdhc_host *hp; 1552 int done = 0; 1553 uint16_t status; 1554 uint16_t error; 1555 1556 /* We got an interrupt, but we don't know from which slot. */ 1557 for (size_t host = 0; host < sc->sc_nhosts; host++) { 1558 hp = sc->sc_host[host]; 1559 if (hp == NULL) 1560 continue; 1561 1562 if (ISSET(sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) { 1563 /* Find out which interrupts are pending. */ 1564 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS); 1565 status = xstatus; 1566 error = xstatus >> 16; 1567 if (error) 1568 xstatus |= SDHC_ERROR_INTERRUPT; 1569 else if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1570 continue; /* no interrupt for us */ 1571 /* Acknowledge the interrupts we are about to handle. */ 1572 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus); 1573 } else { 1574 /* Find out which interrupts are pending. */ 1575 error = 0; 1576 status = HREAD2(hp, SDHC_NINTR_STATUS); 1577 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)) 1578 continue; /* no interrupt for us */ 1579 /* Acknowledge the interrupts we are about to handle. */ 1580 HWRITE2(hp, SDHC_NINTR_STATUS, status); 1581 if (ISSET(status, SDHC_ERROR_INTERRUPT)) { 1582 /* Acknowledge error interrupts. */ 1583 error = HREAD2(hp, SDHC_EINTR_STATUS); 1584 HWRITE2(hp, SDHC_EINTR_STATUS, error); 1585 } 1586 } 1587 1588 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp), 1589 status, error)); 1590 1591 /* Claim this interrupt. */ 1592 done = 1; 1593 1594 /* 1595 * Service error interrupts. 1596 */ 1597 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR| 1598 SDHC_DATA_TIMEOUT_ERROR)) { 1599 hp->intr_error_status |= error; 1600 hp->intr_status |= status; 1601 cv_broadcast(&hp->intr_cv); 1602 } 1603 1604 /* 1605 * Wake up the sdmmc event thread to scan for cards. 1606 */ 1607 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)) { 1608 sdmmc_needs_discover(hp->sdmmc); 1609 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1610 HCLR4(hp, SDHC_NINTR_STATUS_EN, 1611 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1612 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1613 status & (SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)); 1614 } 1615 } 1616 1617 /* 1618 * Wake up the blocking process to service command 1619 * related interrupt(s). 1620 */ 1621 if (ISSET(status, SDHC_COMMAND_COMPLETE| 1622 SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY| 1623 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) { 1624 hp->intr_status |= status; 1625 if (ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED)) { 1626 HCLR4(hp, SDHC_NINTR_SIGNAL_EN, 1627 status & (SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY)); 1628 } 1629 cv_broadcast(&hp->intr_cv); 1630 } 1631 1632 /* 1633 * Service SD card interrupts. 1634 */ 1635 if (!ISSET(sc->sc_flags, SDHC_FLAG_ENHANCED) 1636 && ISSET(status, SDHC_CARD_INTERRUPT)) { 1637 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp))); 1638 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT); 1639 sdmmc_card_intr(hp->sdmmc); 1640 } 1641 } 1642 1643 return done; 1644} 1645 1646#ifdef SDHC_DEBUG 1647void 1648sdhc_dump_regs(struct sdhc_host *hp) 1649{ 1650 1651 printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE, 1652 HREAD4(hp, SDHC_PRESENT_STATE)); 1653 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) 1654 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL, 1655 HREAD1(hp, SDHC_POWER_CTL)); 1656 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS, 1657 HREAD2(hp, SDHC_NINTR_STATUS)); 1658 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS, 1659 HREAD2(hp, SDHC_EINTR_STATUS)); 1660 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN, 1661 HREAD2(hp, SDHC_NINTR_STATUS_EN)); 1662 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN, 1663 HREAD2(hp, SDHC_EINTR_STATUS_EN)); 1664 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN, 1665 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)); 1666 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN, 1667 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)); 1668 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES, 1669 HREAD4(hp, SDHC_CAPABILITIES)); 1670 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES, 1671 HREAD4(hp, SDHC_MAX_CAPABILITIES)); 1672} 1673#endif 1674