1/* $NetBSD: if_dereg.h,v 1.2.28.3 2004/09/21 13:32:38 skrll Exp $ */ 2 3/* 4 * Copyright (c) 1982, 1986 Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90 32 */ 33 34/* 35 * DEC DEUNA interface 36 */ 37#ifdef notdef 38struct dedevice { 39 union { 40 short p0_w; 41 char p0_b[2]; 42 } u_p0; 43#define pcsr0 u_p0.p0_w 44#define pclow u_p0.p0_b[0] 45#define pchigh u_p0.p0_b[1] 46 short pcsr1; 47 short pcsr2; 48 short pcsr3; 49}; 50#endif 51 52#define DE_PCSR0 0 53#define DE_PCSR1 2 54#define DE_PCSR2 4 55#define DE_PCSR3 6 56 57/* 58 * PCSR 0 bit descriptions 59 */ 60#define PCSR0_SERI 0x8000 /* Status error interrupt */ 61#define PCSR0_PCEI 0x4000 /* Port command error interrupt */ 62#define PCSR0_RXI 0x2000 /* Receive done interrupt */ 63#define PCSR0_TXI 0x1000 /* Transmit done interrupt */ 64#define PCSR0_DNI 0x0800 /* Done interrupt */ 65#define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */ 66#define PCSR0_FATI 0x0100 /* Fatal error interrupt */ 67#define PCSR0_INTR 0x0080 /* Interrupt summary */ 68#define PCSR0_INTE 0x0040 /* Interrupt enable */ 69#define PCSR0_RSET 0x0020 /* DEUNA reset */ 70#define PCSR0_CMASK 0x000f /* command mask */ 71 72#define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET" 73 74/* bits 0-3 are for the PORT_COMMAND */ 75#define CMD_NOOP 0x0 76#define CMD_GETPCBB 0x1 /* Get PCB Block */ 77#define CMD_GETCMD 0x2 /* Execute command in PCB */ 78#define CMD_STEST 0x3 /* Self test mode */ 79#define CMD_START 0x4 /* Reset xmit and receive ring ptrs */ 80#define CMD_BOOT 0x5 /* Boot DEUNA */ 81#define CMD_PDMD 0x8 /* Polling demand */ 82#define CMD_TMRO 0x9 /* Sanity timer on */ 83#define CMD_TMRF 0xa /* Sanity timer off */ 84#define CMD_RSTT 0xb /* Reset sanity timer */ 85#define CMD_STOP 0xf /* Suspend operation */ 86 87/* 88 * PCSR 1 bit descriptions 89 */ 90#define PCSR1_XPWR 0x8000 /* Transceiver power BAD */ 91#define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */ 92#define PCSR1_STCODE 0x3f00 /* Self test error code */ 93#define PCSR1_PCTO 0x0080 /* Port command timed out */ 94#define PCSR1_ILLINT 0x0040 /* Illegal interrupt */ 95#define PCSR1_TIMEOUT 0x0020 /* Timeout */ 96#define PCSR1_POWER 0x0010 /* Power fail */ 97#define PCSR1_RMTC 0x0008 /* Remote console reserved */ 98#define PCSR1_STMASK 0x0007 /* State */ 99 100/* bit 0-3 are for STATE */ 101#define STAT_RESET 0x0 102#define STAT_PRIMLD 0x1 /* Primary load */ 103#define STAT_READY 0x2 104#define STAT_RUN 0x3 105#define STAT_UHALT 0x5 /* UNIBUS halted */ 106#define STAT_NIHALT 0x6 /* NI halted */ 107#define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */ 108 109#define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC" 110 111/* 112 * Port Control Block Base 113 */ 114struct de_pcbb { 115 int16_t pcbb0; /* function */ 116 int16_t pcbb2; /* command specific */ 117 int16_t pcbb4; 118 int16_t pcbb6; 119}; 120 121/* PCBB function codes */ 122#define FC_NOOP 0x00 /* NO-OP */ 123#define FC_LSUADDR 0x01 /* Load and start microaddress */ 124#define FC_RDDEFAULT 0x02 /* Read default physical address */ 125#define FC_RDPHYAD 0x04 /* Read physical address */ 126#define FC_WTPHYAD 0x05 /* Write physical address */ 127#define FC_RDMULTI 0x06 /* Read multicast address list */ 128#define FC_WTMULTI 0x07 /* Read multicast address list */ 129#define FC_RDRING 0x08 /* Read ring format */ 130#define FC_WTRING 0x09 /* Write ring format */ 131#define FC_RDCNTS 0x0a /* Read counters */ 132#define FC_RCCNTS 0x0b /* Read and clear counters */ 133#define FC_RDMODE 0x0c /* Read mode */ 134#define FC_WTMODE 0x0d /* Write mode */ 135#define FC_RDSTATUS 0x0e /* Read port status */ 136#define FC_RCSTATUS 0x0f /* Read and clear port status */ 137#define FC_DUMPMEM 0x10 /* Dump internal memory */ 138#define FC_LOADMEM 0x11 /* Load internal memory */ 139#define FC_RDSYSID 0x12 /* Read system ID parameters */ 140#define FC_WTSYSID 0x13 /* Write system ID parameters */ 141#define FC_RDSERAD 0x14 /* Read load server address */ 142#define FC_WTSERAD 0x15 /* Write load server address */ 143 144/* 145 * Unibus Data Block Base (UDBB) for ring buffers 146 */ 147struct de_udbbuf { 148 int16_t b_tdrbl; /* Transmit desc ring base low 16 bits */ 149 int8_t b_tdrbh; /* Transmit desc ring base high 2 bits */ 150 int8_t b_telen; /* Length of each transmit entry */ 151 int16_t b_trlen; /* Number of entries in the XMIT desc ring */ 152 int16_t b_rdrbl; /* Receive desc ring base low 16 bits */ 153 int8_t b_rdrbh; /* Receive desc ring base high 2 bits */ 154 int8_t b_relen; /* Length of each receive entry */ 155 int16_t b_rrlen; /* Number of entries in the RECV desc ring */ 156}; 157 158/* 159 * Transmit/Receive Ring Entry 160 */ 161struct de_ring { 162 int16_t r_slen; /* Segment length */ 163 int16_t r_segbl; /* Segment address (low 16 bits) */ 164 int8_t r_segbh; /* Segment address (hi 2 bits) */ 165 u_int8_t r_flags; /* Status flags */ 166 u_int16_t r_tdrerr; /* Errors */ 167#define r_lenerr r_tdrerr 168}; 169 170#define XFLG_OWN 0x80 /* If 0 then owned by driver */ 171#define XFLG_ERRS 0x40 /* Error summary */ 172#define XFLG_MTCH 0x20 /* Address match on xmit request */ 173#define XFLG_MORE 0x10 /* More than one entry required */ 174#define XFLG_ONE 0x08 /* One collision encountered */ 175#define XFLG_DEF 0x04 /* Transmit deferred */ 176#define XFLG_STP 0x02 /* Start of packet */ 177#define XFLG_ENP 0x01 /* End of packet */ 178 179#define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP" 180 181#define XERR_BUFL 0x8000 /* Buffer length error */ 182#define XERR_UBTO 0x4000 /* UNIBUS tiemout */ 183#define XERR_LCOL 0x1000 /* Late collision */ 184#define XERR_LCAR 0x0800 /* Loss of carrier */ 185#define XERR_RTRY 0x0400 /* Failed after 16 retries */ 186#define XERR_TDR 0x03ff /* TDR value */ 187 188#define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY" 189 190#define RFLG_OWN 0x80 /* If 0 then owned by driver */ 191#define RFLG_ERRS 0x40 /* Error summary */ 192#define RFLG_FRAM 0x20 /* Framing error */ 193#define RFLG_OFLO 0x10 /* Message overflow */ 194#define RFLG_CRC 0x08 /* CRC error */ 195#define RFLG_STP 0x02 /* Start of packet */ 196#define RFLG_ENP 0x01 /* End of packet */ 197 198#define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP" 199 200#define RERR_BUFL 0x8000 /* Buffer length error */ 201#define RERR_UBTO 0x4000 /* UNIBUS tiemout */ 202#define RERR_NCHN 0x2000 /* No data chaining */ 203#define RERR_MLEN 0x0fff /* Message length */ 204 205#define RERR_BITS "\20\20BUFL\17UBTO\16NCHN" 206 207/* mode description bits */ 208#define MOD_HDX 0x0001 /* Half duplex mode */ 209#define MOD_LOOP 0x0004 /* Enable internal loopback */ 210#define MOD_DTCR 0x0008 /* Disables CRC generation */ 211#define MOD_DMNT 0x0200 /* Disable maintenance features */ 212#define MOD_ECT 0x0400 /* Enable collision test */ 213#define MOD_TPAD 0x1000 /* Transmit message pad enable */ 214#define MOD_DRDC 0x2000 /* Disable data chaining */ 215#define MOD_ENAL 0x4000 /* Enable all multicast */ 216#define MOD_PROM 0x8000 /* Enable promiscuous mode */ 217