1/* $NetBSD: pcscpreg.h,v 1.1 1999/01/06 23:23:33 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Izumi Tsutsui. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * Am53c974 DMA engine registers 34 */ 35 36#define DMA_CMD 0x40 /* Command */ 37#define DMACMD_RSVD 0xFFFFFF28 /* reserved */ 38#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */ 39#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */ 40#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */ 41#define DMACMD_DIAG 0x00000004 /* Diagnostic */ 42#define DMACMD_CMD 0x00000003 /* Command Code Bit */ 43#define DMACMD_IDLE 0x00000000 /* Idle */ 44#define DMACMD_BLAST 0x00000001 /* Blast */ 45#define DMACMD_ABORT 0x00000002 /* Abort */ 46#define DMACMD_START 0x00000003 /* Start */ 47 48#define DMA_STC 0x44 /* Start Transfer Count */ 49#define DMA_SPA 0x48 /* Start Physical Address */ 50#define DMA_WBC 0x4C /* Working Byte Counter */ 51#define DMA_WAC 0x50 /* Working Address Counter */ 52 53#define DMA_STAT 0x54 /* Status Register */ 54#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */ 55#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */ 56#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */ 57#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */ 58#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */ 59#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */ 60#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */ 61#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */ 62 63#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */ 64#define DMA_WMAC 0x5C /* Working MDL Counter */ 65#define DMA_SBAC 0x70 /* SCSI Bus and Control */ 66