1/* $NetBSD: pciide_pdc202xx_reg.h,v 1.14 2007/12/25 18:33:42 perry Exp $ */ 2 3/* 4 * Copyright (c) 1999 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28/* 29 * Registers definitions for PROMISE PDC20246/PDC20262 PCI IDE controller. 30 * Unfortunably the HW docs are not publically available. I've been able 31 * to get a partial one for the PDC20246, and a better one for the PDC20262 32 * from Promise. 33 */ 34 35#define PDC2xx_STATE 0x50 36#define PDC2xx_STATE_IDERAID 0x0001 37#define PDC2xx_STATE_NATIVE 0x0080 38/* controller initial state values(PDC20246 only) */ 39#define PDC246_STATE_SHIPID 0x8000 40#define PDC246_STATE_IOCHRDY 0x0400 41#define PDC246_STATE_LBA(channel) (0x0100 << (channel)) 42#define PDC246_STATE_ISAIRQ 0x0008 43#define PDC246_STATE_EN(channel) (0x0002 << (channel)) 44/* controller initial state values(PDC20262 only) */ 45#define PDC262_STATE_EN(chan) (0x1000 << (chan)) 46#define PDC262_STATE_80P(chan) (0x0400 << (chan)) 47 48/* per-drive timings */ 49#define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel)) 50#define PDC2xx_TIM_SET_PA(r, x) (((r) & 0xfffffff0) | ((x) & 0xf)) 51#define PDC2xx_TIM_SET_PB(r, x) (((r) & 0xffffe0ff) | (((x) & 0x1f) << 8)) 52#define PDC2xx_TIM_SET_MB(r, x) (((r) & 0xffff1fff) | (((x) & 0x7) << 13)) 53#define PDC2xx_TIM_SET_MC(r, x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 54#define PDC2xx_TIM_PRE 0x00000010 55#define PDC2xx_TIM_IORDY 0x00000020 56#define PDC2xx_TIM_ERRDY 0x00000040 57#define PDC2xx_TIM_SYNC 0x00000080 58#define PDC2xx_TIM_DMAW 0x00100000 59#define PDC2xx_TIM_DMAR 0x00200000 60#define PDC2xx_TIM_IORDYp 0x00400000 61#define PDC2xx_TIM_DMARQp 0x00800000 62 63/* The following are extensions of the DMA registers */ 64 65/* Ultra-DMA mode 3/4 control (PDC20262 only, 1 byte) */ 66#define PDC262_U66 0x11 67#define PDC262_U66_EN(chan) (0x2 << ((chan) *2)) 68/* primary mode (1 byte) */ 69#define PDC2xx_PM 0x1a 70/* secondary mode (1 byte) */ 71#define PDC2xx_SM 0x1b 72/* System control register (4 bytes) */ 73#define PDC2xx_SCR 0x1c 74#define PDC2xx_SCR_SET_GEN(r,x) (((r) & 0xffffff00) | ((x) & 0xff)) 75#define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel)) 76#define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel)) 77#define PDC2xx_SCR_INT(channel) (0x00000400 << (4 * channel)) 78#define PDC2xx_SCR_ERR(channel) (0x00000800 << (4 * channel)) 79#define PDC2xx_SCR_SET_I2C(r,x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 80#define PDC2xx_SCR_SET_POLL(r,x) (((r) & 0xff0fffff) | (((x) & 0xf) << 20)) 81#define PDC2xx_SCR_DMA 0x01000000 82#define PDC2xx_SCR_IORDY 0x02000000 83#define PDC2xx_SCR_G2FD 0x04000000 84#define PDC2xx_SCR_FLOAT 0x08000000 85#define PDC2xx_SCR_RSET 0x10000000 86#define PDC2xx_SCR_TST 0x20000000 87/* Values for "General Purpose Register" (PDC2026{2|5} only) */ 88#define PDC262_SCR_GEN_LAT 0x20 89#define PDC265_SCR_GEN_LAT 0x03 90 91/* ATAPI port ((PDC20262 only) (4 bytes) */ 92#define PDC262_ATAPI(chan) (0x20 + (4 * (chan))) 93#define PDC262_ATAPI_WC_MASK 0x00000fff 94#define PDC262_ATAPI_DMA_READ 0x00001000 95#define PDC262_ATAPI_DMA_WRITE 0x00002000 96#define PDC262_ATAPI_UDMA 0x00004000 97#define PDC262_ATAPI_LBA48_READ 0x05000000 98#define PDC262_ATAPI_LBA48_WRITE 0x06000000 99 100/* 101 * The timings provided here cmoes from the PDC20262 docs. I hope they are 102 * right for the PDC20246 too ... 103 */ 104 105static const int8_t pdc2xx_pa[] __unused = 106 {0x9, 0x5, 0x3, 0x2, 0x1}; 107static const int8_t pdc2xx_pb[] __unused = 108 {0x13, 0xc, 0x8, 0x6, 0x4}; 109static const int8_t pdc2xx_dma_mb[] __unused = 110 {0x3, 0x3, 0x3}; 111static const int8_t pdc2xx_dma_mc[] __unused = 112 {0x5, 0x4, 0x3}; 113static const int8_t pdc2xx_udma_mb[] __unused = 114 {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 115static const int8_t pdc2xx_udma_mc[] __unused = 116 {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 117