1/* $NetBSD: if_lii.c,v 1.9 2010/04/05 07:20:26 joerg Exp $ */ 2 3/* 4 * Copyright (c) 2008 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.9 2010/04/05 07:20:26 joerg Exp $"); 35 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/types.h> 40#include <sys/device.h> 41#include <sys/endian.h> 42#include <sys/kernel.h> 43#include <sys/sockio.h> 44 45#include <net/if.h> 46#include <net/if_media.h> 47#include <net/if_ether.h> 48 49#include <net/bpf.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pcidevs.h> 57 58#include <dev/pci/if_liireg.h> 59 60/* #define LII_DEBUG */ 61#ifdef LII_DEBUG 62#define DPRINTF(x) printf x 63#else 64#define DPRINTF(x) 65#endif 66 67struct lii_softc { 68 device_t sc_dev; 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_tag; 71 72 bus_space_tag_t sc_mmiot; 73 bus_space_handle_t sc_mmioh; 74 75 /* 76 * We allocate a big chunk of DMA-safe memory for all data exchanges. 77 * It is unfortunate that this chip doesn't seem to do scatter-gather. 78 */ 79 bus_dma_tag_t sc_dmat; 80 bus_dmamap_t sc_ringmap; 81 bus_dma_segment_t sc_ringseg; 82 83 uint8_t *sc_ring; /* the whole area */ 84 size_t sc_ringsize; 85 86 struct rx_pkt *sc_rxp; /* the part used for RX */ 87 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 88 bus_addr_t sc_txsp; 89 char *sc_txdbase; 90 bus_addr_t sc_txdp; 91 92 unsigned int sc_rxcur; 93 /* the active area is [ack; cur[ */ 94 int sc_txs_cur; 95 int sc_txs_ack; 96 int sc_txd_cur; 97 int sc_txd_ack; 98 bool sc_free_tx_slots; 99 100 void *sc_ih; 101 102 struct ethercom sc_ec; 103 struct mii_data sc_mii; 104 callout_t sc_tick_ch; 105 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 106 107 int (*sc_memread)(struct lii_softc *, uint32_t, 108 uint32_t *); 109}; 110 111static int lii_match(device_t, cfdata_t, void *); 112static void lii_attach(device_t, device_t, void *); 113 114static int lii_reset(struct lii_softc *); 115static bool lii_eeprom_present(struct lii_softc *); 116static int lii_read_macaddr(struct lii_softc *, uint8_t *); 117static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 118static void lii_spi_configure(struct lii_softc *); 119static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 120static void lii_setmulti(struct lii_softc *); 121static void lii_tick(void *); 122 123static int lii_alloc_rings(struct lii_softc *); 124static int lii_free_tx_space(struct lii_softc *); 125 126static int lii_mii_readreg(device_t, int, int); 127static void lii_mii_writereg(device_t, int, int, int); 128static void lii_mii_statchg(device_t); 129 130static int lii_media_change(struct ifnet *); 131static void lii_media_status(struct ifnet *, struct ifmediareq *); 132 133static int lii_init(struct ifnet *); 134static void lii_start(struct ifnet *); 135static void lii_stop(struct ifnet *, int); 136static void lii_watchdog(struct ifnet *); 137static int lii_ioctl(struct ifnet *, u_long, void *); 138 139static int lii_intr(void *); 140static void lii_rxintr(struct lii_softc *); 141static void lii_txintr(struct lii_softc *); 142 143CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc), 144 lii_match, lii_attach, NULL, NULL); 145 146/* #define LII_DEBUG_REGS */ 147#ifndef LII_DEBUG_REGS 148#define AT_READ_4(sc,reg) \ 149 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 150#define AT_READ_2(sc,reg) \ 151 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 152#define AT_READ_1(sc,reg) \ 153 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 154#define AT_WRITE_4(sc,reg,val) \ 155 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 156#define AT_WRITE_2(sc,reg,val) \ 157 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 158#define AT_WRITE_1(sc,reg,val) \ 159 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 160#else 161static inline uint32_t 162AT_READ_4(struct lii_softc *sc, bus_size_t reg) 163{ 164 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg); 165 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r); 166 return r; 167} 168 169static inline uint16_t 170AT_READ_2(struct lii_softc *sc, bus_size_t reg) 171{ 172 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg); 173 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r); 174 return r; 175} 176 177static inline uint8_t 178AT_READ_1(struct lii_softc *sc, bus_size_t reg) 179{ 180 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg); 181 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r); 182 return r; 183} 184 185static inline void 186AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val) 187{ 188 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val); 189 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val); 190} 191 192static inline void 193AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val) 194{ 195 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val); 196 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val); 197} 198 199static inline void 200AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val) 201{ 202 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val); 203 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val); 204} 205#endif 206 207/* 208 * Those are the default Linux parameters. 209 */ 210 211#define AT_TXD_NUM 64 212#define AT_TXD_BUFFER_SIZE 8192 213#define AT_RXD_NUM 64 214 215/* 216 * Assuming (you know what that word makes of you) the chunk of memory 217 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the 218 * first 120 bytes of it, so that the space for the packets, and not the 219 * whole descriptors themselves, are on a 128-byte boundary. 220 */ 221 222#define AT_RXD_PADDING 120 223 224static int 225lii_match(device_t parent, cfdata_t cfmatch, void *aux) 226{ 227 struct pci_attach_args *pa = aux; 228 229 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100); 231} 232 233static void 234lii_attach(device_t parent, device_t self, void *aux) 235{ 236 struct lii_softc *sc = device_private(self); 237 struct pci_attach_args *pa = aux; 238 uint8_t eaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp = &sc->sc_ec.ec_if; 240 pci_intr_handle_t ih; 241 const char *intrstr; 242 pcireg_t cmd; 243 bus_size_t memsize = 0; 244 245 aprint_naive("\n"); 246 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n"); 247 248 sc->sc_dev = self; 249 sc->sc_pc = pa->pa_pc; 250 sc->sc_tag = pa->pa_tag; 251 sc->sc_dmat = pa->pa_dmat; 252 253 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 254 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 255 cmd &= ~PCI_COMMAND_IO_ENABLE; 256 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd); 257 258 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) { 259 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 260 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 261 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 262 break; 263 default: 264 aprint_error_dev(self, "invalid base address register\n"); 265 break; 266 } 267 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0, 268 &sc->sc_mmiot, &sc->sc_mmioh, NULL, &memsize) != 0) { 269 aprint_error_dev(self, "failed to map registers\n"); 270 return; 271 } 272 273 if (lii_reset(sc)) 274 return; 275 276 lii_spi_configure(sc); 277 278 if (lii_eeprom_present(sc)) 279 sc->sc_memread = lii_eeprom_read; 280 else 281 sc->sc_memread = lii_spi_read; 282 283 if (lii_read_macaddr(sc, eaddr)) 284 return; 285 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN); 286 287 aprint_normal_dev(self, "Ethernet address %s\n", 288 ether_sprintf(eaddr)); 289 290 if (pci_intr_map(pa, &ih) != 0) { 291 aprint_error_dev(self, "failed to map interrupt\n"); 292 goto fail; 293 } 294 intrstr = pci_intr_string(sc->sc_pc, ih); 295 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, lii_intr, sc); 296 if (sc->sc_ih == NULL) { 297 aprint_error_dev(self, "failed to establish interrupt"); 298 if (intrstr != NULL) 299 aprint_error(" at %s", intrstr); 300 aprint_error("\n"); 301 goto fail; 302 } 303 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 304 305 if (lii_alloc_rings(sc)) 306 goto fail; 307 308 callout_init(&sc->sc_tick_ch, 0); 309 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc); 310 311 sc->sc_mii.mii_ifp = ifp; 312 sc->sc_mii.mii_readreg = lii_mii_readreg; 313 sc->sc_mii.mii_writereg = lii_mii_writereg; 314 sc->sc_mii.mii_statchg = lii_mii_statchg; 315 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 316 lii_media_status); 317 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1, 318 MII_OFFSET_ANY, 0); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 320 321 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 322 ifp->if_softc = sc; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = lii_ioctl; 325 ifp->if_start = lii_start; 326 ifp->if_watchdog = lii_watchdog; 327 ifp->if_init = lii_init; 328 ifp->if_stop = lii_stop; 329 IFQ_SET_READY(&ifp->if_snd); 330 331 /* 332 * While the device does support HW VLAN tagging, there is no 333 * real point using that feature. 334 */ 335 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 336 337 if_attach(ifp); 338 ether_ifattach(ifp, eaddr); 339 340 if (pmf_device_register(self, NULL, NULL)) 341 pmf_class_network_register(self, ifp); 342 else 343 aprint_error_dev(self, "couldn't establish power handler\n"); 344 345 return; 346 347fail: 348 if (sc->sc_ih != NULL) { 349 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 350 sc->sc_ih = NULL; 351 } 352 if (memsize) 353 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, memsize); 354} 355 356static int 357lii_reset(struct lii_softc *sc) 358{ 359 int i; 360 361 DPRINTF(("lii_reset\n")); 362 363 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST); 364 DELAY(1000); 365 366 for (i = 0; i < 10; ++i) { 367 if (AT_READ_4(sc, ATL2_BIS) == 0) 368 break; 369 DELAY(1000); 370 } 371 372 if (i == 10) { 373 aprint_error_dev(sc->sc_dev, "reset failed\n"); 374 return 1; 375 } 376 377 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE); 378 DELAY(10); 379 380 /* Init PCI-Express module */ 381 /* Magic Numbers Warning */ 382 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF); 383 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF); 384 385 return 0; 386} 387 388static bool 389lii_eeprom_present(struct lii_softc *sc) 390{ 391 /* 392 * The Linux driver does this, but then it has a very weird way of 393 * checking whether the PCI configuration space exposes the Vital 394 * Product Data capability, so maybe it's not really needed. 395 */ 396 397#ifdef weirdloonix 398 uint32_t val; 399 400 val = AT_READ_4(sc, ATL2_SFC); 401 if (val & SFC_EN_VPD) 402 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD)); 403#endif 404 405 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 406 NULL, NULL) == 1; 407} 408 409static int 410lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 411{ 412 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 413 414 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val)); 415 416 return r; 417} 418 419static void 420lii_spi_configure(struct lii_softc *sc) 421{ 422 /* 423 * We don't offer a way to configure the SPI Flash vendor parameter, so 424 * the table is given for reference 425 */ 426 static const struct lii_spi_flash_vendor { 427 const char *sfv_name; 428 const uint8_t sfv_opcodes[9]; 429 } lii_sfv[] = { 430 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 431 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 432 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 433 }; 434#define SF_OPCODE_WRSR 0 435#define SF_OPCODE_READ 1 436#define SF_OPCODE_PRGM 2 437#define SF_OPCODE_WREN 3 438#define SF_OPCODE_WRDI 4 439#define SF_OPCODE_RDSR 5 440#define SF_OPCODE_RDID 6 441#define SF_OPCODE_SECT_ER 7 442#define SF_OPCODE_CHIP_ER 8 443 444#define SF_DEFAULT_VENDOR 0 445 static const uint8_t vendor = SF_DEFAULT_VENDOR; 446 447 /* 448 * Why isn't WRDI used? Heck if I know. 449 */ 450 451 AT_WRITE_1(sc, ATL2_SFOP_WRSR, 452 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 453 AT_WRITE_1(sc, ATL2_SFOP_READ, 454 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 455 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM, 456 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 457 AT_WRITE_1(sc, ATL2_SFOP_WREN, 458 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 459 AT_WRITE_1(sc, ATL2_SFOP_RDSR, 460 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 461 AT_WRITE_1(sc, ATL2_SFOP_RDID, 462 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 463 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE, 464 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 465 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE, 466 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 467} 468 469#define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 470 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 471 << SFC_CS_SETUP_SHIFT) \ 472 | (((clkhi) & SFC_CLK_HI_MASK) \ 473 << SFC_CLK_HI_SHIFT) \ 474 | (((clklo) & SFC_CLK_LO_MASK) \ 475 << SFC_CLK_LO_SHIFT) \ 476 | (((cshold) & SFC_CS_HOLD_MASK) \ 477 << SFC_CS_HOLD_SHIFT) \ 478 | (((cshi) & SFC_CS_HI_MASK) \ 479 << SFC_CS_HI_SHIFT) \ 480 | (((ins) & SFC_INS_MASK) \ 481 << SFC_INS_SHIFT)) 482 483/* Magic settings from the Linux driver */ 484 485#define CUSTOM_SPI_CS_SETUP 2 486#define CUSTOM_SPI_CLK_HI 2 487#define CUSTOM_SPI_CLK_LO 2 488#define CUSTOM_SPI_CS_HOLD 2 489#define CUSTOM_SPI_CS_HI 3 490 491static int 492lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 493{ 494 uint32_t v; 495 int i; 496 497 AT_WRITE_4(sc, ATL2_SF_DATA, 0); 498 AT_WRITE_4(sc, ATL2_SF_ADDR, reg); 499 500 v = SFC_WAIT_READY | 501 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 502 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 503 504 AT_WRITE_4(sc, ATL2_SFC, v); 505 v |= SFC_START; 506 AT_WRITE_4(sc, ATL2_SFC, v); 507 508 for (i = 0; i < 10; ++i) { 509 DELAY(1000); 510 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START)) 511 break; 512 } 513 if (i == 10) 514 return EBUSY; 515 516 *val = AT_READ_4(sc, ATL2_SF_DATA); 517 return 0; 518} 519 520static int 521lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 522{ 523 uint32_t offset = 0x100; 524 uint32_t val, val1, addr0 = 0, addr1 = 0; 525 uint8_t found = 0; 526 527 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 528 offset += 4; 529 530 /* Each chunk of data starts with a signature */ 531 if ((val & 0xff) != 0x5a) 532 break; 533 if ((*sc->sc_memread)(sc, offset, &val1)) 534 break; 535 536 offset += 4; 537 538 val >>= 16; 539 switch (val) { 540 case ATL2_MAC_ADDR_0: 541 addr0 = val1; 542 ++found; 543 break; 544 case ATL2_MAC_ADDR_1: 545 addr1 = val1; 546 ++found; 547 break; 548 default: 549 continue; 550 } 551 } 552 553 if (found < 2) { 554 /* Make sure we try the BIOS method before giving up */ 555 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0)); 556 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1)); 557 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 558 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 559 aprint_error_dev(sc->sc_dev, 560 "error reading MAC address\n"); 561 return 1; 562 } 563 } else { 564 addr0 = htole32(addr0); 565 addr1 = htole32(addr1); 566 } 567 568 ea[0] = (addr1 & 0x0000ff00) >> 8; 569 ea[1] = (addr1 & 0x000000ff); 570 ea[2] = (addr0 & 0xff000000) >> 24; 571 ea[3] = (addr0 & 0x00ff0000) >> 16; 572 ea[4] = (addr0 & 0x0000ff00) >> 8; 573 ea[5] = (addr0 & 0x000000ff); 574 575 return 0; 576} 577 578static int 579lii_mii_readreg(device_t dev, int phy, int reg) 580{ 581 struct lii_softc *sc = device_private(dev); 582 uint32_t val; 583 int i; 584 585 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 586 587 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 588 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 589 590 val |= MDIOC_READ; 591 592 AT_WRITE_4(sc, ATL2_MDIOC, val); 593 594 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 595 DELAY(2); 596 val = AT_READ_4(sc, ATL2_MDIOC); 597 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 598 break; 599 } 600 601 if (i == MDIO_WAIT_TIMES) 602 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy, 603 reg); 604 605 return (val & 0x0000ffff); 606} 607 608static void 609lii_mii_writereg(device_t dev, int phy, int reg, int data) 610{ 611 struct lii_softc *sc = device_private(dev); 612 uint32_t val; 613 int i; 614 615 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 616 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 617 618 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 619 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 620 621 /* val |= MDIOC_WRITE; */ 622 623 AT_WRITE_4(sc, ATL2_MDIOC, val); 624 625 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 626 DELAY(2); 627 val = AT_READ_4(sc, ATL2_MDIOC); 628 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 629 break; 630 } 631 632 if (i == MDIO_WAIT_TIMES) 633 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy, 634 reg); 635} 636 637static void 638lii_mii_statchg(device_t dev) 639{ 640 struct lii_softc *sc = device_private(dev); 641 uint32_t val; 642 643 DPRINTF(("lii_mii_statchg\n")); 644 645 val = AT_READ_4(sc, ATL2_MACC); 646 647 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 648 val |= MACC_FDX; 649 else 650 val &= ~MACC_FDX; 651 652 AT_WRITE_4(sc, ATL2_MACC, val); 653} 654 655static int 656lii_media_change(struct ifnet *ifp) 657{ 658 struct lii_softc *sc = ifp->if_softc; 659 660 DPRINTF(("lii_media_change\n")); 661 662 if (ifp->if_flags & IFF_UP) 663 mii_mediachg(&sc->sc_mii); 664 return 0; 665} 666 667static void 668lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 669{ 670 struct lii_softc *sc = ifp->if_softc; 671 672 DPRINTF(("lii_media_status\n")); 673 674 mii_pollstat(&sc->sc_mii); 675 imr->ifm_status = sc->sc_mii.mii_media_status; 676 imr->ifm_active = sc->sc_mii.mii_media_active; 677} 678 679static int 680lii_init(struct ifnet *ifp) 681{ 682 struct lii_softc *sc = ifp->if_softc; 683 uint32_t val; 684 int error; 685 686 DPRINTF(("lii_init\n")); 687 688 lii_stop(ifp, 0); 689 690 memset(sc->sc_ring, 0, sc->sc_ringsize); 691 692 /* Disable all interrupts */ 693 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff); 694 695 /* XXX endianness */ 696 AT_WRITE_4(sc, ATL2_MAC_ADDR_0, 697 sc->sc_eaddr[2] << 24 | 698 sc->sc_eaddr[3] << 16 | 699 sc->sc_eaddr[4] << 8 | 700 sc->sc_eaddr[5]); 701 AT_WRITE_4(sc, ATL2_MAC_ADDR_1, 702 sc->sc_eaddr[0] << 8 | 703 sc->sc_eaddr[1]); 704 705 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0); 706/* XXX 707 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 708*/ 709 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO, 710 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 711 + AT_RXD_PADDING); 712 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO, 713 sc->sc_txsp & 0xffffffff); 714 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO, 715 sc->sc_txdp & 0xffffffff); 716 717 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 718 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM); 719 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM); 720 721 /* 722 * Inter Paket Gap Time = 0x60 (IPGT) 723 * Minimum inter-frame gap for RX = 0x50 (MIFG) 724 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 725 * 96-bit IPG window = 0x60 (IPGR2) 726 */ 727 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060); 728 729 /* 730 * Collision window = 0x37 (LCOL) 731 * Maximum # of retrans = 0xf (RETRY) 732 * Maximum binary expansion # = 0xa (ABEBT) 733 * IPG to start jam = 0x7 (JAMIPG) 734 */ 735 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 | 736 MHDC_EXC_DEF_EN); 737 738 /* 100 means 200us */ 739 AT_WRITE_2(sc, ATL2_IMTIV, 100); 740 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN); 741 742 /* 500000 means 100ms */ 743 AT_WRITE_2(sc, ATL2_IALTIV, 50000); 744 745 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN 746 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 747 748 /* unit unknown for TX cur-through threshold */ 749 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177); 750 751 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 752 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12); 753 754 sc->sc_rxcur = 0; 755 sc->sc_txs_cur = sc->sc_txs_ack = 0; 756 sc->sc_txd_cur = sc->sc_txd_ack = 0; 757 sc->sc_free_tx_slots = true; 758 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur); 759 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 760 761 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN); 762 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN); 763 764 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT); 765 766 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0); 767 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff); 768 AT_WRITE_4(sc, ATL2_ISR, 0); 769 if (error) { 770 aprint_error_dev(sc->sc_dev, "init failed\n"); 771 goto out; 772 } 773 774 lii_setmulti(sc); 775 776 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX; 777 778 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 779 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 780 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 781 782 if (ifp->if_flags & IFF_PROMISC) 783 val |= MACC_PROMISC_EN; 784 else if (ifp->if_flags & IFF_ALLMULTI) 785 val |= MACC_ALLMULTI_EN; 786 787 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 788 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 789 790 AT_WRITE_4(sc, ATL2_MACC, val); 791 792 mii_mediachg(&sc->sc_mii); 793 794 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK); 795 796 callout_schedule(&sc->sc_tick_ch, hz); 797 798 ifp->if_flags |= IFF_RUNNING; 799 ifp->if_flags &= ~IFF_OACTIVE; 800 801out: 802 return error; 803} 804 805static void 806lii_tx_put(struct lii_softc *sc, struct mbuf *m) 807{ 808 int left; 809 struct tx_pkt_header *tph = 810 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 811 812 memset(tph, 0, sizeof *tph); 813 tph->txph_size = m->m_pkthdr.len; 814 815 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 816 817 /* 818 * We already know we have enough space, so if there is a part of the 819 * space ahead of txd_cur that is active, it doesn't matter because 820 * left will be large enough even without it. 821 */ 822 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 823 824 if (left > m->m_pkthdr.len) { 825 m_copydata(m, 0, m->m_pkthdr.len, 826 sc->sc_txdbase + sc->sc_txd_cur); 827 sc->sc_txd_cur += m->m_pkthdr.len; 828 } else { 829 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 830 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 831 sc->sc_txd_cur = m->m_pkthdr.len - left; 832 } 833 834 /* Round to a 32-bit boundary */ 835 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 836 if (sc->sc_txd_cur == sc->sc_txd_ack) 837 sc->sc_free_tx_slots = false; 838} 839 840static int 841lii_free_tx_space(struct lii_softc *sc) 842{ 843 int space; 844 845 if (sc->sc_txd_cur >= sc->sc_txd_ack) 846 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 847 sc->sc_txd_ack; 848 else 849 space = sc->sc_txd_ack - sc->sc_txd_cur; 850 851 /* Account for the tx_pkt_header */ 852 return (space - 4); 853} 854 855static void 856lii_start(struct ifnet *ifp) 857{ 858 struct lii_softc *sc = ifp->if_softc; 859 struct mbuf *m0; 860 861 DPRINTF(("lii_start\n")); 862 863 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 864 return; 865 866 for (;;) { 867 IFQ_POLL(&ifp->if_snd, m0); 868 if (m0 == NULL) 869 break; 870 871 if (!sc->sc_free_tx_slots || 872 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 873 ifp->if_flags |= IFF_OACTIVE; 874 break; 875 } 876 877 lii_tx_put(sc, m0); 878 879 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 880 881 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 882 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 883 if (sc->sc_txs_cur == sc->sc_txs_ack) 884 sc->sc_free_tx_slots = false; 885 886 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 887 888 IFQ_DEQUEUE(&ifp->if_snd, m0); 889 890 bpf_mtap(ifp, m0); 891 m_freem(m0); 892 } 893} 894 895static void 896lii_stop(struct ifnet *ifp, int disable) 897{ 898 struct lii_softc *sc = ifp->if_softc; 899 900 callout_stop(&sc->sc_tick_ch); 901 902 ifp->if_timer = 0; 903 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 904 905 mii_down(&sc->sc_mii); 906 907 lii_reset(sc); 908 909 AT_WRITE_4(sc, ATL2_IMR, 0); 910} 911 912static int 913lii_intr(void *v) 914{ 915 struct lii_softc *sc = v; 916 uint32_t status; 917 918 status = AT_READ_4(sc, ATL2_ISR); 919 if (status == 0) 920 return 0; 921 922 DPRINTF(("lii_intr (%x)\n", status)); 923 924 /* Clear the interrupt and disable them */ 925 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT); 926 927 if (status & (ISR_PHY | ISR_MANUAL)) { 928 /* Ack PHY interrupt. Magic register */ 929 if (status & ISR_PHY) 930 (void)lii_mii_readreg(sc->sc_dev, 1, 19); 931 mii_mediachg(&sc->sc_mii); 932 } 933 934 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 935 lii_init(&sc->sc_ec.ec_if); 936 return 1; 937 } 938 939 if (status & ISR_RX_EVENT) { 940#ifdef LII_DEBUG 941 if (!(status & ISR_RS_UPDATE)) 942 printf("rxintr %08x\n", status); 943#endif 944 lii_rxintr(sc); 945 } 946 947 if (status & ISR_TX_EVENT) 948 lii_txintr(sc); 949 950 /* Re-enable interrupts */ 951 AT_WRITE_4(sc, ATL2_ISR, 0); 952 953 return 1; 954} 955 956static void 957lii_rxintr(struct lii_softc *sc) 958{ 959 struct ifnet *ifp = &sc->sc_ec.ec_if; 960 struct rx_pkt *rxp; 961 struct mbuf *m; 962 uint16_t size; 963 964 DPRINTF(("lii_rxintr\n")); 965 966 for (;;) { 967 rxp = &sc->sc_rxp[sc->sc_rxcur]; 968 if (rxp->rxp_update == 0) 969 break; 970 971 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 972 rxp->rxp_size, rxp->rxp_flags)); 973 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 974 rxp->rxp_update = 0; 975 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) { 976 ++ifp->if_ierrors; 977 continue; 978 } 979 980 MGETHDR(m, M_DONTWAIT, MT_DATA); 981 if (m == NULL) { 982 ++ifp->if_ierrors; 983 continue; 984 } 985 size = rxp->rxp_size - ETHER_CRC_LEN; 986 if (size > MHLEN) { 987 MCLGET(m, M_DONTWAIT); 988 if ((m->m_flags & M_EXT) == 0) { 989 m_freem(m); 990 ++ifp->if_ierrors; 991 continue; 992 } 993 } 994 995 m->m_pkthdr.rcvif = ifp; 996 /* Copy the packet withhout the FCS */ 997 m->m_pkthdr.len = m->m_len = size; 998 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 999 ++ifp->if_ipackets; 1000 1001 bpf_mtap(ifp, m); 1002 1003 (*ifp->if_input)(ifp, m); 1004 } 1005 1006 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur); 1007} 1008 1009static void 1010lii_txintr(struct lii_softc *sc) 1011{ 1012 struct ifnet *ifp = &sc->sc_ec.ec_if; 1013 struct tx_pkt_status *txs; 1014 struct tx_pkt_header *txph; 1015 1016 DPRINTF(("lii_txintr\n")); 1017 1018 for (;;) { 1019 txs = &sc->sc_txs[sc->sc_txs_ack]; 1020 if (txs->txps_update == 0) 1021 break; 1022 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 1023 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 1024 sc->sc_free_tx_slots = true; 1025 1026 txs->txps_update = 0; 1027 1028 txph = (struct tx_pkt_header *) 1029 (sc->sc_txdbase + sc->sc_txd_ack); 1030 1031 if (txph->txph_size != txs->txps_size) 1032 aprint_error_dev(sc->sc_dev, 1033 "mismatched status and packet\n"); 1034 /* 1035 * Move ack by the packet size, taking the packet header in 1036 * account and round to the next 32-bit boundary 1037 * (7 = sizeof(header) + 3) 1038 */ 1039 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 1040 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 1041 1042 if (txs->txps_flags & ATL2_TXF_SUCCESS) 1043 ++ifp->if_opackets; 1044 else 1045 ++ifp->if_oerrors; 1046 ifp->if_flags &= ~IFF_OACTIVE; 1047 } 1048 1049 if (sc->sc_free_tx_slots) 1050 lii_start(ifp); 1051} 1052 1053static int 1054lii_alloc_rings(struct lii_softc *sc) 1055{ 1056 int nsegs; 1057 bus_size_t bs; 1058 1059 /* 1060 * We need a big chunk of DMA-friendly memory because descriptors 1061 * are not separate from data on that crappy hardware, which means 1062 * we'll have to copy data from and to that memory zone to and from 1063 * the mbufs. 1064 * 1065 * How lame is that? Using the default values from the Linux driver, 1066 * we allocate space for receiving up to 64 full-size Ethernet frames, 1067 * and only 8kb for transmitting up to 64 Ethernet frames. 1068 */ 1069 1070 sc->sc_ringsize = bs = AT_RXD_PADDING 1071 + AT_RXD_NUM * sizeof(struct rx_pkt) 1072 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1073 + AT_TXD_BUFFER_SIZE; 1074 1075 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1076 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1077 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n"); 1078 return 1; 1079 } 1080 1081 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1082 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1083 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n"); 1084 goto fail; 1085 } 1086 1087 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1088 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1089 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n"); 1090 goto fail1; 1091 } 1092 1093 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1094 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1095 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n"); 1096 goto fail2; 1097 } 1098 1099 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1100 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1101 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1102 sc->sc_txdbase = ((char *)sc->sc_txs) 1103 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1104 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1105 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1106 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1107 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1108 1109 return 0; 1110 1111fail2: 1112 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1113fail1: 1114 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1115fail: 1116 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1117 return 1; 1118} 1119 1120static void 1121lii_watchdog(struct ifnet *ifp) 1122{ 1123 struct lii_softc *sc = ifp->if_softc; 1124 1125 aprint_error_dev(sc->sc_dev, "watchdog timeout\n"); 1126 ++ifp->if_oerrors; 1127 lii_init(ifp); 1128} 1129 1130static int 1131lii_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1132{ 1133 struct lii_softc *sc = ifp->if_softc; 1134 int s, error; 1135 1136 s = splnet(); 1137 1138 switch(cmd) { 1139 case SIOCADDMULTI: 1140 case SIOCDELMULTI: 1141 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1142 if (ifp->if_flags & IFF_RUNNING) 1143 lii_setmulti(sc); 1144 error = 0; 1145 } 1146 break; 1147 case SIOCSIFMEDIA: 1148 case SIOCGIFMEDIA: 1149 error = ifmedia_ioctl(ifp, (struct ifreq *)data, 1150 &sc->sc_mii.mii_media, cmd); 1151 break; 1152 default: 1153 error = ether_ioctl(ifp, cmd, data); 1154 if (error == ENETRESET) { 1155 if (ifp->if_flags & IFF_RUNNING) 1156 lii_setmulti(sc); 1157 error = 0; 1158 } 1159 break; 1160 } 1161 1162 splx(s); 1163 1164 return error; 1165} 1166 1167static void 1168lii_setmulti(struct lii_softc *sc) 1169{ 1170 struct ethercom *ec = &sc->sc_ec; 1171 struct ifnet *ifp = &ec->ec_if; 1172 uint32_t mht0 = 0, mht1 = 0, crc; 1173 struct ether_multi *enm; 1174 struct ether_multistep step; 1175 1176 /* Clear multicast hash table */ 1177 AT_WRITE_4(sc, ATL2_MHT, 0); 1178 AT_WRITE_4(sc, ATL2_MHT + 4, 0); 1179 1180 ifp->if_flags &= ~IFF_ALLMULTI; 1181 1182 ETHER_FIRST_MULTI(step, ec, enm); 1183 while (enm != NULL) { 1184 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1185 ifp->if_flags |= IFF_ALLMULTI; 1186 mht0 = mht1 = 0; 1187 goto alldone; 1188 } 1189 1190 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1191 1192 if (crc & (1 << 31)) 1193 mht1 |= (1 << ((crc >> 26) & 0x0000001f)); 1194 else 1195 mht0 |= (1 << ((crc >> 26) & 0x0000001f)); 1196 1197 ETHER_NEXT_MULTI(step, enm); 1198 } 1199 1200alldone: 1201 AT_WRITE_4(sc, ATL2_MHT, mht0); 1202 AT_WRITE_4(sc, ATL2_MHT+4, mht1); 1203} 1204 1205static void 1206lii_tick(void *v) 1207{ 1208 struct lii_softc *sc = v; 1209 int s; 1210 1211 s = splnet(); 1212 mii_tick(&sc->sc_mii); 1213 splx(s); 1214 1215 callout_schedule(&sc->sc_tick_ch, hz); 1216} 1217