1/* $NetBSD */ 2/*- 3 * Copyright (c) 2010 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Jean-Yves Migeon <jym@NetBSD.org> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 31 */ 32 33#ifndef _DEV_PCI_IF_BNXVAR_H_ 34#define _DEV_PCI_IF_BNXVAR_H_ 35 36#ifdef _KERNEL_OPT 37#include "opt_inet.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/device.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <sys/workqueue.h> 50 51#include <net/if.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_ether.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_inarp.h> 62#endif 63 64#include <net/if_vlanvar.h> 65 66#include <net/bpf.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70#include <dev/pci/pcidevs.h> 71 72#include <dev/mii/mii.h> 73#include <dev/mii/miivar.h> 74#include <dev/mii/miidevs.h> 75#include <dev/mii/brgphyreg.h> 76 77/* 78 * PCI registers defined in the PCI 2.2 spec. 79 */ 80#define BNX_PCI_BAR0 0x10 81#define BNX_PCI_PCIX_CMD 0x40 82 83/****************************************************************************/ 84/* Convenience definitions. */ 85/****************************************************************************/ 86#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 87#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 88#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 89#define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 90#define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 91#define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 92#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 93#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 94#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 95#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 96 97/****************************************************************************/ 98/* BNX Device State Data Structure */ 99/****************************************************************************/ 100 101#define BNX_STATUS_BLK_SZ sizeof(struct status_block) 102#define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 103#define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 104#define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 105 106struct bnx_pkt { 107 TAILQ_ENTRY(bnx_pkt) pkt_entry; 108 bus_dmamap_t pkt_dmamap; 109 struct mbuf *pkt_mbuf; 110 u_int16_t pkt_end_desc; 111}; 112 113TAILQ_HEAD(bnx_pkt_list, bnx_pkt); 114 115struct bnx_softc 116{ 117 device_t bnx_dev; 118 struct ethercom bnx_ec; 119 struct pci_attach_args bnx_pa; 120 121 struct ifmedia bnx_ifmedia; /* TBI media info */ 122 123 bus_space_tag_t bnx_btag; /* Device bus tag */ 124 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 125 bus_size_t bnx_size; 126 127 void *bnx_intrhand; /* Interrupt handler */ 128 129 /* packet allocation workqueue */ 130 struct workqueue *bnx_wq; 131 132 /* ASIC Chip ID. */ 133 u_int32_t bnx_chipid; 134 135 /* General controller flags. */ 136 u_int32_t bnx_flags; 137 138 /* PHY specific flags. */ 139 u_int32_t bnx_phy_flags; 140 141 /* Values that need to be shared with the PHY driver. */ 142 u_int32_t bnx_shared_hw_cfg; 143 u_int32_t bnx_port_hw_cfg; 144 145 u_int16_t bus_speed_mhz; /* PCI bus speed */ 146 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 147 u_int32_t bnx_flash_size; /* Flash NVRAM size */ 148 u_int32_t bnx_shmem_base; /* Shared Memory base address */ 149 char * bnx_name; /* Name string */ 150 151 /* Tracks the version of bootcode firmware. */ 152 u_int32_t bnx_fw_ver; 153 154 /* Tracks the state of the firmware. 0 = Running while any */ 155 /* other value indicates that the firmware is not responding. */ 156 u_int16_t bnx_fw_timed_out; 157 158 /* An incrementing sequence used to coordinate messages passed */ 159 /* from the driver to the firmware. */ 160 u_int16_t bnx_fw_wr_seq; 161 162 /* An incrementing sequence used to let the firmware know that */ 163 /* the driver is still operating. Without the pulse, management */ 164 /* firmware such as IPMI or UMP will operate in OS absent state. */ 165 u_int16_t bnx_fw_drv_pulse_wr_seq; 166 167 /* Ethernet MAC address. */ 168 u_char eaddr[6]; 169 170 /* These setting are used by the host coalescing (HC) block to */ 171 /* to control how often the status block, statistics block and */ 172 /* interrupts are generated. */ 173 u_int16_t bnx_tx_quick_cons_trip_int; 174 u_int16_t bnx_tx_quick_cons_trip; 175 u_int16_t bnx_rx_quick_cons_trip_int; 176 u_int16_t bnx_rx_quick_cons_trip; 177 u_int16_t bnx_comp_prod_trip_int; 178 u_int16_t bnx_comp_prod_trip; 179 u_int16_t bnx_tx_ticks_int; 180 u_int16_t bnx_tx_ticks; 181 u_int16_t bnx_rx_ticks_int; 182 u_int16_t bnx_rx_ticks; 183 u_int16_t bnx_com_ticks_int; 184 u_int16_t bnx_com_ticks; 185 u_int16_t bnx_cmd_ticks_int; 186 u_int16_t bnx_cmd_ticks; 187 u_int32_t bnx_stats_ticks; 188 189 /* The address of the integrated PHY on the MII bus. */ 190 int bnx_phy_addr; 191 192 /* The device handle for the MII bus child device. */ 193 struct mii_data bnx_mii; 194 195 /* Driver maintained TX chain pointers and byte counter. */ 196 u_int16_t rx_prod; 197 u_int16_t rx_cons; 198 u_int32_t rx_prod_bseq; /* Counts the bytes used. */ 199 u_int16_t tx_prod; 200 u_int16_t tx_cons; 201 u_int32_t tx_prod_bseq; /* Counts the bytes used. */ 202 203 struct callout bnx_timeout; 204 205 /* Frame size and mbuf allocation size for RX frames. */ 206 u_int32_t max_frame_size; 207 int mbuf_alloc_size; 208 209 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 210 u_int32_t rx_mode; 211 212 /* Bus tag for the bnx controller. */ 213 bus_dma_tag_t bnx_dmatag; 214 215 /* H/W maintained TX buffer descriptor chain structure. */ 216 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 217 int tx_bd_chain_rseg[TX_PAGES]; 218 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 219 struct tx_bd *tx_bd_chain[TX_PAGES]; 220 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 221 222 /* H/W maintained RX buffer descriptor chain structure. */ 223 bus_dma_segment_t rx_bd_chain_seg[RX_PAGES]; 224 int rx_bd_chain_rseg[RX_PAGES]; 225 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 226 struct rx_bd *rx_bd_chain[RX_PAGES]; 227 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 228 229 /* H/W maintained status block. */ 230 bus_dma_segment_t status_seg; 231 int status_rseg; 232 bus_dmamap_t status_map; 233 struct status_block *status_block; /* virtual address */ 234 bus_addr_t status_block_paddr; /* Physical address */ 235 236 /* H/W maintained context block */ 237 int ctx_pages; 238 bus_dma_segment_t ctx_segs[4]; 239 int ctx_rsegs[4]; 240 bus_dmamap_t ctx_map[4]; 241 void *ctx_block[4]; 242 243 /* Driver maintained status block values. */ 244 u_int16_t last_status_idx; 245 u_int16_t hw_rx_cons; 246 u_int16_t hw_tx_cons; 247 248 /* H/W maintained statistics block. */ 249 bus_dma_segment_t stats_seg; 250 int stats_rseg; 251 bus_dmamap_t stats_map; 252 struct statistics_block *stats_block; /* Virtual address */ 253 bus_addr_t stats_block_paddr; /* Physical address */ 254 255 /* Bus tag for RX/TX mbufs. */ 256 bus_dma_segment_t rx_mbuf_seg; 257 int rx_mbuf_rseg; 258 bus_dma_segment_t tx_mbuf_seg; 259 int tx_mbuf_rseg; 260 261 /* S/W maintained mbuf TX chain structure. */ 262 kmutex_t tx_pkt_mtx; 263 u_int tx_pkt_count; 264 struct bnx_pkt_list tx_free_pkts; 265 struct bnx_pkt_list tx_used_pkts; 266 267 /* S/W maintained mbuf RX chain structure. */ 268 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 269 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 270 271 /* Track the number of rx_bd and tx_bd's in use. */ 272 u_int16_t free_rx_bd; 273 u_int16_t max_rx_bd; 274 u_int16_t used_tx_bd; 275 u_int16_t max_tx_bd; 276 277 /* Provides access to hardware statistics through sysctl. */ 278 u_int64_t stat_IfHCInOctets; 279 u_int64_t stat_IfHCInBadOctets; 280 u_int64_t stat_IfHCOutOctets; 281 u_int64_t stat_IfHCOutBadOctets; 282 u_int64_t stat_IfHCInUcastPkts; 283 u_int64_t stat_IfHCInMulticastPkts; 284 u_int64_t stat_IfHCInBroadcastPkts; 285 u_int64_t stat_IfHCOutUcastPkts; 286 u_int64_t stat_IfHCOutMulticastPkts; 287 u_int64_t stat_IfHCOutBroadcastPkts; 288 289 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 290 u_int32_t stat_Dot3StatsCarrierSenseErrors; 291 u_int32_t stat_Dot3StatsFCSErrors; 292 u_int32_t stat_Dot3StatsAlignmentErrors; 293 u_int32_t stat_Dot3StatsSingleCollisionFrames; 294 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 295 u_int32_t stat_Dot3StatsDeferredTransmissions; 296 u_int32_t stat_Dot3StatsExcessiveCollisions; 297 u_int32_t stat_Dot3StatsLateCollisions; 298 u_int32_t stat_EtherStatsCollisions; 299 u_int32_t stat_EtherStatsFragments; 300 u_int32_t stat_EtherStatsJabbers; 301 u_int32_t stat_EtherStatsUndersizePkts; 302 u_int32_t stat_EtherStatsOverrsizePkts; 303 u_int32_t stat_EtherStatsPktsRx64Octets; 304 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 305 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 306 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 307 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 308 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 309 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 310 u_int32_t stat_EtherStatsPktsTx64Octets; 311 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 312 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 313 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 314 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 315 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 316 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 317 u_int32_t stat_XonPauseFramesReceived; 318 u_int32_t stat_XoffPauseFramesReceived; 319 u_int32_t stat_OutXonSent; 320 u_int32_t stat_OutXoffSent; 321 u_int32_t stat_FlowControlDone; 322 u_int32_t stat_MacControlFramesReceived; 323 u_int32_t stat_XoffStateEntered; 324 u_int32_t stat_IfInFramesL2FilterDiscards; 325 u_int32_t stat_IfInRuleCheckerDiscards; 326 u_int32_t stat_IfInFTQDiscards; 327 u_int32_t stat_IfInMBUFDiscards; 328 u_int32_t stat_IfInRuleCheckerP4Hit; 329 u_int32_t stat_CatchupInRuleCheckerDiscards; 330 u_int32_t stat_CatchupInFTQDiscards; 331 u_int32_t stat_CatchupInMBUFDiscards; 332 u_int32_t stat_CatchupInRuleCheckerP4Hit; 333 334 /* Mbuf allocation failure counter. */ 335 u_int32_t mbuf_alloc_failed; 336 337 /* TX DMA mapping failure counter. */ 338 u_int32_t tx_dma_map_failures; 339 340#ifdef BNX_DEBUG 341 /* Track the number of enqueued mbufs. */ 342 int tx_mbuf_alloc; 343 int rx_mbuf_alloc; 344 345 /* Track the distribution buffer segments. */ 346 u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1]; 347 348 /* Track how many and what type of interrupts are generated. */ 349 u_int32_t interrupts_generated; 350 u_int32_t interrupts_handled; 351 u_int32_t rx_interrupts; 352 u_int32_t tx_interrupts; 353 354 u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ 355 u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */ 356 u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ 357 u_int32_t tx_full_count; /* Number of times the TX chain was full. */ 358 u_int32_t mbuf_sim_alloc_failed;/* Mbuf simulated allocation failure counter. */ 359 u_int32_t l2fhdr_status_errors; 360 u_int32_t unexpected_attentions; 361 u_int32_t lost_status_block_updates; 362#endif 363}; 364 365struct bnx_firmware_header { 366 int bnx_COM_FwReleaseMajor; 367 int bnx_COM_FwReleaseMinor; 368 int bnx_COM_FwReleaseFix; 369 u_int32_t bnx_COM_FwStartAddr; 370 u_int32_t bnx_COM_FwTextAddr; 371 int bnx_COM_FwTextLen; 372 u_int32_t bnx_COM_FwDataAddr; 373 int bnx_COM_FwDataLen; 374 u_int32_t bnx_COM_FwRodataAddr; 375 int bnx_COM_FwRodataLen; 376 u_int32_t bnx_COM_FwBssAddr; 377 int bnx_COM_FwBssLen; 378 u_int32_t bnx_COM_FwSbssAddr; 379 int bnx_COM_FwSbssLen; 380 381 int bnx_RXP_FwReleaseMajor; 382 int bnx_RXP_FwReleaseMinor; 383 int bnx_RXP_FwReleaseFix; 384 u_int32_t bnx_RXP_FwStartAddr; 385 u_int32_t bnx_RXP_FwTextAddr; 386 int bnx_RXP_FwTextLen; 387 u_int32_t bnx_RXP_FwDataAddr; 388 int bnx_RXP_FwDataLen; 389 u_int32_t bnx_RXP_FwRodataAddr; 390 int bnx_RXP_FwRodataLen; 391 u_int32_t bnx_RXP_FwBssAddr; 392 int bnx_RXP_FwBssLen; 393 u_int32_t bnx_RXP_FwSbssAddr; 394 int bnx_RXP_FwSbssLen; 395 396 int bnx_TPAT_FwReleaseMajor; 397 int bnx_TPAT_FwReleaseMinor; 398 int bnx_TPAT_FwReleaseFix; 399 u_int32_t bnx_TPAT_FwStartAddr; 400 u_int32_t bnx_TPAT_FwTextAddr; 401 int bnx_TPAT_FwTextLen; 402 u_int32_t bnx_TPAT_FwDataAddr; 403 int bnx_TPAT_FwDataLen; 404 u_int32_t bnx_TPAT_FwRodataAddr; 405 int bnx_TPAT_FwRodataLen; 406 u_int32_t bnx_TPAT_FwBssAddr; 407 int bnx_TPAT_FwBssLen; 408 u_int32_t bnx_TPAT_FwSbssAddr; 409 int bnx_TPAT_FwSbssLen; 410 411 int bnx_TXP_FwReleaseMajor; 412 int bnx_TXP_FwReleaseMinor; 413 int bnx_TXP_FwReleaseFix; 414 u_int32_t bnx_TXP_FwStartAddr; 415 u_int32_t bnx_TXP_FwTextAddr; 416 int bnx_TXP_FwTextLen; 417 u_int32_t bnx_TXP_FwDataAddr; 418 int bnx_TXP_FwDataLen; 419 u_int32_t bnx_TXP_FwRodataAddr; 420 int bnx_TXP_FwRodataLen; 421 u_int32_t bnx_TXP_FwBssAddr; 422 int bnx_TXP_FwBssLen; 423 u_int32_t bnx_TXP_FwSbssAddr; 424 int bnx_TXP_FwSbssLen; 425 426 /* Followed by blocks of data, each sized according to 427 * the (rather obvious) block length stated above. 428 * 429 * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, 430 * bnx_COM_FwBss, bnx_COM_FwSbss, 431 * 432 * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, 433 * bnx_RXP_FwBss, bnx_RXP_FwSbss, 434 * 435 * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, 436 * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, 437 * 438 * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, 439 * bnx_TXP_FwBss, bnx_TXP_FwSbss, 440 */ 441}; 442 443#endif /* _DEV_PCI_IF_BNXVAR_H_ */ 444