1/* $NetBSD: emuxkireg.h,v 1.7 2005/12/11 12:22:49 christos Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Yannick Montulet. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _DEV_PCI_EMUXKIREG_H_ 33#define _DEV_PCI_EMUXKIREG_H_ 34 35/* 36 * Register values for Creative EMU10000. The register values have been 37 * taken from GPLed SBLive! header file published by Creative. The comments 38 * have been stripped to avoid GPL pollution in kernel. The Creative version 39 * including comments is available in Linux 2.4.* kernel as file 40 * drivers/sound/emu10k1/8010.h 41 */ 42 43/* 44 * Audigy specific registers contain an '_A_' 45 * Audigy2 specific registers contain an '_A2_' 46 */ 47 48#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg)) 49 50#define EMU_PTR 0x00 51#define EMU_PTR_CHNO_MASK 0x0000003f 52#define EMU_PTR_ADDR_MASK 0x07ff0000 53#define EMU_A_PTR_ADDR_MASK 0x0fff0000 54 55#define EMU_DATA 0x04 56 57#define EMU_IPR 0x08 58#define EMU_IPR_RATETRCHANGE 0x01000000 59#define EMU_IPR_FXDSP 0x00800000 60#define EMU_IPR_FORCEINT 0x00400000 61#define EMU_PCIERROR 0x00200000 62#define EMU_IPR_VOLINCR 0x00100000 63#define EMU_IPR_VOLDECR 0x00080000 64#define EMU_IPR_MUTE 0x00040000 65#define EMU_IPR_MICBUFFULL 0x00020000 66#define EMU_IPR_MICBUFHALFFULL 0x00010000 67#define EMU_IPR_ADCBUFFULL 0x00008000 68#define EMU_IPR_ADCBUFHALFFULL 0x00004000 69#define EMU_IPR_EFXBUFFULL 0x00002000 70#define EMU_IPR_EFXBUFHALFFULL 0x00001000 71#define EMU_IPR_GPSPDIFSTCHANGE 0x00000800 72#define EMU_IPR_CDROMSTCHANGE 0x00000400 73#define EMU_IPR_INTERVALTIMER 0x00000200 74#define EMU_IPR_MIDITRANSBUFE 0x00000100 75#define EMU_IPR_MIDIRECVBUFE 0x00000080 76#define EMU_IPR_A_MIDITRANSBUFE2 0x10000000 77#define EMU_IPR_A_MIDIRECBUFE2 0x08000000 78#define EMU_IPR_CHANNELLOOP 0x00000040 79#define EMU_IPR_CHNOMASK 0x0000003f 80 81#define EMU_INTE 0x0c 82 83#define EMU_INTE_VSB_MASK 0xc0000000 84#define EMU_INTE_VSB_220 0x00000000 85#define EMU_INTE_VSB_240 0x40000000 86#define EMU_INTE_VSB_260 0x80000000 87#define EMU_INTE_VSB_280 0xc0000000 88 89#define EMU_INTE_VMPU_MASK 0x30000000 90#define EMU_INTE_VMPU_300 0x00000000 91#define EMU_INTE_VMPU_310 0x10000000 92#define EMU_INTE_VMPU_320 0x20000000 93#define EMU_INTE_VMPU_330 0x30000000 94#define EMU_INTE_MDMAENABLE 0x08000000 95#define EMU_INTE_SDMAENABLE 0x04000000 96#define EMU_INTE_MPICENABLE 0x02000000 97#define EMU_INTE_SPICENABLE 0x01000000 98#define EMU_INTE_VSBENABLE 0x00800000 99#define EMU_INTE_ADLIBENABLE 0x00400000 100#define EMU_INTE_MPUENABLE 0x00200000 101#define EMU_INTE_FORCEINT 0x00100000 102#define EMU_INTE_MRHANDENABLE 0x00080000 103#define EMU_INTE_SAMPLERATER 0x00002000 104#define EMU_INTE_FXDSPENABLE 0x00001000 105#define EMU_INTE_PCIERRENABLE 0x00000800 106#define EMU_INTE_VOLINCRENABLE 0x00000400 107#define EMU_INTE_VOLDECRENABLE 0x00000200 108#define EMU_INTE_MUTEENABLE 0x00000100 109#define EMU_INTE_MICBUFENABLE 0x00000080 110#define EMU_INTE_ADCBUFENABLE 0x00000040 111#define EMU_INTE_EFXBUFENABLE 0x00000020 112#define EMU_INTE_GPSPDIFENABLE 0x00000010 113#define EMU_INTE_CDSPDIFENABLE 0x00000008 114#define EMU_INTE_INTERTIMERENB 0x00000004 115#define EMU_INTE_MIDITXENABLE 0x00000002 116#define EMU_INTE_MIDIRXENABLE 0x00000001 117#define EMU_INTE_A_MIDITXENABLE2 0x00020000 118#define EMU_INTE_A_MIDIRXENABLE2 0x00010000 119 120#define EMU_WC 0x10 121#define EMU_WC_SAMPLECOUNTER_MASK 0x03FFFFC0 122#define EMU_WC_SAMPLECOUNTER EMU_MKSUBREG(20, 6, EMU_WC) 123#define EMU_WC_CURRENTCHANNEL 0x0000003F 124 125#define EMU_HCFG 0x14 126#define EMU_HCFG_LEGACYFUNC_MASK 0xe0000000 127#define EMU_HCFG_LEGACYFUNC_MPU 0x00000000 128#define EMU_HCFG_LEGACYFUNC_SB 0x40000000 129#define EMU_HCFG_LEGACYFUNC_AD 0x60000000 130#define EMU_HCFG_LEGACYFUNC_MPIC 0x80000000 131#define EMU_HCFG_LEGACYFUNC_MDMA 0xa0000000 132#define EMU_HCFG_LEGACYFUNC_SPCI 0xc0000000 133#define EMU_HCFG_LEGACYFUNC_SDMA 0xe0000000 134#define EMU_HCFG_IOCAPTUREADDR 0x1f000000 135#define EMU_HCFG_LEGACYWRITE 0x00800000 136#define EMU_HCFG_LEGACYWORD 0x00400000 137#define EMU_HCFG_LEGACYINT 0x00200000 138 139#define EMU_HCFG_CODECFMT_MASK 0x00070000 140#define EMU_HCFG_CODECFMT_AC97 0x00000000 141#define EMU_HCFG_CODECFMT_I2S 0x00010000 142#define EMU_HCFG_GPINPUT0 0x00004000 143#define EMU_HCFG_GPINPUT1 0x00002000 144#define EMU_HCFG_GPOUTPUT_MASK 0x00001c00 145#define EMU_HCFG_JOYENABLE 0x00000200 146#define EMU_HCFG_PHASETRACKENABLE 0x00000100 147#define EMU_HCFG_AC3ENABLE_MASK 0x000000e0 148#define EMU_HCFG_AC3ENABLE_ZVIDEO 0x00000080 149#define EMU_HCFG_AC3ENABLE_CDSPDIF 0x00000040 150#define EMU_HCFG_AC3ENABLE_GPSPDIF 0x00000020 151#define EMU_HCFG_AUTOMUTE 0x00000010 152#define EMU_HCFG_LOCKSOUNDCACHE 0x00000008 153#define EMU_HCFG_LOCKTANKCACHE_MASK 0x00000004 154#define EMU_HCFG_LOCKTANKCACHE EMU_MKSUBREG(1, 2, EMU_HCFG) 155#define EMU_HCFG_MUTEBUTTONENABLE 0x00000002 156#define EMU_HCFG_AUDIOENABLE 0x00000001 157 158#define EMU_MUDATA 0x18 159#define EMU_MUCMD 0x19 160#define EMU_MUCMD_RESET 0xff 161#define EMU_MUCMD_ENTERUARTMODE 0x3f 162 163#define EMU_MUSTAT EMU_MUCMD 164#define EMU_MUSTAT_IRDYN 0x80 165#define EMU_MUSTAT_ORDYN 0x40 166 167#define EMU_A_IOCFG 0x18 168#define EMU_A_GPINPUT_MASK 0xff00 169#define EMU_A_GPOUTPUT_MASK 0x00ff 170#define EMU_A_IOCFG_GPOUT0 0x0040 171#define EMU_A_IOCFG_GPOUT1 0x0004 172 173#define EMU_TIMER 0x1a 174#define EMU_TIMER_RATE_MASK 0x000003ff 175#define EMU_TIMER_RATE EMU_MKSUBREG(10, 0, EMU_TIMER) 176 177#define EMU_AC97DATA 0x1c 178#define EMU_AC97ADDR 0x1e 179#define EMU_AC97ADDR_RDY 0x80 180#define EMU_AC97ADDR_ADDR 0x7f 181 182#define EMU_A2_PTR 0x20 183#define EMU_A2_DATA 0x24 184 185#define EMU_A2_SRCSEL 0x600000 186#define EMU_A2_SRCSEL_ENABLE_SPDIF 0x00000004 187#define EMU_A2_SRCSEL_ENABLE_SRCMULTI 0x00000010 188#define EMU_A2_SRCMULTI 0x6e0000 189#define EMU_A2_SRCMULTI_ENABLE_INPUT 0xff00ff00 190 191/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 192 193#define EMU_CHAN_CPF 0x00 194 195#define EMU_CHAN_CPF_PITCH_MASK 0xffff0000 196#define EMU_CHAN_CPF_PITCH EMU_MKSUBREG(16, 16, EMU_CHAN_CPF) 197#define EMU_CHAN_CPF_STEREO_MASK 0x00008000 198#define EMU_CHAN_CPF_STEREO EMU_MKSUBREG(1, 15, EMU_CHAN_CPF) 199#define EMU_CHAN_CPF_STOP_MASK 0x00004000 200#define EMU_CHAN_CPF_FRACADDRESS_MASK 0x00003fff 201 202 203#define EMU_CHAN_PTRX 0x01 204#define EMU_CHAN_PTRX_PITCHTARGET_MASK 0xffff0000 205#define EMU_CHAN_PTRX_PITCHTARGET EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX) 206#define EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 207#define EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX) 208#define EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK 0x000000ff 209#define EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX) 210 211#define EMU_CHAN_CVCF 0x02 212#define EMU_CHAN_CVCF_CURRVOL_MASK 0xffff0000 213#define EMU_CHAN_CVCF_CURRVOL EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF) 214#define EMU_CHAN_CVCF_CURRFILTER_MASK 0x0000ffff 215#define EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF) 216 217#define EMU_CHAN_VTFT 0x03 218#define EMU_CHAN_VTFT_VOLUMETARGET_MASK 0xffff0000 219#define EMU_CHAN_VTFT_VOLUMETARGET EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT) 220#define EMU_CHAN_VTFT_FILTERTARGET_MASK 0x0000ffff 221#define EMU_CHAN_VTFT_FILTERTARGET EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT) 222 223#define EMU_CHAN_Z1 0x05 224#define EMU_CHAN_Z2 0x04 225 226#define EMU_CHAN_PSST 0x06 227#define EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK 0xff000000 228#define EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST) 229#define EMU_CHAN_PSST_LOOPSTARTADDR_MASK 0x00ffffff 230#define EMU_CHAN_PSST_LOOPSTARTADDR EMU_MKSUBREG(24, 0, EMU_CHAN_PSST) 231 232#define EMU_CHAN_DSL 0x07 233#define EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK 0xff000000 234#define EMU_CHAN_DSL_FXSENDAMOUNT_D EMU_MKSUBREG(8, 24, EMU_CHAN_DSL) 235#define EMU_CHAN_DSL_LOOPENDADDR_MASK 0x00ffffff 236#define EMU_CHAN_DSL_LOOPENDADDR EMU_MKSUBREG(24, 0, EMU_CHAN_DSL) 237 238#define EMU_CHAN_CCCA 0x08 239#define EMU_CHAN_CCCA_RESONANCE 0xf0000000 240#define EMU_CHAN_CCCA_INTERPROMMASK 0x0e000000 241#define EMU_CHAN_CCCA_INTERPROM_0 0x00000000 242#define EMU_CHAN_CCCA_INTERPROM_1 0x02000000 243#define EMU_CHAN_CCCA_INTERPROM_2 0x04000000 244#define EMU_CHAN_CCCA_INTERPROM_3 0x06000000 245#define EMU_CHAN_CCCA_INTERPROM_4 0x08000000 246#define EMU_CHAN_CCCA_INTERPROM_5 0x0a000000 247#define EMU_CHAN_CCCA_INTERPROM_6 0x0c000000 248#define EMU_CHAN_CCCA_INTERPROM_7 0x0e000000 249#define EMU_CHAN_CCCA_8BITSELECT 0x01000000 250#define EMU_CHAN_CCCA_CURRADDR_MASK 0x00ffffff 251#define EMU_CHAN_CCCA_CURRADDR EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA) 252 253#define EMU_CHAN_CCR 0x09 254#define EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK 0xfe000000 255#define EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR) 256#define EMU_CHAN_CCR_CACHELOOPFLAG 0x01000000 257#define EMU_CHAN_CCR_INTERLEAVEDSAMPLES 0x00800000 258#define EMU_CHAN_CCR_WORDSIZEDSAMPLES 0x00400000 259#define EMU_CHAN_CCR_READADDRESS_MASK 0x003f0000 260#define EMU_CHAN_CCR_READADDRESS EMU_MKSUBREG(6, 16, EMU_CHAN_CCR) 261#define EMU_CHAN_CCR_LOOPINVALSIZE 0x0000fe00 262#define EMU_CHAN_CCR_LOOPFLAG 0x00000100 263#define EMU_CHAN_CCR_CACHELOOPADDRHI 0x000000ff 264 265#define EMU_CHAN_CLP 0x0a 266#define EMU_CHAN_CLP_CACHELOOPADDR 0x0000ffff 267 268#define EMU_CHAN_FXRT 0x0b 269#define EMU_CHAN_FXRT_CHANNELA 0x000f0000 270#define EMU_CHAN_FXRT_CHANNELB 0x00f00000 271#define EMU_CHAN_FXRT_CHANNELC 0x0f000000 272#define EMU_CHAN_FXRT_CHANNELD 0xf0000000 273 274#define EMU_CHAN_MAPA 0x0c 275#define EMU_CHAN_MAPB 0x0d 276 277#define EMU_CHAN_MAP_PTE_MASK 0xffffe000 278#define EMU_CHAN_MAP_PTI_MASK 0x00001fff 279 280 281#define EMU_CHAN_ENVVOL 0x10 282#define EMU_CHAN_ENVVOL_MASK 0x0000ffff 283 284 285#define EMU_CHAN_ATKHLDV 0x11 286#define EMU_CHAN_ATKHLDV_PHASE0 0x00008000 287#define EMU_CHAN_ATKHLDV_HOLDTIME_MASK 0x00007f00 288#define EMU_CHAN_ATKHLDV_ATTACKTIME_MASK 0x0000007f 289 290 291#define EMU_CHAN_DCYSUSV 0x12 292#define EMU_CHAN_DCYSUSV_PHASE1_MASK 0x00008000 293#define EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 294#define EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 0x00000080 295#define EMU_CHAN_DCYSUSV_DECAYTIME_MASK 0x0000007f 296 297 298#define EMU_CHAN_LFOVAL1 0x13 299#define EMU_CHAN_LFOVAL_MASK 0x0000ffff 300 301#define EMU_CHAN_ENVVAL 0x14 302#define EMU_CHAN_ENVVAL_MASK 0x0000ffff 303 304#define EMU_CHAN_ATKHLDM 0x15 305#define EMU_CHAN_ATKHLDM_PHASE0 0x00008000 306#define EMU_CHAN_ATKHLDM_HOLDTIME 0x00007f00 307#define EMU_CHAN_ATKHLDM_ATTACKTIME 0x0000007f 308 309#define EMU_CHAN_DCYSUSM 0x16 310#define EMU_CHAN_DCYSUSM_PHASE1_MASK 0x00008000 311#define EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 312#define EMU_CHAN_DCYSUSM_DECAYTIME_MASK 0x0000007f 313 314#define EMU_CHAN_LFOVAL2 0x17 315#define EMU_CHAN_LFOVAL2_MASK 0x0000ffff 316 317#define EMU_CHAN_IP 0x18 318#define EMU_CHAN_IP_MASK 0x0000ffff 319#define EMU_CHAN_IP_UNITY 0x0000e000 320 321#define EMU_CHAN_IFATN 0x19 322#define EMU_CHAN_IFATN_FILTERCUTOFF_MASK 0x0000ff00 323#define EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8, EMU_CHAN_IFATN) 324#define EMU_CHAN_IFATN_ATTENUATION_MASK 0x000000ff 325#define EMU_CHAN_IFATN_ATTENUATION EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN) 326 327#define EMU_CHAN_PEFE 0x1a 328#define EMU_CHAN_PEFE_PITCHAMOUNT_MASK 0x0000ff00 329#define EMU_CHAN_PEFE_PITCHAMOUNT EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE) 330#define EMU_CHAN_PEFE_FILTERAMOUNT_MASK 0x000000ff 331#define EMU_CHAN_PEFE_FILTERAMOUNT EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE) 332 333#define EMU_CHAN_FMMOD 0x1b 334#define EMU_CHAN_FMMOD_MODVIBRATO 0x0000ff00 335#define EMU_CHAN_FMMOD_MOFILTER 0x000000ff 336 337#define EMU_CHAN_TREMFRQ 0x1c 338#define EMU_CHAN_TREMFRQ_DEPTH 0x0000ff00 339 340#define EMU_CHAN_FM2FRQ2 0x1d 341#define EMU_CHAN_FM2FRQ2_DEPTH 0x0000ff00 342#define EMU_CHAN_FM2FRQ2_FREQUENCY 0x000000ff 343 344#define EMU_CHAN_TEMPENV 0x1e 345#define EMU_CHAN_TEMPENV_MASK 0x0000ffff 346 347#define EMU_CHAN_CD0 0x20 348#define EMU_CHAN_CD1 0x21 349#define EMU_CHAN_CD2 0x22 350#define EMU_CHAN_CD3 0x23 351#define EMU_CHAN_CD4 0x24 352#define EMU_CHAN_CD5 0x25 353#define EMU_CHAN_CD6 0x26 354#define EMU_CHAN_CD7 0x27 355#define EMU_CHAN_CD8 0x28 356#define EMU_CHAN_CD9 0x29 357#define EMU_CHAN_CDA 0x2a 358#define EMU_CHAN_CDB 0x2b 359#define EMU_CHAN_CDC 0x2c 360#define EMU_CHAN_CDD 0x2d 361#define EMU_CHAN_CDE 0x2e 362#define EMU_CHAN_CDF 0x2f 363 364/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */ 365 366#define EMU_PTB 0x40 367#define EMU_PTB_MASK 0xfffff000 368 369#define EMU_TCB 0x41 370#define EMU_TCB_MASK 0xfffff000 371 372#define EMU_ADCCR 0x42 373#define EMU_ADCCR_RCHANENABLE 0x00000010 374#define EMU_A_ADCCR_RCHANENABLE 0x00000020 375#define EMU_ADCCR_LCHANENABLE 0x00000008 376#define EMU_A_ADCCR_LCHANENABLE 0x00000010 377#define EMU_ADCCR_SAMPLERATE_MASK 0x00000007 378#define EMU_A_ADCCR_SAMPLERATE_MASK 0x0000000f 379#define EMU_ADCCR_SAMPLERATE_48 0x00000000 380#define EMU_ADCCR_SAMPLERATE_44 0x00000001 381#define EMU_ADCCR_SAMPLERATE_32 0x00000002 382#define EMU_ADCCR_SAMPLERATE_24 0x00000003 383#define EMU_ADCCR_SAMPLERATE_22 0x00000004 384#define EMU_ADCCR_SAMPLERATE_16 0x00000005 385#define EMU_A_ADCCR_SAMPLERATE_12 0x00000006 386#define EMU_ADCCR_SAMPLERATE_11 0x00000006 387#define EMU_A_ADCCR_SAMPLERATE_11 0x00000007 388#define EMU_ADCCR_SAMPLERATE_8 0x00000007 389#define EMU_A_ADCCR_SAMPLERATE_8 0x00000008 390 391#define EMU_FXWC 0x43 392#define EMU_TCBS 0x44 393#define EMU_TCBS_MASK 0x00000007 394#define EMU_TCBS_BUFFSIZE_16K 0x00000000 395#define EMU_TCBS_BUFFSIZE_32K 0x00000001 396#define EMU_TCBS_BUFFSIZE_64K 0x00000002 397#define EMU_TCBS_BUFFSIZE_128K 0x00000003 398#define EMU_TCBS_BUFFSIZE_256K 0x00000004 399#define EMU_TCBS_BUFFSIZE_512K 0x00000005 400#define EMU_TCBS_BUFFSIZE_1024K 0x00000006 401#define EMU_TCBS_BUFFSIZE_2048K 0x00000007 402 403#define EMU_MICBA 0x45 404#define EMU_ADCBA 0x46 405#define EMU_FXBA 0x47 406#define EMU_RECBA_MASK 0xfffff000 407 408#define EMU_MICBS 0x49 409#define EMU_ADCBS 0x4a 410#define EMU_FXBS 0x4b 411#define EMU_RECBS_BUFSIZE_NONE 0x00000000 412#define EMU_RECBS_BUFSIZE_384 0x00000001 413#define EMU_RECBS_BUFSIZE_448 0x00000002 414#define EMU_RECBS_BUFSIZE_512 0x00000003 415#define EMU_RECBS_BUFSIZE_640 0x00000004 416#define EMU_RECBS_BUFSIZE_768 0x00000005 417#define EMU_RECBS_BUFSIZE_896 0x00000006 418#define EMU_RECBS_BUFSIZE_1024 0x00000007 419#define EMU_RECBS_BUFSIZE_1280 0x00000008 420#define EMU_RECBS_BUFSIZE_1536 0x00000009 421#define EMU_RECBS_BUFSIZE_1792 0x0000000a 422#define EMU_RECBS_BUFSIZE_2048 0x0000000b 423#define EMU_RECBS_BUFSIZE_2560 0x0000000c 424#define EMU_RECBS_BUFSIZE_3072 0x0000000d 425#define EMU_RECBS_BUFSIZE_3584 0x0000000e 426#define EMU_RECBS_BUFSIZE_4096 0x0000000f 427#define EMU_RECBS_BUFSIZE_5120 0x00000010 428#define EMU_RECBS_BUFSIZE_6144 0x00000011 429#define EMU_RECBS_BUFSIZE_7168 0x00000012 430#define EMU_RECBS_BUFSIZE_8192 0x00000013 431#define EMU_RECBS_BUFSIZE_10240 0x00000014 432#define EMU_RECBS_BUFSIZE_12288 0x00000015 433#define EMU_RECBS_BUFSIZE_14366 0x00000016 434#define EMU_RECBS_BUFSIZE_16384 0x00000017 435#define EMU_RECBS_BUFSIZE_20480 0x00000018 436#define EMU_RECBS_BUFSIZE_24576 0x00000019 437#define EMU_RECBS_BUFSIZE_28672 0x0000001a 438#define EMU_RECBS_BUFSIZE_32768 0x0000001b 439#define EMU_RECBS_BUFSIZE_40960 0x0000001c 440#define EMU_RECBS_BUFSIZE_49152 0x0000001d 441#define EMU_RECBS_BUFSIZE_57344 0x0000001e 442#define EMU_RECBS_BUFSIZE_65536 0x0000001f 443 444#define EMU_CDCS 0x50 445#define EMU_GPSCS 0x51 446 447#define EMU_DBG 0x52 448#define EMU_DBG_ZC 0x80000000 449#define EMU_DBG_SATURATION_OCCURRED 0x02000000 450#define EMU_DBG_SATURATION_ADDR 0x01ff0000 451#define EMU_DBG_SINGLE_STEP 0x00008000 452#define EMU_DBG_STEP 0x00004000 453#define EMU_DBG_CONDITION_CODE 0x00003e00 454#define EMU_DBG_SINGLE_STEP_ADDR 0x000001ff 455 456#define EMU_A_DBG 0x53 457#define EMU_A_DBG_SINGLE_STEP 0x00020000 458#define EMU_A_DBG_ZC 0x40000000 459#define EMU_A_DBG_STEP_ADDR 0x000003ff 460#define EMU_A_DBG_SATURATION_OCCRD 0x20000000 461#define EMU_A_DBG_SATURATION_ADDR 0x0ffc0000 462 463#define EMU_SPCS0 0x54 464#define EMU_SPCS1 0x55 465#define EMU_SPCS2 0x56 466#define EMU_SPCS_CLKACCYMASK 0x30000000 467#define EMU_SPCS_CLKACCY_1000PPM 0x00000000 468#define EMU_SPCS_CLKACCY_50PPM 0x10000000 469#define EMU_SPCS_CLKACCY_VARIABLE 0x20000000 470#define EMU_SPCS_SAMPLERATEMASK 0x0f000000 471#define EMU_SPCS_SAMPLERATE_44 0x00000000 472#define EMU_SPCS_SAMPLERATE_48 0x02000000 473#define EMU_SPCS_SAMPLERATE_32 0x03000000 474#define EMU_SPCS_CHANNELNUMMASK 0x00f00000 475#define EMU_SPCS_CHANNELNUM_UNSPEC 0x00000000 476#define EMU_SPCS_CHANNELNUM_LEFT 0x00100000 477#define EMU_SPCS_CHANNELNUM_RIGHT 0x00200000 478#define EMU_SPCS_SOURCENUMMASK 0x000f0000 479#define EMU_SPCS_SOURCENUM_UNSPEC 0x00000000 480#define EMU_SPCS_GENERATIONSTATUS 0x00008000 481#define EMU_SPCS_CATEGORYCODEMASK 0x00007f00 482#define EMU_SPCS_MODEMASK 0x000000c0 483#define EMU_SPCS_EMPHASISMASK 0x00000038 484#define EMU_SPCS_EMPHASIS_NONE 0x00000000 485#define EMU_SPCS_EMPHASIS_50_15 0x00000008 486#define EMU_SPCS_COPYRIGHT 0x00000004 487#define EMU_SPCS_NOTAUDIODATA 0x00000002 488#define EMU_SPCS_PROFESSIONAL 0x00000001 489 490#define EMU_CLIEL 0x58 491#define EMU_CLIEH 0x59 492#define EMU_CLIPL 0x5a 493#define EMU_CLIPH 0x5b 494#define EMU_SOLEL 0x5c 495#define EMU_SOLEH 0x5d 496 497#define EMU_SPBYPASS 0x5e 498#define EMU_SPBYPASS_ENABLE 0x00000001 499#define EMU_SPBYPASS_24_BITS 0x00000f00 500 501#define EMU_AC97SLOT 0x5f 502#define EMU_AC97SLOT_CENTER 0x00000010 503#define EMU_AC97SLOT_LFE 0x00000020 504 505#define EMU_CDSRCS 0x60 506#define EMU_GPSRCS 0x61 507#define EMU_ZVSRCS 0x62 508#define EMU_SRCS_SPDIFLOCKED 0x02000000 509#define EMU_SRCS_RATELOCKED 0x01000000 510#define EMU_SRCS_ESTSAMPLERATE 0x0007ffff 511 512#define EMU_MICIDX 0x63 513#define EMU_A_MICIDX 0x64 514#define EMU_ADCIDX 0x64 515#define EMU_A_ADCIDX 0x63 516#define EMU_FXIDX 0x65 517#define EMU_RECIDX_MASK 0x0000ffff 518#define EMU_RECIDX(idxreg) (0x10000000|(idxreg)) 519/* 520#define EMU_MICIDX_IDX 0x10000063 521#define EMU_ADCIDX_IDX 0x10000064 522#define EMU_FXIDX_IDX 0x10000065 523*/ 524 525#define EMU_A_MUDATA1 0x70 526#define EMU_A_MUCMD1 0x71 527#define EMU_A_MUSTAT1 EMU_A_MUCMD1 528#define EMU_A_MUDATA2 0x72 529#define EMU_A_MUCMD2 0x73 530#define EMU_A_MUSTAT2 EMU_A_MUCMD2 531#define EMU_A_FXWC1 0x74 532#define EMU_A_FXWC2 0x75 533#define EMU_A_SPDIF_SAMPLERATE 0x76 534#define EMU_A_SPDIF_48000 0x00000080 535#define EMU_A_SPDIF_44100 0x00000000 536#define EMU_A_SPDIF_96000 0x00000040 537#define EMU_A2_SPDIF_SAMPLERATE EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE) 538#define EMU_A2_SPDIF_MASK 0x00000e00 539#define EMU_A2_SPDIF_UNKNOWN 0x2 540 541#define EMU_A_CHAN_FXRT2 0x7c 542#define EMU_A_CHAN_FXRT_CHANNELE 0x0000003f 543#define EMU_A_CHAN_FXRT_CHANNELF 0x00003f00 544#define EMU_A_CHAN_FXRT_CHANNELG 0x003f0000 545#define EMU_A_CHAN_FXRT_CHANNELH 0x3f000000 546#define EMU_A_CHAN_SENDAMOUNTS 0x7d 547#define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK 0xff000000 548#define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK 0x00ff0000 549#define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK 0x0000ff00 550#define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK 0x000000ff 551#define EMU_A_CHAN_FXRT1 0x7e 552#define EMU_A_CHAN_FXRT_CHANNELA 0x0000003f 553#define EMU_A_CHAN_FXRT_CHANNELB 0x00003f00 554#define EMU_A_CHAN_FXRT_CHANNELC 0x003f0000 555#define EMU_A_CHAN_FXRT_CHANNELD 0x3f000000 556 557#define EMU_FXGPREGBASE 0x100 558#define EMU_A_FXGPREGBASE 0x400 559 560#define EMU_TANKMEMDATAREGBASE 0x200 561#define EMU_TANKMEMDATAREG_MASK 0x000fffff 562 563#define EMU_TANKMEMADDRREGBASE 0x300 564#define EMU_TANKMEMADDRREG_ADDR_MASK 0x000fffff 565#define EMU_TANKMEMADDRREG_CLEAR 0x00800000 566#define EMU_TANKMEMADDRREG_ALIGN 0x00400000 567#define EMU_TANKMEMADDRREG_WRITE 0x00200000 568#define EMU_TANKMEMADDRREG_READ 0x00100000 569 570#define EMU_MICROCODEBASE 0x400 571#define EMU_A_MICROCODEBASE 0x600 572#define EMU_DSP_LOWORD_OPX_MASK 0x000ffc00 573#define EMU_DSP_LOWORD_OPY_MASK 0x000003ff 574#define EMU_DSP_HIWORD_OPCODE_MASK 0x00f00000 575#define EMU_DSP_HIWORD_RESULT_MASK 0x000ffc00 576#define EMU_DSP_HIWORD_OPA_MASK 0x000003ff 577#define EMU_A_DSP_LOWORD_OPX_MASK 0x007ff000 578#define EMU_A_DSP_LOWORD_OPY_MASK 0x000007ff 579#define EMU_A_DSP_HIWORD_OPCODE_MASK 0x0f000000 580#define EMU_A_DSP_HIWORD_RESULT_MASK 0x007ff000 581#define EMU_A_DSP_HIWORD_OPA_MASK 0x000007ff 582 583#define EMU_DSP_OP_MACS 0x0 584#define EMU_DSP_OP_MACS1 0x1 585#define EMU_DSP_OP_MACW 0x2 586#define EMU_DSP_OP_MACW1 0x3 587#define EMU_DSP_OP_MACINTS 0x4 588#define EMU_DSP_OP_MACINTW 0x5 589#define EMU_DSP_OP_ACC3 0x6 590#define EMU_DSP_OP_MACMV 0x7 591#define EMU_DSP_OP_ANDXOR 0x8 592#define EMU_DSP_OP_TSTNEG 0x9 593#define EMU_DSP_OP_LIMIT 0xA 594#define EMU_DSP_OP_LIMIT1 0xB 595#define EMU_DSP_OP_LOG 0xC 596#define EMU_DSP_OP_EXP 0xD 597#define EMU_DSP_OP_INTERP 0xE 598#define EMU_DSP_OP_SKIP 0xF 599 600 601#define EMU_DSP_FX(num) (num) 602 603#define EMU_DSP_IOL(base, num) (base + (num << 1)) 604#define EMU_DSP_IOR(base, num) (EMU_DSP_IOL(base, num) + 1) 605 606#define EMU_DSP_INL_BASE 0x010 607#define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num)) 608#define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num)) 609#define EMU_A_DSP_INL_BASE 0x040 610#define EMU_A_DSP_INL(num) (EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num)) 611#define EMU_A_DSP_INR(num) (EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num)) 612#define EMU_DSP_IN_AC97 0 613#define EMU_DSP_IN_CDSPDIF 1 614#define EMU_DSP_IN_ZOOM 2 615#define EMU_DSP_IN_TOSOPT 3 616#define EMU_DSP_IN_LVDLM1 4 617#define EMU_DSP_IN_LVDCOS 5 618#define EMU_DSP_IN_LVDLM2 6 619#define EMU_DSP_IN_UNKNOWN 7 620 621#define EMU_DSP_OUTL_BASE 0x020 622#define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num)) 623#define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num)) 624#define EMU_DSP_OUT_A_FRONT 0 625#define EMU_DSP_OUT_D_FRONT 1 626#define EMU_DSP_OUT_D_CENTER 2 627#define EMU_DSP_OUT_DRIVE_HP 3 628#define EMU_DSP_OUT_AD_REAR 4 629#define EMU_DSP_OUT_ADC 5 630#define EMU_DSP_OUTL_MIC 6 631 632#define EMU_A_DSP_OUTL_BASE 0x060 633#define EMU_A_DSP_OUTL(num) (EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num)) 634#define EMU_A_DSP_OUTR(num) (EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num)) 635#define EMU_A_DSP_OUT_D_FRONT 0 636#define EMU_A_DSP_OUT_D_CENTER 1 637#define EMU_A_DSP_OUT_DRIVE_HP 2 638#define EMU_A_DSP_OUT_DREAR 3 639#define EMU_A_DSP_OUT_A_FRONT 4 640#define EMU_A_DSP_OUT_A_CENTER 5 641#define EMU_A_DSP_OUT_A_REAR 7 642#define EMU_A_DSP_OUT_ADC 11 643 644#define EMU_DSP_CST_BASE 0x40 645#define EMU_A_DSP_CST_BASE 0xc0 646#define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num) 647#define EMU_A_DSP_CST(num) (EMU_A_DSP_CST_BASE + num) 648/* 64900 = 0x00000000 65001 = 0x00000001 65102 = 0x00000002 65203 = 0x00000003 65304 = 0x00000004 65405 = 0x00000008 65506 = 0x00000010 65607 = 0x00000020 65708 = 0x00000100 65809 = 0x00010000 6590A = 0x00080000 6600B = 0x10000000 6610C = 0x20000000 6620D = 0x40000000 6630E = 0x80000000 6640F = 0x7FFFFFFF 66510 = 0xFFFFFFFF 66611 = 0xFFFFFFFE 66712 = 0xC0000000 66813 = 0x4F1BBCDC 66914 = 0x5A7EF9DB 67015 = 0x00100000 671*/ 672 673#define EMU_DSP_HWR_ACC 0x056 674#define EMU_DSP_HWR_CCR 0x057 675#define EMU_DSP_HWR_CCR_S 0x04 676#define EMU_DSP_HWR_CCR_Z 0x03 677#define EMU_DSP_HWR_CCR_M 0x02 678#define EMU_DSP_HWR_CCR_N 0x01 679#define EMU_DSP_HWR_CCR_B 0x00 680#define EMU_DSP_HWR_NOISE0 0x058 681#define EMU_DSP_HWR_NOISE1 0x059 682#define EMU_DSP_HWR_INTR 0x05A 683#define EMU_DSP_HWR_DBAC 0x05B 684 685#define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num) 686#define EMU_A_DSP_GPR(num) (EMU_A_FXGPREGBASE + num) 687 688#endif /* _DEV_PCI_EMUXKIREG_H_ */ 689