1/************************************************************************** 2 3Copyright (c) 2007, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29 30/* This file is automatically generated --- do not edit */ 31 32#ifndef _TCB_DEFS_H 33#define _TCB_DEFS_H 34 35#define W_TCB_T_STATE 0 36#define S_TCB_T_STATE 0 37#define M_TCB_T_STATE 0xfULL 38#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 39 40#define W_TCB_TIMER 0 41#define S_TCB_TIMER 4 42#define M_TCB_TIMER 0x1ULL 43#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) 44 45#define W_TCB_DACK_TIMER 0 46#define S_TCB_DACK_TIMER 5 47#define M_TCB_DACK_TIMER 0x1ULL 48#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) 49 50#define W_TCB_DEL_FLAG 0 51#define S_TCB_DEL_FLAG 6 52#define M_TCB_DEL_FLAG 0x1ULL 53#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) 54 55#define W_TCB_L2T_IX 0 56#define S_TCB_L2T_IX 7 57#define M_TCB_L2T_IX 0x7ffULL 58#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 59 60#define W_TCB_SMAC_SEL 0 61#define S_TCB_SMAC_SEL 18 62#define M_TCB_SMAC_SEL 0x3ULL 63#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 64 65#define W_TCB_TOS 0 66#define S_TCB_TOS 20 67#define M_TCB_TOS 0x3fULL 68#define V_TCB_TOS(x) ((x) << S_TCB_TOS) 69 70#define W_TCB_MAX_RT 0 71#define S_TCB_MAX_RT 26 72#define M_TCB_MAX_RT 0xfULL 73#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 74 75#define W_TCB_T_RXTSHIFT 0 76#define S_TCB_T_RXTSHIFT 30 77#define M_TCB_T_RXTSHIFT 0xfULL 78#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 79 80#define W_TCB_T_DUPACKS 1 81#define S_TCB_T_DUPACKS 2 82#define M_TCB_T_DUPACKS 0xfULL 83#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 84 85#define W_TCB_T_MAXSEG 1 86#define S_TCB_T_MAXSEG 6 87#define M_TCB_T_MAXSEG 0xfULL 88#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 89 90#define W_TCB_T_FLAGS1 1 91#define S_TCB_T_FLAGS1 10 92#define M_TCB_T_FLAGS1 0xffffffffULL 93#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1) 94 95#define W_TCB_T_FLAGS2 2 96#define S_TCB_T_FLAGS2 10 97#define M_TCB_T_FLAGS2 0x7fULL 98#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2) 99 100#define W_TCB_SND_SCALE 2 101#define S_TCB_SND_SCALE 17 102#define M_TCB_SND_SCALE 0xfULL 103#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 104 105#define W_TCB_RCV_SCALE 2 106#define S_TCB_RCV_SCALE 21 107#define M_TCB_RCV_SCALE 0xfULL 108#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 109 110#define W_TCB_SND_UNA_RAW 2 111#define S_TCB_SND_UNA_RAW 25 112#define M_TCB_SND_UNA_RAW 0x7ffffffULL 113#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 114 115#define W_TCB_SND_NXT_RAW 3 116#define S_TCB_SND_NXT_RAW 20 117#define M_TCB_SND_NXT_RAW 0x7ffffffULL 118#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW) 119 120#define W_TCB_RCV_NXT 4 121#define S_TCB_RCV_NXT 15 122#define M_TCB_RCV_NXT 0xffffffffULL 123#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT) 124 125#define W_TCB_RCV_ADV 5 126#define S_TCB_RCV_ADV 15 127#define M_TCB_RCV_ADV 0xffffULL 128#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 129 130#define W_TCB_SND_MAX_RAW 5 131#define S_TCB_SND_MAX_RAW 31 132#define M_TCB_SND_MAX_RAW 0x7ffffffULL 133#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW) 134 135#define W_TCB_SND_CWND 6 136#define S_TCB_SND_CWND 26 137#define M_TCB_SND_CWND 0x7ffffffULL 138#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND) 139 140#define W_TCB_SND_SSTHRESH 7 141#define S_TCB_SND_SSTHRESH 21 142#define M_TCB_SND_SSTHRESH 0x7ffffffULL 143#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH) 144 145#define W_TCB_T_RTT_TS_RECENT_AGE 8 146#define S_TCB_T_RTT_TS_RECENT_AGE 16 147#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 148#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 149 150#define W_TCB_T_RTSEQ_RECENT 9 151#define S_TCB_T_RTSEQ_RECENT 16 152#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 153#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 154 155#define W_TCB_T_SRTT 10 156#define S_TCB_T_SRTT 16 157#define M_TCB_T_SRTT 0xffffULL 158#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 159 160#define W_TCB_T_RTTVAR 11 161#define S_TCB_T_RTTVAR 0 162#define M_TCB_T_RTTVAR 0xffffULL 163#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 164 165#define W_TCB_TS_LAST_ACK_SENT_RAW 11 166#define S_TCB_TS_LAST_ACK_SENT_RAW 16 167#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL 168#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 169 170#define W_TCB_DIP 12 171#define S_TCB_DIP 11 172#define M_TCB_DIP 0xffffffffULL 173#define V_TCB_DIP(x) ((x) << S_TCB_DIP) 174 175#define W_TCB_SIP 13 176#define S_TCB_SIP 11 177#define M_TCB_SIP 0xffffffffULL 178#define V_TCB_SIP(x) ((x) << S_TCB_SIP) 179 180#define W_TCB_DP 14 181#define S_TCB_DP 11 182#define M_TCB_DP 0xffffULL 183#define V_TCB_DP(x) ((x) << S_TCB_DP) 184 185#define W_TCB_SP 14 186#define S_TCB_SP 27 187#define M_TCB_SP 0xffffULL 188#define V_TCB_SP(x) ((x) << S_TCB_SP) 189 190#define W_TCB_TIMESTAMP 15 191#define S_TCB_TIMESTAMP 11 192#define M_TCB_TIMESTAMP 0xffffffffULL 193#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 194 195#define W_TCB_TIMESTAMP_OFFSET 16 196#define S_TCB_TIMESTAMP_OFFSET 11 197#define M_TCB_TIMESTAMP_OFFSET 0xfULL 198#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 199 200#define W_TCB_TX_MAX 16 201#define S_TCB_TX_MAX 15 202#define M_TCB_TX_MAX 0xffffffffULL 203#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 204 205#define W_TCB_TX_HDR_PTR_RAW 17 206#define S_TCB_TX_HDR_PTR_RAW 15 207#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 208#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 209 210#define W_TCB_TX_LAST_PTR_RAW 18 211#define S_TCB_TX_LAST_PTR_RAW 0 212#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 213#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW) 214 215#define W_TCB_TX_COMPACT 18 216#define S_TCB_TX_COMPACT 17 217#define M_TCB_TX_COMPACT 0x1ULL 218#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT) 219 220#define W_TCB_RX_COMPACT 18 221#define S_TCB_RX_COMPACT 18 222#define M_TCB_RX_COMPACT 0x1ULL 223#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT) 224 225#define W_TCB_RCV_WND 18 226#define S_TCB_RCV_WND 19 227#define M_TCB_RCV_WND 0x7ffffffULL 228#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND) 229 230#define W_TCB_RX_HDR_OFFSET 19 231#define S_TCB_RX_HDR_OFFSET 14 232#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL 233#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET) 234 235#define W_TCB_RX_FRAG0_START_IDX_RAW 20 236#define S_TCB_RX_FRAG0_START_IDX_RAW 9 237#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL 238#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW) 239 240#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21 241#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4 242#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL 243#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 244 245#define W_TCB_RX_FRAG0_LEN 21 246#define S_TCB_RX_FRAG0_LEN 31 247#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL 248#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN) 249 250#define W_TCB_RX_FRAG1_LEN 22 251#define S_TCB_RX_FRAG1_LEN 26 252#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL 253#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN) 254 255#define W_TCB_NEWRENO_RECOVER 23 256#define S_TCB_NEWRENO_RECOVER 21 257#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL 258#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER) 259 260#define W_TCB_PDU_HAVE_LEN 24 261#define S_TCB_PDU_HAVE_LEN 16 262#define M_TCB_PDU_HAVE_LEN 0x1ULL 263#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN) 264 265#define W_TCB_PDU_LEN 24 266#define S_TCB_PDU_LEN 17 267#define M_TCB_PDU_LEN 0xffffULL 268#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 269 270#define W_TCB_RX_QUIESCE 25 271#define S_TCB_RX_QUIESCE 1 272#define M_TCB_RX_QUIESCE 0x1ULL 273#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE) 274 275#define W_TCB_RX_PTR_RAW 25 276#define S_TCB_RX_PTR_RAW 2 277#define M_TCB_RX_PTR_RAW 0x1ffffULL 278#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW) 279 280#define W_TCB_CPU_NO 25 281#define S_TCB_CPU_NO 19 282#define M_TCB_CPU_NO 0x7fULL 283#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO) 284 285#define W_TCB_ULP_TYPE 25 286#define S_TCB_ULP_TYPE 26 287#define M_TCB_ULP_TYPE 0xfULL 288#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 289 290#define W_TCB_RX_FRAG1_PTR_RAW 25 291#define S_TCB_RX_FRAG1_PTR_RAW 30 292#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 293#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 294 295#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 296#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 297#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL 298#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 299 300#define W_TCB_RX_FRAG2_PTR_RAW 27 301#define S_TCB_RX_FRAG2_PTR_RAW 10 302#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 303#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 304 305#define W_TCB_RX_FRAG2_LEN_RAW 27 306#define S_TCB_RX_FRAG2_LEN_RAW 27 307#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL 308#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW) 309 310#define W_TCB_RX_FRAG3_PTR_RAW 28 311#define S_TCB_RX_FRAG3_PTR_RAW 22 312#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 313#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW) 314 315#define W_TCB_RX_FRAG3_LEN_RAW 29 316#define S_TCB_RX_FRAG3_LEN_RAW 7 317#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL 318#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW) 319 320#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 321#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2 322#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL 323#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 324 325#define W_TCB_PDU_HDR_LEN 30 326#define S_TCB_PDU_HDR_LEN 29 327#define M_TCB_PDU_HDR_LEN 0xffULL 328#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 329 330#define W_TCB_SLUSH1 31 331#define S_TCB_SLUSH1 5 332#define M_TCB_SLUSH1 0x7ffffULL 333#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1) 334 335#define W_TCB_ULP_RAW 31 336#define S_TCB_ULP_RAW 24 337#define M_TCB_ULP_RAW 0xffULL 338#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 339 340#define W_TCB_DDP_RDMAP_VERSION 25 341#define S_TCB_DDP_RDMAP_VERSION 30 342#define M_TCB_DDP_RDMAP_VERSION 0x1ULL 343#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION) 344 345#define W_TCB_MARKER_ENABLE_RX 25 346#define S_TCB_MARKER_ENABLE_RX 31 347#define M_TCB_MARKER_ENABLE_RX 0x1ULL 348#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX) 349 350#define W_TCB_MARKER_ENABLE_TX 26 351#define S_TCB_MARKER_ENABLE_TX 0 352#define M_TCB_MARKER_ENABLE_TX 0x1ULL 353#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX) 354 355#define W_TCB_CRC_ENABLE 26 356#define S_TCB_CRC_ENABLE 1 357#define M_TCB_CRC_ENABLE 0x1ULL 358#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE) 359 360#define W_TCB_IRS_ULP 26 361#define S_TCB_IRS_ULP 2 362#define M_TCB_IRS_ULP 0x1ffULL 363#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 364 365#define W_TCB_ISS_ULP 26 366#define S_TCB_ISS_ULP 11 367#define M_TCB_ISS_ULP 0x1ffULL 368#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 369 370#define W_TCB_TX_PDU_LEN 26 371#define S_TCB_TX_PDU_LEN 20 372#define M_TCB_TX_PDU_LEN 0x3fffULL 373#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 374 375#define W_TCB_TX_PDU_OUT 27 376#define S_TCB_TX_PDU_OUT 2 377#define M_TCB_TX_PDU_OUT 0x1ULL 378#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT) 379 380#define W_TCB_CQ_IDX_SQ 27 381#define S_TCB_CQ_IDX_SQ 3 382#define M_TCB_CQ_IDX_SQ 0xffffULL 383#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 384 385#define W_TCB_CQ_IDX_RQ 27 386#define S_TCB_CQ_IDX_RQ 19 387#define M_TCB_CQ_IDX_RQ 0xffffULL 388#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 389 390#define W_TCB_QP_ID 28 391#define S_TCB_QP_ID 3 392#define M_TCB_QP_ID 0xffffULL 393#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 394 395#define W_TCB_PD_ID 28 396#define S_TCB_PD_ID 19 397#define M_TCB_PD_ID 0xffffULL 398#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 399 400#define W_TCB_STAG 29 401#define S_TCB_STAG 3 402#define M_TCB_STAG 0xffffffffULL 403#define V_TCB_STAG(x) ((x) << S_TCB_STAG) 404 405#define W_TCB_RQ_START 30 406#define S_TCB_RQ_START 3 407#define M_TCB_RQ_START 0x3ffffffULL 408#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 409 410#define W_TCB_RQ_MSN 30 411#define S_TCB_RQ_MSN 29 412#define M_TCB_RQ_MSN 0x3ffULL 413#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN) 414 415#define W_TCB_RQ_MAX_OFFSET 31 416#define S_TCB_RQ_MAX_OFFSET 7 417#define M_TCB_RQ_MAX_OFFSET 0xfULL 418#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 419 420#define W_TCB_RQ_WRITE_PTR 31 421#define S_TCB_RQ_WRITE_PTR 11 422#define M_TCB_RQ_WRITE_PTR 0x3ffULL 423#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 424 425#define W_TCB_INB_WRITE_PERM 31 426#define S_TCB_INB_WRITE_PERM 21 427#define M_TCB_INB_WRITE_PERM 0x1ULL 428#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM) 429 430#define W_TCB_INB_READ_PERM 31 431#define S_TCB_INB_READ_PERM 22 432#define M_TCB_INB_READ_PERM 0x1ULL 433#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM) 434 435#define W_TCB_ORD_L_BIT_VLD 31 436#define S_TCB_ORD_L_BIT_VLD 23 437#define M_TCB_ORD_L_BIT_VLD 0x1ULL 438#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 439 440#define W_TCB_RDMAP_OPCODE 31 441#define S_TCB_RDMAP_OPCODE 24 442#define M_TCB_RDMAP_OPCODE 0xfULL 443#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 444 445#define W_TCB_TX_FLUSH 31 446#define S_TCB_TX_FLUSH 28 447#define M_TCB_TX_FLUSH 0x1ULL 448#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 449 450#define W_TCB_TX_OOS_RXMT 31 451#define S_TCB_TX_OOS_RXMT 29 452#define M_TCB_TX_OOS_RXMT 0x1ULL 453#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 454 455#define W_TCB_TX_OOS_TXMT 31 456#define S_TCB_TX_OOS_TXMT 30 457#define M_TCB_TX_OOS_TXMT 0x1ULL 458#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 459 460#define W_TCB_SLUSH_AUX2 31 461#define S_TCB_SLUSH_AUX2 31 462#define M_TCB_SLUSH_AUX2 0x1ULL 463#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2) 464 465#define W_TCB_RX_FRAG1_PTR_RAW2 25 466#define S_TCB_RX_FRAG1_PTR_RAW2 30 467#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL 468#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2) 469 470#define W_TCB_RX_DDP_FLAGS 26 471#define S_TCB_RX_DDP_FLAGS 15 472#define M_TCB_RX_DDP_FLAGS 0xffffULL 473#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS) 474 475#define W_TCB_SLUSH_AUX3 26 476#define S_TCB_SLUSH_AUX3 31 477#define M_TCB_SLUSH_AUX3 0x1ffULL 478#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3) 479 480#define W_TCB_RX_DDP_BUF0_OFFSET 27 481#define S_TCB_RX_DDP_BUF0_OFFSET 8 482#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL 483#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 484 485#define W_TCB_RX_DDP_BUF0_LEN 27 486#define S_TCB_RX_DDP_BUF0_LEN 30 487#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL 488#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN) 489 490#define W_TCB_RX_DDP_BUF1_OFFSET 28 491#define S_TCB_RX_DDP_BUF1_OFFSET 20 492#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL 493#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 494 495#define W_TCB_RX_DDP_BUF1_LEN 29 496#define S_TCB_RX_DDP_BUF1_LEN 10 497#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL 498#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 499 500#define W_TCB_RX_DDP_BUF0_TAG 30 501#define S_TCB_RX_DDP_BUF0_TAG 0 502#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 503#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 504 505#define W_TCB_RX_DDP_BUF1_TAG 31 506#define S_TCB_RX_DDP_BUF1_TAG 0 507#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 508#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 509 510#define S_TF_DACK 10 511#define V_TF_DACK(x) ((x) << S_TF_DACK) 512 513#define S_TF_NAGLE 11 514#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 515 516#define S_TF_RECV_SCALE 12 517#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE) 518 519#define S_TF_RECV_TSTMP 13 520#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP) 521 522#define S_TF_RECV_SACK 14 523#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK) 524 525#define S_TF_TURBO 15 526#define V_TF_TURBO(x) ((x) << S_TF_TURBO) 527 528#define S_TF_KEEPALIVE 16 529#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 530 531#define S_TF_TCAM_BYPASS 17 532#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS) 533 534#define S_TF_CORE_FIN 18 535#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 536 537#define S_TF_CORE_MORE 19 538#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 539 540#define S_TF_MIGRATING 20 541#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 542 543#define S_TF_ACTIVE_OPEN 21 544#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN) 545 546#define S_TF_ASK_MODE 22 547#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE) 548 549#define S_TF_NON_OFFLOAD 23 550#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 551 552#define S_TF_MOD_SCHD 24 553#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD) 554 555#define S_TF_MOD_SCHD_REASON0 25 556#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0) 557 558#define S_TF_MOD_SCHD_REASON1 26 559#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1) 560 561#define S_TF_MOD_SCHD_RX 27 562#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX) 563 564#define S_TF_CORE_PUSH 28 565#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 566 567#define S_TF_RCV_COALESCE_ENABLE 29 568#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 569 570#define S_TF_RCV_COALESCE_PUSH 30 571#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 572 573#define S_TF_RCV_COALESCE_LAST_PSH 31 574#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 575 576#define S_TF_RCV_COALESCE_HEARTBEAT 32 577#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT) 578 579#define S_TF_LOCK_TID 33 580#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 581 582#define S_TF_DACK_MSS 34 583#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 584 585#define S_TF_CCTRL_SEL0 35 586#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 587 588#define S_TF_CCTRL_SEL1 36 589#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 590 591#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37 592#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY) 593 594#define S_TF_TX_PACE_AUTO 38 595#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 596 597#define S_TF_PEER_FIN_HELD 39 598#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD) 599 600#define S_TF_CORE_URG 40 601#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 602 603#define S_TF_RDMA_ERROR 41 604#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR) 605 606#define S_TF_SSWS_DISABLED 42 607#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 608 609#define S_TF_DUPACK_COUNT_ODD 43 610#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD) 611 612#define S_TF_TX_CHANNEL 44 613#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL) 614 615#define S_TF_RX_CHANNEL 45 616#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 617 618#define S_TF_TX_PACE_FIXED 46 619#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 620 621#define S_TF_RDMA_FLM_ERROR 47 622#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR) 623 624#define S_TF_RX_FLOW_CONTROL_DISABLE 48 625#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 626 627#define S_TF_DDP_INDICATE_OUT 15 628#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 629 630#define S_TF_DDP_ACTIVE_BUF 16 631#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 632 633#define S_TF_DDP_BUF0_VALID 17 634#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 635 636#define S_TF_DDP_BUF1_VALID 18 637#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID) 638 639#define S_TF_DDP_BUF0_INDICATE 19 640#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 641 642#define S_TF_DDP_BUF1_INDICATE 20 643#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE) 644 645#define S_TF_DDP_PUSH_DISABLE_0 21 646#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 647 648#define S_TF_DDP_PUSH_DISABLE_1 22 649#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1) 650 651#define S_TF_DDP_OFF 23 652#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 653 654#define S_TF_DDP_WAIT_FRAG 24 655#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 656 657#define S_TF_DDP_BUF_INF 25 658#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 659 660#define S_TF_DDP_RX2TX 26 661#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 662 663#define S_TF_DDP_BUF0_FLUSH 27 664#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 665 666#define S_TF_DDP_BUF1_FLUSH 28 667#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH) 668 669#define S_TF_DDP_PSH_NO_INVALIDATE 29 670#define V_TF_DDP_PSH_NO_INVALIDATE(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE) 671 672#endif /* _TCB_DEFS_H */ 673