1/* $NetBSD: z8536reg.h,v 1.2 2008/05/23 10:46:53 hauke Exp $ */ 2 3/*- 4 * Copyright (c) 2008 Hauke Fath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * Zilog Z8536 CIO (Counter/Timer and Parallel I/O Unit) 29 * Register Definitions 30 * 31 * The CIO has four registers: One control register, and three data 32 * registers for ports A/B/C. To set up the CIO through the control 33 * register, first write the number of the internal register to it, 34 * then access or set the selected register contents. Once selected, 35 * an internal register can be polled continuously by reading out the 36 * control port. 37 * 38 * Internal registers are read-writable, except where noted. 39 */ 40#define Z8536_IOSIZE 0x04 41 42#define Z8536_MICR 0x00 /* Master Interrupt Control Register */ 43#define MICR_RESET 0x01 /* Chip Reset */ 44#define MICR_RJA 0x02 /* Only z8036 (ZBUS version) */ 45#define MICR_CTVIS 0x04 /* CT vector includes status */ 46#define MICR_PBVIS 0x08 /* Port B vector includes status */ 47#define MICR_PAVIS 0x10 /* Port A vector includes status */ 48#define MICR_NV 0x20 /* No Vector (NV) */ 49#define MICR_DLC 0x40 /* Disable Lower Chain (DLC) */ 50#define MICR_MIE 0x80 /* Master Interrupt Enable (MIE) */ 51 52#define Z8536_MCCR 0x01 /* Master Configuration Register */ 53#define MCCR_CTINDPT 0x00 /* Counter/Timers Independent */ 54#define MCCR_CT1GT2 0x01 /* CT 1 /OUTPUT gates CT 2 */ 55#define MCCR_CT1TR2 0x02 /* CT 1 /OUTPUT triggers CT 2 */ 56#define MCCR_CT1CT2 0x03 /* CT 1 /OUTPUT is CT 2's COUNT */ 57#define MCCR_PAE 0x04 /* Port A Enable */ 58#define MCCR_PLC 0x08 /* Port Link Control (A/B) */ 59#define MCCR_PC_CT3E 0x10 /* Counter/Timer 3 + Port C Enable */ 60#define MCCR_CT2E 0x20 /* Counter/Timer 2 Enable */ 61#define MCCR_CT1E 0x40 /* Counter/Timer 1 Enable */ 62#define MCCR_PBE 0x80 /* Port B Enable */ 63 64/* Interrupt Vector Registers */ 65#define Z8536_IVRA 0x02 /* Port A Interrupt Vector */ 66#define Z8536_IVRB 0x03 /* Port B Interrupt Vector */ 67#define Z8536_IVRCT 0x04 /* Counter/Timer Interrupt Vector */ 68 69/* Port C setup */ 70#define Z8536_DPPRC 0x05 /* Port C Data Path Polarity */ 71#define Z8536_DDRC 0x06 /* Port C Data Direction */ 72#define Z8536_SIOCRC 0x07 /* Port C Special I/O Control */ 73 74#define Z8536_PCSRA 0x08 /* Port A Command and Status */ 75#define Z8536_PCSRB 0x09 /* Port B Command and Status */ 76 77/* Z8536_PCSRA + Z8536_PCSRB command and status bits */ 78#define PCSR_IOE 0x01 /* Interrupt on error */ 79#define PCSR_PMF 0x02 /* Pattern match flag (RO) */ 80#define PCSR_IRF 0x04 /* Input register full (RO) */ 81#define PCSR_ORE 0x08 /* Output register empty (RO) */ 82#define PCSR_ERR 0x10 /* Interrupt error */ 83#define PCSR_IP 0x20 /* Interrupt pending */ 84#define PCSR_IE 0x40 /* Interrupt enable */ 85#define PCSR_IUS 0x80 /* Interrupt under service */ 86/* PCSR{A,B} interrupt bits: IUS/IE/IP */ 87#define PCSR_NULL 0x00 /* Null Code */ 88#define PCSR_CLR_IP_IUS 0x20 /* Clear IP and IUS */ 89#define PCSR_SET_IUS 0x40 /* Set Interrupt Under Service */ 90#define PCSR_CLR_IUS 0x60 /* Clear Interrupt Under Service */ 91#define PCSR_SET_IP 0x80 /* Set Interrupt Pending */ 92#define PCSR_CLR_IP 0xA0 /* Clear Interrupt Pending */ 93#define PCSR_SET_IE 0xC0 /* Set Interrupt Enable */ 94#define PCSR_CLR_IE 0xE0 /* Clear Interrupt Enable */ 95 96/* Counter/Timer 1..3 Command and Status Registers */ 97#define Z8536_CTCSR1 0x0A /* CT 1 Command and Status */ 98#define Z8536_CTCSR2 0x0B /* CT 2 Command and Status */ 99#define Z8536_CTCSR3 0x0C /* CT 3 Command and Status */ 100 101/* CTCSR setup bits */ 102#define CTCS_CIP 0x01 /* Count in Progress (RO) */ 103#define CTCS_TCB 0x02 /* Trigger Command Bit (WO) */ 104#define CTCS_GCB 0x04 /* Gate Command Bit */ 105#define CTCS_RCC 0x08 /* Read Counter Control */ 106#define CTCS_ERR 0x10 /* Interrupt Error (RO) */ 107#define CTCS_IP 0x20 /* Interrupt Pending */ 108#define CTCS_IE 0x40 /* Interrupt Enable */ 109#define CTCS_IUS 0x80 /* Interrupt Under Service */ 110 111/* CTCSR interrupt bits: IUS/IE/IP */ 112#define CTCS_NULL 0x00 /* Null Code */ 113#define CTCS_CLR_IP_IUS 0x20 /* Clear IP and IUS */ 114#define CTCS_SET_IUS 0x40 /* Set Interrupt Under Service */ 115#define CTCS_CLR_IUS 0x60 /* Clear Interrupt Under Service */ 116#define CTCS_SET_IP 0x80 /* Set Interrupt Pending */ 117#define CTCS_CLR_IP 0xA0 /* Clear Interrupt Pending */ 118#define CTCS_SET_IE 0xC0 /* Set Interrupt Enable */ 119#define CTCS_CLR_IE 0xE0 /* Clear Interrupt Enable */ 120 121/* Avoid changing intr bits unintendedly */ 122#define CTCSR_MASK(FLAGS) ((FLAGS) & 0x3f) 123 124/* The port data registers are directly accessible at their own IO address */ 125#define Z8536_PDRA 0x0D /* Port A Data Register */ 126#define Z8536_PDRB 0x0E /* Port B Data Register */ 127#define Z8536_PDRC 0x0F /* Port C Data Register */ 128 129/* Bytewise access to current count registers (read-only) */ 130#define Z8536_CTCCR1_MSB 0x10 /* CT 1 Current Count MSB */ 131#define Z8536_CTCCR1_LSB 0x11 /* CT 1 Current Count LSB */ 132#define Z8536_CTCCR2_MSB 0x12 /* CT 2 Current Count MSB */ 133#define Z8536_CTCCR2_LSB 0x13 /* CT 2 Current Count LSB */ 134#define Z8536_CTCCR3_MSB 0x14 /* CT 3 Current Count MSB */ 135#define Z8536_CTCCR3_LSB 0x15 /* CT 3 Current Count LSB */ 136 137/* Bytewise access to time constant registers */ 138#define Z8536_CTTCR1_MSB 0x16 /* CT 1 Time Constant MSB */ 139#define Z8536_CTTCR1_LSB 0x17 /* CT 1 Time Constant LSB */ 140#define Z8536_CTTCR2_MSB 0x18 /* CT 2 Time Constant MSB */ 141#define Z8536_CTTCR2_LSB 0x19 /* CT 2 Time Constant LSB */ 142#define Z8536_CTTCR3_MSB 0x1A /* CT 3 Time Constant MSB */ 143#define Z8536_CTTCR3_LSB 0x1B /* CT 3 Time Constant LSB */ 144 145/* Counter/Timer Mode specification */ 146#define Z8536_CTMSR1 0x1C /* CT 1 Mode Specification */ 147#define Z8536_CTMSR2 0x1D /* CT 2 Mode Specification */ 148#define Z8536_CTMSR3 0x1E /* CT 3 Mode Specification */ 149#define CTMS_DCS_PULSE 0x00 /* Pulse Output */ 150#define CTMS_DCS_ONESHOT 0x01 /* One-Shot Output */ 151#define CTMS_DCS_SQUARE 0x02 /* Square Wave Output */ 152#define CTMS_REB 0x04 /* Retrigger Enable */ 153#define CTMS_EGE 0x08 /* External Gate Enable */ 154#define CTMS_ETE 0x10 /* External Trigger Enable */ 155#define CTMS_ECE 0x20 /* External Count Enable */ 156#define CTMS_EOE 0x40 /* External Output Enable */ 157#define CTMS_CSC 0x80 /* Continuous / Single Cycle */ 158 159#define Z8536_CVR 0x1F /* Current Interrupt Vector (RO) */ 160 161/* Port A specification registers */ 162#define Z8536_PMSRA 0x20 /* Port A Mode Specification */ 163#define Z8536_PHSRA 0x21 /* Port A Handshake Specification */ 164#define Z8536_DPPRA 0x22 /* Port A Data Path Polarity */ 165#define Z8536_DDRA 0x23 /* Port A Data Direction */ 166#define Z8536_SIOCRA 0x24 /* Port A Special I/O Control */ 167#define Z8536_PPRA 0x25 /* Port A Pattern Polarity */ 168#define Z8536_PTRA 0x26 /* Port A Pattern Transition */ 169#define Z8536_PMRA 0x27 /* Port A Pattern Mask */ 170 171/* Port B specification registers */ 172#define Z8536_PMSRB 0x28 /* Port B Mode Specification */ 173#define Z8536_PHSRB 0x29 /* Port B Handshake Specification */ 174#define Z8536_DPPRB 0x2A /* Port B Data Path Polarity */ 175#define Z8536_DDRB 0x2B /* Port B Data Direction */ 176#define Z8536_SIOCRB 0x2C /* Port B Special I/O Control */ 177#define Z8536_PPRB 0x2D /* Port B Pattern Polarity */ 178#define Z8536_PTRB 0x2E /* Port B Pattern Transition */ 179#define Z8536_PMRB 0x2F /* Port B Pattern Mask */ 180 181/* Bit definitions, common to ports A and B */ 182 183/* Z8536_PMSRA + Z8536_PMSRB port mode specification bits */ 184#define PMSR_LPM 0x01 /* Bit mode: latched */ 185#define PMSR_DTE 0x01 /* Hsk mode: deskew timer enable */ 186/* 187 * PMS1 PMS0 Pattern mode specification 188 * 0 0 disable pattern match 189 * 0 1 "and" mode, transition-triggered interrupt 190 * 1 0 "or" mode, transition-triggered interrupt 191 * 1 1 "or-priority encoded vector" mode, level- 192 * triggered interrupt (only transparent LPM mode) 193 */ 194#define PMSR_PMS0 0x02 195#define PMSR_PMS1 0x04 196#define PMSR_PMS_OFF 0x00 /* Disable pattern match */ 197#define PMSR_PMS_AND 0x02 /* "and" mode, transition-triggered */ 198#define PMSR_PMS_OR 0x04 /* "or" mode, transition-triggered */ 199/* 200 * "or-priority encoded vector" mode, level-triggered interrupt 201 * (only in transparent LPM mode) 202 */ 203#define PMSR_PMS_OR_PEV 0x06 204#define PMSR_IMO 0x08 /* Interrupt on match only */ 205#define PMSR_SB 0x10 /* Single buffered mode */ 206#define PMSR_ITB 0x20 /* Interrupt on two bytes */ 207/* 208 * PTS1 PTS0 Port type selects 209 * 0 0 bit port 210 * 0 1 input port 211 * 1 0 output port 212 * 1 1 bidirectional port 213 */ 214#define PMSR_PTS0 0x40 215#define PMSR_PTS1 0x80 216#define PMSR_PTS_BIT 0x00 217#define PMSR_PTS_IN 0x40 218#define PMSR_PTS_OUT 0x80 219#define PMSR_PTS_BIDI 0xC0 220/* 221 * Z8536_PHSRA + Z8536_PHSRB port handshake specification bits 222 * Bits 0-2 set deskew timer for output ports 223 * 224 * RWS2 RWS1 RWS0 Status signals on port C 225 * 0 0 0 REQUEST/-WAIT disabled 226 * 0 0 1 output -WAIT 227 * 0 1 1 input -WAIT 228 * 1 0 0 special REQUEST 229 * 1 0 1 output REQUEST 230 * 1 1 1 input REQUEST 231 */ 232#define PHSR_RWS0 0x08 233#define PHSR_RWS1 0x10 234#define PHSR_RWS2 0x20 235/* 236 * HTS1 HTS0 Handshake type specification 237 * 0 0 interlocked handshake 238 * 0 1 strobed handshake 239 * 1 0 pulsed handshake 240 * 1 1 three-wire-handshake 241 */ 242#define PHSR_HTS0 0x40 243#define PHSR_HTS1 0x80 244#define PHSR_HTS_INT 0x00 245#define PHSR_HTS_STR 0x40 246#define PHSR_HTS_PUL 0x80 247#define PHSR_HTS_TWI 0xC0 248