1/* $NetBSD$ */ 2 3/* 4 * Ben Harris, 2001 5 * 6 * This file is in the public domain. 7 */ 8 9/* mc6854reg.h - Motorola 6854 Advanced Data Link Controller registers */ 10 11/* 12 * The 6854 has two address lines, and uses one of the bits of CR1 as 13 * an additional register select. 14 */ 15#define MC6854_CR1 0 /* Control Register #1 (W) */ 16#define MC6854_CR2 1 /* Control Register #2 (W) (AC = 0) */ 17#define MC6854_CR3 1 /* Control Register #3 (W) (AC = 1) */ 18#define MC6854_TXFIFOFC 2 /* Transmit FIFO (Frame Continue) (W) */ 19#define MC6854_TXFIFOFT 3 /* Transmit FIFO (Frame Terminate) (W) (AC = 0) */ 20#define MC6854_CR4 3 /* Control Register #4 (W) (AC = 1) */ 21 22#define MC6854_SR1 0 /* Status Register #1 (R) */ 23#define MC6854_SR2 1 /* Status Register #2 (R) */ 24#define MC6854_RXFIFO 2 /* Receiver FIFO (R) */ 25 26/* Control Regsiter #1 bits */ 27#define MC6854_CR1_AC 0x01 /* Address Control */ 28#define MC6854_CR1_RIE 0x02 /* Receiver Interrupt Enable */ 29#define MC6854_CR1_TIE 0x04 /* Transmitter Interrupt Enable */ 30#define MC6854_CR1_RDSR_MODE 0x08 /* Receiver Data Service Request Mode */ 31#define MC6854_CR1_TDSR_MODE 0x10 /* Transmitter Data Service Request Mode*/ 32#define MC6854_CR1_DISCONTINUE 0x20 /* Rx Frame Discontinue */ 33#define MC6854_CR1_RX_RS 0x40 /* Receiver Reset */ 34#define MC6854_CR1_TX_RS 0x80 /* Transmitter Reset */ 35#define MC6854_CR1_BITS \ 36 "\20\1AC\2RIE\3TIE\4RDSR_MODE\5TDSR_MODE\6DISCONTINUE\7RX_RS\10TX_RS" 37 38/* Control Register #2 bits */ 39#define MC6854_CR2_PSE 0x01 /* Prioritized Status Enable */ 40#define MC6854_CR2_2_1_BYTE 0x02 /* 2-Byte/1-Byte Transfer */ 41#define MC6854_CR2_F_M_IDLE 0x04 /* Flag/Mark Idle Select */ 42#define MC6854_CR2_FC_TDRA_SEL 0x08 /* Frame Complete/TDRA Select */ 43#define MC6854_CR2_TX_LAST 0x10 /* Transmit Last Data */ 44#define MC6854_CR2_CLR_RX_ST 0x20 /* Clear Receiver Status */ 45#define MC6854_CR2_CLR_TX_ST 0x40 /* Clear Transmitter Status */ 46#define MC6854_CR2_RTS 0x80 /* Request-to-Send Control */ 47#define MC6854_CR2_BITS \ 48 "\20\1PSE\22_1_BYTE\3F_M_IDLE\4RC_TDRA_SEL" \ 49 "\5TX_LAST\6CLR_RX_ST\7CLR_TX_ST\10RTS" 50 51/* Control Register #3 bits */ 52#define MC6854_CR3_LCF 0x01 /* Logical Control Field Select */ 53#define MC6854_CR3_CEX 0x02 /* Extended Control Field Select */ 54#define MC6854_CR3_AEX 0x04 /* Auto/Address Extend Mode */ 55#define MC6854_CR3_00_01_IDLE 0x08 /* 00/01 Idle */ 56#define MC6854_CR3_FDSE 0x10 /* Flag Detect Status Enable */ 57#define MC6854_CR3_LOOP 0x20 /* LOOP/NON-LOOP Mode */ 58#define MC6854_CR3_GAP_TST 0x40 /* Go Active On Poll/Test */ 59#define MC6854_CR3_LOC_DTR 0x80 /* Loop On-Line Control/DTR Control */ 60#define MC6854_CR3_BITS \ 61 "\20\1LCF\2CEX\3AEX\400_01_IDLE\5FDSE\6LOOP\7GAP_TST\10LOC_DTR" 62 63/* Control Register #4 bits */ 64#define MC6854_CR4_FF_F 0x01 /* Double/Single Flag Interframe Control*/ 65#define MC6854_CR4_TX_WL_MASK 0x06 /* Transmitter Word Length Select: */ 66#define MC6854_CR4_TX_WL_5BITS 0x00 /* 5 bits */ 67#define MC6854_CR4_TX_WL_6BITS 0x02 /* 6 bits */ 68#define MC6854_CR4_TX_WL_7BITS 0x04 /* 7 bits */ 69#define MC6854_CR4_TX_WL_8BITS 0x06 /* 8 bits */ 70#define MC6854_CR4_RX_WL_MASK 0x18 /* Receiver Word Length Select: */ 71#define MC6854_CR4_RX_WL_5BITS 0x00 /* 5 bits */ 72#define MC6854_CR4_RX_WL_6BITS 0x08 /* 6 bits */ 73#define MC6854_CR4_RX_WL_7BITS 0x10 /* 7 bits */ 74#define MC6854_CR4_RX_WL_8BITS 0x18 /* 8 bits */ 75#define MC6854_CR4_ABT 0x20 /* Transmit Abort */ 76#define MC6854_CR4_ABTEX 0x40 /* Abort Extend */ 77#define MC6854_CR4_NRZI_NRZ 0x80 /* NRZI (Zero Complement)/NRZ Select */ 78 79/* Status Register #1 bits */ 80#define MC6854_SR1_RDA 0x01 /* Receiver Data Available */ 81#define MC6854_SR1_S2RQ 0x02 /* Status Register #2 Read Request */ 82#define MC6854_SR1_LOOP 0x04 /* Loop Status */ 83#define MC6854_SR1_FD 0x08 /* Flag Detected */ 84#define MC6854_SR1_NCTS 0x10 /* not Clear-to-Send */ 85#define MC6854_SR1_TXU 0x20 /* Transmitter Underrun */ 86#define MC6854_SR1_TDRA 0x40 /* Transmitter Data Register Available */ 87#define MC6854_SR1_FC 0x40 /* Frame Complete */ 88#define MC6854_SR1_IRQ 0x80 /* Interrupt Request */ 89 90#define MC6854_SR1_BITS "\20\1RDA\2S2RQ\3LOOP\4FD\5NCTS\6TXU\7TDRA_FC\10IRQ" 91 92/* Status Register #2 bits */ 93#define MC6854_SR2_AP 0x01 /* Address Present */ 94#define MC6854_SR2_FV 0x02 /* Frame Valid */ 95#define MC6854_SR2_RX_IDLE 0x04 /* Inactive Idle Received */ 96#define MC6854_SR2_RXABT 0x08 /* Abort Received */ 97#define MC6854_SR2_ERR 0x10 /* FCS/Invalid Frame Error */ 98#define MC6854_SR2_NDCD 0x20 /* not Data Carrier Detect */ 99#define MC6854_SR2_OVRN 0x40 /* Receiver Overrun */ 100#define MC6854_SR2_RDA 0x80 /* Receiver Data Available */ 101 102#define MC6854_SR2_BITS "\20\1AP\2FV\3RX_IDLE\4RXABT\5ERR\6NDCD\7OVRN\10RDA" 103 104