1/*
2 * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 *---------------------------------------------------------------------------
26 *
27 *	i4b_ipac.h - definitions for the Siemens IPAC PSB2115 chip
28 *	==========================================================
29 *
30 *	$Id: ipac.h,v 1.4 2011/08/07 20:05:08 jakllsch Exp $
31 *
32 *      last edit-date: [Thu Jan  6 14:54:19 2000]
33 *
34 *---------------------------------------------------------------------------
35 */
36
37#ifndef _I4B_IPAC_H_
38#define _I4B_IPAC_H_
39
40#define IPAC_BFIFO_LEN	64	/* 64 bytes B-channel FIFO on chip	*/
41
42#define IPAC_HSCXA_OFF	0x00
43#define IPAC_HSCXB_OFF	0x40
44#define IPAC_ISAC_OFF	0x80
45#define IPAC_IPAC_OFF	0xc0
46
47/* chip version */
48
49#define	IPAC_V11	0x01	/* IPAC Version 1.1 */
50#define	IPAC_V12	0x02	/* IPAC Version 1.2 */
51
52/*
53 * definitions of registers and bits for the IPAC ISDN chip.
54 */
55
56typedef struct ipac_reg {
57
58	/* most registers can be read/written, but have different names */
59	/* so define a union with read/write names to make that clear */
60
61	union {
62		struct {
63			unsigned char ipac_conf;
64			unsigned char ipac_ista;
65			unsigned char ipac_id;
66			unsigned char ipac_acfg;
67			unsigned char ipac_aoe;
68			unsigned char ipac_arx;
69			unsigned char ipac_pita1;
70			unsigned char ipac_pita2;
71			unsigned char ipac_pota1;
72			unsigned char ipac_pota2;
73			unsigned char ipac_pcfg;
74			unsigned char ipac_scfg;
75			unsigned char ipac_timr2;
76		} ipac_r;
77		struct {
78			unsigned char ipac_conf;
79			unsigned char ipac_mask;
80			unsigned char ipac_dummy;
81			unsigned char ipac_acfg;
82			unsigned char ipac_aoe;
83			unsigned char ipac_atx;
84			unsigned char ipac_pita1;
85			unsigned char ipac_pita2;
86			unsigned char ipac_pota1;
87			unsigned char ipac_pota2;
88			unsigned char ipac_pcfg;
89			unsigned char ipac_scfg;
90			unsigned char ipac_timr2;
91		} ipac_w;
92	} ipac_rw;
93} ipac_reg_t;
94
95#define REG_OFFSET(type, field) (uintptr_t)(&(((type *)0)->field))
96
97/* IPAC read registers */
98
99#define IPAC_CONF  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_conf)
100#define IPAC_ISTA  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_ista)
101#define IPAC_ID    REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_id)
102#define IPAC_ACFG  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_acfg)
103#define IPAC_AOE   REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_aoe)
104#define IPAC_ARX   REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_arx)
105#define IPAC_PITA1 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pita1)
106#define IPAC_PITA2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pita2)
107#define IPAC_POTA1 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pota1)
108#define IPAC_POTA2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pota2)
109#define IPAC_PCFG  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_pcfg)
110#define IPAC_SCFG  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_scfg)
111#define IPAC_TIMR2 REG_OFFSET(ipac_reg_t, ipac_rw.ipac_r.ipac_timr2)
112
113/* IPAC write registers */
114
115#define IPAC_MASK  REG_OFFSET(ipac_reg_t, ipac_rw.ipac_w.ipac_mask)
116#define IPAC_ATX   REG_OFFSET(ipac_reg_t, ipac_rw.ipac_w.ipac_atx)
117
118/* register bits */
119
120#define IPAC_CONF_AMP  0x80
121#define IPAC_CONF_CFS  0x40
122#define IPAC_CONF_TEM  0x20
123#define IPAC_CONF_PDS  0x10
124#define IPAC_CONF_IDH  0x08
125#define IPAC_CONF_SGO  0x04
126#define IPAC_CONF_ODS  0x02
127#define IPAC_CONF_IOF  0x01
128
129#define IPAC_ISTA_INT1 0x80
130#define IPAC_ISTA_INT0 0x40
131#define IPAC_ISTA_ICD  0x20
132#define IPAC_ISTA_EXD  0x10
133#define IPAC_ISTA_ICA  0x08
134#define IPAC_ISTA_EXA  0x04
135#define IPAC_ISTA_ICB  0x02
136#define IPAC_ISTA_EXB  0x01
137
138#define IPAC_MASK_INT1 0x80
139#define IPAC_MASK_INT0 0x40
140#define IPAC_MASK_ICD  0x20
141#define IPAC_MASK_EXD  0x10
142#define IPAC_MASK_ICA  0x08
143#define IPAC_MASK_EXA  0x04
144#define IPAC_MASK_ICB  0x02
145#define IPAC_MASK_EXB  0x01
146
147#define IPAC_ACFG_OD7  0x80
148#define IPAC_ACFG_OD6  0x40
149#define IPAC_ACFG_OD5  0x20
150#define IPAC_ACFG_OD4  0x10
151#define IPAC_ACFG_OD3  0x08
152#define IPAC_ACFG_OD2  0x04
153#define IPAC_ACFG_EL1  0x02
154#define IPAC_ACFG_EL2  0x01
155
156#define IPAC_AOE_OE7   0x80
157#define IPAC_AOE_OE6   0x40
158#define IPAC_AOE_OE5   0x20
159#define IPAC_AOE_OE4   0x10
160#define IPAC_AOE_OE3   0x08
161#define IPAC_AOE_OE2   0x04
162
163#define IPAC_ARX_AR7   0x80
164#define IPAC_ARX_AR6   0x40
165#define IPAC_ARX_AR5   0x20
166#define IPAC_ARX_AR4   0x10
167#define IPAC_ARX_AR3   0x08
168#define IPAC_ARX_AR2   0x04
169
170#define IPAC_ATX_AT7   0x80
171#define IPAC_ATX_AT6   0x40
172#define IPAC_ATX_AT5   0x20
173#define IPAC_ATX_AT4   0x10
174#define IPAC_ATX_AT3   0x08
175#define IPAC_ATX_AT2   0x04
176
177#define IPAC_PITA1_ENA  0x80
178#define IPAC_PITA1_DUDD 0x40
179
180#define IPAC_PITA2_ENA  0x80
181#define IPAC_PITA2_DUDD 0x40
182
183#define IPAC_POTA1_ENA  0x80
184#define IPAC_POTA1_DUDD 0x40
185
186#define IPAC_POTA2_ENA  0x80
187#define IPAC_POTA2_DUDD 0x40
188
189#define IPAC_PCFG_DPS  0x80
190#define IPAC_PCFG_ACL  0x40
191#define IPAC_PCFG_LED  0x20
192#define IPAC_PCFG_PLD  0x10
193#define IPAC_PCFG_FBS  0x08
194#define IPAC_PCFG_CSL2 0x04
195#define IPAC_PCFG_CSL1 0x02
196#define IPAC_PCFG_CSL0 0x01
197
198#define IPAC_SCFG_PRI  0x80
199#define IPAC_SCFG_TXD  0x40
200#define IPAC_SCFG_TLEN 0x20
201
202#define IPAC_TIMR2_TMD 0x80
203
204#endif /* _I4B_IPAC_H_ */
205