1/* $NetBSD: dm9000reg.h,v 1.1 2010/09/08 22:01:29 ahoka Exp $ */ 2 3/* 4 * Copyright (c) 2009 Paul Fleischer 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* Registers accesible on the DM9000, extracted from pp. 11-12 from the data sheet */ 30 31/* There are two interesting addresses for the DM9000 32 * (at least in the context of the FriendlyARM MINI2440) 33 * The I/O or register select address, which is the base address. 34 * The DATA address, which is located at offset 4 from the base address. 35 * 36 * Chances are that this will not work generally, as it really depends on how the address lines are 37 * mapped from the CPU to the DM9000. But for now it is a good starting point. 38 */ 39#define DM9000_IOSIZE 4 /* XXX: Depends on the wiring of the address lines. */ 40 41#define DM9000_NCR 0x00 42#define DM9000_NCR_RST (1 << 0) 43#define DM9000_NCR_LBK_MASK (0x06) 44#define DM9000_NCR_LBK_SHIFT (1) 45#define DM9000_NCR_LBK_MAC_INTERNAL ( 1 << DM9000_NCR_LBK_SHIFT ) 46#define DM9000_NCR_LBK_NORMAL ( 0 << DM9000_NCR_LBK_SHIFT) 47#define DM9000_NCR_LBK_INT_PHY ( 2 << DM9000_NCR_LBK_SHIFT) 48#define DM9000_NCR_FDX (1 << 3) 49#define DM9000_NCR_FCOL (1 << 4) 50#define DM9000_NCR_WAKEEN (1 << 6) 51#define DM9000_NCR_EXY_PHY (1 << 7) 52#define DM9000_NSR 0x01 53#define DM9000_NSR_RXOV (1 << 1) 54#define DM9000_NSR_TX1END (1 << 2) 55#define DM9000_NSR_TX2END (1 << 3) 56#define DM9000_NSR_WAKEST (1 << 5) 57#define DM9000_NSR_LINKST (1 << 6) 58#define DM9000_NSR_SPEED (1 << 7) 59#define DM9000_TCR 0x02 60#define DM9000_TCR_TXREQ (1 << 0) 61#define DM9000_TCR_CRC_DIS1 (1 << 1) 62#define DM9000_TCR_PAD_DIS1 (1 << 2) 63#define DM9000_TCR_CRC_DIS2 (1 << 3) 64#define DM9000_TCR_PAD_DIS2 (1 << 4) 65#define DM9000_TCR_EXCECM (1 << 5) 66#define DM9000_TCR_TJDIS (1 << 6) 67#define DM9000_TSR1 0x03 68#define DM9000_TSR2 0x04 69#define DM9000_RCR 0x05 70#define DM9000_RCR_RXEN (1 << 0) 71#define DM9000_RCR_PRMSC (1 << 1) 72#define DM9000_RCR_RUNT (1 << 2) 73#define DM9000_RCR_ALL (1 << 3) 74#define DM9000_RCR_DIS_CRC (1 << 4) 75#define DM9000_RCR_DIS_LONG (1 << 5) 76#define DM9000_RCR_WTDIS (1 << 6) 77#define DM9000_RSR 0x06 78#define DM9000_RSR_FOE (1<<0) 79#define DM9000_RSR_CE (1<<1) 80#define DM9000_RSR_AE (1<<2) 81#define DM9000_RSR_PLE (1<<3) 82#define DM9000_RSR_RWTO (1<<4) 83#define DM9000_RSR_LCS (1<<5) 84#define DM9000_RSR_MF (1<<6) 85#define DM9000_RSR_RF (1<<7) 86#define DM9000_ROCR 0x07 87#define DM9000_BPTR 0x08 88#define DM9000_FCTR 0x09 89#define DM9000_FCR 0x0A 90#define DM9000_FCR_FLCE (1 << 0) 91#define DM9000_FCR_RXPCS (1 << 1) 92#define DM9000_FCR_RXPS (1 << 2) 93#define DM9000_FCR_BKPM (1 << 3) 94#define DM9000_FCR_BKPA (1 << 4) 95#define DM9000_FCR_TXPEN (1 << 5) 96#define DM9000_FCR_TXPF (1 << 6) 97#define DM9000_FCR_TXP0 (1 << 7) 98#define DM9000_EPCR 0x0B 99#define DM9000_EPCR_ERRE (1 << 0) 100#define DM9000_EPCR_ERPRW (1 << 1) 101#define DM9000_EPCR_ERPRR (1 << 2) 102#define DM9000_EPCR_EPOS_EEPROM (0 << 3) 103#define DM9000_EPCR_EPOS_PHY (1 << 3) 104#define DM9000_EPCR_WEP (1 << 4) 105#define DM9000_EPCR_REEP (1 << 5) 106#define DM9000_EPAR 0x0C 107#define DM9000_EPAR_EROA_MASK 0x3F /* bits 0-5 */ 108#define DM9000_EPAR_INT_PHY 0x40 /* EPAR[7:6] = 01 for internal PHY */ 109#define DM9000_EPDRL 0x0D 110#define DM9000_EPDRH 0x0E 111#define DM9000_WCR 0x0F 112 113#define DM9000_PAB0 0x10 114#define DM9000_PAB1 0x11 115#define DM9000_PAB2 0x12 116#define DM9000_PAB3 0x13 117#define DM9000_PAB4 0x14 118#define DM9000_PAB5 0x15 119 120#define DM9000_MAB0 0x16 121#define DM9000_MAB1 0x17 122#define DM9000_MAB2 0x18 123#define DM9000_MAB3 0x19 124#define DM9000_MAB4 0x1A 125#define DM9000_MAB5 0x1B 126#define DM9000_MAB6 0x1C 127#define DM9000_MAB7 0x1D 128 129#define DM9000_GPCR 0x1E 130#define DM9000_GPCR_GPIO0_OUT (1 << 0) 131#define DM9000_GPR 0x1F 132#define DM9000_GPR_PHY_PWROFF (1 << 0) 133#define DM9000_TRPAL 0x22 134#define DM9000_TRPAH 0x23 135#define DM9000_RWPAL 0x24 136#define DM9000_RWPAH 0x25 137 138#define DM9000_VID0 0x28 139#define DM9000_VID1 0x29 140 141#define DM9000_PID0 0x2A 142#define DM9000_PID1 0x2B 143 144#define DM9000_CHIPR 0x2C 145#define DM9000_SMCR 0x2F 146#define DM9000_MRCMDX 0xF0 147#define DM9000_MRCMD 0xF2 148#define DM9000_MRRL 0xF4 149#define DM9000_MRRH 0xF5 150#define DM9000_MWCMDX 0xF6 151#define DM9000_MWCMD 0xF8 152#define DM9000_MWRL 0xFA 153#define DM9000_MWRH 0xFB 154#define DM9000_TXPLL 0xFC 155#define DM9000_TXPLH 0xFD 156#define DM9000_ISR 0xFE 157#define DM9000_IOMODE_MASK 0xC0 158#define DM9000_IOMODE_SHIFT 6 159#define DM9000_ISR_PRS (1<<0) 160#define DM9000_ISR_PTS (1<<1) 161#define DM9000_ISR_ROS (1<<2) 162#define DM9000_ISR_ROOS (1<<3) 163#define DM9000_ISR_UNDERRUN (1<<4) 164#define DM9000_ISR_LNKCHNG (1<<5) 165#define DM9000_IMR 0xFF 166#define DM9000_IMR_PRM (1<<0) 167#define DM9000_IMR_PTM (1<<1) 168#define DM9000_IMR_ROM (1<<2) 169#define DM9000_IMR_ROOM (1<<3) 170#define DM9000_IMR_PAR (1<<7) 171 172#define DM9000_PHY_BMCR 0x00 173#define DM9000_PHY_BMCR_COLL_TEST (1<<7) 174#define DM9000_PHY_BMCR_DUPLEX_MODE (1<<8) 175#define DM9000_PHY_BMCR_RESTART_AN (1<<9) 176#define DM9000_PHY_BMCR_ISOLATE (1<<10) 177#define DM9000_PHY_BMCR_POWER_DOWN (1<<11) 178#define DM9000_PHY_BMCR_AUTO_NEG_EN (1<<12) 179#define DM9000_PHY_BMCR_SPEED_SELECT (1<<13) 180#define DM9000_PHY_BMCR_LOOPBACK (1<<14) 181#define DM9000_PHY_BMCR_RESET (1<<15) 182#define DM9000_PHY_BMSR 0x01 183#define DM9000_PHY_BMSR_EXT_CAP (1<<0) 184#define DM9000_PHY_BMSR_JAB_DET (1<<1) 185#define DM9000_PHY_BMSR_LINK_ST (1<<2) 186#define DM9000_PHY_BMSR_AUTO_NEG_AB (1<<3) 187#define DM9000_PHY_BMSR_REMOTE_FAULT (1<<4) 188#define DM9000_PHY_BMSR_AUTO_NEG_COM (1<<5) 189#define DM9000_PHY_BMSR_MF_PRE_SUP (1<<6) 190#define DM9000_PHY_BMSR_10BASE_HALF_DUPLEX (1<<11) 191#define DM9000_PHY_BMSR_10BASE_FULL_DUPLEX (1<<12) 192#define DM9000_PHY_BMSR_100BASE_HALF_DUPLEX (1<<13) 193#define DM9000_PHY_BMSR_100BASE_FULL_DUPLEX (1<<14) 194#define DM9000_PHY_BMSR_100BASE_T4 (1<<15) 195#define DM9000_PHY_PHYID1 0x02 196#define DM9000_PHY_PHYID2 0x03 197#define DM9000_PHY_ANAR 0x04 198#define DM9000_PHY_ANAR_10_HDX (1<<5) 199#define DM9000_PHY_ANAR_10_FDX (1<<6) 200#define DM9000_PHY_ANAR_TX_HDX (1<<7) 201#define DM9000_PHY_ANAR_TX_FDX (1<<8) 202#define DM9000_PHY_ANLPAR 0x05 203#define DM9000_PHY_ANER 0x06 204#define DM9000_PHY_DSCR 0x16 205#define DM9000_PHY_DSCSR 0x17 206#define DM9000_PHY_10BTCSR 0x18 207