1/* $NetBSD: adwlib.h,v 1.15.22.2 2005/03/04 16:41:24 skrll Exp $ */ 2 3/* 4 * Definitions for low level routines and data structures 5 * for the Advanced Systems Inc. SCSI controllers chips. 6 * 7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * Author: Baldassare Dante Profeta <dante@mclink.it> 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40/* 41 * Ported from: 42 */ 43/* 44 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 45 * 46 * Copyright (c) 1995-2000 Advanced System Products, Inc. 47 * All Rights Reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that redistributions of source 51 * code retain the above copyright notice and this comment without 52 * modification. 53 */ 54 55#ifndef _ADVANSYS_WIDE_LIBRARY_H_ 56#define _ADVANSYS_WIDE_LIBRARY_H_ 57 58 59/* 60 * --- Adw Library Constants and Macros 61 */ 62 63#define ADW_LIB_VERSION_MAJOR 5 64#define ADW_LIB_VERSION_MINOR 8 65 66 67/* If the result wraps when calculating tenths, return 0. */ 68#define ADW_TENTHS(num, den) \ 69 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 70 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 71 72 73/* 74 * Define Adw Reset Hold Time grater than 25 uSec. 75 * See AdwResetSCSIBus() for more info. 76 */ 77#define ASC_SCSI_RESET_HOLD_TIME_US 60 78 79/* 80 * Define Adw EEPROM constants. 81 */ 82 83#define ASC_EEP_DVC_CFG_BEGIN (0x00) 84#define ASC_EEP_DVC_CFG_END (0x15) 85#define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 86#define ASC_EEP_MAX_WORD_ADDR (0x1E) 87 88#define ASC_EEP_DELAY_MS 100 89 90/* 91 * EEPROM bits reference by the RISC after initialization. 92 */ 93#define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 94#define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 95#define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 96 97/* 98 * EEPROM configuration format 99 * 100 * Field naming convention: 101 * 102 * *_enable indicates the field enables or disables the feature. The 103 * value is never reset. 104 * 105 * *_able indicates both whether a feature should be enabled or disabled 106 * and whether a device isi capable of the feature. At initialization 107 * this field may be set, but later if a device is found to be incapable 108 * of the feature, the field is cleared. 109 * 110 * Default values are maintained in the structure Default_EEPROM_Config. 111 */ 112#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 113#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 114/* 115 * For the ASC3550 Bit 13 is Termination Polarity control bit. 116 * For later ICs Bit 13 controls whether the CIS (Card Information 117 * Service Section) is loaded from EEPROM. 118 */ 119#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 120#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 121 122/* 123 * ASC38C1600 Bit 11 124 * 125 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 126 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 127 * Function 0 will specify INT B. 128 * 129 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 130 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 131 * Function 1 will specify INT A. 132 */ 133#define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 134 135typedef struct adw_eeprom 136{ 137 /* Word Offset, Description */ 138 139 u_int16_t cfg_lsw; /* 00 power up initialization */ 140 /* bit 13 set - Term Polarity Control */ 141 /* bit 14 set - BIOS Enable */ 142 /* bit 15 set - Big Endian Mode */ 143 u_int16_t cfg_msw; /* 01 unused */ 144 u_int16_t disc_enable; /* 02 disconnect enable */ 145 u_int16_t wdtr_able; /* 03 Wide DTR able */ 146 union { 147 u_int16_t sdtr_able; /* 04 Synchronous DTR able */ 148 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 149 } sdtr1; 150 u_int16_t start_motor; /* 05 send start up motor */ 151 u_int16_t tagqng_able; /* 06 tag queuing able */ 152 u_int16_t bios_scan; /* 07 BIOS device control */ 153 u_int16_t scam_tolerant; /* 08 no scam */ 154 155 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */ 156 u_int8_t bios_boot_delay; /* power up wait */ 157 158 u_int8_t scsi_reset_delay; /* 10 reset delay */ 159 u_int8_t bios_id_lun; /* first boot device scsi id & lun */ 160 /* high nibble is lun */ 161 /* low nibble is scsi id */ 162 163 u_int8_t termination_se; /* 11 0 - automatic */ 164 /* 1 - low off / high off */ 165 /* 2 - low off / high on */ 166 /* 3 - low on / high on */ 167 /* There is no low on / high off */ 168 169 u_int8_t termination_lvd; /* 11 0 - automatic */ 170 /* 1 - low off / high off */ 171 /* 2 - low off / high on */ 172 /* 3 - low on / high on */ 173 /* There is no low on / high off */ 174 175 u_int16_t bios_ctrl; /* 12 BIOS control bits */ 176 /* bit 0 BIOS don't act as initiator. */ 177 /* bit 1 BIOS > 1 GB support */ 178 /* bit 2 BIOS > 2 Disk Support */ 179 /* bit 3 BIOS don't support removables */ 180 /* bit 4 BIOS support bootable CD */ 181 /* bit 5 BIOS scan enabled */ 182 /* bit 6 BIOS support multiple LUNs */ 183 /* bit 7 BIOS display of message */ 184 /* bit 8 SCAM disabled */ 185 /* bit 9 Reset SCSI bus during init. */ 186 /* bit 10 */ 187 /* bit 11 No verbose initialization. */ 188 /* bit 12 SCSI parity enabled */ 189 /* bit 13 */ 190 /* bit 14 */ 191 /* bit 15 */ 192 union { 193 u_int16_t ultra_able; /* 13 ULTRA speed able */ 194 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 195 } sdtr2; 196 union { 197 u_int16_t reserved2; /* 14 reserved */ 198 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 199 } sdtr3; 200 u_int8_t max_host_qng; /* 15 maximum host queuing */ 201 u_int8_t max_dvc_qng; /* maximum per device queuing */ 202 u_int16_t dvc_cntl; /* 16 control bit for driver */ 203 union { 204 u_int16_t bug_fix; /* 17 control bit for bug fix */ 205 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 206 } sdtr4; 207 u_int16_t serial_number[3]; /* 18 - 20 Board serial number */ 208 u_int16_t check_sum; /* 21 EEP check sum */ 209 u_int8_t oem_name[16]; /* 22 OEM name */ 210 u_int16_t dvc_err_code; /* 30 last device driver error code */ 211 u_int16_t adv_err_code; /* 31 last uc and Adw Lib error code */ 212 u_int16_t adv_err_addr; /* 32 last uc error address */ 213 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */ 214 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adw Lib error code */ 215 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */ 216 u_int16_t reserved1[20]; /* 36 - 55 reserved */ 217 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */ 218 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */ 219 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */ 220 u_int16_t subsysid; /* 59 SubSystem ID */ 221 u_int16_t reserved2[4]; /* 60 - 63 reserved */ 222} ADW_EEPROM; 223 224 225/* 226 * EEPROM Commands 227 */ 228#define ASC_EEP_CMD_READ 0x80 229#define ASC_EEP_CMD_WRITE 0x40 230#define ASC_EEP_CMD_WRITE_ABLE 0x30 231#define ASC_EEP_CMD_WRITE_DISABLE 0x00 232 233#define ASC_EEP_CMD_DONE 0x0200 234#define ASC_EEP_CMD_DONE_ERR 0x0001 235 236/* cfg_word */ 237#define EEP_CFG_WORD_BIG_ENDIAN 0x8000 238 239/* bios_ctrl */ 240#define BIOS_CTRL_BIOS 0x0001 241#define BIOS_CTRL_EXTENDED_XLAT 0x0002 242#define BIOS_CTRL_GT_2_DISK 0x0004 243#define BIOS_CTRL_BIOS_REMOVABLE 0x0008 244#define BIOS_CTRL_BOOTABLE_CD 0x0010 245#define BIOS_CTRL_MULTIPLE_LUN 0x0040 246#define BIOS_CTRL_DISPLAY_MSG 0x0080 247#define BIOS_CTRL_NO_SCAM 0x0100 248#define BIOS_CTRL_RESET_SCSI_BUS 0x0200 249#define BIOS_CTRL_INIT_VERBOSE 0x0800 250#define BIOS_CTRL_SCSI_PARITY 0x1000 251#define BIOS_CTRL_AIPP_DIS 0x2000 252 253#define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 254#define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */ 255 256#define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 257#define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */ 258 259#define ADW_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */ 260#define ADW_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */ 261#define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */ 262 263/* 264 * Byte I/O register address from base of 'iop_base'. 265 */ 266#define IOPB_INTR_STATUS_REG 0x00 267#define IOPB_CHIP_ID_1 0x01 268#define IOPB_INTR_ENABLES 0x02 269#define IOPB_CHIP_TYPE_REV 0x03 270#define IOPB_RES_ADDR_4 0x04 271#define IOPB_RES_ADDR_5 0x05 272#define IOPB_RAM_DATA 0x06 273#define IOPB_RES_ADDR_7 0x07 274#define IOPB_FLAG_REG 0x08 275#define IOPB_RES_ADDR_9 0x09 276#define IOPB_RISC_CSR 0x0A 277#define IOPB_RES_ADDR_B 0x0B 278#define IOPB_RES_ADDR_C 0x0C 279#define IOPB_RES_ADDR_D 0x0D 280#define IOPB_SOFT_OVER_WR 0x0E 281#define IOPB_RES_ADDR_F 0x0F 282#define IOPB_MEM_CFG 0x10 283#define IOPB_RES_ADDR_11 0x11 284#define IOPB_GPIO_DATA 0x12 285#define IOPB_RES_ADDR_13 0x13 286#define IOPB_FLASH_PAGE 0x14 287#define IOPB_RES_ADDR_15 0x15 288#define IOPB_GPIO_CNTL 0x16 289#define IOPB_RES_ADDR_17 0x17 290#define IOPB_FLASH_DATA 0x18 291#define IOPB_RES_ADDR_19 0x19 292#define IOPB_RES_ADDR_1A 0x1A 293#define IOPB_RES_ADDR_1B 0x1B 294#define IOPB_RES_ADDR_1C 0x1C 295#define IOPB_RES_ADDR_1D 0x1D 296#define IOPB_RES_ADDR_1E 0x1E 297#define IOPB_RES_ADDR_1F 0x1F 298#define IOPB_DMA_CFG0 0x20 299#define IOPB_DMA_CFG1 0x21 300#define IOPB_TICKLE 0x22 301#define IOPB_DMA_REG_WR 0x23 302#define IOPB_SDMA_STATUS 0x24 303#define IOPB_SCSI_BYTE_CNT 0x25 304#define IOPB_HOST_BYTE_CNT 0x26 305#define IOPB_BYTE_LEFT_TO_XFER 0x27 306#define IOPB_BYTE_TO_XFER_0 0x28 307#define IOPB_BYTE_TO_XFER_1 0x29 308#define IOPB_BYTE_TO_XFER_2 0x2A 309#define IOPB_BYTE_TO_XFER_3 0x2B 310#define IOPB_ACC_GRP 0x2C 311#define IOPB_RES_ADDR_2D 0x2D 312#define IOPB_DEV_ID 0x2E 313#define IOPB_RES_ADDR_2F 0x2F 314#define IOPB_SCSI_DATA 0x30 315#define IOPB_RES_ADDR_31 0x31 316#define IOPB_RES_ADDR_32 0x32 317#define IOPB_SCSI_DATA_HSHK 0x33 318#define IOPB_SCSI_CTRL 0x34 319#define IOPB_RES_ADDR_35 0x35 320#define IOPB_RES_ADDR_36 0x36 321#define IOPB_RES_ADDR_37 0x37 322#define IOPB_RAM_BIST 0x38 323#define IOPB_PLL_TEST 0x39 324#define IOPB_PCI_INT_CFG 0x3A 325#define IOPB_RES_ADDR_3B 0x3B 326#define IOPB_RFIFO_CNT 0x3C 327#define IOPB_RES_ADDR_3D 0x3D 328#define IOPB_RES_ADDR_3E 0x3E 329#define IOPB_RES_ADDR_3F 0x3F 330 331/* 332 * Word I/O register address from base of 'iop_base'. 333 */ 334#define IOPW_CHIP_ID_0 0x00 /* CID0 */ 335#define IOPW_CTRL_REG 0x02 /* CC */ 336#define IOPW_RAM_ADDR 0x04 /* LA */ 337#define IOPW_RAM_DATA 0x06 /* LD */ 338#define IOPW_RES_ADDR_08 0x08 339#define IOPW_RISC_CSR 0x0A /* CSR */ 340#define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 341#define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 342#define IOPW_RES_ADDR_10 0x10 343#define IOPW_SEL_MASK 0x12 /* SM */ 344#define IOPW_RES_ADDR_14 0x14 345#define IOPW_FLASH_ADDR 0x16 /* FA */ 346#define IOPW_RES_ADDR_18 0x18 347#define IOPW_EE_CMD 0x1A /* EC */ 348#define IOPW_EE_DATA 0x1C /* ED */ 349#define IOPW_SFIFO_CNT 0x1E /* SFC */ 350#define IOPW_RES_ADDR_20 0x20 351#define IOPW_Q_BASE 0x22 /* QB */ 352#define IOPW_QP 0x24 /* QP */ 353#define IOPW_IX 0x26 /* IX */ 354#define IOPW_SP 0x28 /* SP */ 355#define IOPW_PC 0x2A /* PC */ 356#define IOPW_RES_ADDR_2C 0x2C 357#define IOPW_RES_ADDR_2E 0x2E 358#define IOPW_SCSI_DATA 0x30 /* SD */ 359#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 360#define IOPW_SCSI_CTRL 0x34 /* SC */ 361#define IOPW_HSHK_CFG 0x36 /* HCFG */ 362#define IOPW_SXFR_STATUS 0x36 /* SXS */ 363#define IOPW_SXFR_CNTL 0x38 /* SXL */ 364#define IOPW_SXFR_CNTH 0x3A /* SXH */ 365#define IOPW_RES_ADDR_3C 0x3C 366#define IOPW_RFIFO_DATA 0x3E /* RFD */ 367 368/* 369 * Doubleword I/O register address from base of 'iop_base'. 370 */ 371#define IOPDW_RES_ADDR_0 0x00 372#define IOPDW_RAM_DATA 0x04 373#define IOPDW_RES_ADDR_8 0x08 374#define IOPDW_RES_ADDR_C 0x0C 375#define IOPDW_RES_ADDR_10 0x10 376#define IOPDW_COMMA 0x14 377#define IOPDW_COMMB 0x18 378#define IOPDW_RES_ADDR_1C 0x1C 379#define IOPDW_SDMA_ADDR0 0x20 380#define IOPDW_SDMA_ADDR1 0x24 381#define IOPDW_SDMA_COUNT 0x28 382#define IOPDW_SDMA_ERROR 0x2C 383#define IOPDW_RDMA_ADDR0 0x30 384#define IOPDW_RDMA_ADDR1 0x34 385#define IOPDW_RDMA_COUNT 0x38 386#define IOPDW_RDMA_ERROR 0x3C 387 388#define ADW_CHIP_ID_BYTE 0x25 389#define ADW_CHIP_ID_WORD 0x04C1 390 391#define ADW_SC_SCSI_BUS_RESET 0x2000 392 393#define ADW_INTR_ENABLE_HOST_INTR 0x01 394#define ADW_INTR_ENABLE_SEL_INTR 0x02 395#define ADW_INTR_ENABLE_DPR_INTR 0x04 396#define ADW_INTR_ENABLE_RTA_INTR 0x08 397#define ADW_INTR_ENABLE_RMA_INTR 0x10 398#define ADW_INTR_ENABLE_RST_INTR 0x20 399#define ADW_INTR_ENABLE_DPE_INTR 0x40 400#define ADW_INTR_ENABLE_GLOBAL_INTR 0x80 401 402#define ADW_INTR_STATUS_INTRA 0x01 403#define ADW_INTR_STATUS_INTRB 0x02 404#define ADW_INTR_STATUS_INTRC 0x04 405 406#define ADW_RISC_CSR_STOP (0x0000) 407#define ADW_RISC_TEST_COND (0x2000) 408#define ADW_RISC_CSR_RUN (0x4000) 409#define ADW_RISC_CSR_SINGLE_STEP (0x8000) 410 411#define ADW_CTRL_REG_HOST_INTR 0x0100 412#define ADW_CTRL_REG_SEL_INTR 0x0200 413#define ADW_CTRL_REG_DPR_INTR 0x0400 414#define ADW_CTRL_REG_RTA_INTR 0x0800 415#define ADW_CTRL_REG_RMA_INTR 0x1000 416#define ADW_CTRL_REG_RES_BIT14 0x2000 417#define ADW_CTRL_REG_DPE_INTR 0x4000 418#define ADW_CTRL_REG_POWER_DONE 0x8000 419#define ADW_CTRL_REG_ANY_INTR 0xFF00 420 421#define ADW_CTRL_REG_CMD_RESET 0x00C6 422#define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5 423#define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4 424#define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 425#define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 426 427#define ADW_TICKLE_NOP 0x00 428#define ADW_TICKLE_A 0x01 429#define ADW_TICKLE_B 0x02 430#define ADW_TICKLE_C 0x03 431 432#define ADW_SCSI_CTRL_RSTOUT 0x2000 433 434#define ADW_IS_INT_PENDING(iot, ioh) \ 435 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) 436 437/* 438 * SCSI_CFG0 Register bit definitions 439 */ 440#define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 441#define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 442#define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */ 443#define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 444#define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 445#define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */ 446#define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */ 447#define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 448#define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 449#define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 450#define ADW_OUR_ID 0x000F /* SCSI ID */ 451 452/* 453 * SCSI_CFG1 Register bit definitions 454 */ 455#define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 456#define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 457#define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 458#define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */ 459#define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 460#define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 461#define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 462#define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */ 463#define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 464#define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 465#define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 466#define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */ 467#define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 468#define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 469#define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 470 471/* 472 * Addendum for ASC-38C0800 Chip 473 * 474 * The ASC-38C1600 Chip uses the same definitions except that the 475 * bus mode override bits [12:10] have been moved to byte register 476 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 477 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 478 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 479 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 480 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 481 */ 482#define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 483#define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 484#define ADW_HVD 0x1000 /* HVD Device Detect */ 485#define ADW_LVD 0x0800 /* LVD Device Detect */ 486#define ADW_SE 0x0400 /* SE Device Detect */ 487#define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */ 488#define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 489#define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 490#define ADW_TERM_SE 0x0030 /* SE Termination Bits */ 491#define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 492#define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 493#define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 494#define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 495#define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 496#define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */ 497#define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 498#define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 499 500 501#define CABLE_ILLEGAL_A 0x7 502 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 503 504#define CABLE_ILLEGAL_B 0xB 505 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 506 507/* 508 The following table details the SCSI_CFG1 Termination Polarity, 509 Termination Control and Cable Detect bits. 510 511 Cable Detect | Termination 512 Bit 3 2 1 0 | 5 4 | Notes 513 _____________|________|____________________ 514 1 1 1 0 | on on | Internal wide only 515 1 1 0 1 | on on | Internal narrow only 516 1 0 1 1 | on on | External narrow only 517 0 x 1 1 | on on | External wide only 518 1 1 0 0 | on off| Internal wide and internal narrow 519 1 0 1 0 | on off| Internal wide and external narrow 520 0 x 1 0 | off off| Internal wide and external wide 521 1 0 0 1 | on off| Internal narrow and external narrow 522 0 x 0 1 | on off| Internal narrow and external wide 523 1 1 1 1 | on on | No devices are attached 524 x 0 0 0 | on on | Illegal (all 3 connectors are used) 525 0 x 0 0 | on on | Illegal (all 3 connectors are used) 526 527 x means don't-care (either '0' or '1') 528 529 If term_pol (bit 13) is '0' (active-low terminator enable), then: 530 'on' is '0' and 'off' is '1'. 531 532 If term_pol bit is '1' (meaning active-hi terminator enable), then: 533 'on' is '1' and 'off' is '0'. 534 */ 535 536/* 537 * MEM_CFG Register bit definitions 538 */ 539#define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 540#define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */ 541#define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */ 542#define ADW_RAM_SZ_2KB 0x00 /* 2 KB */ 543#define ADW_RAM_SZ_4KB 0x04 /* 4 KB */ 544#define ADW_RAM_SZ_8KB 0x08 /* 8 KB */ 545#define ADW_RAM_SZ_16KB 0x0C /* 16 KB */ 546#define ADW_RAM_SZ_32KB 0x10 /* 32 KB */ 547#define ADW_RAM_SZ_64KB 0x14 /* 64 KB */ 548 549/* 550 * DMA_CFG0 Register bit definitions 551 * 552 * This register is only accessible to the host. 553 */ 554#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 555#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 556#define FIFO_THRESH_16B 0x00 /* 16 bytes */ 557#define FIFO_THRESH_32B 0x20 /* 32 bytes */ 558#define FIFO_THRESH_48B 0x30 /* 48 bytes */ 559#define FIFO_THRESH_64B 0x40 /* 64 bytes */ 560#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 561#define FIFO_THRESH_96B 0x60 /* 96 bytes */ 562#define FIFO_THRESH_112B 0x70 /* 112 bytes */ 563#define START_CTL 0x0C /* DMA start conditions */ 564#define START_CTL_TH 0x00 /* Wait threshold level (default) */ 565#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 566#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 567#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 568#define READ_CMD 0x03 /* Memory Read Method */ 569#define READ_CMD_MR 0x00 /* Memory Read */ 570#define READ_CMD_MRL 0x02 /* Memory Read Long */ 571#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 572 573/* 574 * ASC-38C0800 RAM BIST Register bit definitions 575 */ 576#define RAM_TEST_MODE 0x80 577#define PRE_TEST_MODE 0x40 578#define NORMAL_MODE 0x00 579#define RAM_TEST_DONE 0x10 580#define RAM_TEST_STATUS 0x0F 581#define RAM_TEST_HOST_ERROR 0x08 582#define RAM_TEST_INTRAM_ERROR 0x04 583#define RAM_TEST_RISC_ERROR 0x02 584#define RAM_TEST_SCSI_ERROR 0x01 585#define RAM_TEST_SUCCESS 0x00 586#define PRE_TEST_VALUE 0x05 587#define NORMAL_VALUE 0x00 588 589/* 590 * ASC38C1600 Definitions 591 * 592 * IOPB_PCI_INT_CFG Bit Field Definitions 593 */ 594 595#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 596 597/* 598 * Bit 1 can be set to change the interrupt for the Function to operate in 599 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 600 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 601 * mode, otherwise the operating mode is undefined. 602 */ 603#define TOTEMPOLE 0x02 604 605/* 606 * Bit 0 can be used to change the Int Pin for the Function. The value is 607 * 0 by default for both Functions with Function 0 using INT A and Function 608 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 609 * INT A is used. 610 * 611 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 612 * value specified in the PCI Configuration Space. 613 */ 614#define INTAB 0x01 615 616 617#define ADW_MAX_TID 15 /* max. target identifier */ 618#define ADW_MAX_LUN 7 /* max. logical unit number */ 619 620 621/* 622 * Adw Library Status Definitions 623 */ 624#define ADW_TRUE 1 625#define ADW_FALSE 0 626#define ADW_NOERROR 1 627#define ADW_SUCCESS 1 628#define ADW_BUSY 0 629#define ADW_ERROR (-1) 630 631 632/* 633 * Warning code values for AdwInitFrom*EEP() functions 634 */ 635#define ADW_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 636#define ADW_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 637#define ADW_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 638#define ADW_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */ 639#define ADW_WARN_ERROR 0xFFFF /* ADW_ERROR return */ 640 641/* 642 * Error code values for AdwInitAsc*Driver() functions 643 */ 644#define ADW_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ 645#define ADW_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 646#define ADW_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ 647#define ADW_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 648#define ADW_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ 649#define ADW_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 650#define ADW_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ 651#define ADW_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 652#define ADW_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ 653#define ADW_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ 654#define ADW_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ 655#define ADW_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ 656#define ADW_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ 657#define ADW_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ 658 659/* 660 * BIOS LRAM variable absolute offsets. 661 */ 662#define BIOS_CODESEG 0x54 663#define BIOS_CODELEN 0x56 664#define BIOS_SIGNATURE 0x58 665#define BIOS_VERSION 0x5A 666 667/* 668 * Chip Type flag values 669 */ 670#define ADW_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 671#define ADW_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 672#define ADW_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 673 674/* 675 * Adapter temporary configuration structure 676 * 677 * This structure can be discarded after initialization. Don't add 678 * fields here needed after initialization. 679 * 680 * Field naming convention: 681 * 682 * *_enable indicates the field enables or disables a feature. The 683 * value of the field is never reset. 684 */ 685typedef struct adw_dvc_cfg { 686 u_int16_t disc_enable; /* enable disconnection */ 687 u_int8_t chip_version; /* chip version */ 688 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 */ 689 u_int16_t pci_device_id; /* PCI device code number */ 690 u_int16_t lib_version; /* Adw Library version number */ 691 u_int16_t control_flag; /* Microcode Control Flag */ 692 u_int16_t mcode_date; /* Microcode date */ 693 u_int16_t mcode_version; /* Microcode version */ 694 u_int16_t pci_slot_info; /* high byte device/function number 695 bits 7-3 device num., 696 bits 2-0 function num. 697 low byte bus num. */ 698 u_int16_t serial1; /* EEPROM serial number word 1 */ 699 u_int16_t serial2; /* EEPROM serial number word 2 */ 700 u_int16_t serial3; /* EEPROM serial number word 3 */ 701} ADW_DVC_CFG; 702 703 704#define NO_OF_SG_PER_BLOCK 15 705 706typedef struct adw_sg_block { 707 u_int8_t reserved1; 708 u_int8_t reserved2; 709 u_int8_t reserved3; 710 u_int8_t sg_cnt; /* Valid entries in block. */ 711 u_int32_t sg_ptr; /* links to next sg block */ 712 struct { 713 u_int32_t sg_addr; /* SG element address */ 714 u_int32_t sg_count; /* SG element count */ 715 } sg_list[NO_OF_SG_PER_BLOCK]; 716} ADW_SG_BLOCK; 717 718 719/* 720 * Adapter operation variable structure. 721 * 722 * One structure is required per host adapter. 723 * 724 * Field naming convention: 725 * 726 * *_able indicates both whether a feature should be enabled or disabled 727 * and whether a device is capable of the feature. At initialization 728 * this field may be set, but later if a device is found to be incapable 729 * of the feature, the field is cleared. 730 */ 731#define CCB_HASH_SIZE 32 /* hash table size for phystokv */ 732#define CCB_HASH_SHIFT 9 733#define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1)) 734 735typedef int (* ADW_CALLBACK) (int); 736 737typedef struct adw_softc { 738 739 struct device sc_dev; 740 741 bus_space_tag_t sc_iot; 742 bus_space_handle_t sc_ioh; 743 bus_dma_tag_t sc_dmat; 744 bus_dmamap_t sc_dmamap_control; /* maps the control structures */ 745 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */ 746 void *sc_ih; 747 748 struct adw_control *sc_control; /* control structures */ 749 750 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE]; 751 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb; 752 TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb; 753 struct scsipi_adapter sc_adapter; 754 struct scsipi_channel sc_channel; 755 756 int sc_freeze_dev[ADW_MAX_TID+1]; 757 758 ADW_CALLBACK isr_callback; /* pointer to function, called in AdwISR() */ 759 ADW_CALLBACK async_callback; /* pointer to function, called in AdwISR() */ 760 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */ 761 u_int16_t wdtr_able; /* try WDTR for a device */ 762 u_int16_t sdtr_able; /* try SDTR for a device */ 763 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */ 764 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 765 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 766 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 767 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 768 u_int16_t tagqng_able; /* try tagged queuing with a device */ 769 u_int16_t ppr_able; /* PPR message capable per TID bitmask. */ 770 u_int16_t start_motor; /* start motor command allowed */ 771 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */ 772 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */ 773 u_int8_t chip_no; /* should be assigned by caller */ 774 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */ 775 u_int8_t irq_no; /* IRQ number */ 776 u_int8_t chip_type; /* chip SCSI target ID */ 777 u_int16_t no_scam; /* scam_tolerant of EEPROM */ 778 u_int32_t drv_ptr; /* driver pointer to private structure */ 779 u_int8_t chip_scsi_id; /* chip SCSI target ID */ 780 u_int8_t bist_err_code; 781 u_int16_t carr_pending_cnt; /* Count of pending carriers. */ 782 struct adw_carrier *carr_freelist; /* Carrier free list. */ 783 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */ 784 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */ 785 /* 786 * Note: The following fields will not be used after initialization. The 787 * driver may discard the buffer after initialization is done. 788 */ 789 ADW_DVC_CFG cfg; /* temporary configuration structure */ 790} ADW_SOFTC; 791 792 793/* 794 * ADW_SCSI_REQ_Q - microcode request structure 795 * 796 * All fields in this structure up to byte 60 are used by the microcode. 797 * The microcode makes assumptions about the size and ordering of fields 798 * in this structure. Do not change the structure definition here without 799 * coordinating the change with the microcode. 800 */ 801typedef struct adw_scsi_req_q { 802 u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */ 803 u_int8_t target_cmd; 804 u_int8_t target_id; /* Device target identifier. */ 805 u_int8_t target_lun; /* Device target logical unit number. */ 806 u_int32_t data_addr; /* Data buffer physical address. */ 807 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */ 808 u_int32_t sense_addr; /* Sense buffer physical address. */ 809 u_int32_t carr_ba; /* Carrier p-address */ 810 u_int8_t mflag; /* Adw Library flag field. */ 811 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */ 812 u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 813 u_int8_t scsi_cntl; 814 u_int8_t done_status; /* Completion status. (see below) */ 815 u_int8_t scsi_status; /* SCSI status byte. (see below) */ 816 u_int8_t host_status; /* ,uCode host status. (see below) */ 817 u_int8_t sg_working_ix; /* ,uCode working SG variable. */ 818 u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */ 819 u_int32_t sg_real_addr; /* SG list physical address. */ 820 u_int32_t scsiq_rptr; /* Iternal pointer to ADW_SCSI_REQ_Q */ 821 u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */ 822 u_int32_t ccb_ptr; /* CCB Physical Address */ 823 u_int32_t carr_va; /* Carrier v-address (unused) */ 824 /* 825 * End of microcode structure - 60 bytes. The rest of the structure 826 * is used by the Adw Library and ignored by the microcode. 827 */ 828 struct scsi_sense_data *vsense_addr; /* Sense buffer virtual address. */ 829 u_char *vdata_addr; /* Data buffer virtual address. */ 830} ADW_SCSI_REQ_Q; 831 832/* 833 * ASC_SCSI_REQ_Q 'done_status' return values. 834 */ 835#define QD_NO_STATUS 0x00 /* Request not completed yet. */ 836#define QD_NO_ERROR 0x01 837#define QD_ABORTED_BY_HOST 0x02 838#define QD_WITH_ERROR 0x04 839 840/* 841 * ASC_SCSI_REQ_Q 'host_status' return values. 842 */ 843#define QHSTA_NO_ERROR 0x00 844#define QHSTA_M_SEL_TIMEOUT 0x11 845#define QHSTA_M_DATA_OVER_RUN 0x12 846#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 847#define QHSTA_M_QUEUE_ABORTED 0x15 848#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 849#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 850#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 851#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 852#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 853#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 854#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 855/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 856#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 857#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 858#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 859#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 860#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 861#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 862#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 863#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 864#define QHSTA_M_WTM_TIMEOUT 0x41 865#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 866#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 867#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 868#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 869#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 870#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 871 872/* 873 * ASC_SCSI_REQ_Q 'scsi_status' return values. 874 */ 875#define SCSI_STATUS_GOOD 0x00 876#define SCSI_STATUS_CHECK_CONDITION 0x02 877#define SCSI_STATUS_CONDITION_MET 0x04 878#define SCSI_STATUS_TARGET_BUSY 0x08 879#define SCSI_STATUS_INTERMID 0x10 880#define SCSI_STATUS_INTERMID_COND_MET 0x14 881#define SCSI_STATUS_RSERV_CONFLICT 0x18 882#define SCSI_STATUS_CMD_TERMINATED 0x22 883#define SCSI_STATUS_QUEUE_FULL 0x28 884 885 886/* 887 * Microcode idle loop commands 888 */ 889#define IDLE_CMD_COMPLETED 0 890#define IDLE_CMD_STOP_CHIP 0x0001 891#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 892#define IDLE_CMD_SEND_INT 0x0004 893#define IDLE_CMD_ABORT 0x0008 894#define IDLE_CMD_DEVICE_RESET 0x0010 895#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 896#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 897#define IDLE_CMD_SCSIREQ 0x0080 898 899#define IDLE_CMD_STATUS_SUCCESS 0x0001 900#define IDLE_CMD_STATUS_FAILURE 0x0002 901 902/* 903 * AdwSendIdleCmd() flag definitions. 904 */ 905#define ADW_NOWAIT 0x01 906 907/* 908 * Wait loop time out values. 909 */ 910#define SCSI_WAIT_10_SEC 10UL /* 10 seconds */ 911#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 912#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 913#define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */ 914#define SCSI_MAX_RETRY 10 /* retry count */ 915 916#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 917#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 918#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 919 920#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 921 922 923/* Read byte from a register. */ 924#define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \ 925 bus_space_read_1((iot), (ioh), (reg_off)) 926 927/* Write byte to a register. */ 928#define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \ 929 bus_space_write_1((iot), (ioh), (reg_off), (byte)) 930 931/* Read word (2 bytes) from a register. */ 932#define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \ 933 bus_space_read_2((iot), (ioh), (reg_off)) 934 935/* Write word (2 bytes) to a register. */ 936#define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \ 937 bus_space_write_2((iot), (ioh), (reg_off), (word)) 938 939/* Write double word (4 bytes) to a register. */ 940#define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \ 941 bus_space_write_4((iot), (ioh), (reg_off), (dword)) 942 943/* Read byte from LRAM. */ 944#define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \ 945do { \ 946 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 947 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \ 948} while (0) 949 950/* Write byte to LRAM. */ 951#define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \ 952do { \ 953 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 954 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \ 955} while (0) 956 957/* Read word (2 bytes) from LRAM. */ 958#define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \ 959do { \ 960 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 961 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \ 962} while (0) 963 964/* Write word (2 bytes) to LRAM. */ 965#define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \ 966do { \ 967 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 968 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \ 969} while (0) 970 971/* Write double word (4 bytes) to LRAM */ 972/* Because of unspecified C language ordering don't use auto-increment. */ 973#define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \ 974do { \ 975 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \ 976 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 977 (u_int16_t) ((dword) & 0xFFFF)); \ 978 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \ 979 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \ 980 (u_int16_t) ((dword >> 16) & 0xFFFF)); \ 981} while (0) 982 983/* Read word (2 bytes) from LRAM assuming that the address is already set. */ 984#define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \ 985 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \ 986 987/* Write word (2 bytes) to LRAM assuming that the address is already set. */ 988#define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \ 989 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)) 990 991/* 992 * Define macro to check for Condor signature. 993 * 994 * Evaluate to ADW_TRUE if a Condor chip is found the specified port 995 * address 'iop_base'. Otherwise evalue to ADW_FALSE. 996 */ 997#define ADW_FIND_SIGNATURE(iot, ioh) \ 998 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \ 999 ADW_CHIP_ID_BYTE) && \ 1000 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \ 1001 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE) 1002 1003/* 1004 * Define macro to Return the version number of the chip at 'iop_base'. 1005 * 1006 * The second parameter 'bus_type' is currently unused. 1007 */ 1008#define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \ 1009 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV) 1010 1011/* 1012 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 1013 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 1014 * 1015 * If the request has not yet been sent to the device it will simply be 1016 * aborted from RISC memory. If the request is disconnected it will be 1017 * aborted on reselection by sending an Abort Message to the target ID. 1018 * 1019 * Return value: 1020 * ADW_TRUE(1) - Queue was successfully aborted. 1021 * ADW_FALSE(0) - Queue was not found on the active queue list. 1022 */ 1023#define ADW_ABORT_CCB(sc, ccb_ptr) \ 1024 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey) 1025 1026/* 1027 * Send a Bus Device Reset Message to the specified target ID. 1028 * 1029 * All outstanding commands will be purged if sending the 1030 * Bus Device Reset Message is successful. 1031 * 1032 * Return Value: 1033 * ADW_TRUE(1) - All requests on the target are purged. 1034 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1035 * are not purged. 1036 */ 1037#define ADW_RESET_DEVICE(sc, target_id) \ 1038 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0) 1039 1040/* 1041 * SCSI Wide Type definition. 1042 */ 1043#define ADW_SCSI_BIT_ID_TYPE u_int16_t 1044 1045/* 1046 * AdwInitScsiTarget() 'cntl_flag' options. 1047 */ 1048#define ADW_SCAN_LUN 0x01 1049#define ADW_CAPINFO_NOLUN 0x02 1050 1051/* 1052 * Convert target id to target id bit mask. 1053 */ 1054#define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID)) 1055 1056/* 1057 * Adv Library functions available to drivers. 1058 */ 1059 1060int AdwInitFromEEPROM(ADW_SOFTC *); 1061int AdwInitDriver(ADW_SOFTC *); 1062int AdwExeScsiQueue(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 1063int AdwISR(ADW_SOFTC *); 1064void AdwResetChip(bus_space_tag_t, bus_space_handle_t); 1065int AdwSendIdleCmd(ADW_SOFTC *, u_int16_t, u_int32_t); 1066int AdwResetSCSIBus(ADW_SOFTC *); 1067int AdwResetCCB(ADW_SOFTC *); 1068 1069#endif /* _ADVANSYS_WIDE_LIBRARY_H_ */ 1070