1/*	$NetBSD: zssp.c,v 1.12 2012/01/25 16:51:17 tsutsui Exp $	*/
2/*	$OpenBSD: zaurus_ssp.c,v 1.6 2005/04/08 21:58:49 uwe Exp $	*/
3
4/*
5 * Copyright (c) 2005 Uwe Stuehler <uwe@bsdx.de>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/cdefs.h>
21__KERNEL_RCSID(0, "$NetBSD: zssp.c,v 1.12 2012/01/25 16:51:17 tsutsui Exp $");
22
23#include <sys/param.h>
24#include <sys/systm.h>
25#include <sys/device.h>
26#include <sys/bus.h>
27
28#include <arm/xscale/pxa2x0reg.h>
29#include <arm/xscale/pxa2x0var.h>
30#include <arm/xscale/pxa2x0_gpio.h>
31
32#include <zaurus/dev/zsspvar.h>
33#include <zaurus/zaurus/zaurus_var.h>
34
35#define GPIO_ADS7846_CS_C3000	14	/* SSP SFRM */
36#define GPIO_MAX1111_CS_C3000	20
37#define GPIO_TG_CS_C3000	53
38#define GPIO_ADS7846_CS_C860	24	/* SSP SFRM */
39#define GPIO_MAX1111_CS_C860	20
40#define GPIO_TG_CS_C860		19
41
42#define SSCR0_ADS7846_C3000	0x06ab /* 12bit/Microwire/div by 7 */
43#define SSCR0_MAX1111		0x0387
44#define	SSCR0_LZ9JG18		0x01ab
45#define SSCR0_ADS7846_C860	0x00ab /* 12bit/Microwire/div by 7 */
46
47struct zssp_ads7846 {
48	u_int gpio;
49	uint32_t sscr0;
50};
51struct zssp_max1111 {
52	u_int gpio;
53	uint32_t sscr0;
54};
55struct zssp_lz9jg18 {
56	u_int gpio;
57	uint32_t sscr0;
58	int sclk_pin;
59	int sfrm_pin;
60	int txd_pin;
61	int rxd_pin;
62};
63
64struct zssp_softc {
65	device_t sc_dev;
66	bus_space_tag_t sc_iot;
67	bus_space_handle_t sc_ioh;
68	bus_addr_t sc_ssp;
69	struct zssp_ads7846 ads7846;
70	struct zssp_max1111 max1111;
71	struct zssp_lz9jg18 lz9jg18;
72};
73
74static int	zssp_match(device_t, cfdata_t, void *);
75static void	zssp_attach(device_t, device_t, void *);
76static int	zssp_search(device_t, cfdata_t, const int *, void *);
77static int	zssp_print(void *, const char *);
78
79CFATTACH_DECL_NEW(zssp, sizeof(struct zssp_softc),
80	zssp_match, zssp_attach, NULL, NULL);
81
82static void	zssp_init(void);
83static bool	zssp_resume(device_t dv, const pmf_qual_t *);
84
85static struct zssp_softc *zssp_sc;
86
87static int
88zssp_match(device_t parent, cfdata_t cf, void *aux)
89{
90
91	if (zssp_sc != NULL)
92		return 0;
93	return 1;
94}
95
96static void
97zssp_attach(device_t parent, device_t self, void *aux)
98{
99	struct zssp_softc *sc = device_private(self);
100
101	sc->sc_dev = self;
102	zssp_sc = sc;
103
104	aprint_normal("\n");
105	aprint_naive("\n");
106
107	sc->sc_iot = &pxa2x0_bs_tag;
108	if (ZAURUS_ISC1000 || ZAURUS_ISC3000) {
109		sc->sc_ssp = PXA2X0_SSP1_BASE;
110		sc->ads7846.gpio     = GPIO_ADS7846_CS_C3000;
111		sc->ads7846.sscr0    = SSCR0_ADS7846_C3000;
112		sc->max1111.gpio     = GPIO_MAX1111_CS_C3000;
113		sc->max1111.sscr0    = SSCR0_MAX1111;
114		sc->lz9jg18.gpio     = GPIO_TG_CS_C3000;
115		sc->lz9jg18.sscr0    = SSCR0_LZ9JG18;
116		sc->lz9jg18.sclk_pin = 19;
117		sc->lz9jg18.sfrm_pin = 14;
118		sc->lz9jg18.txd_pin  = 87;
119		sc->lz9jg18.rxd_pin  = 86;
120	} else {
121		sc->sc_ssp = PXA2X0_SSP_BASE;
122		sc->ads7846.gpio     = GPIO_ADS7846_CS_C860;
123		sc->ads7846.sscr0    = SSCR0_ADS7846_C860;
124		sc->max1111.gpio     = GPIO_MAX1111_CS_C860;
125		sc->max1111.sscr0    = SSCR0_MAX1111;
126		sc->lz9jg18.gpio     = GPIO_TG_CS_C860;
127		sc->lz9jg18.sscr0    = SSCR0_LZ9JG18;
128		sc->lz9jg18.sclk_pin = 23;
129		sc->lz9jg18.sfrm_pin = 24;
130		sc->lz9jg18.txd_pin  = 25;
131		sc->lz9jg18.rxd_pin  = 26;
132	}
133
134	if (bus_space_map(sc->sc_iot, sc->sc_ssp, PXA2X0_SSP_SIZE,
135	    0, &sc->sc_ioh)) {
136		aprint_error_dev(sc->sc_dev, "can't map bus space\n");
137		return;
138	}
139
140	if (!pmf_device_register(sc->sc_dev, NULL, zssp_resume))
141		aprint_error_dev(sc->sc_dev,
142		    "couldn't establish power handler\n");
143
144	zssp_init();
145
146	/* Attach all devices */
147	config_search_ia(zssp_search, self, "zssp", sc);
148}
149
150static int
151zssp_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
152{
153	struct zssp_attach_args aa;
154
155	aa.zaa_name = cf->cf_name;
156
157	if (config_match(parent, cf, &aa))
158		config_attach(parent, cf, &aa, zssp_print);
159
160	return 0;
161}
162
163static int
164zssp_print(void *aux, const char *name)
165{
166
167	return UNCONF;
168}
169
170/*
171 * Initialize the dedicated SSP unit and disable all chip selects.
172 * This function is called with interrupts disabled.
173 */
174static void
175zssp_init(void)
176{
177	struct zssp_softc *sc;
178
179	if (__predict_false(zssp_sc == NULL)) {
180		aprint_error("%s: not configured.\n", __func__);
181		return;
182	}
183	sc = zssp_sc;
184
185	pxa2x0_clkman_config(CKEN_SSP, 1);
186
187	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->lz9jg18.sscr0);
188	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0);
189
190	pxa2x0_gpio_set_function(sc->ads7846.gpio, GPIO_OUT|GPIO_SET);
191	pxa2x0_gpio_set_function(sc->max1111.gpio, GPIO_OUT|GPIO_SET);
192	pxa2x0_gpio_set_function(sc->lz9jg18.gpio, GPIO_OUT|GPIO_SET);
193}
194
195static bool
196zssp_resume(device_t dv, const pmf_qual_t *qual)
197{
198	int s;
199
200	s = splhigh();
201	zssp_init();
202	splx(s);
203
204	return true;
205}
206
207/*
208 * Transmit a single data word to one of the ICs, keep the chip selected
209 * afterwards, and don't wait for data to be returned in SSDR.  Interrupts
210 * must be held off until zssp_ic_stop() gets called.
211 */
212void
213zssp_ic_start(int ic, uint32_t data)
214{
215	struct zssp_softc *sc;
216
217	if (__predict_false(zssp_sc == NULL)) {
218		aprint_error("%s: not configured.\n", __func__);
219		return;
220	}
221	sc = zssp_sc;
222
223	/* disable other ICs */
224	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
225	if (ic != ZSSP_IC_ADS7846)
226		pxa2x0_gpio_set_bit(sc->ads7846.gpio);
227	if (ic != ZSSP_IC_LZ9JG18)
228		pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
229	if (ic != ZSSP_IC_MAX1111)
230		pxa2x0_gpio_set_bit(sc->max1111.gpio);
231
232	/* activate the chosen one */
233	switch (ic) {
234	case ZSSP_IC_ADS7846:
235		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0,
236		    sc->ads7846.sscr0);
237		pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
238		delay(1);	/* ADS7846 Tcss = 100ns */
239		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data);
240		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
241		    & SSSR_TNF) != SSSR_TNF)
242			continue;	/* poll */
243		break;
244	case ZSSP_IC_LZ9JG18:
245		pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
246		break;
247	case ZSSP_IC_MAX1111:
248		pxa2x0_gpio_clear_bit(sc->max1111.gpio);
249		break;
250	}
251}
252
253/*
254 * Read the last value from SSDR and deactivate all chip-selects.
255 */
256uint32_t
257zssp_ic_stop(int ic)
258{
259	struct zssp_softc *sc;
260	uint32_t rv;
261
262	if (__predict_false(zssp_sc == NULL)) {
263		aprint_error("%s: not configured.\n", __func__);
264		return 0;
265	}
266	sc = zssp_sc;
267
268	switch (ic) {
269	case ZSSP_IC_ADS7846:
270		/* read result of last command */
271		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
272		    & SSSR_RNE) != SSSR_RNE)
273			continue;	/* poll */
274		rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
275		break;
276	case ZSSP_IC_LZ9JG18:
277	case ZSSP_IC_MAX1111:
278		/* last value received is irrelevant or undefined */
279	default:
280		rv = 0;
281		break;
282	}
283
284	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
285	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
286	pxa2x0_gpio_set_bit(sc->max1111.gpio);
287
288	return rv;
289}
290
291/*
292 * Activate one of the chip-select lines, transmit one word value in
293 * each direction, and deactivate the chip-select again.
294 */
295uint32_t
296zssp_ic_send(int ic, uint32_t data)
297{
298
299	switch (ic) {
300	case ZSSP_IC_MAX1111:
301		return (zssp_read_max1111(data));
302	case ZSSP_IC_ADS7846:
303		return (zssp_read_ads7846(data));
304	case ZSSP_IC_LZ9JG18:
305		zssp_write_lz9jg18(data);
306		return 0;
307	default:
308		aprint_error("zssp: zssp_ic_send: invalid IC %d\n", ic);
309		return 0;
310	}
311}
312
313int
314zssp_read_max1111(uint32_t cmd)
315{
316	struct zssp_softc *sc;
317	int data[3];
318	int voltage[3];	/* voltage[0]: dummy */
319	int i;
320	int s;
321
322	if (__predict_false(zssp_sc == NULL)) {
323		aprint_error("%s: not configured.\n", __func__);
324		return 0;
325	}
326	sc = zssp_sc;
327
328	s = splhigh();
329
330	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
331	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->max1111.sscr0);
332
333	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
334	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
335	pxa2x0_gpio_clear_bit(sc->max1111.gpio);
336
337	delay(1);
338
339	memset(data, 0, sizeof(data));
340	data[0] = cmd;
341	for (i = 0; i < __arraycount(data); i++) {
342		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data[i]);
343		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
344		    & SSSR_TNF) != SSSR_TNF)
345			continue;	/* poll */
346		/* XXX is this delay necessary? */
347		delay(1);
348		while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
349		    & SSSR_RNE) != SSSR_RNE)
350			continue;	/* poll */
351		voltage[i] = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
352		    SSP_SSDR);
353	}
354
355	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
356	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
357	pxa2x0_gpio_set_bit(sc->max1111.gpio);
358
359	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
360
361	splx(s);
362
363	/* XXX no idea what this means, but it's what Linux would do. */
364	if ((voltage[1] & 0xc0) != 0 || (voltage[2] & 0x3f) != 0)
365		return -1;
366	return ((voltage[1] << 2) & 0xfc) | ((voltage[2] >> 6) & 0x03);
367}
368
369/* XXX - only does CS_ADS7846 */
370uint32_t
371zssp_read_ads7846(uint32_t cmd)
372{
373	struct zssp_softc *sc;
374	uint32_t val;
375	int s;
376
377	if (__predict_false(zssp_sc == NULL)) {
378		aprint_error("%s: not configured\n", __func__);
379		return 0;
380	}
381	sc = zssp_sc;
382
383	s = splhigh();
384
385	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0);
386	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, sc->ads7846.sscr0);
387
388	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
389	pxa2x0_gpio_set_bit(sc->max1111.gpio);
390	pxa2x0_gpio_clear_bit(sc->ads7846.gpio);
391	delay(1);	/* ADS7846 Tcss = 100ns */
392
393	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd);
394
395	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
396	    & SSSR_TNF) != SSSR_TNF)
397		continue;	/* poll */
398
399	delay(1);
400
401	while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR)
402	    & SSSR_RNE) != SSSR_RNE)
403		continue;	/* poll */
404
405	val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR);
406
407	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
408
409	splx(s);
410
411	return val;
412}
413
414void
415zssp_write_lz9jg18(uint32_t data)
416{
417	struct zssp_softc *sc;
418	int sclk_fn;
419	int sfrm_fn;
420	int txd_fn;
421	int rxd_fn;
422	int i;
423	int s;
424
425	KASSERT(zssp_sc != NULL);
426	sc = zssp_sc;
427
428	/* XXX this creates a DAC command from a backlight duty value. */
429	data = 0x40 | (data & 0x1f);
430
431	s = splhigh();
432
433	sclk_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sclk_pin);
434	sfrm_fn = pxa2x0_gpio_get_function(sc->lz9jg18.sfrm_pin);
435	txd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.txd_pin);
436	rxd_fn = pxa2x0_gpio_get_function(sc->lz9jg18.rxd_pin);
437
438	pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, GPIO_OUT | GPIO_SET);
439	pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, GPIO_OUT | GPIO_CLR);
440	pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, GPIO_OUT | GPIO_CLR);
441	pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, GPIO_IN);
442
443	pxa2x0_gpio_set_bit(sc->max1111.gpio);
444	pxa2x0_gpio_set_bit(sc->ads7846.gpio);
445	pxa2x0_gpio_clear_bit(sc->lz9jg18.gpio);
446
447	delay(10);
448
449	for (i = 0; i < 8; i++) {
450		if (data & 0x80)
451			pxa2x0_gpio_set_bit(sc->lz9jg18.txd_pin);
452		else
453			pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
454		delay(10);
455		pxa2x0_gpio_set_bit(sc->lz9jg18.sclk_pin);
456		delay(10);
457		pxa2x0_gpio_clear_bit(sc->lz9jg18.sclk_pin);
458		delay(10);
459		data <<= 1;
460	}
461
462	pxa2x0_gpio_clear_bit(sc->lz9jg18.txd_pin);
463	pxa2x0_gpio_set_bit(sc->lz9jg18.gpio);
464
465	pxa2x0_gpio_set_function(sc->lz9jg18.sclk_pin, sclk_fn);
466	pxa2x0_gpio_set_function(sc->lz9jg18.sfrm_pin, sfrm_fn);
467	pxa2x0_gpio_set_function(sc->lz9jg18.txd_pin, txd_fn);
468	pxa2x0_gpio_set_function(sc->lz9jg18.rxd_pin, rxd_fn);
469
470	splx(s);
471}
472