1/*	$NetBSD: pci_gio.c,v 1.9 2011/07/01 18:53:46 dyoung Exp $	*/
2
3/*
4 * Copyright (c) 2006 Stephen M. Rumble
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
13 *    derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.9 2011/07/01 18:53:46 dyoung Exp $");
29
30/*
31 * Glue for PCI devices that are connected to the GIO bus by various little
32 * GIO<->PCI ASICs.
33 *
34 * We presently support the following boards:
35 *	o Phobos G100/G130/G160	(if_tlp, lxtphy)
36 *	o Set Engineering GFE	(if_tl, nsphy)
37 */
38
39#include "opt_pci.h"
40#include "pci.h"
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/device.h>
45#include <sys/malloc.h>
46#include <sys/extent.h>
47
48#include <sys/bus.h>
49#include <machine/machtype.h>
50
51#include <sgimips/gio/giovar.h>
52#include <sgimips/gio/gioreg.h>
53#include <sgimips/gio/giodevs.h>
54
55#include <sgimips/dev/imcvar.h>
56
57#include <mips/cache.h>
58
59#include <dev/pci/pcivar.h>
60#include <dev/pci/pcireg.h>
61#include <dev/pci/pcidevs.h>
62#include <dev/pci/pciconf.h>
63
64int giopci_debug = 0;
65#define DPRINTF(_x)	if (giopci_debug) printf _x
66
67struct giopci_softc {
68	struct device			sc_dev;
69	struct sgimips_pci_chipset	sc_pc;
70	int				sc_slot;
71	int				sc_gprid;
72	uint32_t			sc_pci_len;
73	bus_space_tag_t			sc_iot;
74	bus_space_handle_t		sc_ioh;
75};
76
77static int	giopci_match(struct device *, struct cfdata *, void *);
78static void	giopci_attach(struct device *, struct device *, void *);
79static int	giopci_bus_maxdevs(pci_chipset_tag_t, int);
80static pcireg_t	giopci_conf_read(pci_chipset_tag_t, pcitag_t, int);
81static void	giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
82static int	giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
83static int	giopci_intr_map(const struct pci_attach_args *,
84		    pci_intr_handle_t *);
85static const char *
86		giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
87static void    *giopci_intr_establish(int, int, int (*)(void *), void *);
88static void	giopci_intr_disestablish(void *);
89
90#define PHOBOS_PCI_OFFSET	0x00100000
91#define PHOBOS_PCI_LENGTH	128		/* ~arbitrary */
92#define PHOBOS_TULIP_START	0x00101000
93#define PHOBOS_TULIP_END	0x001fffff
94
95#define SETENG_MAGIC_OFFSET	0x00020000
96#define SETENG_MAGIC_VALUE	0x00001000
97#define SETENG_PCI_OFFSET	0x00080000
98#define SETENG_PCI_LENGTH	128		/* ~arbitrary */
99#define SETENG_TLAN_START	0x00100000
100#define SETENG_TLAN_END		0x001fffff
101
102CFATTACH_DECL(giopci, sizeof(struct giopci_softc),
103    giopci_match, giopci_attach, NULL, NULL);
104
105static int
106giopci_match(struct device *parent, struct cfdata *match, void *aux)
107{
108	struct gio_attach_args *ga = aux;
109	int gprid;
110
111	/*
112	 * I think that these cards are all GIO32-bis or GIO64. Thus
113	 * they work in either Indigo2/Challenge M or
114	 * Indy/Challenge S/Indigo R4k, according to form factor. However,
115	 * there are some exceptions (e.g. my Indigo R4k won't power
116	 * on with the Set Engineering card installed).
117	 */
118	if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
119		return (0);
120
121	gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
122	if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 ||
123	    gprid == PHOBOS_G160 || gprid == SETENG_GFE)
124		return (1);
125
126	return (0);
127}
128
129static void
130giopci_attach(struct device *parent, struct device *self, void *aux)
131{
132	struct giopci_softc *sc = (void *)self;
133	pci_chipset_tag_t pc = &sc->sc_pc;
134	struct gio_attach_args *ga = aux;
135	uint32_t pci_off, pci_len, arb;
136	struct pcibus_attach_args pba;
137	u_long m_start, m_end;
138#ifdef PCI_NETBSD_CONFIGURE
139	extern int pci_conf_debug;
140
141	pci_conf_debug = giopci_debug;
142#endif
143
144	sc->sc_iot	= ga->ga_iot;
145	sc->sc_slot	= ga->ga_slot;
146	sc->sc_gprid	= GIO_PRODUCT_PRODUCTID(ga->ga_product);
147
148	if (mach_type == MACH_SGI_IP22 &&
149	    mach_subtype == MACH_SGI_IP22_FULLHOUSE)
150		arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
151	else
152		arb = GIO_ARB_RT | GIO_ARB_MST;
153
154	if (gio_arb_config(ga->ga_slot, arb)) {
155		printf(": failed to configure GIO bus arbiter\n");
156		return;
157	}
158
159#if (NIMC > 0)
160	imc_disable_sysad_parity();
161#endif
162
163	switch (sc->sc_gprid) {
164	case PHOBOS_G100:
165	case PHOBOS_G130:
166	case PHOBOS_G160:
167		pci_off = PHOBOS_PCI_OFFSET;
168		pci_len = PHOBOS_PCI_LENGTH;
169		m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
170		m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
171		break;
172
173	case SETENG_GFE:
174		/*
175		 * NB: The SetEng board does not allow the ThunderLAN's DMA
176		 *     engine to properly transfer segments that span page
177		 *     boundaries. See sgimips/autoconf.c where we catch a
178		 *     tl(4) device attachment and create an appropriate
179		 *     proplib entry to enable the workaround.
180		 */
181		pci_off = SETENG_PCI_OFFSET;
182		pci_len = SETENG_PCI_LENGTH;
183		m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
184		m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
185		bus_space_write_4(ga->ga_iot, ga->ga_ioh,
186		    SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
187		break;
188
189	default:
190		panic("giopci_attach: unsupported GIO product id 0x%02x",
191		    sc->sc_gprid);
192	}
193
194	if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
195	    &sc->sc_ioh)) {
196		printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname);
197		return;
198	}
199	sc->sc_pci_len = pci_len;
200
201	pc->pc_bus_maxdevs	= giopci_bus_maxdevs;
202	pc->pc_conf_read	= giopci_conf_read;
203	pc->pc_conf_write	= giopci_conf_write;
204	pc->pc_conf_hook	= giopci_conf_hook;
205	pc->pc_intr_map		= giopci_intr_map;
206	pc->pc_intr_string	= giopci_intr_string;
207	pc->intr_establish	= giopci_intr_establish;
208	pc->intr_disestablish	= giopci_intr_disestablish;
209	pc->iot			= ga->ga_iot;
210	pc->ioh			= ga->ga_ioh;
211	pc->cookie		= sc;
212
213	printf(": %s\n", gio_product_string(sc->sc_gprid));
214
215#ifdef PCI_NETBSD_CONFIGURE
216	pc->pc_memext = extent_create("giopcimem", m_start, m_end,
217	    NULL, 0, EX_NOWAIT);
218	pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0,
219	    mips_cache_info.mci_dcache_align);
220#endif
221
222	memset(&pba, 0, sizeof(pba));
223	pba.pba_memt	= SGIMIPS_BUS_SPACE_MEM;
224	pba.pba_dmat	= ga->ga_dmat;
225	pba.pba_pc	= pc;
226	pba.pba_flags	= PCI_FLAGS_MEM_OKAY;
227	/* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY  -- true ?! */
228
229	config_found_ia(self, "pcibus", &pba, pcibusprint);
230}
231
232static int
233giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
234{
235
236	return (busno == 0);
237}
238
239static pcireg_t
240giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
241{
242	struct giopci_softc *sc = pc->cookie;
243	int bus, dev, func;
244	pcireg_t data;
245
246	pci_decompose_tag(pc, tag, &bus, &dev, &func);
247	if (bus != 0 || dev != 0 || func != 0)
248		return (0);
249
250	/* XXX - should just use bus_space_peek */
251	if (reg >= sc->sc_pci_len) {
252		DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg));
253		return (0);
254	}
255
256	DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg));
257	data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
258	DPRINTF(("%08x\n", data));
259
260	return (data);
261}
262
263static void
264giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
265{
266	struct giopci_softc *sc = pc->cookie;
267	int bus, dev, func;
268
269	pci_decompose_tag(pc, tag, &bus, &dev, &func);
270	if (bus != 0 || dev != 0 || func != 0)
271		return;
272
273	/* XXX - should just use bus_space_poke */
274	if (reg >= sc->sc_pci_len) {
275		DPRINTF(("giopci_conf_write: reg 0x%x out of bounds "
276		    "(val = 0x%08x)\n", reg, data));
277		return;
278	}
279
280	DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data));
281	bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data);
282}
283
284static int
285giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function,
286    pcireg_t id)
287{
288
289	/* All devices use memory accesses only. */
290	return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM);
291}
292
293static int
294giopci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
295{
296	struct giopci_softc *sc = pa->pa_pc->cookie;
297
298	*ihp = sc->sc_slot;
299
300	return (0);
301}
302
303static const char *
304giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
305{
306	static char str[10];
307
308	snprintf(str, sizeof(str), "slot %s",
309	    (ih == GIO_SLOT_EXP0) ? "EXP0" :
310	    (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX");
311	return (str);
312}
313
314static void *
315giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg)
316{
317
318	return (gio_intr_establish(slot, level, func, arg));
319}
320
321static void
322giopci_intr_disestablish(void *cookie)
323{
324
325	panic("giopci_intr_disestablish: impossible.");
326}
327