1/* $NetBSD$ */ 2 3/* Structure for the IPL Control Block on RS/6000 machines */ 4 5#ifndef _IPLCB_H_ 6#define _IPLCB_H_ 7 8#define MAX_BUCS 32 9 10struct ipl_directory { 11 char iplcb_id[8]; /* ascii string id */ 12 uint32_t gpr_save_off; /* offset to gpr_save area */ 13 uint32_t cb_bitmap_size; /* size of bitmap and CB */ 14 uint32_t bitmap_off; /* offset to bitmap */ 15 uint32_t bitmap_size; /* size of bitmap */ 16 uint32_t iplinfo_off; 17 uint32_t iplinfo_size; 18 uint32_t iocc_post_off; 19 uint32_t iocc_post_size; 20 uint32_t nio_post_off; 21 uint32_t nio_post_size; 22 uint32_t sjl_post_off; 23 uint32_t sjl_post_size; 24 uint32_t scsi_post_off; 25 uint32_t scsi_post_size; 26 uint32_t eth_post_off; 27 uint32_t eth_post_size; 28 uint32_t tok_post_off; 29 uint32_t tok_post_size; 30 uint32_t ser_post_off; 31 uint32_t ser_post_size; 32 uint32_t par_post_off; 33 uint32_t par_post_size; 34 uint32_t rsc_post_off; 35 uint32_t rsc_post_size; 36 uint32_t lega_post_off; 37 uint32_t lega_post_size; 38 uint32_t kbd_post_off; 39 uint32_t kbd_post_size; 40 uint32_t ram_post_off; 41 uint32_t ram_post_size; 42 uint32_t sga_post_off; 43 uint32_t sga_post_size; 44 uint32_t fm2_post_off; 45 uint32_t fm2_post_size; 46 uint32_t net_boot_result_off; 47 uint32_t net_boot_result_size; 48 uint32_t csc_result_off; 49 uint32_t csc_result_size; 50 uint32_t menu_result_off; 51 uint32_t menu_result_size; 52 uint32_t cons_result_off; 53 uint32_t cons_result_size; 54 uint32_t diag_result_off; 55 uint32_t diag_result_size; 56 uint32_t rom_scan_off; /* pres of ROMSCAN adaptor */ 57 uint32_t rom_scan_size; 58 uint32_t sky_post_off; 59 uint32_t sky_post_size; 60 uint32_t global_off; 61 uint32_t global_size; 62 uint32_t mouse_off; 63 uint32_t mouse_size; 64 uint32_t vrs_off; 65 uint32_t vrs_size; 66 uint32_t taur_post_off; 67 uint32_t taur_post_size; 68 uint32_t ent_post_off; 69 uint32_t ent_post_size; 70 uint32_t vrs40_off; 71 uint32_t vrs40_size; 72 uint32_t gpr_save_area1[64]; 73 uint32_t sysinfo_offset; 74 uint32_t sysinfo_size; 75 uint32_t bucinfo_off; 76 uint32_t bucinfo_size; 77 uint32_t procinfo_off; 78 uint32_t procinfo_size; 79 uint32_t fm2_ioinfo_off; 80 uint32_t fm2_ioinfo_size; 81 uint32_t proc_post_off; 82 uint32_t proc_post_size; 83 uint32_t sysvpd_off; 84 uint32_t sysvpd_size; 85 uint32_t memdata_off; 86 uint32_t memdata_size; 87 uint32_t l2data_off; 88 uint32_t l2data_size; 89 uint32_t fddi_post_off; 90 uint32_t fddi_post_size; 91 uint32_t golden_vpd_off; 92 uint32_t golden_vpd_size; 93 uint32_t nvram_cache_off; 94 uint32_t nvram_cache_size; 95 uint32_t user_struct_off; 96 uint32_t user_struct_size; 97 uint32_t residual_off; 98 uint32_t residual_size; 99}; 100 101struct ipl_cb { 102 uint32_t gpr_save[32]; 103 struct ipl_directory dir; 104}; 105 106struct sys_info { 107 int nrof_procs; 108 int coherency_size; /* size of coherence block */ 109 int resv_size; /* size of reservation granule */ 110 u_char *arb_ctrl_addr; /* real addr of arbiter control reg */ 111 u_char *phys_id_addr; /* real addr of phys id reg */ 112 int nrof_bsrr; /* nrof 4 byte bos slot reset regs */ 113 u_char *bssr_addr; /* real addr of bssr */ 114 int tod_type; /* time of day type */ 115 u_char *todr_addr; /* real address of todr regs */ 116 u_char *rsr_addr; /* real address of reset status reg */ 117 u_char *pksr_addr; /* RA of power/keylock status reg */ 118 u_char *prcr_addr; /* RA of power/reset control reg */ 119 u_char *sssr_addr; /* RA of system specific regs */ 120 u_char *sir_addr; /* RA of system intr regs */ 121 u_char *scr_addr; /* RA of standard conf reg */ 122 u_char *dscr_addr; /* RA of dev spec. config reg */ 123 int nvram_size; /* in bytes */ 124 u_char *nvram_addr; /* RA of nvram */ 125 u_char *vpd_rom_addr; /* RA of VPD ROM space */ 126 int ipl_rom_size; /* in bytes */ 127 u_char *ipl_rom_addr; /* RA of IPL ROM space */ 128 u_char *g_mfrr_addr; /* RA of global mffr reg if != 0 */ 129 u_char *g_tb_addr; /* RA of global timebase if != 0 */ 130 int g_tb_type; /* global timebase type */ 131 int g_tb_mult; /* global timebase multiplier */ 132 int sp_errorlog_off;/* offset from BA of NVRAM to 133 * service processor error log tbl */ 134 u_char *pcccr_addr; /* RA of connectivity config reg */ 135 u_char *spocr_addr; /* RA of software power off ctrl reg */ 136 u_char *pfeivr_addr; /* RA of EPOW ext intr reg */ 137 /* Available Processor Mask interface */ 138 int access_id_waddr;/* type of access to loc_waddr */ 139 u_char *loc_waddr; /* RA of APM space write */ 140 int access_id_raddr;/* type of access to loc_raddr */ 141 u_char *loc_raddr; /* RA of APM space read */ 142 int architecture; /* Architecutre of this box: 143 * RS6K = 1 = rs/6000 old mca 144 * RSPC = 2 = PReP */ 145 int implementation; 146 /* Implementation of this box: 147 * RS6K_UP_MCA = 1 = POWER1, POWER2, RSC, PPC single proc 148 * RS6K_SMP_MCA = 2 = PPC SMP 149 * RSCP_UP_PCI = 3 = PPC/PReP single proc 150 */ 151 char pkg_desc[16]; /* NULL term ASCII string: */ 152 /* "rs6k" POWER1, POWER2, RSC, PPC single proc 153 * "rs6ksmp" PPC SMP 154 * "rspc" PReP 155 */ 156}; 157 158typedef struct buid_data { 159 int buid_value; /* assigned BUID value. 160 * values only have meaning if nrof_buids != 0. 161 * assigned in order until nrof_buids is satisfied, unused 162 * ones will be -1 163 */ 164 u_char *buid_sptr; /* pointer to buid's post structure */ 165} buid_data_t; 166 167struct buc_info { 168 uint32_t nrof_structs; /* nrof bucs present */ 169 uint32_t index; /* 0 <= index <= num_of_structs - 1 */ 170 uint32_t struct_size; /* in bytes */ 171 int bsrr_off; /* bus slot reset reg offset */ 172 uint32_t bsrr_mask; /* bssr mask */ 173 int bscr_val; /* config register value to enable */ 174 int cfg_status; /* 0 buc not configured 175 * 1 buc configd via config regs 176 * 2 configd via hardware defaults 177 * -1 config failed */ 178 int dev_type; /* 1 buc is executable memory 179 * 2 buc is a processor 180 * 3 buc is an io type */ 181 int nrof_buids; /* nrof buids needed by buc <=4 */ 182 buid_data_t buid_data[4]; 183 int mem_alloc1; /* 1st mem alloc required in MB */ 184 u_char *mem_addr1; /* RA of mem_alloc1 area */ 185 int mem_alloc2; /* 2nd mem alloc required */ 186 u_char *mem_addr2; /* RA of mem_alloc2 area */ 187 int vpd_rom_width; /* width of vpd interface in bytes */ 188 int cfg_addr_incr; /* config addr increment in bytes */ 189 int device_id_reg; /* std. config reg contents */ 190 uint32_t aux_info_off; /* iplcb offset to the device specific 191 * array for this buc. ie, if this is 192 * a proc, offset is the 193 * processor_info struct. 194 */ 195 uint32_t feature_rom_code; /* romscan post flag */ 196 uint32_t IOCC_flag; /* 0 not IOCC 1 = IOCC */ 197 char location[4]; /* location of the BUC */ 198}; 199 200struct proc_info { 201 uint32_t nrof_structs; 202 uint32_t index; 203 uint32_t struct_size; 204 uint32_t per_buc_info_off; /* iplcb offset to buc_info for me */ 205 u_char *proc_int_area; 206 /* Base Addr of this proc's intr presentation layer regs 207 * BA+0 (CPPR||XISR without side effects) 208 * BA+4 (CPPR||XISR with side effects) 209 * BA+8 (DSIER) 210 * BA+12 (MFRR) 211 * BA+xx (Additional Optional MFRR's) 212 */ 213 uint32_t proc_int_area_size; /* size/4 == nrof intr pres regs */ 214 int proc_present; /* 0 no, -1 dead, 1 running, 2 loop 215 * 3 reset state */ 216 uint32_t test_run; /* which tests were run on proc */ 217 uint32_t test_stat; /* test status */ 218 int link; /* 0 = loop until nonzero !=0 branch to 219 * link addr */ 220 u_char *lind_addr; /* see above */ 221 union { 222 uint32_t p_id; /* unique proc id */ 223 struct { 224 uint16_t p_nodeid; /* phys NUMA nodeid */ 225 uint16_t p_cpuid; /* phys cpu id */ 226 } s0; 227 } u0; 228 int architecture; /* proc arch */ 229 int implementation; /* proc type */ 230 int version; /* proc version */ 231 int width; /* proc data word size */ 232 int cache_attrib; /* bit 0 = cache not, cache is present 233 * bit 1 = separate cache/combined */ 234 int coherency_size; /* size of coherence block */ 235 int resv_size; /* size of reservation granule */ 236 int icache_block; /* L1 icache block size */ 237 int dcache_block; /* L1 dcache block size */ 238 int icache_size; /* L1 icache size */ 239 int dcache_size; /* L1 dcache size */ 240 int icache_line; /* L1 icache line size */ 241 int dcache_line; /* L1 dcache line size */ 242 int icache_asc; /* L1 icache associativity */ 243 int dcache_asc; /* L1 dcache associativity */ 244 int L2_cache_size; /* L2 cache size */ 245 int L2_cach_asc; /* L2 cache associativity */ 246 int tlb_attrib; /* tlb buffer attribute bitfield 247 * 0 present/not present 248 * 1 separate/combined i/d 249 * 4 proc supports tlbia */ 250 int itlb_size; /* entries */ 251 int dtlb_size; 252 int itlb_asc; 253 int dtlb_asc; 254 int slb_attrib; /* segment lookaside buffer bitfield 255 * 0 slb not/present 256 * 1 separate/combined i/d */ 257 int islb_size; /* entries */ 258 int dslb_size; 259 int islb_asc; 260 int dslb_asc; 261 int priv_lck_cnt; /* spin lock count */ 262 int rtc_type; /* RTC type */ 263 int rtcXint; /* nanosec per timebase tick int mult*/ 264 int rtcXfrac; /* same, but fraction multiplier */ 265 int bus_freq; /* bus clock in Hz */ 266 int tb_freq; /* time base clockfreq */ 267 char proc_desc[16]; /* processor name ASCII string */ 268}; 269 270/* One SIMM is a nibble wide and will have the value of: 271 * 0x0 == good or 0xf == bad 272 */ 273struct simm_def { 274 u_char simm_7and8; 275 u_char simm_3and4; 276 u_char simm_5and6; 277 u_char simm_1and2; 278}; 279 280/* 281 * The IPL Info structure is mostly good for telling us the cache sizes and 282 * model codes. The whole thing is unreasonably large and verbose. 283 */ 284 285struct ipl_info { 286 /* IPL controller and device interface routine */ 287 u_char *iplcnd_ptr; /* ROM Reserved */ 288 uint32_t iplcnd_size; 289 /* NVRAM expansion code */ 290 u_char *nvram_exp_ptr; /* ROM Reserved */ 291 uint32_t nvram_exp_size; 292 /* IPL ROM stack high addr */ 293 u_char *ipl_ros_stack_ptr; /* ROM Reserved */ 294 uint32_t ipl_ros_stack_size; 295 /* IPL Record */ 296 u_char *ipl_rec_ptr; /* ROM Reserved */ 297 uint32_t ipl_rec_size; 298 /* Lowest addr needed by IPL ROM */ 299 u_char *ros_workarea_lwm; /* ROM Reserved */ 300 /* IPL ROM entry table. t=0, SR15 */ 301 u_char *ros_entry_tbl_ptr; /* ROM Reserved */ 302 uint32_t ros_entry_tbl_size; 303 /* Memory bit maps nrof bytes per bit. 16K/bit */ 304 uint32_t bit_map_bytes_per_bit; /* ROM Reserved */ 305 /* Highest addressable real address byte + 1. */ 306 uint32_t ram_size; /* ROM Reserved */ 307 /* 308 * Model Field: 309 * 0xWWXXYYZZ 310 * WW == 0x00. hardware is SGR ss32 or ss64. (ss is speed in MHz) 311 * icache is 8k. 312 * XX == reserved 313 * YY == reserved 314 * ZZ == model code: 315 * bits 0,1 (low order) == style 316 * 00=Tower 01=Desktop 10=Rack 11=Reserved 317 * bits 2,3 == relative speed 318 * 00=slow 01=Medium 10=High 11=Fast 319 * bit 4 == number of combo chips 320 * 0 = 2 chips. 1 = 1 chip. 321 * bit 5 == Number of DCU's. 322 * 0 = 4 DCU's cache is 64k. 323 * 1 = 2 DCU's cache is 32K. 324 * bits 6,7 = Reserved 325 * WW != 0x00: 326 * WW == 0x01. Hardware is SGR ss32 or ss64 RS1. (POWER) 327 * WW == 0x02. RSC (RISC Single Chip) 328 * WW == 0x04. POWER2/RS2 329 * WW == 0x08. PowerPC 330 * XX == Package type 331 * bits 0,1 (low order) == style 332 * 00=Tower 01=Desktop 10=Rack 11=Entry Server 333 * bit 2 - AIX Hardware verification test supp (rspc) 334 * bit 3 - AIX Hardware error log analysis supp (rspc) 335 * bit 4-7 reserved 336 * YY == Reserved 337 * ZZ == Model code. (useless) 338 * Icache K size is obtained from entry icache. 339 * Dcache K size is obtained from entry dcache. 340 */ 341 uint32_t model; 342 /* Power status and keylock register decode. IO Addr 0x4000E4. 343 * 32bit reg: 344 * Power Status bits 0-9 345 * Reserved bits 10-27 346 * Keylock decode bits 28-31: (X == don't care) 347 * 28 29 30 31 348 * 1 1 X X Workstation 349 * 0 1 X X Supermini 350 * 0 0 X X Expansion 351 * X X 1 1 Normal mode 352 * X X 1 0 Service mode 353 * X X 0 1 Secure mode 354 */ 355 uint32_t powkey_reg; /* ROM Reserved */ 356 /* Set to zero during power on, inc'd with each warm IPL */ 357 int32_t soft_reboot_count; 358 /* Set and used by IPL controller, all are ROM Reserved */ 359 int32_t nvram_section1_valid; /* 0 if CRC bad */ 360 int32_t nvram_exp_valid; /* 0 if CRC bad */ 361 u_char prevboot_dev[36]; /* last normal mode ipl */ 362 char reserved[28]; 363 /* Pointer to the IPLCB in memory */ 364 u_char *iplcb_ptr; /* ROM Reserved */ 365 /* Pointer to compressed BIOS code */ 366 u_char *bios_ptr; /* ROM Reserved */ 367 uint32_t bios_size; 368 uint32_t cre[16]; /* Storage Configuration Registers. */ 369 uint32_t bscr[16]; /* Bit steering registers */ 370 /* Unimplemented and ROM Reserved */ 371 struct { 372 uint32_t synd; 373 uint32_t addr; 374 uint32_t status; 375 } single_bit_error[16]; 376 uint32_t reserved_array[5*16]; 377 /* Memory extent test indicators */ 378 u_char extent_test_ind[16]; /* 0 = untested, 1 = tested */ 379 /* Memory bit steering register settig conflict indicator */ 380 u_char bit_steer_conflict[16]; /* 1 = conflict */ 381 /* Set by IPL controller, ROM Reserved */ 382 uint32_t ipl_ledval; /* IPL LED value */ 383 uint32_t ipl_device; /* ??? */ 384 char unused[18]; 385 386 /* Copied from IPL Rom VPD area */ 387 char vpd_planar_partno[8]; 388 char vpd_planar_ecno[8]; 389 char vpd_proc_serialno[8]; 390 char vpd_ipl_ros_partno[8]; 391 char vpd_ipl_ros_version[14]; 392 char ipl_ros_copyright[49]; 393 char ipl_ros_timestamp[10]; 394 395 /* Copied from NVRAM */ 396 union { 397 uint32_t chip_signature; 398 struct chip_sig { 399 u_char cop_bus_addr; 400 u_char obsolete_u_num; 401 u_char dd_num; 402 u_char partno; 403 } chip_sig; 404 } floating_point, fixed_point, instruction_cache_unit, 405 storage_control_unit, combo_1, combo_2, data_control_unit_0, 406 data_control_unit_1, data_control_unit_2, data_control_unit_3; 407 408 /* Memory SIMM error information. 409 * 8 cards (A-H) 8 simms per card (1-8). 410 * Two cache line sizes. if 128 use memory_card_1n data, 411 * otherwise use memory_card_9n or memory_card_Tn. 412 */ 413 union { 414 char memcd_errinfo[32]; 415 uint32_t slots_of_simm[8]; 416 struct { /* cache line size 128 */ 417 struct simm_def memory_card_1H; 418 struct simm_def memory_card_1F; 419 struct simm_def memory_card_1G; 420 struct simm_def memory_card_1E; 421 struct simm_def memory_card_1D; 422 struct simm_def memory_card_1B; 423 struct simm_def memory_card_1C; 424 struct simm_def memory_card_1A; 425 } simm_stuff_1; 426 struct { /* cache line size 64 */ 427 struct simm_def memory_card_9H; 428 struct simm_def memory_card_9D; 429 struct simm_def memory_card_9F; 430 struct simm_def memory_card_9B; 431 struct simm_def memory_card_9G; 432 struct simm_def memory_card_9C; 433 struct simm_def memory_card_9E; 434 struct simm_def memory_card_9A; 435 } simm_stuff_9; 436 struct { /* cache line size 64 */ 437 struct simm_def memory_card_TB; 438 struct simm_def memory_card_TC; 439 } simm_stuff_T; 440 } simm_info; 441 442 /* MESR error info at IPL ROM memory config time. 443 * Two cache line sizes, similar to above. 444 * find one of the following values in the word variable: 445 * 0x00000000 no MESR error occurred when configuring this extent 446 * 0xe0400000 timeout. no memcard is in the slot. 447 * otherwise, an error occurred, so the card exists but will not 448 * be used. 449 */ 450 union { 451 char extent_errinfo[64]; 452 struct { /* cacheline 128 */ 453 uint32_t ext_0_slot_HandD; 454 uint32_t ext_1_slot_HandD; 455 uint32_t ext_2_slot_HandD; 456 uint32_t ext_3_slot_HandD; 457 uint32_t ext_4_slot_FandB; 458 uint32_t ext_5_slot_FandB; 459 uint32_t ext_6_slot_FandB; 460 uint32_t ext_7_slot_FandB; 461 uint32_t ext_8_slot_GandC; 462 uint32_t ext_9_slot_GandC; 463 uint32_t ext_10_slot_GandC; 464 uint32_t ext_11_slot_GandC; 465 uint32_t ext_12_slot_EandA; 466 uint32_t ext_13_slot_EandA; 467 uint32_t ext_14_slot_EandA; 468 uint32_t ext_15_slot_EandA; 469 } MESR_err_1; 470 struct { /* cacheline of 64 */ 471 uint32_t ext_0_slot_H; 472 uint32_t ext_1_slot_H; 473 uint32_t ext_2_slot_D; 474 uint32_t ext_3_slot_D; 475 uint32_t ext_4_slot_F; 476 uint32_t ext_5_slot_F; 477 uint32_t ext_6_slot_B; 478 uint32_t ext_7_slot_B; 479 uint32_t ext_8_slot_G; 480 uint32_t ext_9_slot_G; 481 uint32_t ext_10_slot_C; 482 uint32_t ext_11_slot_C; 483 uint32_t ext_12_slot_E; 484 uint32_t ext_13_slot_E; 485 uint32_t ext_14_slot_A; 486 uint32_t ext_15_slot_A; 487 } MESR_err_9; 488 } config_err_info; 489 char unused_errinfo[64]; 490 491 /* 492 * Memory card VPD data area 493 * cacheline sizes like above. 494 * 0xffffffff = card is present, no VPD 495 * 0x22222222 = card present with errors 496 * 0x11111111 = no card 497 * otherwise it's good. 498 */ 499 union { 500 char memcd_vpd[128]; 501 struct { /* cacheline 128 */ 502 char ext_0_HandD[20]; 503 char ext_4_FandB[20]; 504 char ext_8_GandC[20]; 505 char ext_12_EandA[20]; 506 } memory_vpd_1; 507 struct { /* cacheline 64 */ 508 char ext_0_slot_H[10]; 509 char dmy_0[2]; 510 char ext_2_slot_D[10]; 511 char dmy_2[2]; 512 char ext_4_slot_F[10]; 513 char dmy_4[2]; 514 char ext_6_slot_B[10]; 515 char dmy_6[2]; 516 char ext_8_slot_G[10]; 517 char dmy_8[2]; 518 char ext_10_slot_C[10]; 519 char dmy_10[2]; 520 char ext_12_slot_E[10]; 521 char dmy_12[2]; 522 char ext_14_slot_A[10]; 523 char dmy_14[2]; 524 } memory_vpd_9; 525 } memcd_vpd; 526 527 int32_t cache_line_size; 528 /* Component reset register test results for BUID 20. 529 * Anything other than 0x00AA55FF is horked. 530 */ 531 int32_t CRR_results; 532 /* IO planar level register 533 * 0x1YYXXXXX = family 2 534 * 0x8YYXXXXX = table/desktop YY is engineering level, X reserved 535 * -1 == not present 536 * Values in MSB has following meaning: 537 * 0x80 = table/desktop 538 * 0x40 = reserved 539 * 0x20 = reserved 540 * 0x10 = rack planar 541 * 0x08 = standard IO 542 * 0x04 = power connector not connected 543 * 0x02, 0x01 reserved 544 */ 545 int32_t io_planar_level_reg; /* BUID 20 */ 546 int32_t io_planar_level_reg_21; 547 int32_t io_planar_level_reg_22; 548 int32_t io_planar_level_reg_23; 549 550 /* Component regsiter test results for the other BUID's */ 551 int32_t CRR_results_21; 552 int32_t CRR_results_22; 553 int32_t CRR_results_23; 554 555 /* CRR results for BUID 20 */ 556 int32_t CRR_results_20_0; /* should contain 0x00000000 */ 557 int32_t CRR_results_20_a; /* should contain 0xaaaaaaaa */ 558 int32_t CRR_results_20_5; /* should contain 0x55555555 */ 559 int32_t CRR_results_20_f; /* should contain 0xffffffff */ 560 int32_t CRR_results_21_0; /* should contain 0x00000000 */ 561 int32_t CRR_results_21_a; /* should contain 0xaaaaaaaa */ 562 int32_t CRR_results_21_5; /* should contain 0x55555555 */ 563 int32_t CRR_results_21_f; /* should contain 0xffffffff */ 564 int32_t CRR_results_22_0; /* should contain 0x00000000 */ 565 int32_t CRR_results_22_a; /* should contain 0xaaaaaaaa */ 566 int32_t CRR_results_22_5; /* should contain 0x55555555 */ 567 int32_t CRR_results_22_f; /* should contain 0xffffffff */ 568 int32_t CRR_results_23_0; /* should contain 0x00000000 */ 569 int32_t CRR_results_23_a; /* should contain 0xaaaaaaaa */ 570 int32_t CRR_results_23_5; /* should contain 0x55555555 */ 571 int32_t CRR_results_23_f; /* should contain 0xffffffff */ 572 573 /* IO interrupt test results for BUID 21 */ 574 int32_t io_intr_results_21; 575 /* pointer to IPL rom code in mem */ 576 u_char *rom_ram_addr; /* ROM Reserved */ 577 uint32_t rom_ram_size; 578 /* Storage control config register, ROM Reserved */ 579 uint32_t sccr_toggle_one_meg; 580 /* read from OCS NVRAM area */ 581 uint32_t aix_model_code; /* 4 bytes from 0xA0003d0 */ 582 /* The following entries are read from the OCS NVRAM area 583 * ---------: dcache size = 0x0040 icache size = 0x0008 584 * ---------: dcache size = 0x0020 icache size = 0x0008 585 * ---------: dcache size = 0x0008 icache size = 0x0008 586 * ---------: dcache size = 0x0040 icache size = 0x0020 587 * ---------: dcache size = 0x0020 icache size = 0x0008 588 */ 589 int32_t dcache_size; /* 4 bytes from NVRAM 0xA0003d4 */ 590 int32_t icache_size; /* 4 bytes from NVRAM address 0xA0003d8 */ 591 char vpd_model_id[8]; 592 593 /* saves the ptr to lowest addr needed by IPL rom */ 594 u_char *low_boundary_save; /* ROM Reserved */ 595 /* Pointer to romscan entry point and data area. ROM Reserved */ 596 u_char *romscan_code_ptr; /* runtime entry point of rom scan */ 597 u_char *rom_boot_data_area; /* runtime user ram ( >= 4K)*/ 598}; 599 600 601 602 603#endif /* _IPLCB_H_ */ 604