1/* $NetBSD: e500reg.h,v 1.9 2011/06/30 04:45:04 matt Exp $ */ 2/*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#include <sys/cdefs.h> 38 39#ifdef _LOCORE 40#define __PPCBIT(n) (1 << (31 - (n))) 41#define __PPCBITS(m, n) (((1 << ((n) - (m) + 1)) - 1) << (31 - (m))) 42#else 43#define __PPCBIT(n) __BIT(31-(n)) 44#define __PPCBITS(m,n) __BITS(31-(n),31-(m)) 45#endif 46 47#define GUR_SIZE 0x100000 48#define GUR_BPTR 0x0020 /* Boot Page Translation */ 49#define BPTR_EN __PPCBIT(0) /* Boot Page Enabled */ 50#define BPTR_BOOT_PAGE __PPCBITS(8,31) /* high 24 bits of phys addr */ 51 52#define DDRC1_BASE 0x02000 53#define DDRC2_BASE 0x06000 54#define DDRC_SIZE 0x01000 55 56#ifdef DDRC_PRIVATE 57#define CS_BNDS(n) (0x000 + 0x008 * (n)) 58#define BNDS_SA __PPCBITS(4,15) 59#define BNDS_SA_GET(n) (((n) & BNDS_SA) << 8) 60#define BNDS_EA __PPCBITS(20,31) 61#define BNDS_EA_GET(n) (((n) & BNDS_EA) << 24) 62#define BNDS_SIZE_GET(n) \ 63 ((((((n) & BNDS_EA) + __LOWEST_SET_BIT(BNDS_EA)) << 16) - (((n) & BNDS_SA))) << 8) 64#define CS_CONFIG(n) (0x080 + 0x004 * (n)) 65#define CS_CONFIG_EN __PPCBIT(0) 66 67#define DDR_SDRAM_CFG 0x110 68#define SDRAM_CFG_MEM_EN __PPCBIT(0) 69#define SDRAM_CFG_SREN __PPCBIT(1) 70#define SDRAM_CFG_ECC_EN __PPCBIT(2) 71#define SDRAM_CFG_RDEN __PPCBIT(3) 72#define SDRAM_CFG_TYPE __PPCBITS(5,7) 73#define SDRAM_CFG_TYPE_DDR2 3 74#define SDRAM_CFG_TYPE_DDR3 7 75#define SDRAM_CFG_DYN_PWR __PPCBIT(10) 76#define SDRAM_CFG_DBW __PPCBITS(11,12) 77#define SDRAM_CFG_DBW_64BIT 0 78#define SDRAM_CFG_DBW_32BIT 1 79 80#define CAPTURE_DATA_HI 0xe20 81#define CAPTURE_DATA_LO 0xe24 82#define CAPTURE_ECC 0xe28 83 84#define ERR_DETECT 0xe40 85#define ERR_DISABLE 0xe44 86#define ERR_INT_EN 0xe48 87 88#define ERR_MMEE __PPCBIT(0) 89#define ERR_APEE __PPCBIT(23) 90#define ERR_ACEE __PPCBIT(24) 91#define ERR_MBEE __PPCBIT(28) 92#define ERR_SBEE __PPCBIT(29) 93#define ERR_MSEE __PPCBIT(31) 94 95#define CAPTURE_ATTRIBUTES 0xe4c 96#define CATTR_BNUM __PPCBITS(1,3) 97#define CATTR_TSIZ __PPCBITS(5,7) 98#define CATTR_TSRC __PPCBITS(11,15) 99#define CATTR_TTYP __PPCBITS(18,19) 100#define CATTR_VLD __PPCBIT(31) 101 102#define CAPTURE_ADDRESS 0xe50 103#define CAPTURE_EXT_ADDRESS 0xe54 104 105#define ERR_SBE 0xe58 106#define ERR_SBE_SBET __PPCBITS(8,15) 107#define ERR_SBE_SBEC __PPCBITS(24,31) 108 109#endif /* DDRC_PRIVATE */ 110 111#define GPIO_BASE 0x0fc00 112#define GPIO_SIZE 0x00020 113 114#ifdef GPIO_PRIVATE 115 116#define GPDIR 0x00 /* GPIO direction register */ 117#define GPODR 0x04 /* GPIO open drain register */ 118#define GPDAT 0x08 /* GPIO data register */ 119#define GPIER 0x0C /* GPIO interrupt event register */ 120#define GPIMR 0x10 /* GPIO interrupt mask register */ 121#define GPICR 0x14 /* GPIO external interrupt control register */ 122 123#endif /* GPIO_PRIVATE */ 124 125#define PCIE1_BASE 0x0a000 126#define PCIE2_MPC8572_BASE 0x09000 /* P2020 too */ 127#define PCIE3_MPC8572_BASE 0x08000 /* P2020 too */ 128#define PCIX1_MPC8548_BASE 0x08000 129#define PCIX2_MPC8548_BASE 0x09000 130#define PCIE2_MPC8544_BASE 0x09000 /* MPC8536 too */ 131#define PCIE3_MPC8544_BASE 0x0b000 /* MPC8536 too */ 132#define PCIX1_MPC8544_BASE 0x08000 /* MPC8536 too */ 133#define PCI_SIZE 0x01000 134 135#ifdef PCI_PRIVATE 136 137/* PCI Express Configuration Access Registers */ 138#define PEX_CONFIG_ADDR 0x000 /* PCI Express configuration address register */ 139#define PCI_CONFIG_ADDR PEX_CONFIG_ADDR 140#define PEX_CONFIG_ADDR_EN __PPCBIT(0) 141#define PEX_CONFIG_ADDR_TAG(b,d,f,r) (((b) << 16) | ((d) << 11) | ((f) << 8) | (r)) 142#define PEX_CONFIG_DATA 0x004 /* PCI Express configuration data register */ 143#define PCI_CONFIG_DATA PEX_CONFIG_DATA 144#define PCI_INT_ACK 0x008 /* PCI Interrupt Acknowledge */ 145#define PEX_OTB_CPL_TOR 0x00C /* PCI Express outbound completion timeout register */ 146#define PEX_CONF_RTY_TOR 0x010 /* PCI Express configuration retry timeout register */ 147#define PEX_CONFIG 0x014 /* PCI Express configuration register */ 148 149/* PCI Express Power Management Event & Message Registers */ 150#define PEX_PME_MES_DR 0x020 /* PCI Express PME & message detect register */ 151#define PEX_PME_MES_DISR 0x024 /* PCI Express PME & message disable register */ 152#define PEX_PME_MES_IER 0x028 /* PCI Express PME & message interrupt enable register */ 153#define PEX_PMCR 0x02C /* PCI Express power management command register */ 154 155/* PCI Express IP Block Revision Registers */ 156#define PEX_IP_BLK_REV1 0xBF8 /* IP block revision register 1 */ 157#define PEX_IP_BLK_REV2 0xBFC /* IP block revision register 2 */ 158 159/* PCI Express / PCI-X ATMU Registers */ 160#define PEXOWAR_EN __PPCBIT(0) /* enable window */ 161#define PEXOWAR_ROE __PPCBIT(3) /* relaxed ordering enable */ 162#define PEXOWAR_NS __PPCBIT(4) /* no snoop enable */ 163#define PEXOWAR_TC __PPCBITS(8,10) /* traffic class PCIEX only */ 164#define PEXOWAR_TC0 __SHIFTIN(0, PEXOWAR_TC) 165#define PEXOWAR_TC1 __SHIFTIN(1, PEXOWAR_TC) 166#define PEXOWAR_TC2 __SHIFTIN(2, PEXOWAR_TC) 167#define PEXOWAR_TC3 __SHIFTIN(3, PEXOWAR_TC) 168#define PEXOWAR_TC4 __SHIFTIN(4, PEXOWAR_TC) 169#define PEXOWAR_TC5 __SHIFTIN(5, PEXOWAR_TC) 170#define PEXOWAR_TC6 __SHIFTIN(6, PEXOWAR_TC) 171#define PEXOWAR_TC7 __SHIFTIN(7, PEXOWAR_TC) 172#define PEXOWAR_RTT __PPCBITS(12,15) /* read transaction type */ 173#define PEXOWAR_RTT_CONF __SHIFTIN(2, PEXOWAR_RTT) /* PCIEX only */ 174#define PEXOWAR_RTT_MEM __SHIFTIN(4, PEXOWAR_RTT) 175#define PEXOWAR_RTT_IO __SHIFTIN(8, PEXOWAR_RTT) 176#define PEXOWAR_WTT __PPCBITS(16,19) /* write transaction type */ 177#define PEXOWAR_WTT_CONF __SHIFTIN(2, PEXOWAR_WTT) /* PCIEX only */ 178#define PEXOWAR_WTT_MEM __SHIFTIN(4, PEXOWAR_WTT) 179#define PEXOWAR_WTT_IO __SHIFTIN(8, PEXOWAR_WTT) 180#define PEXOWAR_OWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 181 182/* PCI Express / PCI-X ATMU Registers */ 183#define PEXIWAR_EN __PPCBIT(0) /* enable window */ 184#define PEXIWAR_PF __PPCBIT(3) /* prefetchable */ 185#define PEXIWAR_TRGT __PPCBITS(8,11) /* traffic class PCIEX only */ 186#define PEXIWAR_TRGT_PCI1 __SHIFTIN(0, PEXIWAR_TRGT) 187#define PEXIWAR_TRGT_PCI2 __SHIFTIN(1, PEXIWAR_TRGT) 188#define PEXIWAR_TRGT_PCIEX __SHIFTIN(2, PEXIWAR_TRGT) 189#define PEXIWAR_TRGT_SRIO __SHIFTIN(12, PEXIWAR_TRGT) 190#define PEXIWAR_TRGT_LOCALMEM __SHIFTIN(15, PEXIWAR_TRGT) 191#define PEXIWAR_RTT __PPCBITS(12,15) /* read transaction type */ 192#define PEXIWAR_RTT_MEM __SHIFTIN(4, PEXIWAR_RTT) 193#define PEXIWAR_RTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_RTT) 194#define PEXIWAR_RTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_RTT) 195#define PEXIWAR_RTT_MEM_ULCKL2 __SHIFTIN(7, PEXIWAR_RTT) 196#define PEXIWAR_WTT __PPCBITS(16,19) /* write transaction type */ 197#define PEXIWAR_WTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_WTT) 198#define PEXIWAR_WTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_WTT) 199#define PEXIWAR_WTT_MEM_ALLOL2 __SHIFTIN(6, PEXIWAR_WTT) 200#define PEXIWAR_WTT_MEM_ALCKL2 __SHIFTIN(7, PEXIWAR_WTT) 201#define PEXIWAR_IWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 202#define PEXIWAR_IWS_GET(n) __SHIFTOUT((n), PEXIWAR_IWS) 203 204/* Outbound Window 0 (Default) */ 205#define PEXOTAR0 0xC00 /* PCI Express outbound translation address register 0 (default) */ 206#define PEXOTEAR0 0xC04 /* PCI Express outbound translation extended address register 0 (default) */ 207#define PEXOWAR0 0xC10 /* PCI Express outbound window attributes register 0 (default) */ 208 209/* Outbound Window 1 */ 210#define PEXOTAR1 0xC20 /* PCI Express outbound translation address register 1 */ 211#define PEXOTEAR1 0xC24 /* PCI Express outbound translation extended address register 1 */ 212#define PEXOWBAR1 0xC28 /* PCI Express outbound window base address register 1 */ 213#define PEXOWAR1 0xC30 /* PCI Express outbound window attributes register 1 */ 214 215/* Outbound Window 2 */ 216#define PEXOTAR2 0xC40 /* PCI Express outbound translation address register 2 */ 217#define PEXOTEAR2 0xC44 /* PCI Express outbound translation extended address register 2 */ 218#define PEXOWBAR2 0xC48 /* PCI Express outbound window base address register 2 */ 219#define PEXOWAR2 0xC50 /* PCI Express outbound window attributes register 2 */ 220 221/* Outbound Window 3 */ 222#define PEXOTAR3 0xC60 /* PCI Express outbound translation address register 3 */ 223#define PEXOTEAR3 0xC64 /* PCI Express outbound translation extended address register 3 */ 224#define PEXOWBAR3 0xC68 /* PCI Express outbound window base address register 3 */ 225#define PEXOWAR3 0xC70 /* PCI Express outbound window attributes register 3 */ 226 227/* Outbound Window 4 */ 228#define PEXOTAR4 0xC80 /* PCI Express outbound translation address register 4 */ 229#define PEXOTEAR4 0xC84 /* PCI Express outbound translation extended address register 4 */ 230#define PEXOWBAR4 0xC88 /* PCI Express outbound window base address register 4 */ 231#define PEXOWAR4 0xC90 /* PCI Express outbound window attributes register 4 */ 232 233/* Inbound Window 3 */ 234#define PEXITAR3 0xDA0 /* PCI Express inbound translation address register 3 */ 235#define PEXIWBAR3 0xDA8 /* PCI Express inbound window base address register 3 */ 236#define PEXIWBEAR3 0xDAC /* PCI Express inbound window base extended address register 3 */ 237#define PEXIWAR3 0xDB0 /* PCI Express inbound window attributes register 3 */ 238 239/* Inbound Window 2 */ 240#define PEXITAR2 0xDC0 /* PCI Express inbound translation address register 2 */ 241#define PEXIWBAR2 0xDC8 /* PCI Express inbound window base address register 2 */ 242#define PEXIWBEAR2 0xDCC /* PCI Express inbound window base extended address register 2 */ 243#define PEXIWAR2 0xDD0 /* PCI Express inbound window attributes register 2 */ 244 245/* Inbound Window 1 */ 246#define PEXITAR1 0xDE0 /* PCI Express inbound translation address register 1 */ 247#define PEXIWBAR1 0xDE8 /* PCI Express inbound window base address register 1 */ 248#define PEXIWAR1 0xDF0 /* PCI Express inbound window attributes register 1 */ 249 250/* PCI Express Error Management Registers */ 251#define PEX_ERR_DR 0xE00 /* PCI Express error detect register */ 252#define PEXERRDR_ICCA __PPCBIT(14) 253#define PEX_ERR_EN 0xE08 /* PCI Express error interrupt enable register */ 254#define PEX_ERR_DISR 0xE10 /* PCI Express error disable register */ 255#define PEX_ERR_CAP_STAT 0xE20 /* PCI Express error capture status register */ 256#define PEX_ERR_CAP_R0 0xE28 /* PCI Express error capture register 0 */ 257#define PEX_ERR_CAP_R1 0xE2C /* PCI Express error capture register 1 */ 258#define PEX_ERR_CAP_R2 0xE30 /* PCI Express error capture register 2 */ 259#define PEX_ERR_CAP_R3 0xE34 /* PCI Express error capture register 3 */ 260 261/* PCI Express Private Configuration Space */ 262 263#define PEX_LTSSM 0x404 264#define LTSSM_L0 16 265 266#define PCI_PBFR 0x44 /* Bus Function Register */ 267#define PBFR_PAH __BIT(0) 268 269#endif /* PCI_PRIVATE */ 270 271#define OPENPIC_BASE 0x40000 272#define OPENPIC_SIZE 0x40000 273 274#define L2CACHE_BASE 0x20000 275#define L2CACHE_SIZE 0x01000 276 277#ifdef L2CACHE_PRIVATE 278#define L2CTL 0x000 279#define L2CTL_L2E __PPCBIT(0) 280#define L2CTL_L2I __PPCBIT(1) 281#define L2CTL_L2SIZ __PPCBITS(2,3) 282#define L2CTL_L2SIZ_GET(x) (1 << (17 + __SHIFTOUT((x), L2CTL_L2SIZ))) 283#define L2CTL_L2DO __PPCBIT(9) 284#define L2CTL_L2IO __PPCBIT(10) 285#define L2CTL_L2INTDIS __PPCBIT(12) 286#define L2CTL_L2SRAM __PPCBITS(13,15) 287#define L2CTL_L2LO __PPCBIT(18) 288#define L2CTL_L2SLC __PPCBIT(19) 289#define L2CTL_L2LFR __PPCBIT(21) 290#define L2CTL_L2LFRID __PPCBITS(22,23) 291#define L2CTL_L2STASHDIS __PPCBIT(28) 292#define L2CTL_L2STASH __PPCBITS(30,31) 293 294#endif /* L2CACHE_PRIVATE */ 295 296#define I2C1_BASE 0x3000 297#define I2C2_BASE 0x3100 298#define I2C_SIZE 0x0100 299 300#ifdef I2C_PRIVATE 301#define I2CADR 0x000 /* i2c address register */ 302#define I2CFDR 0x004 /* i2c frequency divider register */ 303#define I2CCR 0x008 /* i2c control register */ 304#define I2CSR 0x00c /* i2c status register */ 305#define I2CDR 0x010 /* i2c data register */ 306#define I2CDFSSR 0x014 /* i2c address register */ 307#endif /* I2C_PRIVATE */ 308 309#define DUART1_BASE 0x4500 310#define DUART2_BASE 0x4600 311#define DUART_SIZE 0x0100 312 313#define SPI_BASE 0x7000 /* MPC8536 */ 314#define SPI_SIZE 0x1000 315 316#define SATA1_BASE 0x18000 /* MPC8536 */ 317#define SATA2_BASE 0x19000 /* MPC8536 */ 318#define SATA_SIZE 0x01000 319 320#define USB1_BASE 0x22100 /* MPC8536 */ 321#define USB2_BASE 0x23100 /* MPC8536 */ 322#define USB3_BASE 0x2b100 /* MPC8536 */ 323#define USB_SNOOP1 0x0300 /* DMA Snooping Register 1 */ 324#define USB_SNOOP2 0x0304 /* DMA Snooping Register 2 */ 325#define USB_CONTROL 0x0400 /* USB General Purpose Register */ 326#define USB_EN __PPCBIT(29) 327#define USB_ULPI_INT_EN __PPCBIT(31) 328#define USB_SIZE 0x00f00 329 330#define SNOOP_2GB 0x1e 331 332#define ETSEC1_BASE 0x24000 333#define ETSEC2_BASE 0x25000 334#define ETSEC3_BASE 0x26000 335#define ETSEC4_BASE 0x27000 336#define ETSEC_SIZE 0x01000 337 338#define ESDHC_BASE 0x2e000 339#define ESDHC_SIZE 0x01000 340 341#define GLOBAL_BASE 0xe0000 342#define GLOBAL_SIZE 0x01000 343 344#ifdef GLOBAL_PRIVATE 345 346/* Power-On Reset Configuration Values */ 347#define PORPLLSR 0x000 /* POR PLL ratio status register */ 348#define E500_RATIO2 __PPCBITS(2,7) 349#define E500_RATIO2_GET(n) __SHIFTOUT(n, E500_RATIO2) 350#define E500_RATIO __PPCBITS(10,15) 351#define E500_RATIO_GET(n) __SHIFTOUT(n, E500_RATIO) 352#define PCI1_CLK_SEL __PPCBIT(16) 353#define PCI2_CLK_SEL __PPCBIT(17) 354#define PLAT_RATIO __PPCBITS(26,30) 355#define PLAT_RATIO_GET(n) __SHIFTOUT(n, PLAT_RATIO) 356#define PORBMSR 0x004 /* POR boot mode status register */ 357#define PORBMSR_BCFG __PPCBITS(0,1) 358#define PORBMSR_HA __PPCBITS(13,15) 359#define PORBMSR_HA_GET(n) __SHIFTOUT(m, PORBMSR_HA) 360#define PORBMSR_HA_PEXSRIO_AGENT 0 /* PCI Express & SRIO agent mode */ 361#define PORBMSR_HA_SRIO_AGENT 1 /* SRIO agent mode */ 362#define PORBMSR_HA_PEX_AGENT 2 /* PCI Express agent mode */ 363#define PORBMSR_HA_PEXPCI_AGENT2 3 /* PCI[-X] & PCI Express agent mode */ 364#define PORBMSR_HA_PCISRIO_AGENT2 4 /* PCI[-X] & SRIO mode */ 365#define PORBMSR_HA_SRIO_AGENT2 5 /* SRIO agent mode */ 366#define PORBMSR_HA_PCI_AGENT2 6 /* PCI[-X] agent mode */ 367#define PORBMSR_HA_HOST 7 /* Host mode */ 368#define PORIMPSCR 0x008 /* POR I/O impedance status and control register */ 369#define PORDEVSR 0x00C /* POR I/O device status register */ 370#define PORDEVSR_ECW1 __PPCBIT(0) 371#define PORDEVSR_ECW2 __PPCBIT(1) 372#define PORDEVSR_SGMII1_DIS1 __PPCBIT(2) 373#define PORDEVSR_SGMII1_DIS2 __PPCBIT(3) 374#define PORDEVSR_SGMII1_DIS3 __PPCBIT(4) 375#define PORDEVSR_SGMII1_DIS4 __PPCBIT(5) 376#define PORDEVSR_ECP1 __PPCBITS(6,7) 377#define PORDEVSR_PCI1 __PPCBIT(8) 378#define PCI1_PCIX 0 379#define PCI1_PCI1 1 380#define PORDEVSR_IOSEL __PPCBITS(9,12) 381#define IOSEL_MPC8536_OFF 0x01 382#define IOSEL_MPC8536_PCIE1_X4 0x02 383#define IOSEL_MPC8536_PCIE1_X8 0x03 384#define IOSEL_MPC8536_PCIE12_X4 0x05 385#define IOSEL_MPC8536_PCIE1_X4_PCI23_X2 0x07 386#define IOSEL_MPC8544_OFF 0x00 387#define IOSEL_MPC8544_SGMII_ON 0x01 388#define IOSEL_MPC8544_PCIE1_ON 0x02 389#define IOSEL_MPC8544_PCIE1_SGMII_ON 0x03 390#define IOSEL_MPC8544_PCIE12_ON 0x04 391#define IOSEL_MPC8544_PCIE12_SGMII_ON 0x05 392#define IOSEL_MPC8544_PCIE123_ON 0x06 393#define IOSEL_MPC8544_PCIE123_SGMII_ON 0x07 394#define IOSEL_MPC8548_SRIO2500_PCIE1_X4 3 395#define IOSEL_MPC8548_SRIO1250_PCIE1_X4 4 396#define IOSEL_MPC8548_SRIO3125 5 397#define IOSEL_MPC8548_SRIO1250 6 398#define IOSEL_MPC8548_PCIE1_X8 7 399#define IOSEL_MPC8572_PCIE1_X4 2 400#define IOSEL_MPC8572_PCIE12_X4 3 401#define IOSEL_MPC8572_SRIO2500 6 402#define IOSEL_MPC8572_PCIE1_X4_23_X2 7 403#define IOSEL_MPC8572_SRIO2500_PCIE1_X4 11 404#define IOSEL_MPC8572_SRIO1250_PCIE1_X4 12 405#define IOSEL_MPC8572_SRIO3125 13 406#define IOSEL_MPC8572_SRIO1250 14 407#define IOSEL_MPC8572_PCIE1_X8 15 408#define IOSEL_P20x0_PCIE1_X1 0 409#define IOSEL_P20x0_PCIE12_X1_3_X2 2 410#define IOSEL_P20x0_PCIE13_X2 4 411#define IOSEL_P20x0_PCIE1_X4 6 412#define IOSEL_P20x0_PCIE1_X1_SRIO2500_1X 13 413#define IOSEL_P20x0_PCIE12_X1_SGMII23 14 414#define IOSEL_P20x0_PCIE1_X2_SGMII23 15 415#define PORDEVSR_PCI2_ARB __PPCBIT(13) 416#define PORDEVSR_PCI1_ARB __PPCBIT(14) 417#define PORDEVSR_PCI32 __PPCBIT(15) 418#define PCI32_FALSE 0 419#define PCI32_TRUE 1 420#define PORDEVSR_PCI1_SPD __PPCBIT(16) 421#define PORDEVSR_PCI2_SPD __PPCBIT(17) 422#define PORDEVSR_SYS_SPD __PPCBIT(17) /* MPC8536 */ 423#define PORDEVSR_CORE_SPD __PPCBIT(18) /* MPC8536 */ 424#define PORDEVSR_ECP2 __PPCBITS(18,19) 425#define PORDEVSR_ECP3 __PPCBITS(20,21) 426#define PORDEVSR_ECP4 __PPCBITS(22,23) 427#define PORDEVSR_FEC_DIS __PPCBIT(24) 428#define PORDEVSR_RTPE __PPCBIT(25) 429#define PORDEVSR_RIO_CTLS __PPCBIT(28) 430#define PORDEVSR_DEV_ID __PPCBITs(29,31) 431#define PORDBGMSR 0x010 /* POR debug mode status register */ 432#define PORDEVSR2 0x014 /* POR I/O device status register 2 */ 433#define GPPORCR 0x020 /* General-purpose POR configuration register */ 434 435/* Signal Multiplexing and GPIO Controls */ 436#define GPIOCR 0x030 /* GPIO control register */ 437#define GPIOCR_TX2 __PPCBIT(6) /* Enable TSEC2_TX[7:0] as GP output */ 438#define GPIOCR_RX2 __PPCBIT(7) /* Enable TSEC2_RX[7:0] as GP input */ 439#define GPIOCR_PCIOUT __PPCBIT(14) /* Enable PCI2_AD[15:8] as GP output */ 440#define GPIOCR_PCIIN __PPCBIT(15) /* Enable PCI2_AD[7:0] as GP input */ 441#define GPIOCR_GPOUT __PPCBIT(22) /* Enable GPOUT[24:31] as GP output */ 442#define GPOUTDR 0x040 /* General-purpose output data register */ 443#define GPOUTDR_TX2 0x040 /* General-purpose output data register */ 444#define GPOUTDR_PCI 0x041 /* General-purpose output data register */ 445#define GPOUTDR_GPOUT 0x043 /* General-purpose output data register */ 446#define GPINDR 0x050 /* General-purpose input data register */ 447#define GPINDR_RX2 0x059 448#define GPINDR_PCI 0x051 449 450#define PMUXCR 0x060 /* Alternate function signal multiplex control */ 451#define PMUXCR_SD_DATA __PPCBIT(0) 452#define PMUXCR_SDHC_CD __PPCBIT(1) 453#define PMUXCR_SDHC_WP __PPCBIT(2) 454#define PMUXCR_PCI_REQGNT3 __PPCBIT(3) 455#define PMUXCR_TSEC1_TS __PPCBIT(3) 456#define PMUXCR_PCI_REQGNT4 __PPCBIT(4) 457#define PMUXCR_TSEC2_TS __PPCBIT(4) 458#define PMUXCR_USB1 __PPCBIT(5) 459#define PMUXCR_TSEC3_TS __PPCBIT(5) 460#define PMUXCR_USB2 __PPCBIT(6) 461#define PMUXCR_USB __PPCBIT(6) 462#define PMUXCR_DMA0 __PPCBIT(14) 463#define PMUXCR_DMA2 __PPCBIT(15) 464#define PMUXCR_DMA1 __PPCBIT(30) 465#define PMUXCR_DMA3 __PPCBIT(31) 466 467/* Device Disables */ 468#define DEVDISR 0x070 /* Device disable control */ 469#define DEVDISR_PCI1 __PPCBIT(0) 470#define DEVDISR_PCI2 __PPCBIT(1) 471#define DEVDISR_PCIE __PPCBIT(2) 472#define DEVDISR_LBC __PPCBIT(4) 473#define DEVDISR_PCIE2 __PPCBIT(5) 474#define DEVDISR_PCIE3 __PPCBIT(6) 475#define DEVDISR_SEC __PPCBIT(7) 476#define DEVDISR_PME __PPCBIT(8) 477#define DEVDISR_USB1 __PPCBIT(8) /* MPC8536 */ 478#define DEVDISR_TLU1 __PPCBIT(9) 479#define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */ 480#define DEVDISR_TLU2 __PPCBIT(10) 481#define DEVDISR_ESDHC_10 __PPCBIT(10) 482#define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */ 483#define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */ 484#define DEVDISR_SRIO __PPCBIT(12) 485#define DEVDISR_ESDHC_12 __PPCBIT(12) /* MPC8536 */ 486#define DEVDISR_RMSG __PPCBIT(13) 487#define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */ 488#define DEVDISR_DDR2_14 __PPCBIT(14) 489#define DEVDISR_DDR_15 __PPCBIT(15) 490#define DEVDISR_SPI_15 __PPCBIT(15) /* MPC8536 */ 491#define DEVDISR_E500 __PPCBIT(16) 492#define DEVDISR_DDR_16 __PPCBIT(16) /* MPC8536 */ 493#define DEVDISR_TB __PPCBIT(17) 494#define DEVDISR_E500_1 __PPCBIT(18) 495#define DEVDISR_TB_1 __PPCBIT(19) 496#define DEVDISR_SATA2 __PPCBIT(20) /* MPC8536 */ 497#define DEVDISR_DMA __PPCBIT(21) 498#define DEVDISR_DMA2 __PPCBIT(22) 499#define DEVDISR_SRDS2 __PPCBIT(22) /* MPC8536 */ 500#define DEVDISR_TSEC1 __PPCBIT(24) 501#define DEVDISR_TSEC2 __PPCBIT(25) 502#define DEVDISR_TSEC3 __PPCBIT(26) 503#define DEVDISR_TSEC4 __PPCBIT(27) 504#define DEVDISR_FEC __PPCBIT(28) 505#define DEVDISR_SPI_28 __PPCBIT(28) /* P2020 */ 506#define DEVDISR_I2C __PPCBIT(29) 507#define DEVDISR_DUART __PPCBIT(30) 508#define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */ 509 510/* Power Management Registers */ 511#define POWMGTCSR 0x080 /* Power management status and control register */ 512 513/* Interrupt and Reset Status and Control */ 514#define MCPSUMR 0x090 /* Machine check summary register */ 515#define RSTRSCR 0x094 /* Reset request status and control register */ 516 517/* Version Registers */ 518#define PVR 0x0A0 /* Processor version register */ 519#define SVR 0x0A4 /* System version register */ 520 521/* Status Registers */ 522#define RSTCR 0x0B0 /* Reset control register */ 523#define HRESET_REQ __PPCBIT(30) /* hardware reset request */ 524#define LBCVSELCR 0x0C0 /* LBC voltage select control register */ 525#define DDRCSR 0xB20 /* DDR calibration status register */ 526#define DDRCDR 0xB24 /* DDR control driver register */ 527#define DDRCLKDR 0xB28 /* DDR clock disable register */ 528 529/* Debug Control */ 530#define CLKOCR 0xE00 /* Clock out control register */ 531#define SRDSCR0 0xF04 /* LSerDes control register 0 */ 532#define SRDSCR1 0xF08 /* LSerDes control register 1 */ 533#define TSEC12IOOVCR 0xF28 /* eTSEC 1 & 2 overdrive control register */ 534#define TSEC34IOOVCR 0xF2C /* eTSEC 3 & 4 overdrive control register */ 535#endif /* GLOBAL_PRIVATE */ 536 537#define LBC_BASE 0x5000 538#define LBC_SIZE 0x0fff 539 540#ifdef LBC_PRIVATE 541 542#define BR_BA __PPCBITS(0,16) 543#define BR_XBA __PPCBITS(17,18) 544#define BR_PS __PPCBITS(19,20) 545#define BR_PS_8BIT __SHIFTIN(1,BR_PS) 546#define BR_PS_16BIT __SHIFTIN(2,BR_PS) 547#define BR_PS_32BIT __SHIFTIN(3,BR_PS) 548#define BR_DECC __PPCBITS(21,22) 549#define BR_DECC_NONE __SHIFTIN(0,BR_DECC) 550#define BR_DECC_PARITY __SHIFTIN(1,BR_DECC) 551#define BR_DECC_RMWPAR __SHIFTIN(2,BR_DECC) 552#define BR_WP __PPCBIT(23) 553#define BR_MSEL __PPCBITS(24,26) 554#define BR_MSEL_GPCM __SHIFTIN(0,BR_MSEL) 555#define BR_MSEL_FCM __SHIFTIN(1,BR_MSEL) 556#define BR_MSEL_SDRAM __SHIFTIN(3,BR_MSEL) 557#define BR_MSEL_UPMA __SHIFTIN(4,BR_MSEL) 558#define BR_MSEL_UPMB __SHIFTIN(5,BR_MSEL) 559#define BR_MSEL_UPMC __SHIFTIN(6,BR_MSEL) 560#define BR_ATOM __PPCBITS(28,29) 561#define BR_ATOM_NONE __SHIFTIN(0,BR_ATOM) 562#define BR_ATOM_RAWA __SHIFTIN(1,BR_ATOM) 563#define BR_ATOM_WARA __SHIFTIN(2,BR_ATOM) 564#define BR_V __PPCBIT(31) 565 566#define OR_AM __PPCBITS(0,16) 567#define OR_XAM __PPCBITS(17,18) 568#define OR_BCTLD __PPCBIT(19) 569#define OR_CSNT __PPCBIT(20) 570#define OR_ACS __PPCBITS(21,22) 571#define OR_XACS __PPCBIT(23) 572#define OR_SCY __PPCBITS(24,27) 573#define OR_SETA __PPCBIT(28) 574#define OR_TRLX __PPCBIT(29) 575#define OR_EHTR __PPCBIT(30) 576#define OR_EAD __PPCBIT(31) 577 578#define BRn(n) (BR0 + 8*(n)) 579#define ORn(n) (OR0 + 8*(n)) 580#define BR0 0x000 /* Base register 0 */ 581#define OR0 0x004 /* Options register 0 */ 582#define BR1 0x008 /* Base register 1 */ 583#define OR1 0x00C /* Options register 1 */ 584#define BR2 0x010 /* Base register 2 */ 585#define OR2 0x014 /* Options register 2 */ 586#define BR3 0x018 /* Base register 3 */ 587#define OR3 0x01C /* Options register 3 */ 588#define BR4 0x020 /* Base register 4 */ 589#define OR4 0x024 /* Options register 4 */ 590#define BR5 0x028 /* Base register 5 */ 591#define OR5 0x02C /* Options register 5 */ 592#define BR6 0x030 /* Base register 6 */ 593#define OR6 0x034 /* Options register 6 */ 594#define BR7 0x038 /* Base register 7 */ 595#define OR7 0x03C /* Options register 7 */ 596#define MAR 0x068 /* UPM address register */ 597#define MAMR 0x070 /* UPMA mode register */ 598#define MBMR 0x074 /* UPMB mode register */ 599#define MCMR 0x078 /* UPMC mode register */ 600#define MRTPR 0x084 /* Memory refresh timer prescaler register */ 601#define MDR 0x088 /* UPM/FCM data register */ 602#define MDR_AS3 __PPCBITS(0,7) 603#define MDR_AS2 __PPCBITS(8,15) 604#define MDR_AS1 __PPCBITS(16,23) 605#define MDR_AS0 __PPCBITS(24,31) 606#define LSOR 0x090 /* Special Operation Initiation register */ 607#define LSDMR 0x094 /* SDRAM mode register */ 608#define LURT 0x0A0 /* UPM refresh timer */ 609#define LSRT 0x0A4 /* SDRAM refresh timer */ 610#define LTESR 0x0B0 /* Transfer error status register */ 611#define LTESR_BM __PPCBIT(0) 612#define LTESR_FCT __PPCBIT(1) 613#define LTESR_PAR __PPCBIT(2) 614#define LTESR_WP __PPCBIT(5) 615#define LTESR_ATMW __PPCBIT(8) 616#define LTESR_ATMR __PPCBIT(9) 617#define LTESR_CS __PPCBIT(12) 618#define LTESR_UCC __PPCBIT(30) 619#define LTESR_CC __PPCBIT(31) 620#define LTEDR 0x0B4 /* Transfer error disable register */ 621#define LTEDR_BMD __PPCBIT(0) 622#define LTEDR_FCTD __PPCBIT(1) 623#define LTEDR_PARD __PPCBIT(2) 624#define LTEDR_WPD __PPCBIT(5) 625#define LTEDR_WARA __PPCBIT(8) 626#define LTEDR_RAWA __PPCBIT(9) 627#define LTEDR_CSD __PPCBIT(12) 628#define LTEDR_UCCD __PPCBIT(30) 629#define LTEDR_CCD __PPCBIT(31) 630#define LTEIR 0x0B8 /* Transfer error interrupt register */ 631#define LTEIR_BMI __PPCBIT(0) 632#define LTEIR_FCTI __PPCBIT(1) 633#define LTEIR_PARI __PPCBIT(2) 634#define LTEIR_WPI __PPCBIT(5) 635#define LTEIR_WARA __PPCBIT(8) 636#define LTEIR_RAWA __PPCBIT(9) 637#define LTEIR_CSI __PPCBIT(12) 638#define LTEIR_UCCI __PPCBIT(30) 639#define LTEIR_CCI __PPCBIT(31) 640#define LTEATR 0x0BC /* Transfer error attributes register */ 641#define LTEATR_RWB __PPCBIT(3) 642#define LTEATR_SRCID __PPCBITS(11,15) 643#define LTEATR_PB __PPCBITS(16,19) 644#define LTEATR_BNK __PPCBITS(20,27) 645#define LTEATR_V __PPCBIT(31) 646#define LTEAR 0x0C0 /* Transfer error address register */ 647#define LTECCR 0x0C4 /* Transfer error ECC register */ 648#define LTECCR_SBCE __PPCBITS(12,15) 649#define LTECCR_MBUE __PPCBITS(28,31) 650#define LBCR 0x0D0 /* Configuration register */ 651#define LCRR 0x0D4 /* Clock ratio register */ 652 653#define FMR 0x0E0 /* Flash Mode Register */ 654#define FMR_CWTO __PPCBITS(16,19) 655#define FMR_BOOT __PPCBIT(20) 656#define FMR_ECCM __PPCBIT(23) 657#define FMR_AL __PPCBITS(26,27) 658#define FMR_OP __PPCBITS(30,31) 659#define FIR 0x0E4 /* Flash Instruction Register */ 660#define FIR_OP0 __PPCBITS(0,3) 661#define FIR_OP1 __PPCBITS(4,7) 662#define FIR_OP2 __PPCBITS(8,11) 663#define FIR_OP3 __PPCBITS(12,15) 664#define FIR_OP4 __PPCBITS(16,19) 665#define FIR_OP5 __PPCBITS(20,23) 666#define FIR_OP6 __PPCBITS(24,27) 667#define FIR_OP7 __PPCBITS(28,31) 668#define FIR_OP_NOP 0 669#define FIR_OP_CA 1 /* Issue current column address */ 670#define FIR_OP_PA 2 /* Issue current block+page address */ 671#define FIR_OP_UA 3 /* Issue user-defined address byte */ 672#define FIR_OP_CM0 4 /* Issue command from FCR[CMD0] */ 673#define FIR_OP_CM1 5 /* Issue command from FCR[CMD1] */ 674#define FIR_OP_CM2 6 /* Issue command from FCR[CMD2] */ 675#define FIR_OP_CM3 7 /* Issue command from FCR[CMD3] */ 676#define FIR_OP_WB 8 /* Write FBCR bytes of data */ 677#define FIR_OP_WS 9 /* Write one byte of data from MDR */ 678#define FIR_OP_RB 10 /* Read FBCR bytes of data */ 679#define FIR_OP_RS 11 /* Read one byte of data into MDR */ 680#define FIR_OP_CW0 12 /* Wait for LFRB then FCR[CMD0] */ 681#define FIR_OP_CW1 13 /* Wait for LFRB then FCR[CMD1] */ 682#define FIR_OP_RBW 14 /* Wait for LFRB then read FBCR bytes */ 683#define FIR_OP_RSW 15 /* Wait for LFRB then byte into MDR */ 684#define FCR 0xE8 /* Flash Command Register */ 685#define FCR_CMD0 __PPCBITS(0,7) 686#define FCR_CMD1 __PPCBITS(8,15) 687#define FCR_CMD2 __PPCBITS(16,23) 688#define FCR_CMD3 __PPCBITS(24,31) 689#define FBAR 0xEC /* Flash Block Address Register */ 690#define FBAR_BLK __PPCBITS(8,31) 691#define FPAR 0xF0 /* Flash Page Address Register */ 692#define FPAR_S_PI __PPCBITS(17,21) /* Page Index */ 693#define FPAR_S_MS __PPCBIT(22) /* Main(0)/Spare(1) */ 694#define FPAR_S_CI __PPCBITS(23,31) /* Column Index */ 695#define FPAR_L_PI __PPCBITS(14,19) /* Page Index */ 696#define FPAR_L_MS __PPCBIT(20) /* Main(0)/Spare(1) */ 697#define FPAR_L_CI __PPCBITS(21,31) /* Column Index */ 698#define FBCR 0xF4 /* Flash Byte Count Register */ 699#define FBCR_BC __PPCBITS(20,31) 700#define FECC0 0x100 701#define FECC_V __PPCBIT(0) 702#define FECC_ECC __PPCBIT(8,31) 703#define FECC1 0x104 704#define FECC2 0x108 705#define FECC3 0x10C 706 707#define MXMR_RFEN __PPCBIT(1) /* Refresh enable */ 708#define MXMR_OP __PPCBITS(2,3) /* Command opcode */ 709#define MXMR_OP_NORMAL __SHIFTIN(0, MXMR_OP) /* Normal Operation */ 710#define MXMR_OP_WRITE __SHIFTIN(1, MXMR_OP) /* Write to UPM memory */ 711#define MXMR_OP_READ __SHIFTIN(2, MXMR_OP) /* Read from UPM memory */ 712#define MXMR_OP_RUN __SHIFTIN(3, MXMR_OP) /* Run Pattern */ 713#define MXMR_UWPL __PPCBIT(3) /* LUPWAIT is active low */ 714#define MXMR_AM __PPCBITS(5,7) /* Address multiplex size */ 715#define MXMR_DS __PPCBITS(8,9) /* Disable timer period */ 716#define MXMR_DS_1CYCLE __SHIFTIN(0,MXMR_DS) 717#define MXMR_DS_2CYCLE __SHIFTIN(1,MXMR_DS) 718#define MXMR_DS_3CYCLE __SHIFTIN(2,MXMR_DS) 719#define MXMR_DS_4CYCLE __SHIFTIN(3,MXMR_DS) 720#define MXMR_G0CL __PPCBITS(10,12) /* General line 0 control */ 721#define MXMR_G0CL_A12 __SHIFTIN(0,MXMR_G0CL) 722#define MXMR_G0CL_A11 __SHIFTIN(1,MXMR_G0CL) 723#define MXMR_G0CL_A10 __SHIFTIN(2,MXMR_G0CL) 724#define MXMR_G0CL_A9 __SHIFTIN(3,MXMR_G0CL) 725#define MXMR_G0CL_A8 __SHIFTIN(4,MXMR_G0CL) 726#define MXMR_G0CL_A7 __SHIFTIN(5,MXMR_G0CL) 727#define MXMR_G0CL_A6 __SHIFTIN(6,MXMR_G0CL) 728#define MXMR_G0CL_A5 __SHIFTIN(7,MXMR_G0CL) 729#define MXMR_GPL4 __PPCBIT(13) /* LGPL4 output line disable */ 730#define MXMR_RLF __PPCBITS(14,17) /* Read loop field */ 731#define MXMR_WLF __PPCBITS(18,21) /* Write loop field */ 732#define MXMR_TLF __PPCBITS(22,25) /* Refresh loop field */ 733#define MXMR_MAS __PPCBITS(26,31) /* Machine Address */ 734 735#define MRTPR_PTP __PPCBITS(0,7) /* Refresh timers prescaler */ 736 737#endif /* LBC_PRIVATE */ 738