1/* $NetBSD: sbic.c,v 1.31 2007/10/17 19:55:47 garbled Exp $ */ 2 3/* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37/* 38 * Changes Copyright (c) 1996 Steve Woodford 39 * Original Copyright (c) 1994 Christian E. Hopps 40 * 41 * This code is derived from software contributed to Berkeley by 42 * Van Jacobson of Lawrence Berkeley Laboratory. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by the University of 55 * California, Berkeley and its contributors. 56 * 4. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 73 */ 74 75/* 76 * Steve Woodford (SCW), Apr, 1996 77 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 78 * 79 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 80 * 81 * The original driver used features which required at least a WD33C93A 82 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 83 * 84 * This version of the driver is pretty well generic, so should work with 85 * any flavour of WD33C93 chip. 86 */ 87 88#include <sys/cdefs.h> 89__KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.31 2007/10/17 19:55:47 garbled Exp $"); 90 91#include "opt_ddb.h" 92 93#include <sys/param.h> 94#include <sys/systm.h> 95#include <sys/device.h> 96#include <sys/kernel.h> /* For hz */ 97#include <sys/disklabel.h> 98#include <sys/buf.h> 99 100#include <dev/scsipi/scsi_all.h> 101#include <dev/scsipi/scsipi_all.h> 102#include <dev/scsipi/scsiconf.h> 103 104#include <uvm/uvm_extern.h> 105 106#include <mvme68k/mvme68k/isr.h> 107#include <mvme68k/dev/dmavar.h> 108#include <mvme68k/dev/sbicreg.h> 109#include <mvme68k/dev/sbicvar.h> 110 111 112/* 113 * Since I can't find this in any other header files 114 */ 115#define SCSI_PHASE(reg) (reg&0x07) 116 117/* 118 * SCSI delays 119 * In u-seconds, primarily for state changes on the SPC. 120 */ 121#define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 122#define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 123#define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 124 125/* 126 * Convenience macro for waiting for a particular sbic event 127 */ 128#define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 129 130int sbicicmd (struct sbic_softc *, void *, int, void *, int); 131int sbicgo (struct sbic_softc *, struct scsipi_xfer *); 132int sbicdmaok (struct sbic_softc *, struct scsipi_xfer *); 133int sbicwait (sbic_regmap_p, u_char, int , int); 134int sbiccheckdmap (void *, u_long, u_long); 135u_char sbicselectbus (struct sbic_softc *); 136int sbicxfout (sbic_regmap_p, int, void *); 137int sbicxfin (sbic_regmap_p, int, void *); 138int sbicfromscsiperiod (struct sbic_softc *, int); 139int sbictoscsiperiod (struct sbic_softc *, int); 140int sbicpoll (struct sbic_softc *); 141int sbicnextstate (struct sbic_softc *, u_char, u_char); 142int sbicmsgin (struct sbic_softc *); 143int sbicabort (struct sbic_softc *, const char *); 144void sbicxfdone (struct sbic_softc *); 145void sbicerror (struct sbic_softc *, u_char); 146void sbicreset (struct sbic_softc *); 147void sbic_scsidone (struct sbic_acb *, int); 148void sbic_sched (struct sbic_softc *); 149void sbic_save_ptrs (struct sbic_softc *); 150void sbic_load_ptrs (struct sbic_softc *); 151 152/* 153 * Synch xfer parameters, and timing conversions 154 */ 155int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 156int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 157int sbic_cmd_wait = SBIC_CMD_WAIT; 158int sbic_data_wait = SBIC_DATA_WAIT; 159int sbic_init_wait = SBIC_INIT_WAIT; 160 161/* 162 * was broken before.. now if you want this you get it for all drives 163 * on sbic controllers. 164 */ 165u_char sbic_inhibit_sync[8]; 166int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 167int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 168int sbic_parallel_operations = 1; /* Allow command queues */ 169 170/* 171 * Some useful stuff for debugging purposes 172 */ 173#ifdef DEBUG 174int sbicdma_ops = 0; /* total DMA operations */ 175int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 176int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 177int sbicdma_saves = 0; 178 179#define QPRINTF(a) if (sbic_debug > 1) printf a 180 181int sbic_debug = 0; /* Debug all chip related things */ 182int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 183int reselect_debug = 0; /* Debug all reselection related things */ 184int data_pointer_debug = 0; /* Debug Data Pointer related things */ 185 186void sbictimeout(struct sbic_softc *dev); 187 188#else 189#define QPRINTF(a) /* */ 190#endif 191 192 193/* 194 * default minphys routine for sbic based controllers 195 */ 196void 197sbic_minphys(struct buf *bp) 198{ 199 /* 200 * No max transfer at this level. 201 */ 202 minphys(bp); 203} 204 205 206/* 207 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 208 */ 209void 210sbic_save_ptrs(struct sbic_softc *dev) 211{ 212 sbic_regmap_p regs; 213 struct sbic_acb *acb; 214 int count, asr, s; 215 216 /* 217 * Only need to save pointers if DMA was active... 218 */ 219 if (dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0) 220 return; 221 222 regs = dev->sc_sbicp; 223 224 s = splbio(); 225 226 /* 227 * Wait until WD chip is idle 228 */ 229 do { 230 GET_SBIC_asr(regs, asr); 231 if (asr & SBIC_ASR_DBR) { 232 printf("%s: asr %02x canceled!\n", __func__, asr); 233 splx(s); 234 return; 235 } 236 } while(asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 237 238 239 /* 240 * Save important state. 241 * must be done before dmastop 242 */ 243 acb = dev->sc_nexus; 244 acb->sc_dmacmd = dev->sc_dmacmd; 245 246 /* 247 * Fetch the residual count 248 */ 249 SBIC_TC_GET(regs, count); 250 251 /* 252 * Shut down DMA 253 */ 254 dev->sc_dmastop(dev); 255 256 /* 257 * No longer in DMA 258 */ 259 dev->sc_flags &= ~SBICF_INDMA; 260 261 /* 262 * Ensure the WD chip is back in polled I/O mode, with nothing to 263 * transfer. 264 */ 265 SBIC_TC_PUT(regs, 0); 266 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 267 268 /* 269 * Update current count... 270 */ 271 acb->sc_tcnt = count; 272 273 /* 274 * Work out how many bytes were actually transferred 275 */ 276 count = dev->sc_tcnt - count; 277 dev->sc_tcnt = acb->sc_tcnt; 278 279 /* 280 * Fixup partial xfers 281 */ 282 acb->sc_kv.dc_addr += count; 283 acb->sc_kv.dc_count -= count; 284 acb->sc_pa.dc_addr += count; 285 acb->sc_pa.dc_count -= count >> 1; 286 287#ifdef DEBUG 288 if (data_pointer_debug) 289 printf("save at (%p,%x):%x\n", 290 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 291 sbicdma_saves++; 292#endif 293 294 splx(s); 295} 296 297 298/* 299 * DOES NOT RESTART DMA!!! 300 */ 301void 302sbic_load_ptrs(struct sbic_softc *dev) 303{ 304 struct sbic_acb *acb = dev->sc_nexus; 305 int s; 306 307 if (acb->sc_kv.dc_count == 0) { 308 /* 309 * No data to xfer 310 */ 311 return; 312 } 313 314 s = splbio(); 315 316 /* 317 * Reset the Scatter-Gather chain 318 */ 319 dev->sc_last = dev->sc_cur = &acb->sc_pa; 320 321 /* 322 * Restore the Transfer Count and DMA specific data 323 */ 324 dev->sc_tcnt = acb->sc_tcnt; 325 dev->sc_dmacmd = acb->sc_dmacmd; 326 327#ifdef DEBUG 328 sbicdma_ops++; 329#endif 330 331 /* 332 * Need to fixup new segment? 333 */ 334 if (dev->sc_tcnt == 0) { 335 /* 336 * sc_tcnt == 0 implies end of segment 337 */ 338 char *vaddr, *paddr; 339 int count; 340 341 /* 342 * do kvm to pa mappings 343 */ 344 vaddr = acb->sc_kv.dc_addr; 345 paddr = acb->sc_pa.dc_addr = (char *)kvtop((void *)vaddr); 346 347 for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 348 count < acb->sc_kv.dc_count && 349 (char *)kvtop((void *)(vaddr + count + 4)) == 350 paddr + count + 4; 351 count += PAGE_SIZE) 352 ; /* Do nothing */ 353 354 /* 355 * If it's all contiguous... 356 */ 357 if (count > acb->sc_kv.dc_count) { 358 count = acb->sc_kv.dc_count; 359#ifdef DEBUG 360 sbicdma_hits++; 361#endif 362 } 363#ifdef DEBUG 364 else 365 sbicdma_misses++; 366#endif 367 368 acb->sc_tcnt = count; 369 acb->sc_pa.dc_count = count >> 1; 370 371#ifdef DEBUG 372 if (data_pointer_debug) 373 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 374 acb->sc_kv.dc_addr, 375 acb->sc_kv.dc_count, 376 acb->sc_pa.dc_addr, 377 acb->sc_tcnt); 378#endif 379 380 } 381 382 splx(s); 383} 384 385/* 386 * used by specific sbic controller 387 * 388 * it appears that the higher level code does nothing with LUN's 389 * so I will too. I could plug it in, however so could they 390 * in scsi_scsipi_cmd(). 391 */ 392void 393sbic_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 394 void *arg) 395{ 396 struct scsipi_xfer *xs; 397 struct scsipi_periph *periph; 398 struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; 399 struct sbic_acb *acb; 400 int flags, s; 401 402 switch (req) { 403 case ADAPTER_REQ_RUN_XFER: 404 xs = arg; 405 periph = xs->xs_periph; 406 flags = xs->xs_control; 407 408 if (flags & XS_CTL_DATA_UIO) 409 panic("sbic: scsi data uio requested"); 410 411 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 412 panic("sbic_scsicmd: busy"); 413 414 s = splbio(); 415 416 if ((acb = dev->free_list.tqh_first) != NULL) 417 TAILQ_REMOVE(&dev->free_list, acb, chain); 418 419 splx(s); 420 421 if (acb == NULL) { 422#ifdef DEBUG 423 printf("%s: unable to queue request for target %d\n", 424 __func__, periph->periph_target); 425#ifdef DDB 426 Debugger(); 427#endif 428#endif 429 xs->error = XS_RESOURCE_SHORTAGE; 430 scsipi_done(xs); 431 return; 432 } 433 434 if (flags & XS_CTL_DATA_IN) 435 acb->flags = ACB_ACTIVE | ACB_DATAIN; 436 else 437 acb->flags = ACB_ACTIVE; 438 439 acb->xs = xs; 440 acb->clen = xs->cmdlen; 441 acb->sc_kv.dc_addr = xs->data; 442 acb->sc_kv.dc_count = xs->datalen; 443 acb->pa_addr = xs->data ? 444 (char *)kvtop((void *)xs->data) : 0; 445 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 446 447 if (flags & XS_CTL_POLL) { 448 /* 449 * This has major side effects 450 * -- it locks up the machine 451 */ 452 int stat; 453 454 s = splbio(); 455 456 dev->sc_flags |= SBICF_ICMD; 457 458 do { 459 /* 460 * If we already had a nexus, while away 461 * the time until idle... 462 * This is likely only to happen if 463 * a reselection occurs between 464 * here and our earlier check for 465 * ICMD && sc_nexus(which would 466 * have resulted in a panic() had it been true). 467 */ 468 while (dev->sc_nexus) 469 sbicpoll(dev); 470 471 /* 472 * Fix up the new nexus 473 */ 474 dev->sc_nexus = acb; 475 dev->sc_xs = xs; 476 dev->target = periph->periph_target; 477 dev->lun = periph->periph_lun; 478 479 stat = sbicicmd(dev, &acb->cmd, acb->clen, 480 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 481 482 } while (dev->sc_nexus != acb); 483 484 sbic_scsidone(acb, stat); 485 486 splx(s); 487 488 return; 489 } 490 491 s = splbio(); 492 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 493 494 /* 495 * If nothing is active, try to start it now. 496 */ 497 if (dev->sc_nexus == NULL) 498 sbic_sched(dev); 499 500 splx(s); 501 502 return; 503 504 case ADAPTER_REQ_GROW_RESOURCES: 505 /* XXX Not supported. */ 506 return; 507 508 case ADAPTER_REQ_SET_XFER_MODE: 509 /* XXX Not supported. */ 510 return; 511 } 512} 513 514/* 515 * attempt to start the next available command 516 */ 517void 518sbic_sched(struct sbic_softc *dev) 519{ 520 struct scsipi_xfer *xs; 521 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 522 struct sbic_acb *acb; 523 int flags, stat; 524 525 /* 526 * XXXSCW 527 * I'll keep this test here, even though I can't see any obvious way 528 * in which sbic_sched() could be called with sc_nexus non NULL 529 */ 530 if (dev->sc_nexus) 531 return; /* a command is current active */ 532 533 /* 534 * Loop through the ready list looking for work to do... 535 */ 536 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 537 int i, j; 538 539 periph = acb->xs->xs_periph; 540 i = periph->periph_target; 541 j = 1 << periph->periph_lun; 542 543 /* 544 * We've found a potential command, but is the target/lun busy? 545 */ 546 if ((dev->sc_tinfo[i].lubusy & j) == 0) { 547 /* 548 * Nope, it's not busy, so we can use it. 549 */ 550 dev->sc_tinfo[i].lubusy |= j; 551 TAILQ_REMOVE(&dev->ready_list, acb, chain); 552 dev->sc_nexus = acb; 553 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 554 break; 555 } 556 } 557 558 if (acb == NULL) { 559 QPRINTF(("sbicsched: no work\n")); 560 return; /* did not find an available command */ 561 } 562 563#ifdef DEBUG 564 if (data_pointer_debug > 1) 565 printf("sbic_sched(%d,%d)\n", periph->periph_target, 566 periph->periph_lun); 567#endif 568 569 dev->sc_xs = xs = acb->xs; 570 flags = xs->xs_control; 571 572 if (flags & XS_CTL_RESET) 573 sbicreset(dev); 574 575 dev->sc_stat[0] = -1; 576 dev->target = periph->periph_target; 577 dev->lun = periph->periph_lun; 578 579 if (flags & XS_CTL_POLL || (!sbic_parallel_operations && 580 (sbicdmaok(dev, xs) == 0)) ) 581 stat = sbicicmd(dev, &acb->cmd, acb->clen, 582 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 583 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) 584 return; 585 else 586 stat = dev->sc_stat[0]; 587 588 sbic_scsidone(acb, stat); 589} 590 591void 592sbic_scsidone(struct sbic_acb *acb, int stat) 593{ 594 struct scsipi_xfer *xs = acb->xs; 595 struct scsipi_periph *periph = xs->xs_periph; 596 struct sbic_softc *dev = 597 (void *)periph->periph_channel->chan_adapter->adapt_dev; 598 int dosched = 0; 599 600#ifdef DIAGNOSTIC 601 if (acb == NULL || xs == NULL) { 602 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", 603 dev->target, dev->lun); 604#ifdef DDB 605 Debugger(); 606#endif 607 return; 608 } 609#endif 610 611 612#ifdef DEBUG 613 if (data_pointer_debug > 1) 614 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 615 periph->periph_target, periph->periph_lun, 616 dev->target, dev->lun, stat); 617 618 if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) 619 panic("target == hostid"); 620#endif 621 622 xs->status = stat; 623 xs->resid = 0; /* XXXX */ 624 if (xs->error == XS_NOERROR) { 625 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 626 xs->error = XS_BUSY; 627 } 628 629 630 /* 631 * Remove the ACB from whatever queue it's on. We have to do a bit of 632 * a hack to figure out which queue it's on. Note that it is *not* 633 * necessary to cdr down the ready queue, but we must cdr down the 634 * nexus queue and see if it's there, so we can mark the unit as no 635 * longer busy. This code is sickening, but it works. 636 */ 637 if (acb == dev->sc_nexus ) { 638 639 dev->sc_nexus = NULL; 640 dev->sc_xs = NULL; 641 642 dev->sc_tinfo[periph->periph_target].lubusy &= 643 ~(1 << periph->periph_lun); 644 645 if (dev->ready_list.tqh_first) 646 dosched = 1; /* start next command */ 647 648 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 649 650 TAILQ_REMOVE(&dev->ready_list, acb, chain); 651 652 } else { 653 654 struct sbic_acb *a; 655 656 for (a = dev->nexus_list.tqh_first; a != NULL; 657 a = a->chain.tqe_next) { 658 if (a == acb) { 659 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 660 dev->sc_tinfo[periph->periph_target].lubusy &= 661 ~(1 << periph->periph_lun); 662 break; 663 } 664 } 665 666 if (a != NULL) 667 ; 668 else if ( acb->chain.tqe_next ) { 669 TAILQ_REMOVE(&dev->ready_list, acb, chain); 670 } else { 671 printf("%s: can't find matching acb\n", 672 dev->sc_dev.dv_xname); 673#ifdef DDB 674 Debugger(); 675#endif 676 } 677 } 678 679 /* 680 * Put it on the free list. 681 */ 682 acb->flags = ACB_FREE; 683 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 684 685 dev->sc_tinfo[periph->periph_target].cmds++; 686 687 scsipi_done(xs); 688 689 if (dosched) 690 sbic_sched(dev); 691} 692 693int 694sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 695{ 696 697 if (sbic_no_dma || xs->datalen == 0 || 698 xs->datalen & 0x03 || (int)xs->data & 0x03) 699 return 0; 700 701 /* 702 * controller supports DMA to any addresses? 703 */ 704 if ((dev->sc_flags & SBICF_BADDMA) == 0) 705 return 1; 706 707 /* 708 * this address is ok for DMA? 709 */ 710 if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 711 return 1; 712 713 return 0; 714} 715 716int 717sbicwait(sbic_regmap_p regs, u_char until, int timeo, int line) 718{ 719 u_char val; 720 721 if (timeo == 0) 722 timeo = 1000000; /* some large value.. */ 723 724 GET_SBIC_asr(regs, val); 725 726 while ((val & until) == 0) { 727 728 if (timeo-- == 0) { 729 int csr; 730 GET_SBIC_csr(regs, csr); 731 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 732 line, val, csr); 733#if defined(DDB) && defined(DEBUG) 734 Debugger(); 735#endif 736 return val; /* Maybe I should abort */ 737 break; 738 } 739 740 DELAY(1); 741 GET_SBIC_asr(regs, val); 742 } 743 744 return val; 745} 746 747int 748sbicabort(struct sbic_softc *dev, const char *where) 749{ 750 sbic_regmap_p regs = dev->sc_sbicp; 751 u_char csr, asr; 752 753 GET_SBIC_asr(regs, asr); 754 GET_SBIC_csr(regs, csr); 755 756 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 757 dev->sc_dev.dv_xname, where, csr, asr); 758 759 /* 760 * Clean up chip itself 761 */ 762 if (dev->sc_flags & SBICF_SELECTED) { 763 764 while (asr & SBIC_ASR_DBR) { 765 /* 766 * sbic is jammed w/data. need to clear it 767 * But we don't know what direction it needs to go 768 */ 769 GET_SBIC_data(regs, asr); 770 printf("%s: abort %s: clearing data buffer 0x%02x\n", 771 dev->sc_dev.dv_xname, where, asr); 772 GET_SBIC_asr(regs, asr); 773 if (asr & SBIC_ASR_DBR) 774 /* Not the read direction, then */ 775 SET_SBIC_data(regs, asr); 776 GET_SBIC_asr(regs, asr); 777 } 778 779 WAIT_CIP(regs); 780 781 printf("%s: sbicabort - sending ABORT command\n", 782 dev->sc_dev.dv_xname); 783 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 784 WAIT_CIP(regs); 785 786 GET_SBIC_asr(regs, asr); 787 788 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 789 /* 790 * ok, get more drastic.. 791 */ 792 printf("%s: sbicabort - asr %x, trying to reset\n", 793 dev->sc_dev.dv_xname, asr); 794 sbicreset(dev); 795 dev->sc_flags &= ~SBICF_SELECTED; 796 return SBIC_STATE_ERROR; 797 } 798 799 printf("%s: sbicabort - sending DISC command\n", 800 dev->sc_dev.dv_xname); 801 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 802 803 do { 804 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 805 GET_SBIC_asr(regs, asr); 806 GET_SBIC_csr (regs, csr); 807 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 808 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 809 (csr != SBIC_CSR_CMD_INVALID)); 810 811 /* 812 * lets just hope it worked.. 813 */ 814 dev->sc_flags &= ~SBICF_SELECTED; 815 } 816 817 return SBIC_STATE_ERROR; 818} 819 820 821/* 822 * Initialize driver-private structures 823 */ 824void 825sbicinit(struct sbic_softc *dev) 826{ 827 u_int i; 828 829 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 830 831 struct sbic_acb *acb; 832 833 TAILQ_INIT(&dev->ready_list); 834 TAILQ_INIT(&dev->nexus_list); 835 TAILQ_INIT(&dev->free_list); 836 callout_init(&dev->sc_timo_ch, 0); 837 838 dev->sc_nexus = NULL; 839 dev->sc_xs = NULL; 840 841 acb = dev->sc_acb; 842 memset(acb, 0, sizeof(dev->sc_acb)); 843 844 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 845 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 846 acb++; 847 } 848 849 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 850 851#ifdef DEBUG 852 /* 853 * make sure timeout is really not needed 854 */ 855 callout_reset(&dev->sc_timo_ch, 30 * hz, 856 (void *)sbictimeout, dev); 857#endif 858 859 } else 860 panic("sbic: reinitializing driver!"); 861 862 dev->sc_flags |= SBICF_ALIVE; 863 dev->sc_flags &= ~SBICF_SELECTED; 864 865 /* 866 * initialize inhibit array 867 * Never enable Sync, since it just doesn't work on mvme147 :( 868 */ 869 for (i = 0; i < 8; ++i) 870 sbic_inhibit_sync[i] = 1; 871 872 sbicreset(dev); 873} 874 875void 876sbicreset(struct sbic_softc *dev) 877{ 878 sbic_regmap_p regs = dev->sc_sbicp; 879 u_int my_id, s; 880 u_char csr; 881 882 s = splbio(); 883 884 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 885 886 if (dev->sc_clkfreq < 110) 887 my_id |= SBIC_ID_FS_8_10; 888 else if (dev->sc_clkfreq < 160) 889 my_id |= SBIC_ID_FS_12_15; 890 else if (dev->sc_clkfreq < 210) 891 my_id |= SBIC_ID_FS_16_20; 892 893 SET_SBIC_myid(regs, my_id); 894 895 /* 896 * Reset the chip 897 */ 898 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 899 DELAY(25); 900 901 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 902 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 903 904 /* 905 * Set up various chip parameters 906 */ 907 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 908 909 /* 910 * don't allow Selection (SBIC_RID_ES) 911 * until we can handle target mode!! 912 */ 913 SET_SBIC_rselid(regs, SBIC_RID_ER); 914 915 /* 916 * Asynchronous for now 917 */ 918 SET_SBIC_syn(regs, 0); 919 920 /* 921 * Anything else was zeroed by reset 922 */ 923 splx(s); 924 925 dev->sc_flags &= ~SBICF_SELECTED; 926} 927 928void 929sbicerror(struct sbic_softc *dev, u_char csr) 930{ 931 struct scsipi_xfer *xs = dev->sc_xs; 932 933#ifdef DIAGNOSTIC 934 if (xs == NULL) 935 panic("sbicerror: dev->sc_xs == NULL"); 936#endif 937 938 if ( xs->xs_control & XS_CTL_SILENT ) 939 return; 940 941 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 942} 943 944/* 945 * select the bus, return when selected or error. 946 * 947 * Returns the current CSR following selection and optionally MSG out phase. 948 * i.e. the returned CSR *should* indicate CMD phase... 949 * If the return value is 0, some error happened. 950 */ 951u_char 952sbicselectbus(struct sbic_softc *dev) 953{ 954 sbic_regmap_p regs = dev->sc_sbicp; 955 u_char target = dev->target, lun = dev->lun, asr, csr, id; 956 957 /* 958 * if we're already selected, return (XXXX panic maybe?) 959 */ 960 if (dev->sc_flags & SBICF_SELECTED) 961 return 0; 962 963 QPRINTF(("sbicselectbus %d: ", target)); 964 965 /* 966 * issue select 967 */ 968 SET_SBIC_selid(regs, target); 969 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 970 971 GET_SBIC_asr(regs, asr); 972 973 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 974 /* 975 * This means we got ourselves reselected upon 976 */ 977 QPRINTF(("WD busy (reselect?)\n")); 978 return 0; 979 } 980 981 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 982 983 /* 984 * wait for select (merged from separate function may need 985 * cleanup) 986 */ 987 WAIT_CIP(regs); 988 989 do { 990 991 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 992 993 if (asr & SBIC_ASR_LCI) { 994 QPRINTF(("late LCI: asr %02x\n", asr)); 995 return 0; 996 } 997 998 /* 999 * Clear interrupt 1000 */ 1001 GET_SBIC_csr (regs, csr); 1002 1003 QPRINTF(("%02x ", csr)); 1004 1005 /* 1006 * Reselected from under our feet? 1007 */ 1008 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1009 QPRINTF(("got reselected, asr %02x\n", asr)); 1010 /* 1011 * We need to handle this now so we don't lock up later 1012 */ 1013 sbicnextstate(dev, csr, asr); 1014 1015 return 0; 1016 } 1017 1018 /* 1019 * Whoops! 1020 */ 1021 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1022 panic("sbicselectbus: target issued select!"); 1023 return 0; 1024 } 1025 1026 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1027 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1028 csr != SBIC_CSR_SEL_TIMEO); 1029 1030 /* 1031 * Anyone at home? 1032 */ 1033 if (csr == SBIC_CSR_SEL_TIMEO) { 1034 dev->sc_xs->error = XS_SELTIMEOUT; 1035 QPRINTF(("Selection Timeout\n")); 1036 return 0; 1037 } 1038 1039 QPRINTF(("Selection Complete\n")); 1040 1041 /* 1042 * Assume we're now selected 1043 */ 1044 GET_SBIC_selid(regs, id); 1045 dev->target = id; 1046 dev->lun = lun; 1047 dev->sc_flags |= SBICF_SELECTED; 1048 1049 /* 1050 * Enable (or not) reselection 1051 * XXXSCW This is probably not necessary since we don't use use the 1052 * Select-and-Xfer-with-ATN command to initiate a selection... 1053 */ 1054 if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1055 SET_SBIC_rselid (regs, 0); 1056 else 1057 SET_SBIC_rselid (regs, SBIC_RID_ER); 1058 1059 /* 1060 * We only really need to do anything when the target goes to MSG out 1061 * If the device ignored ATN, it's probably old and brain-dead, 1062 * but we'll try to support it anyhow. 1063 * If it doesn't support message out, it definately doesn't 1064 * support synchronous transfers, so no point in even asking... 1065 */ 1066 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1067 /* 1068 * Send identify message (SCSI-2 requires an identify msg) 1069 */ 1070 if (sbic_inhibit_sync[id] && 1071 dev->sc_sync[id].state == SYNC_START) { 1072 /* 1073 * Handle drives that don't want to be asked 1074 * whether to go sync at all. 1075 */ 1076 dev->sc_sync[id].offset = 0; 1077 dev->sc_sync[id].period = sbic_min_period; 1078 dev->sc_sync[id].state = SYNC_DONE; 1079 } 1080 1081 /* 1082 * Do we need to negotiate Synchronous Xfers for this target? 1083 */ 1084 if (dev->sc_sync[id].state != SYNC_START) { 1085 /* 1086 * Nope, we've already negotiated. 1087 * Now see if we should allow the target to 1088 * disconnect/reselect... 1089 */ 1090 if (dev->sc_xs->xs_control & XS_CTL_POLL || 1091 dev->sc_flags & SBICF_ICMD || 1092 !sbic_enable_reselect) 1093 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1094 else 1095 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1096 1097 } else { 1098 /* 1099 * try to initiate a sync transfer. 1100 * So compose the sync message we're going 1101 * to send to the target 1102 */ 1103#ifdef DEBUG 1104 if (sync_debug) 1105 printf("\nSending sync request " 1106 "to target %d ... ", id); 1107#endif 1108 /* 1109 * setup scsi message sync message request 1110 */ 1111 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1112 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1113 dev->sc_msg[2] = 3; 1114 dev->sc_msg[3] = MSG_SYNC_REQ; 1115 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1116 dev->sc_msg[5] = sbic_max_offset; 1117 1118 sbicxfout(regs, 6, dev->sc_msg); 1119 1120 dev->sc_sync[id].state = SYNC_SENT; 1121#ifdef DEBUG 1122 if (sync_debug) 1123 printf ("sent\n"); 1124#endif 1125 } 1126 1127 /* 1128 * There's one interrupt still to come: the change to 1129 * CMD phase... 1130 */ 1131 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1132 GET_SBIC_csr(regs, csr); 1133 } 1134 1135 /* 1136 * set sync or async 1137 */ 1138 if (dev->sc_sync[target].state == SYNC_DONE) { 1139#ifdef DEBUG 1140 if (sync_debug) 1141 printf("select(%d): sync reg = 0x%02x\n", target, 1142 SBIC_SYN(dev->sc_sync[target].offset, 1143 dev->sc_sync[target].period)); 1144#endif 1145 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1146 dev->sc_sync[target].period)); 1147 } else { 1148#ifdef DEBUG 1149 if (sync_debug) 1150 printf("select(%d): sync reg = 0x%02x\n", target, 1151 SBIC_SYN(0,sbic_min_period)); 1152#endif 1153 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1154 } 1155 1156 return csr; 1157} 1158 1159/* 1160 * Information Transfer *to* a Scsi Target. 1161 * 1162 * Note: Don't expect there to be an interrupt immediately after all 1163 * the data is transferred out. The WD spec sheet says that the Transfer- 1164 * Info command for non-MSG_IN phases only completes when the target 1165 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1166 * 1167 * This can have a nasty effect on commands which take a relatively long 1168 * time to complete, for example a START/STOP unit command may remain in 1169 * CMD phase until the disk has spun up. Only then will the target change 1170 * to STATUS phase. This is really only a problem for immediate commands 1171 * since we don't allow disconnection for them (yet). 1172 */ 1173int 1174sbicxfout(sbic_regmap_p regs, int len, void *bp) 1175{ 1176 int wait = sbic_data_wait; 1177 u_char asr, *buf = bp; 1178 1179 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1180 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1181 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1182 1183 /* 1184 * sigh.. WD-PROTO strikes again.. sending the command in one go 1185 * causes the chip to lock up if talking to certain (misbehaving?) 1186 * targets. Anyway, this procedure should work for all targets, but 1187 * it's slightly slower due to the overhead 1188 */ 1189 WAIT_CIP (regs); 1190 1191 SBIC_TC_PUT (regs, 0); 1192 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1193 SBIC_TC_PUT (regs, (unsigned)len); 1194 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1195 1196 /* 1197 * Loop for each byte transferred 1198 */ 1199 do { 1200 1201 GET_SBIC_asr(regs, asr); 1202 1203 if (asr & SBIC_ASR_DBR) { 1204 if (len) { 1205 SET_SBIC_data (regs, *buf); 1206 buf++; 1207 len--; 1208 } else { 1209 SET_SBIC_data (regs, 0); 1210 } 1211 wait = sbic_data_wait; 1212 } 1213 1214 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1215 1216#ifdef DEBUG 1217 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1218#endif 1219 1220 /* 1221 * Normally, an interrupt will be pending when this routing returns. 1222 */ 1223 return len; 1224} 1225 1226/* 1227 * Information Transfer *from* a Scsi Target 1228 * returns # bytes left to read 1229 */ 1230int 1231sbicxfin(sbic_regmap_p regs, int len, void *bp) 1232{ 1233 int wait = sbic_data_wait; 1234 u_char *buf = bp; 1235 u_char asr; 1236#ifdef DEBUG 1237 u_char *obp = bp; 1238#endif 1239 1240 WAIT_CIP(regs); 1241 1242 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1243 SBIC_TC_PUT(regs, (unsigned int)len); 1244 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1245 1246 /* 1247 * Loop for each byte transferred 1248 */ 1249 do { 1250 1251 GET_SBIC_asr(regs, asr); 1252 1253 if (asr & SBIC_ASR_DBR) { 1254 if (len) { 1255 GET_SBIC_data (regs, *buf); 1256 buf++; 1257 len--; 1258 } else { 1259 u_char foo; 1260 GET_SBIC_data (regs, foo); 1261 } 1262 wait = sbic_data_wait; 1263 } 1264 1265 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1266 1267 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1268 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1269 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1270 1271 SBIC_TC_PUT (regs, 0); 1272 1273 /* 1274 * this leaves with one csr to be read 1275 */ 1276 return len; 1277} 1278 1279/* 1280 * SCSI 'immediate' command: issue a command to some SCSI device 1281 * and get back an 'immediate' response (i.e., do programmed xfer 1282 * to get the response data). 'cbuf' is a buffer containing a scsi 1283 * command of length clen bytes. 'buf' is a buffer of length 'len' 1284 * bytes for data. The transfer direction is determined by the device 1285 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1286 * command must supply no data. 1287 * 1288 * Note that although this routine looks like it can handle disconnect/ 1289 * reselect, the fact is that it can't. There is still some work to be 1290 * done to clean this lot up. 1291 */ 1292int 1293sbicicmd(struct sbic_softc *dev, void *cbuf, int clen, void *buf, int len) 1294{ 1295 sbic_regmap_p regs = dev->sc_sbicp; 1296 struct sbic_acb *acb = dev->sc_nexus; 1297 u_char csr, asr; 1298 int still_busy = SBIC_STATE_RUNNING; 1299 1300 /* 1301 * Make sure pointers are OK 1302 */ 1303 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1304 dev->sc_tcnt = acb->sc_tcnt = 0; 1305 1306 acb->sc_dmacmd = 0; 1307 acb->sc_pa.dc_count = 0; /* No DMA */ 1308 acb->sc_kv.dc_addr = buf; 1309 acb->sc_kv.dc_count = len; 1310 1311#ifdef DEBUG 1312 if (data_pointer_debug > 1) 1313 printf("sbicicmd(%d,%d):%d\n", 1314 dev->target, dev->lun, acb->sc_kv.dc_count); 1315#endif 1316 1317 /* 1318 * set the sbic into non-DMA mode 1319 */ 1320 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1321 1322 dev->sc_stat[0] = 0xff; 1323 dev->sc_msg[0] = 0xff; 1324 1325 /* 1326 * We're stealing the SCSI bus 1327 */ 1328 dev->sc_flags |= SBICF_ICMD; 1329 1330 do { 1331 GET_SBIC_asr(regs, asr); 1332 1333 /* 1334 * select the SCSI bus (it's an error if bus isn't free) 1335 */ 1336 if ((dev->sc_flags & SBICF_SELECTED) == 0 && 1337 still_busy != SBIC_STATE_DISCONNECT) { 1338 if ((csr = sbicselectbus(dev)) == 0) { 1339 dev->sc_flags &= ~SBICF_ICMD; 1340 return -1; 1341 } 1342 } else if ((asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == 1343 SBIC_ASR_INT) 1344 GET_SBIC_csr(regs, csr); 1345 else 1346 csr = 0; 1347 1348 if (csr) { 1349 1350 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1351 1352 switch (csr) { 1353 1354 case SBIC_CSR_S_XFERRED: 1355 case SBIC_CSR_DISC: 1356 case SBIC_CSR_DISC_1: 1357 { 1358 u_char phase; 1359 1360 dev->sc_flags &= ~SBICF_SELECTED; 1361 GET_SBIC_cmd_phase(regs, phase); 1362 1363 if (phase == 0x60) { 1364 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1365 still_busy = SBIC_STATE_DONE; /* done */ 1366 } else { 1367#ifdef DEBUG 1368 if (reselect_debug > 1) 1369 printf("sbicicmd: " 1370 "handling disconnect\n"); 1371#endif 1372 still_busy = SBIC_STATE_DISCONNECT; 1373 } 1374 break; 1375 } 1376 1377 case SBIC_CSR_XFERRED | CMD_PHASE: 1378 case SBIC_CSR_MIS | CMD_PHASE: 1379 case SBIC_CSR_MIS_1 | CMD_PHASE: 1380 case SBIC_CSR_MIS_2 | CMD_PHASE: 1381 1382 if (sbicxfout(regs, clen, cbuf)) 1383 still_busy = sbicabort(dev, 1384 "icmd sending cmd"); 1385 break; 1386 1387 case SBIC_CSR_XFERRED | STATUS_PHASE: 1388 case SBIC_CSR_MIS | STATUS_PHASE: 1389 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1390 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1391 1392 /* 1393 * The sbic does the status/cmd-complete 1394 * reading ok, so do this with its 1395 * hi-level commands. 1396 */ 1397#ifdef DEBUG 1398 if (sbic_debug) 1399 printf("SBICICMD status phase " 1400 "(bsy=%d)\n", still_busy); 1401#endif 1402 SET_SBIC_cmd_phase(regs, 0x46); 1403 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1404 break; 1405 1406 default: 1407 still_busy = sbicnextstate(dev, csr, asr); 1408 break; 1409 } 1410 1411 /* 1412 * make sure the last command was taken, 1413 * ie. we're not hunting after an ignored command.. 1414 */ 1415 GET_SBIC_asr(regs, asr); 1416 1417 /* 1418 * tapes may take a loooong time.. 1419 */ 1420 while (asr & SBIC_ASR_BSY) { 1421 1422 if (asr & SBIC_ASR_DBR) { 1423 int i; 1424 1425 printf("sbicicmd: " 1426 "Waiting while sbic is jammed, " 1427 "CSR:%02x,ASR:%02x\n", csr, asr); 1428#ifdef DDB 1429 Debugger(); 1430#endif 1431 /* 1432 * SBIC is jammed 1433 * DUNNO which direction 1434 * Try old direction 1435 */ 1436 GET_SBIC_data(regs, i); 1437 GET_SBIC_asr(regs, asr); 1438 1439 if (asr & SBIC_ASR_DBR) 1440 /* Wants us to write */ 1441 SET_SBIC_data(regs, i); 1442 } 1443 1444 GET_SBIC_asr(regs, asr); 1445 } 1446 } 1447 1448 /* 1449 * wait for last command to complete 1450 */ 1451 if (asr & SBIC_ASR_LCI) { 1452 printf("sbicicmd: last command ignored\n"); 1453 } else if (still_busy >= SBIC_STATE_RUNNING) /* Bsy */ 1454 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1455 1456 /* 1457 * do it again 1458 */ 1459 } while (still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff); 1460 1461 /* 1462 * Sometimes we need to do an extra read of the CSR 1463 */ 1464 GET_SBIC_csr(regs, csr); 1465 1466#ifdef DEBUG 1467 if (data_pointer_debug > 1) 1468 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1469 acb->sc_kv.dc_count, dev->sc_stat[0]); 1470#endif 1471 1472 dev->sc_flags &= ~SBICF_ICMD; 1473 1474 return dev->sc_stat[0]; 1475} 1476 1477/* 1478 * Finish SCSI xfer command: After the completion interrupt from 1479 * a read/write operation, sequence through the final phases in 1480 * programmed i/o. This routine is a lot like sbicicmd except we 1481 * skip (and don't allow) the select, cmd out and data in/out phases. 1482 */ 1483void 1484sbicxfdone(struct sbic_softc *dev) 1485{ 1486 sbic_regmap_p regs = dev->sc_sbicp; 1487 u_char phase, csr; 1488 int s; 1489 1490 QPRINTF(("{")); 1491 s = splbio(); 1492 1493 /* 1494 * have the sbic complete on its own 1495 */ 1496 SBIC_TC_PUT(regs, 0); 1497 SET_SBIC_cmd_phase(regs, 0x46); 1498 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1499 1500 do { 1501 1502 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1503 GET_SBIC_csr(regs, csr); 1504 QPRINTF(("%02x:", csr)); 1505 1506 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1507 (csr != SBIC_CSR_S_XFERRED)); 1508 1509 dev->sc_flags &= ~SBICF_SELECTED; 1510 1511 GET_SBIC_cmd_phase (regs, phase); 1512 QPRINTF(("}%02x", phase)); 1513 1514 if (phase == 0x60) 1515 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1516 else 1517 sbicerror(dev, csr); 1518 1519 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1520 1521 splx(s); 1522} 1523 1524/* 1525 * No DMA chains 1526 */ 1527int 1528sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1529{ 1530 struct sbic_acb *acb = dev->sc_nexus; 1531 sbic_regmap_p regs = dev->sc_sbicp; 1532 int i, dmaflags, count, usedma; 1533 u_char csr, asr, *addr; 1534 1535 dev->target = xs->xs_periph->periph_target; 1536 dev->lun = xs->xs_periph->periph_lun; 1537 1538 usedma = sbicdmaok(dev, xs); 1539 1540#ifdef DEBUG 1541 if (data_pointer_debug > 1) 1542 printf("sbicgo(%d,%d): usedma=%d\n", 1543 dev->target, dev->lun, usedma); 1544#endif 1545 1546 /* 1547 * select the SCSI bus (it's an error if bus isn't free) 1548 */ 1549 if ((csr = sbicselectbus(dev)) == 0) 1550 return 0; /* Not done: needs to be rescheduled */ 1551 1552 dev->sc_stat[0] = 0xff; 1553 1554 /* 1555 * Calculate DMA chains now 1556 */ 1557 if (acb->flags & ACB_DATAIN) 1558 dmaflags = DMAGO_READ; 1559 else 1560 dmaflags = 0; 1561 1562 addr = acb->sc_kv.dc_addr; 1563 count = acb->sc_kv.dc_count; 1564 1565 if (count && ((char *)kvtop((void *)addr) != acb->sc_pa.dc_addr)) { 1566 printf("sbic: DMA buffer mapping changed %p->%x\n", 1567 acb->sc_pa.dc_addr, kvtop((void *)addr)); 1568#ifdef DDB 1569 Debugger(); 1570#endif 1571 } 1572 1573#ifdef DEBUG 1574 ++sbicdma_ops; /* count total DMA operations */ 1575#endif 1576 1577 /* 1578 * Allocate the DMA chain 1579 * Mark end of segment... 1580 */ 1581 acb->sc_tcnt = dev->sc_tcnt = 0; 1582 acb->sc_pa.dc_count = 0; 1583 1584 sbic_load_ptrs(dev); 1585 1586 /* 1587 * Enable interrupts but don't do any DMA 1588 * enintr() also enables interrupts for the sbic 1589 */ 1590 dev->sc_enintr(dev); 1591 1592 if (usedma) { 1593 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1594 acb->sc_pa.dc_count, dmaflags); 1595#ifdef DEBUG 1596 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1597#endif 1598 } else 1599 dev->sc_dmacmd = 0; /* Don't use DMA */ 1600 1601 acb->sc_dmacmd = dev->sc_dmacmd; 1602 1603#ifdef DEBUG 1604 if (data_pointer_debug > 1) { 1605 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1606 dev->sc_cur->dc_addr, 1607 dev->sc_tcnt, 1608 dev->sc_dmacmd); 1609 } 1610#endif 1611 1612 /* 1613 * Lets cycle a while then let the interrupt handler take over. 1614 */ 1615 GET_SBIC_asr(regs, asr); 1616 1617 do { 1618 1619 QPRINTF(("go ")); 1620 1621 /* 1622 * Handle the new phase 1623 */ 1624 i = sbicnextstate(dev, csr, asr); 1625#if 0 1626 WAIT_CIP(regs); 1627#endif 1628 if (i == SBIC_STATE_RUNNING) { 1629 GET_SBIC_asr(regs, asr); 1630 1631 if (asr & SBIC_ASR_LCI) 1632 printf("sbicgo: LCI asr:%02x csr:%02x\n", 1633 asr, csr); 1634 1635 if (asr & SBIC_ASR_INT) 1636 GET_SBIC_csr(regs, csr); 1637 } 1638 1639 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1640 1641 if (i == SBIC_STATE_DONE) { 1642 if (dev->sc_stat[0] == 0xff) 1643#if 0 1644 printf("sbicgo: done & stat = 0xff\n"); 1645#else 1646 ; 1647#endif 1648 else 1649 return 1; /* Did we really finish that fast? */ 1650 } 1651 1652 return 0; 1653} 1654 1655 1656int 1657sbicintr(struct sbic_softc *dev) 1658{ 1659 sbic_regmap_p regs = dev->sc_sbicp; 1660 u_char asr, csr; 1661 int i; 1662 1663 /* 1664 * pending interrupt? 1665 */ 1666 GET_SBIC_asr (regs, asr); 1667 if ((asr & SBIC_ASR_INT) == 0) 1668 return 0; 1669 1670 GET_SBIC_csr(regs, csr); 1671 1672 do { 1673 1674 QPRINTF(("intr[0x%x]", csr)); 1675 1676 i = sbicnextstate(dev, csr, asr); 1677#if 0 1678 WAIT_CIP(regs); 1679#endif 1680 if (i == SBIC_STATE_RUNNING) { 1681 GET_SBIC_asr(regs, asr); 1682 1683 if (asr & SBIC_ASR_LCI) 1684 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1685 1686 if (asr & SBIC_ASR_INT) 1687 GET_SBIC_csr(regs, csr); 1688 } 1689 1690 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1691 1692 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1693 1694 return 1; 1695} 1696 1697/* 1698 * Run commands and wait for disconnect. 1699 * This is only ever called when a command is in progress, when we 1700 * want to busy wait for it to finish. 1701 */ 1702int 1703sbicpoll(struct sbic_softc *dev) 1704{ 1705 sbic_regmap_p regs = dev->sc_sbicp; 1706 u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ 1707 int i; 1708 1709 /* 1710 * Wait for the next interrupt 1711 */ 1712 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1713 1714 do { 1715 GET_SBIC_asr (regs, asr); 1716 1717 if (asr & SBIC_ASR_INT) 1718 GET_SBIC_csr(regs, csr); 1719 1720 QPRINTF(("poll[0x%x]", csr)); 1721 1722 /* 1723 * Handle it 1724 */ 1725 i = sbicnextstate(dev, csr, asr); 1726 1727 WAIT_CIP(regs); 1728 GET_SBIC_asr(regs, asr); 1729 1730 /* 1731 * tapes may take a loooong time.. 1732 */ 1733 while (asr & SBIC_ASR_BSY) { 1734 u_char z = 0; 1735 1736 if (asr & SBIC_ASR_DBR) { 1737 printf("sbipoll: Waiting while sbic is jammed," 1738 " CSR:%02x,ASR:%02x\n", csr, asr); 1739#ifdef DDB 1740 Debugger(); 1741#endif 1742 /* 1743 * SBIC is jammed 1744 * DUNNO which direction 1745 * Try old direction 1746 */ 1747 GET_SBIC_data(regs, z); 1748 GET_SBIC_asr(regs, asr); 1749 1750 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1751 SET_SBIC_data(regs, z); 1752 } 1753 1754 GET_SBIC_asr(regs, asr); 1755 } 1756 1757 if (asr & SBIC_ASR_LCI) 1758 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1759 else if (i == SBIC_STATE_RUNNING) /* BSY */ 1760 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1761 1762 } while (i == SBIC_STATE_RUNNING); 1763 1764 return 1; 1765} 1766 1767/* 1768 * Handle a single msgin 1769 */ 1770int 1771sbicmsgin(struct sbic_softc *dev) 1772{ 1773 sbic_regmap_p regs = dev->sc_sbicp; 1774 int recvlen = 1; 1775 u_char asr, csr, *tmpaddr, *msgaddr; 1776 1777 tmpaddr = msgaddr = dev->sc_msg; 1778 1779 tmpaddr[0] = 0xff; 1780 tmpaddr[1] = 0xff; 1781 1782 GET_SBIC_asr(regs, asr); 1783 1784#ifdef DEBUG 1785 if (reselect_debug > 1) 1786 printf("sbicmsgin asr=%02x\n", asr); 1787#endif 1788 1789 GET_SBIC_selid (regs, csr); 1790 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1791 1792 SBIC_TC_PUT(regs, 0); 1793 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1794 1795 do { 1796 while (recvlen--) { 1797 1798 /* 1799 * Fetch the next byte of the message 1800 */ 1801 RECV_BYTE(regs, *tmpaddr); 1802 1803 /* 1804 * get the command completion interrupt, or we 1805 * can't send a new command (LCI) 1806 */ 1807 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1808 GET_SBIC_csr(regs, csr); 1809 1810#ifdef DEBUG 1811 if (reselect_debug > 1) 1812 printf("sbicmsgin: got %02x csr %02x\n", 1813 *tmpaddr, csr); 1814#endif 1815 1816 tmpaddr++; 1817 1818 if (recvlen) { 1819 /* 1820 * Clear ACK, and wait for the interrupt 1821 * for the next byte 1822 */ 1823 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1824 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1825 GET_SBIC_csr(regs, csr); 1826 } 1827 } 1828 1829 if (msgaddr[0] == 0xff) { 1830 printf("sbicmsgin: sbic swallowed our message\n"); 1831 break; 1832 } 1833 1834#ifdef DEBUG 1835 if (sync_debug) { 1836 GET_SBIC_asr(regs, asr); 1837 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1838 csr, asr, msgaddr[0]); 1839 } 1840#endif 1841 /* 1842 * test whether this is a reply to our sync 1843 * request 1844 */ 1845 if (MSG_ISIDENTIFY(msgaddr[0])) { 1846 1847 /* 1848 * Got IFFY msg -- ack it 1849 */ 1850 QPRINTF(("IFFY")); 1851 1852 } else if (msgaddr[0] == MSG_REJECT && 1853 dev->sc_sync[dev->target].state == SYNC_SENT) { 1854 1855 /* 1856 * Target probably rejected our Sync negotiation. 1857 */ 1858 QPRINTF(("REJECT of SYN")); 1859 1860#ifdef DEBUG 1861 if (sync_debug) 1862 printf("target %d rejected sync, going async\n", 1863 dev->target); 1864#endif 1865 1866 dev->sc_sync[dev->target].period = sbic_min_period; 1867 dev->sc_sync[dev->target].offset = 0; 1868 dev->sc_sync[dev->target].state = SYNC_DONE; 1869 SET_SBIC_syn(regs, 1870 SBIC_SYN(dev->sc_sync[dev->target].offset, 1871 dev->sc_sync[dev->target].period)); 1872 1873 } else if (msgaddr[0] == MSG_REJECT) { 1874 1875 /* 1876 * we'll never REJECt a REJECT message.. 1877 */ 1878 QPRINTF(("REJECT")); 1879 1880 } else if (msgaddr[0] == MSG_SAVE_DATA_PTR) { 1881 1882 /* 1883 * don't reject this either. 1884 */ 1885 QPRINTF(("MSG_SAVE_DATA_PTR")); 1886 1887 } else if (msgaddr[0] == MSG_RESTORE_PTR) { 1888 1889 /* 1890 * don't reject this either. 1891 */ 1892 QPRINTF(("MSG_RESTORE_PTR")); 1893 1894 } else if (msgaddr[0] == MSG_DISCONNECT) { 1895 1896 /* 1897 * Target is disconnecting... 1898 */ 1899 QPRINTF(("DISCONNECT")); 1900 1901#ifdef DEBUG 1902 if (reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT) 1903 printf("sbicmsgin: got disconnect msg %s\n", 1904 (dev->sc_flags & SBICF_ICMD) ? 1905 "rejecting" : ""); 1906#endif 1907 1908 if (dev->sc_flags & SBICF_ICMD) { 1909 /* 1910 * We're in immediate mode. Prevent disconnects. 1911 * prepare to reject the message, NACK 1912 */ 1913 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1914 WAIT_CIP(regs); 1915 } 1916 1917 } else if (msgaddr[0] == MSG_CMD_COMPLETE) { 1918 1919 /* 1920 * !! KLUDGE ALERT !! quite a few drives don't seem to 1921 * really like the current way of sending the 1922 * sync-handshake together with the ident-message, and 1923 * they react by sending command-complete and 1924 * disconnecting right after returning the valid sync 1925 * handshake. So, all I can do is reselect the drive, 1926 * and hope it won't disconnect again. I don't think 1927 * this is valid behavior, but I can't help fixing a 1928 * problem that apparently exists. 1929 * 1930 * Note: we should not get here on `normal' command 1931 * completion, as that condition is handled by the 1932 * high-level sel&xfer resume command used to walk 1933 * thru status/cc-phase. 1934 */ 1935 QPRINTF(("CMD_COMPLETE")); 1936 1937#ifdef DEBUG 1938 if (sync_debug) 1939 printf("GOT MSG %d! target %d acting weird.." 1940 " waiting for disconnect...\n", 1941 msgaddr[0], dev->target); 1942#endif 1943 1944 /* 1945 * Check to see if sbic is handling this 1946 */ 1947 GET_SBIC_asr(regs, asr); 1948 1949 /* 1950 * XXXSCW: I'm not convinced of this, 1951 * we haven't negated ACK yet... 1952 */ 1953 if (asr & SBIC_ASR_BSY) 1954 return SBIC_STATE_RUNNING; 1955 1956 /* 1957 * Let's try this: Assume it works and set status to 00 1958 */ 1959 dev->sc_stat[0] = 0; 1960 1961 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 1962 tmpaddr == &(msgaddr[1])) { 1963 1964 /* 1965 * Target is sending us an extended message. 1966 * We'll assume it's the response to our Sync. 1967 * negotiation. 1968 */ 1969 QPRINTF(("ExtMSG\n")); 1970 1971 /* 1972 * Read in whole extended message. 1973 * First, negate ACK to accept 1974 * the MSG_EXT_MESSAGE byte... 1975 */ 1976 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1977 1978 /* 1979 * Wait for the interrupt for the next byte (length) 1980 */ 1981 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1982 GET_SBIC_csr(regs, csr); 1983 1984#ifdef DEBUG 1985 QPRINTF(("CLR ACK csr %02x\n", csr)); 1986#endif 1987 1988 /* 1989 * Read the length byte 1990 */ 1991 RECV_BYTE(regs, *tmpaddr); 1992 1993 /* 1994 * Wait for command completion IRQ 1995 */ 1996 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1997 GET_SBIC_csr(regs, csr); 1998 1999 /* 2000 * Reload the loop counter 2001 */ 2002 recvlen = *tmpaddr++; 2003 2004 QPRINTF(("Recving ext msg, csr %02x len %02x\n", 2005 csr, recvlen)); 2006 2007 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 2008 msgaddr[1] == 3 && 2009 msgaddr[2] == MSG_SYNC_REQ ) { 2010 2011 /* 2012 * We've received the complete Extended Message Sync. 2013 * Request... 2014 */ 2015 QPRINTF(("SYN")); 2016 2017 /* 2018 * Compute the required Transfer Period for 2019 * the WD chip... 2020 */ 2021 dev->sc_sync[dev->target].period = 2022 sbicfromscsiperiod(dev, msgaddr[3]); 2023 dev->sc_sync[dev->target].offset = msgaddr[4]; 2024 dev->sc_sync[dev->target].state = SYNC_DONE; 2025 2026 /* 2027 * Put the WD chip in synchronous mode 2028 */ 2029 SET_SBIC_syn(regs, 2030 SBIC_SYN(dev->sc_sync[dev->target].offset, 2031 dev->sc_sync[dev->target].period)); 2032#ifdef DEBUG 2033 if (sync_debug) 2034 printf("msgin(%d): sync reg = 0x%02x\n", 2035 dev->target, 2036 SBIC_SYN(dev->sc_sync[dev->target].offset, 2037 dev->sc_sync[dev->target].period)); 2038#endif 2039 2040 printf("%s: target %d now synchronous, " 2041 "period=%dns, offset=%d.\n", 2042 dev->sc_dev.dv_xname, dev->target, 2043 msgaddr[3] * 4, msgaddr[4]); 2044 2045 } else { 2046 2047 /* 2048 * We don't support whatever this message is... 2049 */ 2050#ifdef DEBUG 2051 if (sbic_debug || sync_debug) 2052 printf("sbicmsgin: Rejecting message 0x%02x\n", 2053 msgaddr[0]); 2054#endif 2055 2056 /* 2057 * prepare to reject the message, NACK 2058 */ 2059 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2060 WAIT_CIP(regs); 2061 } 2062 2063 /* 2064 * Negate ACK to complete the transfer 2065 */ 2066 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2067 2068 /* 2069 * Wait for the interrupt for the next byte, or phase change. 2070 * Only read the CSR if we have more data to transfer. 2071 * XXXSCW: We should really verify that we're still in 2072 * MSG IN phase before blindly going back around this loop, 2073 * but that would mean we read the CSR... <sigh> 2074 */ 2075 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2076 if (recvlen > 0) 2077 GET_SBIC_csr(regs, csr); 2078 2079 } while (recvlen > 0); 2080 2081 /* 2082 * Should still have one CSR to read 2083 */ 2084 return SBIC_STATE_RUNNING; 2085} 2086 2087 2088/* 2089 * sbicnextstate() 2090 * return: 2091 * SBIC_STATE_DONE == done 2092 * SBIC_STATE_RUNNING == working 2093 * SBIC_STATE_DISCONNECT == disconnected 2094 * SBIC_STATE_ERROR == error 2095 */ 2096int 2097sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2098{ 2099 sbic_regmap_p regs = dev->sc_sbicp; 2100 struct sbic_acb *acb = dev->sc_nexus; 2101 2102 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2103 2104 switch (csr) { 2105 2106 case SBIC_CSR_XFERRED | CMD_PHASE: 2107 case SBIC_CSR_MIS | CMD_PHASE: 2108 case SBIC_CSR_MIS_1 | CMD_PHASE: 2109 case SBIC_CSR_MIS_2 | CMD_PHASE: 2110 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2111 goto abort; 2112 break; 2113 2114 case SBIC_CSR_XFERRED | STATUS_PHASE: 2115 case SBIC_CSR_MIS | STATUS_PHASE: 2116 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2117 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2118 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2119 2120 /* 2121 * this should be the normal i/o completion case. 2122 * get the status & cmd complete msg then let the 2123 * device driver look at what happened. 2124 */ 2125 sbicxfdone(dev); 2126 2127#ifdef DEBUG 2128 dev->sc_dmatimo = 0; 2129 if (data_pointer_debug > 1) 2130 printf("next dmastop: %d(%p:%lx)\n", 2131 dev->target, 2132 dev->sc_cur->dc_addr, 2133 dev->sc_tcnt); 2134#endif 2135 /* 2136 * Stop the DMA chip 2137 */ 2138 dev->sc_dmastop(dev); 2139 2140 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2141 2142 /* 2143 * Indicate to the upper layers that the command is done 2144 */ 2145 sbic_scsidone(acb, dev->sc_stat[0]); 2146 2147 return SBIC_STATE_DONE; 2148 2149 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2150 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2151 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2152 case SBIC_CSR_MIS | DATA_IN_PHASE: 2153 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2154 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2155 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2156 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2157 /* 2158 * Verify that we expected to transfer data... 2159 */ 2160 if (acb->sc_kv.dc_count <= 0) { 2161 printf("next: DATA phase with xfer count == %d, " 2162 "asr:0x%02x csr:0x%02x\n", 2163 acb->sc_kv.dc_count, asr, csr); 2164 goto abort; 2165 } 2166 2167 /* 2168 * Should we transfer using PIO or DMA ? 2169 */ 2170 if (dev->sc_xs->xs_control & XS_CTL_POLL || 2171 dev->sc_flags & SBICF_ICMD || 2172 acb->sc_dmacmd == 0 ) { 2173 2174 /* 2175 * Do PIO transfer 2176 */ 2177 int i; 2178 2179#ifdef DEBUG 2180 if (data_pointer_debug > 1) 2181 printf("next PIO: %d(%p:%x)\n", dev->target, 2182 acb->sc_kv.dc_addr, 2183 acb->sc_kv.dc_count); 2184#endif 2185 2186 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 2187 /* 2188 * data in 2189 */ 2190 i = sbicxfin(regs, acb->sc_kv.dc_count, 2191 acb->sc_kv.dc_addr); 2192 else 2193 /* 2194 * data out 2195 */ 2196 i = sbicxfout(regs, acb->sc_kv.dc_count, 2197 acb->sc_kv.dc_addr); 2198 2199 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2200 acb->sc_kv.dc_count = i; 2201 2202 /* 2203 * Update current count... 2204 */ 2205 acb->sc_tcnt = dev->sc_tcnt = i; 2206 2207 dev->sc_flags &= ~SBICF_INDMA; 2208 2209 } else { 2210 2211 /* 2212 * Do DMA transfer 2213 * set next DMA addr and dec count 2214 */ 2215 sbic_save_ptrs(dev); 2216 sbic_load_ptrs(dev); 2217 2218 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2219 SBIC_MACHINE_DMA_MODE); 2220 2221#ifdef DEBUG 2222 dev->sc_dmatimo = 1; 2223 if (data_pointer_debug > 1) 2224 printf("next DMA: %d(%p:%lx)\n", dev->target, 2225 dev->sc_cur->dc_addr, 2226 dev->sc_tcnt); 2227#endif 2228 /* 2229 * Start the DMA chip going 2230 */ 2231 dev->sc_tcnt = dev->sc_dmanext(dev); 2232 2233 /* 2234 * Tell the WD chip how much to transfer 2235 * this time around 2236 */ 2237 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2238 2239 /* 2240 * Start the transfer 2241 */ 2242 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2243 2244 /* 2245 * Indicate that we're in DMA mode 2246 */ 2247 dev->sc_flags |= SBICF_INDMA; 2248 } 2249 break; 2250 2251 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2252 case SBIC_CSR_MIS | MESG_IN_PHASE: 2253 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2254 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2255 sbic_save_ptrs(dev); 2256 2257 /* 2258 * Handle a single message in... 2259 */ 2260 return sbicmsgin(dev); 2261 2262 case SBIC_CSR_MSGIN_W_ACK: 2263 /* 2264 * We should never see this since it's handled in 'sbicmsgin()' 2265 * but just for the sake of paranoia... 2266 */ 2267 /* Dunno what I'm ACKing */ 2268 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2269 printf("Acking unknown msgin CSR:%02x",csr); 2270 break; 2271 2272 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2273 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2274 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2275 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2276 /* 2277 * We only ever handle a message out phase here for sending a 2278 * REJECT message. 2279 */ 2280 sbic_save_ptrs(dev); 2281 2282#ifdef DEBUG 2283 if (sync_debug) 2284 printf("sending REJECT msg to last msg.\n"); 2285#endif 2286 2287 SEND_BYTE(regs, MSG_REJECT); 2288 WAIT_CIP(regs); 2289 break; 2290 2291 case SBIC_CSR_DISC: 2292 case SBIC_CSR_DISC_1: 2293 /* 2294 * Try to schedule another target 2295 */ 2296 sbic_save_ptrs(dev); 2297 2298 dev->sc_flags &= ~SBICF_SELECTED; 2299 2300#ifdef DEBUG 2301 if (reselect_debug > 1) 2302 printf("sbicnext target %d disconnected\n", 2303 dev->target); 2304#endif 2305 2306 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2307 2308 ++dev->sc_tinfo[dev->target].dconns; 2309 2310 dev->sc_nexus = NULL; 2311 dev->sc_xs = NULL; 2312 2313 if (acb->xs->xs_control & XS_CTL_POLL || 2314 dev->sc_flags & SBICF_ICMD || 2315 !sbic_parallel_operations ) 2316 return SBIC_STATE_DISCONNECT; 2317 2318 QPRINTF(("sbicnext: calling sbic_sched\n")); 2319 2320 sbic_sched(dev); 2321 2322 QPRINTF(("sbicnext: sbic_sched returned\n")); 2323 2324 return SBIC_STATE_DISCONNECT; 2325 2326 case SBIC_CSR_RSLT_NI: 2327 case SBIC_CSR_RSLT_IFY: 2328 { 2329 /* 2330 * A reselection. 2331 * Note that since we don't enable Advanced Features (assuming 2332 * the WD chip is at least the 'A' revision), we're only ever 2333 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2334 * hell of it, we'll handle it anyway, for all the extra code 2335 * it needs... 2336 */ 2337 u_char newtarget, newlun; 2338 2339 GET_SBIC_rselid(regs, newtarget); 2340 2341 /* 2342 * check SBIC_RID_SIV? 2343 */ 2344 newtarget &= SBIC_RID_MASK; 2345 2346 if (csr == SBIC_CSR_RSLT_IFY) { 2347 2348 /* 2349 * Read Identify msg to avoid lockup 2350 */ 2351 GET_SBIC_data(regs, newlun); 2352 WAIT_CIP(regs); 2353 newlun &= SBIC_TLUN_MASK; 2354 2355 } else { 2356 2357 /* 2358 * Need to read Identify message the hard way, assuming 2359 * the target even sends us one... 2360 */ 2361 for (newlun = 255; newlun; --newlun) { 2362 GET_SBIC_asr(regs, asr); 2363 if (asr & SBIC_ASR_INT) 2364 break; 2365 delay(10); 2366 } 2367 2368 /* 2369 * If we didn't get an interrupt, somethink's up 2370 */ 2371 if ((asr & SBIC_ASR_INT) == 0) { 2372 printf("%s: Reselect without identify?" 2373 " asr %x\n", dev->sc_dev.dv_xname, asr); 2374 newlun = 0; /* XXXX */ 2375 } else { 2376 /* 2377 * We got an interrupt, verify that 2378 * it's a change to message in phase, 2379 * and if so read the message. 2380 */ 2381 GET_SBIC_csr(regs,csr); 2382 2383 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2384 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2385 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2386 /* 2387 * Yup, gone to message in. 2388 * Fetch the target LUN 2389 */ 2390 sbicmsgin(dev); 2391 newlun = dev->sc_msg[0] & 0x07; 2392 2393 } else { 2394 /* 2395 * Whoops! Target didn't go to 2396 * message in phase!! 2397 */ 2398 printf("RSLT_NI - " 2399 "not MESG_IN_PHASE %x\n", csr); 2400 newlun = 0; /* XXXSCW */ 2401 } 2402 } 2403 } 2404 2405 /* 2406 * Ok, we have the identity of the reselecting target. 2407 */ 2408#ifdef DEBUG 2409 if (reselect_debug > 1 || 2410 (reselect_debug && csr == SBIC_CSR_RSLT_NI)) { 2411 printf("sbicnext: reselect %s from targ %d lun %d\n", 2412 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2413 newtarget, newlun); 2414 } 2415#endif 2416 2417 if (dev->sc_nexus) { 2418 /* 2419 * Whoops! We've been reselected with 2420 * an command in progress! 2421 * The best we can do is to put the current command 2422 * back on the ready list and hope for the best. 2423 */ 2424#ifdef DEBUG 2425 if (reselect_debug > 1) { 2426 printf("%s: reselect %s with active command\n", 2427 dev->sc_dev.dv_xname, 2428 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2429 } 2430#endif 2431 2432 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, 2433 chain); 2434 2435 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2436 2437 dev->sc_nexus = NULL; 2438 dev->sc_xs = NULL; 2439 } 2440 2441 /* 2442 * Reload sync values for this target 2443 */ 2444 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2445 SET_SBIC_syn(regs, 2446 SBIC_SYN(dev->sc_sync[newtarget].offset, 2447 dev->sc_sync[newtarget].period)); 2448 else 2449 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2450 2451 /* 2452 * Loop through the nexus list until we find the saved entry 2453 * for the reselecting target... 2454 */ 2455 for (acb = dev->nexus_list.tqh_first; acb; 2456 acb = acb->chain.tqe_next) { 2457 2458 if ( acb->xs->xs_periph->periph_target == newtarget && 2459 acb->xs->xs_periph->periph_lun == newlun) { 2460 /* 2461 * We've found the saved entry. Dequeue it, and 2462 * make it current again. 2463 */ 2464 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2465 2466 dev->sc_nexus = acb; 2467 dev->sc_xs = acb->xs; 2468 dev->sc_flags |= SBICF_SELECTED; 2469 dev->target = newtarget; 2470 dev->lun = newlun; 2471 break; 2472 } 2473 } 2474 2475 if (acb == NULL) { 2476 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2477 dev->sc_dev.dv_xname, 2478 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2479 &dev->nexus_list.tqh_first); 2480 panic("bad reselect in sbic"); 2481 } 2482 2483 if (csr == SBIC_CSR_RSLT_IFY) 2484 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2485 break; 2486 } 2487 default: 2488 abort: 2489 /* 2490 * Something unexpected happened -- deal with it. 2491 */ 2492 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2493 2494#ifdef DDB 2495 Debugger(); 2496#endif 2497 2498#ifdef DEBUG 2499 dev->sc_dmatimo = 0; 2500 if (data_pointer_debug > 1) 2501 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2502 dev->sc_cur->dc_addr, 2503 dev->sc_tcnt); 2504#endif 2505 2506 dev->sc_dmastop(dev); 2507 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2508 if (dev->sc_xs) 2509 sbicerror(dev, csr); 2510 sbicabort(dev, "next"); 2511 2512 if (dev->sc_flags & SBICF_INDMA) { 2513 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2514 2515#ifdef DEBUG 2516 dev->sc_dmatimo = 0; 2517 if (data_pointer_debug > 1) 2518 printf("next dmastop: %d(%p:%lx)\n", 2519 dev->target, 2520 dev->sc_cur->dc_addr, 2521 dev->sc_tcnt); 2522#endif 2523 sbic_scsidone(acb, -1); 2524 } 2525 2526 return SBIC_STATE_ERROR; 2527 } 2528 2529 return SBIC_STATE_RUNNING; 2530} 2531 2532 2533/* 2534 * Check if DMA can not be used with specified buffer 2535 */ 2536int 2537sbiccheckdmap(void *bp, u_long len, u_long mask) 2538{ 2539 u_char *buffer; 2540 u_long phy_buf; 2541 u_long phy_len; 2542 2543 buffer = bp; 2544 2545 if (len == 0) 2546 return 1; 2547 2548 while (len) { 2549 2550 phy_buf = kvtop((void *)buffer); 2551 phy_len = PAGE_SIZE - ((int)buffer & PGOFSET); 2552 2553 if (len < phy_len) 2554 phy_len = len; 2555 2556 if (phy_buf & mask) 2557 return 1; 2558 2559 buffer += phy_len; 2560 len -= phy_len; 2561 } 2562 2563 return 0; 2564} 2565 2566int 2567sbictoscsiperiod(struct sbic_softc *dev, int a) 2568{ 2569 unsigned int fs; 2570 2571 /* 2572 * cycle = DIV / (2 * CLK) 2573 * DIV = FS + 2 2574 * best we can do is 200ns at 20 MHz, 2 cycles 2575 */ 2576 2577 GET_SBIC_myid(dev->sc_sbicp, fs); 2578 2579 fs = (fs >> 6) + 2; /* DIV */ 2580 2581 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2582 2583 if (a < 2) 2584 a = 8; /* map to Cycles */ 2585 2586 return (fs * a) >> 2; /* in 4 ns units */ 2587} 2588 2589int 2590sbicfromscsiperiod(struct sbic_softc *dev, int p) 2591{ 2592 unsigned int fs, ret; 2593 2594 /* 2595 * Just the inverse of the above 2596 */ 2597 GET_SBIC_myid(dev->sc_sbicp, fs); 2598 2599 fs = (fs >> 6) + 2; /* DIV */ 2600 2601 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2602 2603 ret = p << 2; /* in ns units */ 2604 ret = ret / fs; /* in Cycles */ 2605 2606 if (ret < sbic_min_period) 2607 return(sbic_min_period); 2608 2609 /* 2610 * verify rounding 2611 */ 2612 if (sbictoscsiperiod(dev, ret) < p) 2613 ret++; 2614 2615 return (ret >= 8) ? 0 : ret; 2616} 2617 2618#ifdef DEBUG 2619void 2620sbictimeout(struct sbic_softc *dev) 2621{ 2622 int s, asr; 2623 2624 s = splbio(); 2625 2626 if (dev->sc_dmatimo) { 2627 2628 if (dev->sc_dmatimo > 1) { 2629 2630 printf("%s: DMA timeout #%d\n", dev->sc_dev.dv_xname, 2631 dev->sc_dmatimo - 1); 2632 2633 GET_SBIC_asr(dev->sc_sbicp, asr); 2634 2635 if (asr & SBIC_ASR_INT) { 2636 /* 2637 * We need to service a missed IRQ 2638 */ 2639 sbicintr(dev); 2640 } else { 2641 (void)sbicabort(dev, "timeout"); 2642 splx(s); 2643 return; 2644 } 2645 } 2646 2647 dev->sc_dmatimo++; 2648 } 2649 2650 splx(s); 2651 2652 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2653} 2654#endif 2655