1/* $NetBSD: cache_r3k_subr.S,v 1.4 2005/12/11 12:18:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Digital Equipment Corporation and Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permited provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s, 43 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL) 44 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s, 45 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL) 46 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s, 47 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL) 48 * 49 * @(#)locore.s 8.5 (Berkeley) 1/4/94 50 */ 51 52#include <mips/asm.h> 53#include <mips/cpuregs.h> 54 55#include "assym.h" 56 57 .set noreorder 58 59/* 60 * r3k_size_cache: 61 * 62 * This works by writing marker values repeatedly at possible 63 * cache boundaries (256K to 512). Since the cache is direct-mapped 64 * and the address ranges have aliased with given cache size, 65 * whatever value is found at cache location zero indicates the size. 66 */ 67LEAF_NOPROFILE(r3k_size_cache) 68 la v0, 1f 69 or v0, MIPS_KSEG1_START 70 j v0 # run uncached 71 mfc0 v1, MIPS_COP_0_STATUS 721: 73 mtc0 a0, MIPS_COP_0_STATUS # disable interrupts, 74 nop # isolating cache 75 nop 76 nop 77 nop 78 79 li t1, 512 # minimum cache size 80 li t2, 256*1024 # maximum cache size 81 822: sw t2, MIPS_KSEG0_START(t2) 83 bne t2, t1, 2b 84 srl t2, 1 # BDSLOT 85 lw v0, MIPS_KSEG0_START(zero) # magic! cache size is there 86 87 li t1, MIPS_KSEG0_START 88 addu t2, t1, v0 89 903: sw zero, 0(t1) # clear parity 91 sw zero, 4(t1) 92 sw zero, 8(t1) 93 sw zero, 12(t1) 94 sb zero, 0(t1) # invalidate 95 sb zero, 4(t1) 96 sb zero, 8(t1) 97 addu t1, 16 98 bne t1, t2, 3b 99 sb zero, -4(t1) # BDSLOT 100 101 # 4 cycles to pipeline to drain. 102 nop 103 nop 104 nop 105 nop 106 107 mtc0 v1, MIPS_COP_0_STATUS 108 nop 109 nop 110 nop 111 nop 112 113 j ra 114 nop 115END(r3k_size_cache) 116 117/* 118 * r3k_picache_size: 119 * 120 * Determine the size of the R3000 I-cache. 121 */ 122LEAF_NOPROFILE(r3k_picache_size) 123 li a0, MIPS1_ISOL_CACHES|MIPS1_SWAP_CACHES 124 j _C_LABEL(r3k_size_cache) 125 nop 126END(r3k_picache_size) 127 128/* 129 * r3k_pdcache_size: 130 * 131 * Determine the size of the R3000 D-cache. 132 */ 133LEAF_NOPROFILE(r3k_pdcache_size) 134 li a0, MIPS1_ISOL_CACHES 135 j _C_LABEL(r3k_size_cache) 136 nop 137END(r3k_pdcache_size) 138 139/* 140 * r3k_picache_do_inv: 141 * 142 * Invalidate a range from the R3000 I-cache. 143 * 144 * Arguments: a0 starting address 145 * a1 ending address 146 * 147 * Addresses must already be cache-line aligned. 148 */ 149LEAF(r3k_picache_do_inv) 150 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 151 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 152 153 la v1, 1f 154 or v1, MIPS_KSEG1_START # Run uncached. 155 j v1 156 nop 157 1581: 159 # Swap the caches (so we store to I$) and isolate them from memory. 160 li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES 161 mtc0 v1, MIPS_COP_0_STATUS 162 nop 163 nop 1641: 165 addu a0, a0, 4 166 bne a0, a1, 1b 167 sb zero, -4(a0) 168 169 # 4 cycles to wait for pipeline to drain. 170 171 nop 172 nop 173 174 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 175 nop 176 nop 177 j ra # Jumps back to cached address. 178 nop 179END(r3k_picache_do_inv) 180 181/* 182 * r3k_pdcache_do_inv: 183 * 184 * Invalidate a range from the R3000 D-cache. 185 * 186 * Arguments: a0 starting address 187 * a1 ending address 188 * 189 * Addresses must already be cache-line aligned. 190 */ 191LEAF(r3k_pdcache_do_inv) 192 mfc0 t0, MIPS_COP_0_STATUS # Save SR. 193 mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts. 194 nop 195 196 # Isolate the caches from memory. 197 li v1, MIPS_SR_ISOL_CACHES 198 mtc0 v1, MIPS_COP_0_STATUS 199 nop 200 nop 2011: 202 sb zero, 0(a0) 203 sb zero, 4(a0) 204 sb zero, 8(a0) 205 sb zero, 12(a0) 206 sb zero, 16(a0) 207 sb zero, 20(a0) 208 sb zero, 24(a0) 209 addu a0, 32 210 bltu a0, a1, 1b 211 sb zero, -4(a0) 212 213 # 4 cycles to wait for pipeline to drain. 214 215 nop 216 nop 217 218 mtc0 t0, MIPS_COP_0_STATUS # Restore SR. 219 nop 220 nop 221 j ra # Jumps back to cached address. 222 nop 223END(r3k_pdcache_do_inv) 224