1/* $NetBSD: aupci.c,v 1.12 2012/01/03 07:36:02 kiyohara Exp $ */
2
3/*-
4 * Copyright (c) 2006 Itronix Inc.
5 * All rights reserved.
6 *
7 * Written by Garrett D'Amore for Itronix Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. The name of Itronix Inc. may not be used to endorse
18 *    or promote products derived from this software without specific
19 *    prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include "opt_pci.h"
35#include "pci.h"
36
37#include <sys/cdefs.h>
38__KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.12 2012/01/03 07:36:02 kiyohara Exp $");
39
40#include <sys/types.h>
41#include <sys/param.h>
42#include <sys/time.h>
43#include <sys/systm.h>
44#include <sys/errno.h>
45#include <sys/device.h>
46#include <sys/malloc.h>
47#include <sys/extent.h>
48
49#include <uvm/uvm_extern.h>
50
51#include <sys/bus.h>
52#include <machine/cpu.h>
53#include <machine/pte.h>
54
55#include <dev/pci/pcivar.h>
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pciconf.h>
58
59#ifdef	PCI_NETBSD_CONFIGURE
60#include <mips/cache.h>
61#endif
62
63#include <mips/alchemy/include/au_himem_space.h>
64#include <mips/alchemy/include/aubusvar.h>
65#include <mips/alchemy/include/aureg.h>
66#include <mips/alchemy/include/auvar.h>
67
68#include <mips/alchemy/dev/aupcireg.h>
69#include <mips/alchemy/dev/aupcivar.h>
70
71struct aupci_softc {
72	device_t			sc_dev;
73	struct mips_pci_chipset		sc_pc;
74	struct mips_bus_space		sc_mem_space;
75	struct mips_bus_space		sc_io_space;
76	struct mips_bus_space		sc_cfg_space;
77
78	bus_space_tag_t			sc_memt;
79	bus_space_tag_t			sc_iot;
80	bus_space_tag_t			sc_cfgt;
81
82	bus_space_tag_t			sc_bust;
83
84	bus_space_handle_t		sc_bush;
85	paddr_t				sc_cfgbase;
86	paddr_t				sc_membase;
87	paddr_t				sc_iobase;
88
89	/* XXX: dma tag */
90};
91
92int		aupcimatch(device_t, struct cfdata *, void *);
93void		aupciattach(device_t, device_t, void *);
94
95#if NPCI > 0
96static void aupci_attach_hook(device_t, device_t, struct pcibus_attach_args *);
97static int aupci_bus_maxdevs(void *, int);
98static pcitag_t aupci_make_tag(void *, int, int, int);
99static void aupci_decompose_tag(void *, pcitag_t, int *, int *, int *);
100static pcireg_t aupci_conf_read(void *, pcitag_t, int);
101static void aupci_conf_write(void *, pcitag_t, int, pcireg_t);
102static const char *aupci_intr_string(void *, pci_intr_handle_t);
103static void aupci_conf_interrupt(void *, int, int, int, int, int *);
104static void *aupci_intr_establish(void *, pci_intr_handle_t, int,
105    int (*)(void *), void *);
106static void aupci_intr_disestablish(void *, void *);
107
108#ifdef	PCI_NETBSD_CONFIGURE
109static struct extent	*io_ex = NULL;
110static struct extent	*mem_ex = NULL;
111#endif	/* PCI_NETBSD_CONFIGURE */
112
113#define	PCI_CFG_READ	0
114#define	PCI_CFG_WRITE	1
115
116#endif	/* NPCI > 0 */
117
118CFATTACH_DECL_NEW(aupci, sizeof(struct aupci_softc),
119    aupcimatch, aupciattach, NULL, NULL);
120
121int aupci_found = 0;
122
123/*
124 * Physical PCI addresses are 36-bits long, so we need to have
125 * adequate storage space for them.
126 */
127#if NPCI > 0
128#if !defined(_MIPS_PADDR_T_64BIT) && !defined(_LP64)
129#error	"aupci requires 64 bit paddr_t!"
130#endif
131#endif
132
133int
134aupcimatch(device_t parent, struct cfdata *match, void *aux)
135{
136	struct aubus_attach_args *aa = (struct aubus_attach_args *)aux;
137
138	if (strcmp(aa->aa_name, "aupci") != 0)
139		return 0;
140
141	if (aupci_found)
142		return 0;
143
144	return 1;
145}
146
147void
148aupciattach(device_t parent, device_t self, void *aux)
149{
150	struct aupci_softc		*sc = device_private(self);
151	struct aubus_attach_args	*aa = (struct aubus_attach_args *)aux;
152	uint32_t			cfg;
153#if NPCI > 0
154	uint32_t			mbar, mask;
155	bus_addr_t			mstart;
156	struct pcibus_attach_args	pba;
157#endif
158
159	aupci_found = 1;
160
161	sc->sc_dev = self;
162	sc->sc_bust = aa->aa_st;
163	if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0,
164		&sc->sc_bush) != 0) {
165		aprint_error(": unable to map PCI registers\n");
166		return;
167	}
168
169#if NPCI > 0
170	/*
171	 * These physical addresses are locked in on the CPUs we have
172	 * seen.  Perhaps these should be passed in via locators, thru
173	 * the configuration file.
174	 */
175	sc->sc_cfgbase = PCI_CONFIG_BASE;
176	sc->sc_membase = PCI_MEM_BASE;
177	sc->sc_iobase = PCI_IO_BASE;
178#endif
179
180	/*
181	 * Configure byte swapping, as YAMON doesn't do it.  YAMON does take
182	 * care of most of the rest of the details (clocking, etc.), however.
183	 */
184#if _BYTE_ORDER == _BIG_ENDIAN
185	/*
186	 * N.B.: This still doesn't do the DMA thing properly.  I have
187	 * not yet figured out how to get DMA access to work properly
188	 * without having bytes swapped while the processor is in
189	 * big-endian mode.  I'm not even sure that the Alchemy part
190	 * can do it without swapping the bytes (which would be a
191	 * bummer, since then only parts which had hardware detection
192	 * and swapping support would work without special hacks in
193	 * their drivers.)
194	 */
195	cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
196	    AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN |
197	    AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA;
198#else
199	cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
200	    AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN;
201#endif
202	bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg);
203
204	cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS);
205
206	aprint_normal(": Alchemy Host-PCI Bridge, %sMHz\n",
207	    (cfg & PCI_STATUS_66MHZ_SUPPORT) ? "66" : "33");
208	aprint_naive("\n");
209
210#if NPCI > 0
211	/*
212	 * PCI configuration space.  Address in this bus are
213	 * orthogonal to other spaces.  We need to make the entire
214	 * 32-bit address space available.
215	 */
216	sc->sc_cfgt = &sc->sc_cfg_space;
217	au_himem_space_init(sc->sc_cfgt, "pcicfg", sc->sc_cfgbase,
218	    0x00000000, 0xffffffff, AU_HIMEM_SPACE_IO);
219
220	/*
221	 * Virtual PCI memory.  Configured so that we don't overlap
222	 * with PCI memory space.
223	 */
224	mask = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MWMASK);
225	mask >>= AUPCI_MWMASK_SHIFT;
226	mask <<= AUPCI_MWMASK_SHIFT;
227
228	mbar = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MBAR);
229	mstart = (mbar & mask) + (~mask + 1);
230
231	sc->sc_memt = &sc->sc_mem_space;
232	au_himem_space_init(sc->sc_memt, "pcimem", sc->sc_membase,
233	    mstart, 0xffffffff, AU_HIMEM_SPACE_LITTLE_ENDIAN);
234
235	/*
236	 * IO space.  Address in this bus are orthogonal to other spaces.
237	 * 16 MB should be plenty.  We don't start from zero to avoid
238	 * potential device bugs.
239	 */
240	sc->sc_iot = &sc->sc_io_space;
241	au_himem_space_init(sc->sc_iot, "pciio",
242	    sc->sc_iobase, AUPCI_IO_START, AUPCI_IO_END,
243	    AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO);
244
245	sc->sc_pc.pc_conf_v = sc;
246	sc->sc_pc.pc_attach_hook = aupci_attach_hook;
247	sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs;
248	sc->sc_pc.pc_make_tag = aupci_make_tag;
249	sc->sc_pc.pc_decompose_tag = aupci_decompose_tag;
250	sc->sc_pc.pc_conf_read = aupci_conf_read;
251	sc->sc_pc.pc_conf_write = aupci_conf_write;
252
253	sc->sc_pc.pc_intr_v = sc;
254	sc->sc_pc.pc_intr_map = aupci_intr_map;
255	sc->sc_pc.pc_intr_string = aupci_intr_string;
256	sc->sc_pc.pc_intr_establish = aupci_intr_establish;
257	sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish;
258	sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt;
259
260#ifdef PCI_NETBSD_CONFIGURE
261	mem_ex = extent_create("pcimem", mstart, 0xffffffff,
262	    NULL, 0, EX_WAITOK);
263
264	io_ex = extent_create("pciio", AUPCI_IO_START, AUPCI_IO_END,
265	    NULL, 0, EX_WAITOK);
266
267	pci_configure_bus(&sc->sc_pc,
268	    io_ex, mem_ex, NULL, 0, mips_cache_info.mci_dcache_align);
269	extent_destroy(mem_ex);
270	extent_destroy(io_ex);
271#endif
272
273	pba.pba_iot = sc->sc_iot;
274	pba.pba_memt = sc->sc_memt;
275	/* XXX: review dma tag logic */
276	pba.pba_dmat = aa->aa_dt;
277	pba.pba_dmat64 = NULL;
278	pba.pba_pc = &sc->sc_pc;
279	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
280	pba.pba_bus = 0;
281	pba.pba_bridgetag = NULL;
282
283	config_found_ia(self, "pcibus", &pba, pcibusprint);
284#endif	/* NPCI > 0 */
285}
286
287#if NPCI > 0
288
289void
290aupci_attach_hook(device_t parent, device_t self,
291    struct pcibus_attach_args *pba)
292{
293}
294
295int
296aupci_bus_maxdevs(void *v, int busno)
297{
298
299	return 32;
300}
301
302pcitag_t
303aupci_make_tag(void *v, int bus, int device, int function)
304{
305	pcitag_t		tag;
306
307	if (bus >= 256 || device >= 32 || function >= 8)
308		panic("aupci_make_tag: bad request");
309
310	tag = (bus << 16) | (device << 11) | (function << 8);
311
312	return tag;
313}
314
315void
316aupci_decompose_tag(void *v, pcitag_t tag, int *b, int *d, int *f)
317{
318
319	if (b != NULL)
320		*b = (tag >> 16) & 0xff;
321	if (d != NULL)
322		*d = (tag >> 11) & 0x1f;
323	if (f != NULL)
324		*f = (tag >> 8) & 0x07;
325}
326
327static inline bool
328aupci_conf_access(void *v, int dir, pcitag_t tag, int reg, pcireg_t *datap)
329{
330	struct aupci_softc	*sc = (struct aupci_softc *)v;
331	uint32_t		status;
332	int			s;
333	bus_addr_t		addr;
334	int			b, d, f;
335	bus_space_handle_t	h;
336
337	aupci_decompose_tag(v, tag, &b, &d, &f);
338	if (b) {
339		/* configuration type 1 */
340		addr = 0x80000000 | tag;
341	} else if (d > 19) {
342		/* device num too big for bus 0 */
343		return false;
344	} else {
345		addr = (0x800 << d) | (f << 8);
346	}
347
348	/* probing illegal target is OK, return an error indication */
349	if (addr == 0)
350		return false;
351
352	if (bus_space_map(sc->sc_cfgt, addr, 256, 0, &h) != 0)
353		return false;
354
355	s = splhigh();
356
357	if (dir == PCI_CFG_WRITE)
358		bus_space_write_4(sc->sc_cfgt, h, reg, *datap);
359	else
360		*datap = bus_space_read_4(sc->sc_cfgt, h, reg);
361
362	DELAY(2);
363
364	/* check for and clear master abort condition */
365	status = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG);
366	bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG,
367	    status & ~(AUPCI_CONFIG_EF));
368
369	splx(s);
370
371	bus_space_unmap(sc->sc_cfgt, h, 256);
372
373	/* if we got a PCI master abort, fail it */
374	if (status & AUPCI_CONFIG_EF)
375		return false;
376
377	return true;
378}
379
380pcireg_t
381aupci_conf_read(void *v, pcitag_t tag, int reg)
382{
383	pcireg_t		data;
384
385	if (aupci_conf_access(v, PCI_CFG_READ, tag, reg, &data) == false)
386		return 0xffffffff;
387
388	return (data);
389}
390
391void
392aupci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
393{
394
395	aupci_conf_access(v, PCI_CFG_WRITE, tag, reg, &data);
396}
397
398const char *
399aupci_intr_string(void *v, pci_intr_handle_t ih)
400{
401	static char	name[16];
402
403	sprintf(name, "irq %u", (unsigned)ih);
404	return (name);
405}
406
407void *
408aupci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
409    int (*handler)(void *), void *arg)
410{
411
412	return (au_intr_establish(ih, 0, ipl, IST_LEVEL_LOW, handler, arg));
413}
414
415void
416aupci_intr_disestablish(void *v, void *cookie)
417{
418
419	au_intr_disestablish(cookie);
420}
421
422void
423aupci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline)
424{
425	/*
426	 * We let the machdep_pci_intr_map take care of IRQ routing.
427	 * On some platforms the BIOS may have handled this properly,
428	 * on others it might not have.  For now we avoid clobbering
429	 * the settings establishsed by the BIOS, so that they will be
430	 * there if the platform logic is confident that it can rely
431	 * on them.
432	 */
433}
434
435#endif
436