1/* $NetBSD: fpu_explode.c,v 1.10 2009/03/14 21:04:11 dsl Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 41 */ 42 43/* 44 * FPU subroutines: `explode' the machine's `packed binary' format numbers 45 * into our internal format. 46 */ 47 48#include <sys/cdefs.h> 49__KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.10 2009/03/14 21:04:11 dsl Exp $"); 50 51#include <sys/types.h> 52#include <sys/systm.h> 53 54#include <machine/ieee.h> 55#include <machine/reg.h> 56 57#include "fpu_arith.h" 58#include "fpu_emulate.h" 59 60 61/* Conversion to internal format -- note asymmetry. */ 62static int fpu_itof(struct fpn *fp, u_int i); 63static int fpu_stof(struct fpn *fp, u_int i); 64static int fpu_dtof(struct fpn *fp, u_int i, u_int j); 65static int fpu_xtof(struct fpn *fp, u_int i, u_int j, u_int k); 66 67/* 68 * N.B.: in all of the following, we assume the FP format is 69 * 70 * --------------------------- 71 * | s | exponent | fraction | 72 * --------------------------- 73 * 74 * (which represents -1**s * 1.fraction * 2**exponent), so that the 75 * sign bit is way at the top (bit 31), the exponent is next, and 76 * then the remaining bits mark the fraction. A zero exponent means 77 * zero or denormalized (0.fraction rather than 1.fraction), and the 78 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 79 * 80 * Since the sign bit is always the topmost bit---this holds even for 81 * integers---we set that outside all the *tof functions. Each function 82 * returns the class code for the new number (but note that we use 83 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 84 */ 85 86/* 87 * int -> fpn. 88 */ 89static int 90fpu_itof(register struct fpn *fp, register u_int i) 91{ 92 93 if (i == 0) 94 return (FPC_ZERO); 95 /* 96 * The value FP_1 represents 2^FP_LG, so set the exponent 97 * there and let normalization fix it up. Convert negative 98 * numbers to sign-and-magnitude. Note that this relies on 99 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 100 */ 101 fp->fp_exp = FP_LG; 102 fp->fp_mant[0] = (int)i < 0 ? -i : i; 103 fp->fp_mant[1] = 0; 104 fp->fp_mant[2] = 0; 105 fpu_norm(fp); 106 return (FPC_NUM); 107} 108 109#define mask(nbits) ((1 << (nbits)) - 1) 110 111/* 112 * All external floating formats convert to internal in the same manner, 113 * as defined here. Note that only normals get an implied 1.0 inserted. 114 */ 115#define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 116 if (exp == 0) { \ 117 if (allfrac == 0) \ 118 return (FPC_ZERO); \ 119 fp->fp_exp = 1 - expbias; \ 120 fp->fp_mant[0] = f0; \ 121 fp->fp_mant[1] = f1; \ 122 fp->fp_mant[2] = f2; \ 123 fpu_norm(fp); \ 124 return (FPC_NUM); \ 125 } \ 126 if (exp == (2 * expbias + 1)) { \ 127 if (allfrac == 0) \ 128 return (FPC_INF); \ 129 fp->fp_mant[0] = f0; \ 130 fp->fp_mant[1] = f1; \ 131 fp->fp_mant[2] = f2; \ 132 return (FPC_QNAN); \ 133 } \ 134 fp->fp_exp = exp - expbias; \ 135 fp->fp_mant[0] = FP_1 | f0; \ 136 fp->fp_mant[1] = f1; \ 137 fp->fp_mant[2] = f2; \ 138 return (FPC_NUM) 139 140/* 141 * 32-bit single precision -> fpn. 142 * We assume a single occupies at most (64-FP_LG) bits in the internal 143 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 144 */ 145static int 146fpu_stof(register struct fpn *fp, register u_int i) 147{ 148 register int exp; 149 register u_int frac, f0, f1; 150#define SNG_SHIFT (SNG_FRACBITS - FP_LG) 151 152 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 153 frac = i & mask(SNG_FRACBITS); 154 f0 = frac >> SNG_SHIFT; 155 f1 = frac << (32 - SNG_SHIFT); 156 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 157} 158 159/* 160 * 64-bit double -> fpn. 161 * We assume this uses at most (96-FP_LG) bits. 162 */ 163static int 164fpu_dtof(register struct fpn *fp, register u_int i, register u_int j) 165{ 166 register int exp; 167 register u_int frac, f0, f1, f2; 168#define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 169 170 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 171 frac = i & mask(DBL_FRACBITS - 32); 172 f0 = frac >> DBL_SHIFT; 173 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 174 f2 = j << (32 - DBL_SHIFT); 175 frac |= j; 176 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 177} 178 179/* 180 * 96-bit extended -> fpn. 181 */ 182static int 183fpu_xtof(register struct fpn *fp, register u_int i, register u_int j, 184 register u_int k) 185{ 186 register int exp; 187 register u_int frac, f0, f1, f2; 188#define EXT_SHIFT (EXT_FRACBITS - 1 - 32 - FP_LG) 189 190 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 191 f0 = j >> EXT_SHIFT; 192 f1 = (j << (32 - EXT_SHIFT)) | (k >> EXT_SHIFT); 193 f2 = k << (32 - EXT_SHIFT); 194 frac = j | k; 195 196 /* m68k extended does not imply denormal by exp==0 */ 197 if (exp == 0) { 198 if (frac == 0) 199 return (FPC_ZERO); 200 fp->fp_exp = - EXT_EXP_BIAS; 201 fp->fp_mant[0] = f0; 202 fp->fp_mant[1] = f1; 203 fp->fp_mant[2] = f2; 204 fpu_norm(fp); 205 return (FPC_NUM); 206 } 207 if (exp == (2 * EXT_EXP_BIAS + 1)) { 208 if (frac == 0) 209 return (FPC_INF); 210 fp->fp_mant[0] = f0; 211 fp->fp_mant[1] = f1; 212 fp->fp_mant[2] = f2; 213 return (FPC_QNAN); 214 } 215 fp->fp_exp = exp - EXT_EXP_BIAS; 216 fp->fp_mant[0] = FP_1 | f0; 217 fp->fp_mant[1] = f1; 218 fp->fp_mant[2] = f2; 219 return (FPC_NUM); 220} 221 222/* 223 * Explode the contents of a memory operand. 224 */ 225void 226fpu_explode(register struct fpemu *fe, register struct fpn *fp, int type, 227 register u_int *space) 228{ 229 register u_int s; 230 231 s = space[0]; 232 fp->fp_sign = s >> 31; 233 fp->fp_sticky = 0; 234 switch (type) { 235 236 case FTYPE_BYT: 237 s >>= 8; 238 case FTYPE_WRD: 239 s >>= 16; 240 case FTYPE_LNG: 241 s = fpu_itof(fp, s); 242 break; 243 244 case FTYPE_SNG: 245 s = fpu_stof(fp, s); 246 break; 247 248 case FTYPE_DBL: 249 s = fpu_dtof(fp, s, space[1]); 250 break; 251 252 case FTYPE_EXT: 253 s = fpu_xtof(fp, s, space[1], space[2]); 254 break; 255 256 default: 257 panic("fpu_explode"); 258 } 259 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 260 /* 261 * Input is a signalling NaN. All operations that return 262 * an input NaN operand put it through a ``NaN conversion'', 263 * which basically just means ``turn on the quiet bit''. 264 * We do this here so that all NaNs internally look quiet 265 * (we can tell signalling ones by their class). 266 */ 267 fp->fp_mant[0] |= FP_QUIETBIT; 268 fe->fe_fpsr |= FPSR_SNAN; /* assert SNAN exception */ 269 s = FPC_SNAN; 270 } 271 fp->fp_class = s; 272} 273