1/* $NetBSD: hd64461pcmciareg.h,v 1.3 2005/12/18 21:47:10 uwe Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _HPCSH_DEV_HD64461PCMCIAREG_H_ 33#define _HPCSH_DEV_HD64461PCMCIAREG_H_ 34 35/* 36 * PCC0 SH7709 Area 6 (memory and I/O card) 37 */ 38 39/* PCC0 Interface Status Register (R) */ 40#define HD64461_PCC0ISR_REG8 0xb0002000 41#define HD64461_PCC0ISR_P0READY HD64461_PCCISR_READY 42#define HD64461_PCC0ISR_IREQ HD64461_PCCISR_READY 43#define HD64461_PCC0ISR_P0MWP HD64461_PCCISR_MWP 44#define HD64461_PCC0ISR_P0VS2 HD64461_PCCISR_VS2 45#define HD64461_PCC0ISR_P0VS1 HD64461_PCCISR_VS1 46#define HD64461_PCC0ISR_P0CD2 HD64461_PCCISR_CD2 47#define HD64461_PCC0ISR_P0CD1 HD64461_PCCISR_CD1 48#define HD64461_PCC0ISR_P0BVD2 HD64461_PCCISR_BVD2 49#define HD64461_PCC0ISR_SPKR0 HD64461_PCCISR_BVD2 50#define HD64461_PCC0ISR_P0BVD1 HD64461_PCCISR_BVD1 51#define HD64461_PCC0ISR_STSCHG0 HD64461_PCCISR_BVD1 52 53/* PCC0 General Contorol Register (R/W) */ 54#define HD64461_PCC0GCR_REG8 0xb0002002 55#define HD64461_PCC0GCR_P0DRVE HD64461_PCCGCR_DRVE 56#define HD64461_PCC0GCR_P0PCCR HD64461_PCCGCR_PCCR 57#define HD64461_PCC0GCR_P0PCCT HD64461_PCCGCR_PCCT 58#define HD64461_PCC0GCR_P0VCC0 HD64461_PCCGCR_VCC0 59#define HD64461_PCC0GCR_P0MMOD HD64461_PCCGCR_MMOD 60#define HD64461_PCC0GCR_P0MMOD_16M HD64461_PCCGCR_MMOD_16M 61#define HD64461_PCC0GCR_P0MMOD_32M HD64461_PCCGCR_MMOD_32M 62/* these bits meaning different for P0MMOD mode */ 63#define HD64461_PCC0GCR_P0PA25 HD64461_PCCGCR_PA25 64#define HD64461_PCC0GCR_P0PA24 HD64461_PCCGCR_PA24 65#define HD64461_PCC0GCR_P0REG HD64461_PCCGCR_PREG 66 67/* PCC0 Card Status Change Register (R/W) */ 68#define HD64461_PCC0CSCR_REG8 0xb0002004 69#define HD64461_PCC0CSCR_P0SCDI HD64461_PCCCSCR_SCDI 70#define HD64461_PCC0CSCR_P0IREQ 0x20 71#define HD64461_PCC0CSCR_P0SC 0x10 72#define HD64461_PCC0CSCR_P0CDC HD64461_PCCCSCR_CDC 73#define HD64461_PCC0CSCR_P0RC HD64461_PCCCSCR_RC 74#define HD64461_PCC0CSCR_P0BW HD64461_PCCCSCR_BW 75#define HD64461_PCC0CSCR_P0BD HD64461_PCCCSCR_BD 76 77/* PCC0 Card Status Change Interrupt Enable Register (R/W) */ 78#define HD64461_PCC0CSCIER_REG8 0xb0002006 79#define HD64461_PCC0CSCIER_P0CRE HD64461_PCCCSCIER_CRE 80 81#define HD64461_PCC0CSCIER_P0IREQE_MASK 0x60 82#define HD64461_PCC0CSCIER_P0IREQE_NONE 0x00 83#define HD64461_PCC0CSCIER_P0IREQE_LEVEL 0x20 84#define HD64461_PCC0CSCIER_P0IREQE_FEDGE 0x40 85#define HD64461_PCC0CSCIER_P0IREQE_REDGE 0x60 86 87#define HD64461_PCC0CSCIER_P0SCE 0x10 88#define HD64461_PCC0CSCIER_P0CDE HD64461_PCCCSCIER_CDE 89#define HD64461_PCC0CSCIER_P0RE HD64461_PCCCSCIER_RE 90#define HD64461_PCC0CSCIER_P0BWE HD64461_PCCCSCIER_BWE 91#define HD64461_PCC0CSCIER_P0BDE HD64461_PCCCSCIER_BDE 92 93/* PCC0 Software Control Register (R/W) */ 94#define HD64461_PCC0SCR_REG8 0xb0002008 95#define HD64461_PCC0SCR_P0VCC1 HD64461_PCCSCR_VCC1 96#define HD64461_PCC0SCR_P0SWP HD64461_PCCSCR_SWP 97 98/* 99 * PCC1 SH7709 Area 5 (memory card only) 100 */ 101/* PCC1 Interface Status Register (R) */ 102#define HD64461_PCC1ISR_REG8 0xb0002010 103#define HD64461_PCC1ISR_P1READY HD64461_PCCISR_READY 104#define HD64461_PCC1ISR_P1MWP HD64461_PCCISR_MWP 105#define HD64461_PCC1ISR_P1VS2 HD64461_PCCISR_VS2 106#define HD64461_PCC1ISR_P1VS1 HD64461_PCCISR_VS1 107#define HD64461_PCC1ISR_P1CD2 HD64461_PCCISR_CD2 108#define HD64461_PCC1ISR_P1CD1 HD64461_PCCISR_CD1 109#define HD64461_PCC1ISR_P1BVD2 HD64461_PCCISR_BVD2 110#define HD64461_PCC1ISR_P1BVD1 HD64461_PCCISR_BVD1 111 112/* PCC1 General Contorol Register (R/W) */ 113#define HD64461_PCC1GCR_REG8 0xb0002012 114#define HD64461_PCC1GCR_P1DRVE HD64461_PCCGCR_DRVE 115#define HD64461_PCC1GCR_P1PCCR HD64461_PCCGCR_PCCR 116#define HD64461_PCC1GCR_RESERVED HD64461_PCCGCR_PCCT 117#define HD64461_PCC1GCR_P1VCC0 HD64461_PCCGCR_VCC0 118#define HD64461_PCC1GCR_P1MMOD HD64461_PCCGCR_MMOD 119#define HD64461_PCC1GCR_P1MMOD_16M HD64461_PCCGCR_MMOD_16M 120#define HD64461_PCC1GCR_P1MMOD_32M HD64461_PCCGCR_MMOD_32M 121#define HD64461_PCC1GCR_P1PA25 HD64461_PCCGCR_PA25 122#define HD64461_PCC1GCR_P1PA24 HD64461_PCCGCR_PA24 123#define HD64461_PCC1GCR_P1REG HD64461_PCCGCR_PREG 124 125/* PCC1 Card Status Change Register (R/W) */ 126#define HD64461_PCC1CSCR_REG8 0xb0002014 127#define HD64461_PCC1CSCR_P1SCDI HD64461_PCCCSCR_SCDI 128#define HD64461_PCC1CSCR_P1CDC HD64461_PCCCSCR_CDC 129#define HD64461_PCC1CSCR_P1RC HD64461_PCCCSCR_RC 130#define HD64461_PCC1CSCR_P1BW HD64461_PCCCSCR_BW 131#define HD64461_PCC1CSCR_P1BD HD64461_PCCCSCR_BD 132 133/* PCC1 Card Status Change Interrupt Enable Register (R/W) */ 134#define HD64461_PCC1CSCIER_REG8 0xb0002016 135#define HD64461_PCC1CSCIER_P1CRE HD64461_PCCCSCIER_CRE 136#define HD64461_PCC1CSCIER_P1CDE HD64461_PCCCSCIER_CDE 137#define HD64461_PCC1CSCIER_P1RE HD64461_PCCCSCIER_RE 138#define HD64461_PCC1CSCIER_P1BWE HD64461_PCCCSCIER_BWE 139#define HD64461_PCC1CSCIER_P1BDE HD64461_PCCCSCIER_BDE 140 141/* PCC1 Software Control Register (R/W) */ 142#define HD64461_PCC1SCR_REG8 0xb0002018 143#define HD64461_PCC1SCR_P1VCC1 HD64461_PCCSCR_VCC1 144#define HD64461_PCC1SCR_P1SWP HD64461_PCCSCR_SWP 145 146/* 147 * General Control 148 */ 149/* PCC0 Output pins Control Register (R/W) */ 150#define HD64461_PCCP0OCR_REG8 0xb000202a 151#define HD64461_PCCP0OCR_P0DEPLUP 0x80 152#define HD64461_PCCP0OCR_P0AEPLUP 0x10 153 154/* PCC1 Output pins Control Register (R/W) */ 155#define HD64461_PCCP1OCR_REG8 0xb000202c 156#define HD64461_PCCP1OCR_P1RST8MA 0x08 157#define HD64461_PCCP1OCR_P1RST4MA 0x04 158#define HD64461_PCCP1OCR_P1RAS8MA 0x02 159#define HD64461_PCCP1OCR_P1RAS4MA 0x01 160 161/* PC Card General Control Register (R/W) */ 162#define HD64461_PCCPGCR_REG8 0xb000202e 163#define HD64461_PCCPGCR_PSSDIR 0x02 164#define HD64461_PCCPGCR_PSSRDWR 0x01 165 166/* 167 * common defines. 168 */ 169#define HD64461_PCC0_REGBASE HD64461_PCC0ISR_REG8 170#define HD64461_PCC1_REGBASE HD64461_PCC1ISR_REG8 171#define HD64461_PCC_ISR_OFS 0x0 172#define HD64461_PCC_GCR_OFS 0x2 173#define HD64461_PCC_CSCR_OFS 0x4 174#define HD64461_PCC_CSCIER_OFS 0x6 175#define HD64461_PCC_SCR_OFS 0x8 176 177#define HD64461_PCCISR(x) \ 178 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 179 HD64461_PCC_ISR_OFS) 180#define HD64461_PCCGCR(x) \ 181 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 182 HD64461_PCC_GCR_OFS) 183#define HD64461_PCCCSCR(x) \ 184 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 185 HD64461_PCC_CSCR_OFS) 186#define HD64461_PCCCSCIER(x) \ 187 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 188 HD64461_PCC_CSCIER_OFS) 189#define HD64461_PCCSCR(x) \ 190 (((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \ 191 HD64461_PCC_SCR_OFS) 192 193#define HD64461_PCCISR_READY 0x80 194#define HD64461_PCCISR_MWP 0x40 195#define HD64461_PCCISR_VS2 0x20 196#define HD64461_PCCISR_VS1 0x10 197#define HD64461_PCCISR_CD2 0x08 198#define HD64461_PCCISR_CD1 0x04 199#define HD64461_PCCISR_BVD2 0x02 200#define HD64461_PCCISR_BVD1 0x01 201 202#define HD64461_PCCGCR_DRVE 0x80 203#define HD64461_PCCGCR_PCCR 0x40 204#define HD64461_PCCGCR_PCCT 0x20 205#define HD64461_PCCGCR_VCC0 0x10 206#define HD64461_PCCGCR_MMOD 0x08 207#define HD64461_PCCGCR_MMOD_16M 0x08 208#define HD64461_PCCGCR_MMOD_32M 0x00 209#define HD64461_PCCGCR_PA25 0x04 210#define HD64461_PCCGCR_PA24 0x02 211#define HD64461_PCCGCR_PREG 0x01 212 213#define HD64461_PCCCSCR_SCDI 0x80 214#define HD64461_PCCCSCR_CDC 0x08 215#define HD64461_PCCCSCR_RC 0x04 216#define HD64461_PCCCSCR_BW 0x02 217#define HD64461_PCCCSCR_BD 0x01 218 219#define HD64461_PCCCSCIER_CRE 0x80 220#define HD64461_PCCCSCIER_CDE 0x08 221#define HD64461_PCCCSCIER_RE 0x04 222#define HD64461_PCCCSCIER_BWE 0x02 223#define HD64461_PCCCSCIER_BDE 0x01 224 225#define HD64461_PCCSCR_VCC1 0x02 226#define HD64461_PCCSCR_SWP 0x01 227 228#endif /* !_HPCSH_DEV_HD64461PCMCIAREG_H_ */ 229