1/* $NetBSD$ */ 2 3/*- 4 * Copyright (c) 2001 Enami Tsugutomo. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#define VRPCIU_BASE 0x0f000c00 /* vr4122 */ 30 31/* 32 * Master Memory/IO Address Window. 33 */ 34#define VRPCIU_MMAW1REG 0x0000 35#define VRPCIU_MMAW2REG 0x0004 36#define VRPCIU_MIOAWREG 0x0010 37 38#define VRPCIU_MAW_IBAMASK 0xff000000 /* Internal Bus Base Address */ 39#define VRPCIU_MAW_ADDRMASK(reg) \ 40 ((((reg) >> 13) & 0x7f) << 24) /* Address Mask */ 41#define VRPCIU_MAW_ADDR(reg) \ 42 (((reg) & VRPCIU_MAW_IBAMASK) & VRPCIU_MAW_ADDRMASK(reg)) 43#define VRPCIU_MAW_SIZE(reg) (~(VRPCIU_MAW_ADDRMASK(reg) | 0x80000000)) 44#define VRPCIU_MAW_WINEN (1 << 12) /* PCI access is enabled */ 45#define VRPCIU_MAW_PCIADDR(reg) (((reg) & 0xff) << 24) /* PCI Address */ 46#define VRPCIU_MAW(start, size) /* XXX */ 47 48/* 49 * Target Address Window. 50 */ 51#define VRPCIU_TAW1REG 0x0008 52#define VRPCIU_TAW2REG 0x000c 53#define VRPCIU_TAW_ADDRMASK(reg) \ 54 ((((reg) >> 13) & 0x7f) << 21) /* Address Mask */ 55#define VRPCIU_TAW_WINEN (1 << 12) /* PCI access is enabled */ 56#define VRPCIU_TAW_IBA(reg) (((reg) & 0x7ff) << 21) /* Internal Bus Address */ 57 58#define VRPCIU_CONFDREG 0x0014 59#define VRPCIU_CONFAREG 0x0018 60#define VRPCIU_MAILREG 0x001c 61#define VRPCIU_BUSERRADREG 0x0024 62#define VRPCIU_INTCNTSTAREG 0x0028 63#define VRPCIU_EXACCREG 0x002c 64#define VRPCIU_RECONTREG 0x0030 65#define VRPCIU_ENREG 0x0034 66#define VRPCIU_CLKSELREG 0x0038 67#define VRPCIU_TRDYVREG 0x003c 68#define VRPCIU_CLKRUNREG 0x0060 69 70#define VRPCIU_CONF_TYPE1 0x1 71#define VRPCIU_CONF_BASE (0x0f000d00 - VRPCIU_BASE) 72#define VRPCIU_CONF_MAILREG 0x10 73#define VRPCIU_CONF_MBA1REG 0x14 74#define VRPCIU_CONF_MBA2REG 0x18 75