1/* $NetBSD: tx39biureg.h,v 1.5 2005/12/11 12:17:34 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/* 32 * Toshiba TX3912/3922 BIU module (Bus Interface Unit) 33 */ 34 35/* 36 * System Address Map 37 */ 38#define TX39_SYSADDR_DRAMBANK0CS1 0x00000000 39#define TX39_SYSADDR_DRAMBANK1CS1 0x02000000 40#define TX39_SYSADDR_DRAMBANK0 0x04000000 41#define TX39_SYSADDR_DRAMBANK1 0x06000000 42#define TX39_SYSADDR_DRAMBANK_LEN 0x02000000 43 44#define TX39_SYSADDR_CARD1 0x08000000 45#define TX39_SYSADDR_CARD2 0x0C000000 46/* 64MByte */ 47#define TX39_SYSADDR_CARD_SIZE 0x04000000 48 49#define TX39_SYSADDR_CS1 0x10000000 50#define TX39_SYSADDR_CS2 0x10400000 51#define TX39_SYSADDR_CS3 0x10800000 52/* 4MByte */ 53#define TX39_SYSADDR_CS_SIZE 0x00400000 54 55#define TX39_SYSADDR_CONFIG_REG 0x10c00000 56#define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000 57 58#define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000 59#define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000 60#define TX39_SYSADDR_CS0 0x11000000 61#define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000 62#define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000 63#define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000 64#define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000 65#define TX39_SYSADDR_KUSEG_CS0 0x50000000 66#define TX39_SYSADDR_KUSEG_CS1 0x58000000 67#define TX39_SYSADDR_KUSEG_CS2 0x5c000000 68#define TX39_SYSADDR_KUSEG_CS3 0x60000000 69/* 64MByte */ 70#define TX39_SYSADDR_KUCS_SIZE 0x04000000 71 72#define TX39_SYSADDR_CARD1MEM 0x64000000 73#define TX39_SYSADDR_CARD2MEM 0x68000000 74#define TX39_SYSADDR_MCS0 0x6c000000 75#define TX39_SYSADDR_MCS1 0x70000000 76#ifdef TX391X 77#define TX39_SYSADDR_MCS2 0x74000000 78#define TX39_SYSADDR_MCS3 0x78000000 79#endif /* TX391X */ 80/* 64MByte */ 81#define TX39_SYSADDR_MCS_SIZE 0x04000000 82 83/* 84 * BIU module registers. 85 */ 86#define TX39_MEMCONFIG0_REG 0x00 87#define TX39_MEMCONFIG1_REG 0x04 88#define TX39_MEMCONFIG2_REG 0x08 89#define TX39_MEMCONFIG3_REG 0x0C 90#define TX39_MEMCONFIG4_REG 0x10 91#define TX39_MEMCONFIG5_REG 0x14 92#define TX39_MEMCONFIG6_REG 0x18 93#define TX39_MEMCONFIG7_REG 0x1C 94#define TX39_MEMCONFIG8_REG 0x20 95 96/* 97 * Memory Configuration 0 Register 98 */ 99/* R/W */ 100#define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000 101#define TX39_MEMCONFIG0_DISDQMINIT 0x20000000 102#define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000 103#define TX39_MEMCONFIG0_SHOWDINO 0x08000000 104#define TX39_MEMCONFIG0_ENRMAP2 0x04000000 105#define TX39_MEMCONFIG0_ENRMAP1 0x02000000 106#define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000 107#define TX39_MEMCONFIG0_ENCS3USER 0x00800000 108#define TX39_MEMCONFIG0_ENCS2USER 0x00400000 109#define TX39_MEMCONFIG0_ENCS1USER 0x00200000 110#define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000 111 112#define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18 113#define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3 114#define TX39_MEMCONFIG0_BANK1CONF(cr) \ 115 (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 116 TX39_MEMCONFIG0_BANK1CONF_MASK) 117#define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \ 118 ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \ 119 (TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT))) 120#define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16 121#define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3 122#define TX39_MEMCONFIG0_BANK0CONF(cr) \ 123 (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 124 TX39_MEMCONFIG0_BANK0CONF_MASK) 125#define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \ 126 ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \ 127 (TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT))) 128#define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3 129#define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2 130#define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1 131#define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0 132 133#define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14 134#define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3 135#define TX39_MEMCONFIG0_ROWSEL1(cr) \ 136 (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 137 TX39_MEMCONFIG0_ROWSEL1_MASK) 138#define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \ 139 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \ 140 (TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT))) 141#define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12 142#define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3 143#define TX39_MEMCONFIG0_ROWSEL0(cr) \ 144 (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 145 TX39_MEMCONFIG0_ROWSEL0_MASK) 146#define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \ 147 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \ 148 (TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT))) 149 150#define TX39_MEMCONFIG0_COLSEL1_SHIFT 8 151#define TX39_MEMCONFIG0_COLSEL1_MASK 0xf 152#define TX39_MEMCONFIG0_COLSEL1(cr) \ 153 (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 154 TX39_MEMCONFIG0_COLSEL1_MASK) 155#define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \ 156 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \ 157 (TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT))) 158#define TX39_MEMCONFIG0_COLSEL0_SHIFT 4 159#define TX39_MEMCONFIG0_COLSEL0_MASK 0xf 160#define TX39_MEMCONFIG0_COLSEL0(cr) \ 161 (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 162 TX39_MEMCONFIG0_COLSEL0_MASK) 163#define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \ 164 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \ 165 (TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT))) 166 167#define TX39_MEMCONFIG0_CS3SIZE 0x00000008 168#define TX39_MEMCONFIG0_CS2SIZE 0x00000004 169#define TX39_MEMCONFIG0_CS1SIZE 0x00000002 170#define TX39_MEMCONFIG0_CS0SIZE 0x00000001 171 172/* 173 * Memory Configuration 1 Register 174 */ 175#ifdef TX391X 176#define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28 177#define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf 178#define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \ 179 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 180 TX39_MEMCONFIG1_MCS3ACCVAL1_MASK) 181#define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \ 182 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \ 183 (TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << \ 184 TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT))) 185 186#define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24 187#define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf 188#define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \ 189 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 190 TX39_MEMCONFIG1_MCS3ACCVAL2_MASK) 191#define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \ 192 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \ 193 (TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << \ 194 TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT))) 195 196#define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20 197#define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf 198#define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \ 199 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 200 TX39_MEMCONFIG1_MCS2ACCVAL1_MASK) 201#define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \ 202 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \ 203 (TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << \ 204 TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT))) 205 206#define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16 207#define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf 208#define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \ 209 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 210 TX39_MEMCONFIG1_MCS2ACCVAL2_MASK) 211#define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \ 212 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \ 213 (TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << \ 214 TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT))) 215#endif /* TX391X */ 216#ifdef TX392X 217#define TX39_MEMCONFIG1_C48MPLLON 0x40000000 218#define TX39_MEMCONFIG1_ENMCS1BE 0x20000000 219#define TX39_MEMCONFIG1_ENMCS0BE 0x10000000 220#define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000 221#define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000 222#define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23 223#define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7 224#define TX39_MEMCONFIG1_BCLKDIV(cr) \ 225 (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 226 TX39_MEMCONFIG1_BCLKDIV_MASK) 227#define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \ 228 ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \ 229 (TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT))) 230#define TX39_MEMCONFIG1_ENBCLK 0x00400000 231#define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000 232#define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000 233#define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000 234#define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000 235#define TX39_MEMCONFIG1_MCS1_32 0x00020000 236#define TX39_MEMCONFIG1_MCS0_32 0x00010000 237#endif /* TX392X */ 238 239#define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12 240#define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf 241#define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \ 242 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 243 TX39_MEMCONFIG1_MCS1ACCVAL1_MASK) 244#define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \ 245 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \ 246 (TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << \ 247 TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT))) 248 249#define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8 250#define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf 251#define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \ 252 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 253 TX39_MEMCONFIG1_MCS1ACCVAL2_MASK) 254#define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \ 255 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \ 256 (TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << \ 257 TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT))) 258 259#define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4 260#define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf 261#define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \ 262 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 263 TX39_MEMCONFIG1_MCS0ACCVAL1_MASK) 264#define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \ 265 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \ 266 (TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << \ 267 TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT))) 268 269#define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0 270#define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf 271#define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \ 272 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 273 TX39_MEMCONFIG1_MCS0ACCVAL2_MASK) 274#define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \ 275 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \ 276 (TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << \ 277 TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT))) 278 279/* 280 * Memory Configuration 2 Register 281 */ 282/* Define access timing. not required yet */ 283#define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28 284#define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf 285#define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \ 286 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 287 TX39_MEMCONFIG2_CS3ACCVAL1_MASK) 288#define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \ 289 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \ 290 (TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT))) 291 292#define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24 293#define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf 294#define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \ 295 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 296 TX39_MEMCONFIG2_CS3ACCVAL2_MASK) 297#define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \ 298 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \ 299 (TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT))) 300 301#define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20 302#define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf 303#define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \ 304 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 305 TX39_MEMCONFIG2_CS2ACCVAL1_MASK) 306#define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \ 307 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \ 308 (TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT))) 309 310#define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16 311#define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf 312#define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \ 313 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 314 TX39_MEMCONFIG2_CS2ACCVAL2_MASK) 315#define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \ 316 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \ 317 (TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT))) 318 319#define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12 320#define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf 321#define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \ 322 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 323 TX39_MEMCONFIG2_CS1ACCVAL1_MASK) 324#define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \ 325 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \ 326 (TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT))) 327 328#define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8 329#define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf 330#define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \ 331 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 332 TX39_MEMCONFIG2_CS1ACCVAL2_MASK) 333#define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \ 334 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \ 335 (TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT))) 336 337#define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4 338#define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf 339#define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \ 340 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 341 TX39_MEMCONFIG2_CS0ACCVAL1_MASK) 342#define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \ 343 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \ 344 (TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT))) 345 346#define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0 347#define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf 348#define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \ 349 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 350 TX39_MEMCONFIG2_CS0ACCVAL2_MASK) 351#define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \ 352 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \ 353 (TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT))) 354 355/* 356 * Memory Configuration 3 Register 357 */ 358/* Define access timing, enable read page mode, PC-Card. */ 359#define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28 360#define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf 361#define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \ 362 (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 363 TX39_MEMCONFIG3_CARD2ACCVAL_MASK) 364#define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \ 365 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \ 366 (TX39_MEMCONFIG3_CARD2ACCVAL_MASK << \ 367 TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT))) 368 369#define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24 370#define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf 371#define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \ 372 (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 373 TX39_MEMCONFIG3_CARD1ACCVAL_MASK) 374#define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \ 375 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \ 376 (TX39_MEMCONFIG3_CARD1ACCVAL_MASK << \ 377 TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT))) 378 379#define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20 380#define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf 381#define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \ 382 (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 383 TX39_MEMCONFIG3_CARD2IOACCVAL_MASK) 384#define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \ 385 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \ 386 (TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << \ 387 TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT))) 388 389#define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16 390#define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf 391#define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \ 392 (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 393 TX39_MEMCONFIG3_CARD1IOACCVAL_MASK) 394#define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \ 395 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \ 396 (TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << \ 397 TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT))) 398#ifdef TX391X 399#define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000 400#define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000 401#define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000 402#define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000 403#endif /* TX391X */ 404#define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800 405#define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400 406#define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200 407#define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100 408#define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080 409#define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040 410#define TX39_MEMCONFIG3_CARD2IOEN 0x00000020 411#define TX39_MEMCONFIG3_CARD1IOEN 0x00000010 412#ifdef TX391X 413#define TX39_MEMCONFIG3_PORT8SEL 0x00000008 414#endif /* TX391X */ 415#ifdef TX392X 416#define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008 417#define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004 418#endif /* TX392X */ 419/* 420 * Memory Configuration 4 Register 421 */ 422/* DMA */ 423#define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000 424#define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000 425#define TX39_MEMCONFIG4_ENARB 0x20000000 426#define TX39_MEMCONFIG4_DISSNOOP 0x10000000 427#define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000 428#define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000 429#define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000 430#define TX39_MEMCONFIG4_ENWATCH 0x01000000 431 432/* 433 * WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz 434 */ 435#define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20 436#define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf 437#define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \ 438 (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 439 TX39_MEMCONFIG4_WATCHTIMEVAL_MASK) 440#define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \ 441 ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \ 442 (TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << \ 443 TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT))) 444 445 446#define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000 447#define TX39_MEMCONFIG4_ENRFSH1 0x00008000 448#define TX39_MEMCONFIG4_ENRFSH0 0x00004000 449 450#define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8 451#define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f 452#define TX39_MEMCONFIG4_RFSHVAL1(cr) \ 453 (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 454 TX39_MEMCONFIG4_RFSHVAL1_MASK) 455#define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \ 456 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \ 457 (TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT))) 458 459#define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0 460#define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f 461#define TX39_MEMCONFIG4_RFSHVAL0(cr) \ 462 (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 463 TX39_MEMCONFIG4_RFSHVAL0_MASK) 464#define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \ 465 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \ 466 (TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT))) 467 468/* 469 * Memory Configuration 5 Register 470 */ 471/* Address remap region 2 */ 472#define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9 473#define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff 474#define TX39_MEMCONFIG5_STARTVAL2(cr) \ 475 (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 476 TX39_MEMCONFIG5_STARTVAL2_MASK) 477#define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \ 478 ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \ 479 (TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT))) 480 481#define TX39_MEMCONFIG5_MASK2_SHIFT 0 482#define TX39_MEMCONFIG5_MASK2_MASK 0xf 483#define TX39_MEMCONFIG5_MASK2(cr) \ 484 (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \ 485 TX39_MEMCONFIG5_MASK2_MASK) 486#define TX39_MEMCONFIG5_MASK2_SET(cr, val) \ 487 ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \ 488 (TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT))) 489 490/* 491 * Memory Configuration 6 Register 492 */ 493/* Address remap region 1 */ 494#define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9 495#define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff 496#define TX39_MEMCONFIG6_STARTVAL1(cr) \ 497 (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 498 TX39_MEMCONFIG6_STARTVAL1_MASK) 499#define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \ 500 ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \ 501 (TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT))) 502 503#define TX39_MEMCONFIG6_MASK1_SHIFT 0 504#define TX39_MEMCONFIG6_MASK1_MASK 0xf 505#define TX39_MEMCONFIG6_MASK1(cr) \ 506 (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \ 507 TX39_MEMCONFIG6_MASK1_MASK) 508#define TX39_MEMCONFIG6_MASK1_SET(cr, val) \ 509 ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \ 510 (TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT))) 511 512/* 513 * Memory Configuration 7 Register 514 */ 515/* Address remap region 2 */ 516#define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9 517#define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff 518#define TX39_MEMCONFIG7_RMAPADD2(cr) \ 519 (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 520 TX39_MEMCONFIG7_RMAPADD2_MASK) 521#define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \ 522 ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \ 523 (TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT))) 524 525/* 526 * Memory Configuration 8 Register 527 */ 528/* Address remap region 1 */ 529#define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9 530#define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff 531#define TX39_MEMCONFIG8_RMAPADD1(cr) \ 532 (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 533 TX39_MEMCONFIG8_RMAPADD1_MASK) 534#define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \ 535 ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \ 536 (TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT))) 537