1/* $NetBSD$ */ 2/*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#include <sys/cdefs.h> 38 39__KERNEL_RCSID(0, "$NetSBD$"); 40 41#include "opt_altivec.h" 42#include "opt_ddb.h" 43#include "opt_mpc85xx.h" 44#include "opt_pci.h" 45#include "gpio.h" 46#include "pci.h" 47 48#define DDRC_PRIVATE 49#define GLOBAL_PRIVATE 50#define L2CACHE_PRIVATE 51#define _POWERPC_BUS_DMA_PRIVATE 52 53#include <sys/param.h> 54#include <sys/cpu.h> 55#include <sys/intr.h> 56#include <sys/msgbuf.h> 57#include <sys/tty.h> 58#include <sys/kcore.h> 59#include <sys/bitops.h> 60#include <sys/bus.h> 61#include <sys/extent.h> 62#include <sys/malloc.h> 63#include <sys/module.h> 64 65#include <uvm/uvm_extern.h> 66 67#include <prop/proplib.h> 68 69#include <dev/cons.h> 70 71#include <dev/ic/comreg.h> 72#include <dev/ic/comvar.h> 73 74#include <net/if.h> 75#include <net/if_media.h> 76#include <dev/mii/miivar.h> 77 78#include <powerpc/cpuset.h> 79#include <powerpc/pcb.h> 80#include <powerpc/spr.h> 81#include <powerpc/booke/spr.h> 82 83#include <powerpc/booke/cpuvar.h> 84#include <powerpc/booke/e500reg.h> 85#include <powerpc/booke/e500var.h> 86#include <powerpc/booke/etsecreg.h> 87#include <powerpc/booke/openpicreg.h> 88#ifdef CADMUS 89#include <evbppc/mpc85xx/cadmusreg.h> 90#endif 91#ifdef PIXIS 92#include <evbppc/mpc85xx/pixisreg.h> 93#endif 94 95struct uboot_bdinfo { 96 uint32_t bd_memstart; 97 uint32_t bd_memsize; 98 uint32_t bd_flashstart; 99 uint32_t bd_flashsize; 100/*10*/ uint32_t bd_flashoffset; 101 uint32_t bd_sramstart; 102 uint32_t bd_sramsize; 103 uint32_t bd_immrbase; 104/*20*/ uint32_t bd_bootflags; 105 uint32_t bd_ipaddr; 106 uint8_t bd_etheraddr[6]; 107 uint16_t bd_ethspeed; 108/*30*/ uint32_t bd_intfreq; 109 uint32_t bd_cpufreq; 110 uint32_t bd_baudrate; 111/*3c*/ uint8_t bd_etheraddr1[6]; 112/*42*/ uint8_t bd_etheraddr2[6]; 113/*48*/ uint8_t bd_etheraddr3[6]; 114/*4e*/ uint16_t bd_pad; 115}; 116 117/* 118 * booke kernels need to set module_machine to this for modules to work. 119 */ 120char module_machine_booke[] = "powerpc-booke"; 121 122void initppc(vaddr_t, vaddr_t, void *, void *, void *, void *); 123 124#define MEMREGIONS 4 125phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 126phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 127static u_int nmemr; 128 129#ifndef CONSFREQ 130# define CONSFREQ -1 /* inherit from firmware */ 131#endif 132#ifndef CONSPEED 133# define CONSPEED 115200 134#endif 135#ifndef CONMODE 136# define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 137#endif 138#ifndef CONSADDR 139# define CONSADDR DUART2_BASE 140#endif 141 142int comcnfreq = CONSFREQ; 143int comcnspeed = CONSPEED; 144tcflag_t comcnmode = CONMODE; 145bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 146 147#if NPCI > 0 148struct extent *pcimem_ex; 149struct extent *pciio_ex; 150#endif 151 152struct powerpc_bus_space gur_bst = { 153 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 154 .pbs_offset = GUR_BASE, 155 .pbs_limit = GUR_SIZE, 156}; 157 158struct powerpc_bus_space gur_le_bst = { 159 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162}; 163 164const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 165 166#if defined(SYS_CLK) 167static uint64_t e500_sys_clk = SYS_CLK; 168#endif 169#ifdef CADMUS 170static uint8_t cadmus_pci; 171static uint8_t cadmus_csr; 172#ifndef SYS_CLK 173static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 174#endif 175#elif defined(PIXIS) 176static const uint32_t pixis_spd_map[8] = { 177 [PX_SPD_33MHZ] = 33333333, 178 [PX_SPD_40MHZ] = 40000000, 179 [PX_SPD_50MHZ] = 50000000, 180 [PX_SPD_66MHZ] = 66666666, 181 [PX_SPD_83MHZ] = 83333333, 182 [PX_SPD_100MHZ] = 100000000, 183 [PX_SPD_133MHZ] = 133333333, 184 [PX_SPD_166MHZ] = 166666667, 185}; 186static uint8_t pixis_spd; 187#ifndef SYS_CLK 188static uint64_t e500_sys_clk; 189#endif 190#elif !defined(SYS_CLK) 191static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 192#endif 193 194static int e500_cngetc(dev_t); 195static void e500_cnputc(dev_t, int); 196 197static struct consdev e500_earlycons = { 198 .cn_getc = e500_cngetc, 199 .cn_putc = e500_cnputc, 200 .cn_pollc = nullcnpollc, 201}; 202 203/* 204 * List of port-specific devices to attach to the processor local bus. 205 */ 206static const struct cpunode_locators mpc8548_cpunode_locs[] = { 207 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 208 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 209#if defined(MPC8572) || defined(P2020) 210 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 211 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 212 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 213 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 214#endif 215 { "wdog" }, /* not a real device */ 216 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 217 1, { ISOURCE_DUART }, 218 1 + ilog2(DEVDISR_DUART) }, 219 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 220 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 221 1 + ilog2(DEVDISR_TSEC1) }, 222#if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) || defined(P2020) 223 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 224 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 225 1 + ilog2(DEVDISR_TSEC2), 226 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 227 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 228#endif 229#if defined(MPC8544) || defined(MPC8536) 230 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 231 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 232 1 + ilog2(DEVDISR_TSEC3), 233 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 234#endif 235#if defined(MPC8548) || defined(MPC8572) || defined(P2020) 236 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 237 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 238 1 + ilog2(DEVDISR_TSEC3), 239 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 240 SVR_P2020v2 >> 16 } }, 241#endif 242#if defined(MPC8548) || defined(MPC8572) 243 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 244 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 245 1 + ilog2(DEVDISR_TSEC4), 246 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 247#endif 248 { "diic", I2C1_BASE, 2*I2C_SIZE, 0, 249 1, { ISOURCE_I2C }, 250 1 + ilog2(DEVDISR_I2C) }, 251 /* MPC8572 doesn't have any GPIO */ 252 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 253 1, { ISOURCE_GPIO }, 254 0, 255 { 0xffff, SVR_MPC8572v1 >> 16 } }, 256 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 257 1, { ISOURCE_DDR }, 258 1 + ilog2(DEVDISR_DDR_15), 259 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 260#if defined(MPC8536) 261 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 262 1, { ISOURCE_DDR }, 263 1 + ilog2(DEVDISR_DDR_16), 264 { SVR_MPC8536v1 >> 16 } }, 265#endif 266#if defined(MPC8572) 267 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 268 1, { ISOURCE_DDR }, 269 1 + ilog2(DEVDISR_DDR_15), 270 { SVR_MPC8572v1 >> 16 } }, 271 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 272 1, { ISOURCE_DDR }, 273 1 + ilog2(DEVDISR_DDR2_14), 274 { SVR_MPC8572v1 >> 16 } }, 275#endif 276 { "lbc", LBC_BASE, LBC_SIZE, 0, 277 1, { ISOURCE_LBC }, 278 1 + ilog2(DEVDISR_LBC) }, 279#if defined(MPC8544) || defined(MPC8536) 280 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 281 1, { ISOURCE_PCIEX }, 282 1 + ilog2(DEVDISR_PCIE), 283 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 284 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 285 1, { ISOURCE_PCIEX2 }, 286 1 + ilog2(DEVDISR_PCIE2), 287 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 288 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 289 1, { ISOURCE_PCIEX3 }, 290 1 + ilog2(DEVDISR_PCIE3), 291 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 292 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 293 1, { ISOURCE_PCI1 }, 294 1 + ilog2(DEVDISR_PCI1), 295 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 296#endif 297#ifdef MPC8548 298 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 299 1, { ISOURCE_PCIEX }, 300 1 + ilog2(DEVDISR_PCIE), 301 { SVR_MPC8548v1 >> 16 }, }, 302 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 303 1, { ISOURCE_PCI1 }, 304 1 + ilog2(DEVDISR_PCI1), 305 { SVR_MPC8548v1 >> 16 }, }, 306 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 307 1, { ISOURCE_PCI2 }, 308 1 + ilog2(DEVDISR_PCI2), 309 { SVR_MPC8548v1 >> 16 }, }, 310#endif 311#if defined(MPC8572) || defined(P2020) 312 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 313 1, { ISOURCE_PCIEX }, 314 1 + ilog2(DEVDISR_PCIE), 315 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 316 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 317 1, { ISOURCE_PCIEX2 }, 318 1 + ilog2(DEVDISR_PCIE2), 319 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 320 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 321 1, { ISOURCE_PCIEX3_MPC8572 }, 322 1 + ilog2(DEVDISR_PCIE3), 323 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16 } }, 324#endif 325#if defined(MPC8536) || defined(P2020) 326 { "ehci", USB1_BASE, USB_SIZE, 1, 327 1, { ISOURCE_USB1 }, 328 1 + ilog2(DEVDISR_USB1), 329 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16 } }, 330#endif 331#ifdef MPC8536 332 { "ehci", USB2_BASE, USB_SIZE, 2, 333 1, { ISOURCE_USB2 }, 334 1 + ilog2(DEVDISR_USB2), 335 { SVR_MPC8536v1 >> 16 }, }, 336 { "ehci", USB3_BASE, USB_SIZE, 3, 337 1, { ISOURCE_USB3 }, 338 1 + ilog2(DEVDISR_USB3), 339 { SVR_MPC8536v1 >> 16 }, }, 340 { "sata", SATA1_BASE, SATA_SIZE, 1, 341 1, { ISOURCE_SATA1 }, 342 1 + ilog2(DEVDISR_SATA1), 343 { SVR_MPC8536v1 >> 16 }, }, 344 { "sata", SATA2_BASE, SATA_SIZE, 2, 345 1, { ISOURCE_SATA2 }, 346 1 + ilog2(DEVDISR_SATA2), 347 { SVR_MPC8536v1 >> 16 }, }, 348 { "spi", SPI_BASE, SPI_SIZE, 0, 349 1, { ISOURCE_SPI }, 350 1 + ilog2(DEVDISR_SPI_15), 351 { SVR_MPC8536v1 >> 16 }, }, 352 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 353 1, { ISOURCE_ESDHC }, 354 1 + ilog2(DEVDISR_ESDHC_12), 355 { SVR_MPC8536v1 >> 16 }, }, 356#endif 357#if defined(P2020) 358 { "spi", SPI_BASE, SPI_SIZE, 0, 359 1, { ISOURCE_SPI }, 360 1 + ilog2(DEVDISR_SPI_28), 361 { SVR_P2020v2 >> 16 }, }, 362 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 363 1, { ISOURCE_ESDHC }, 364 1 + ilog2(DEVDISR_ESDHC_10), 365 { SVR_P2020v2 >> 16 }, }, 366#endif 367 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 368 { NULL } 369}; 370 371static int 372e500_cngetc(dev_t dv) 373{ 374 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 375 376 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 377 return -1; 378 379 return com0addr[com_data] & 0xff; 380} 381 382static void 383e500_cnputc(dev_t dv, int c) 384{ 385 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 386 int timo = 150000; 387 388 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 389 ; 390 391 com0addr[com_data] = c; 392 __asm("mbar"); 393 394 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 395 ; 396} 397 398static void * 399gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 400{ 401 if (prefetchable) 402 return NULL; 403 if (pa < gur_bst.pbs_offset) 404 return NULL; 405 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 406 return NULL; 407 return (void *)pa; 408} 409 410static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 411 412static void 413e500_cpu_reset(void) 414{ 415 __asm volatile("sync"); 416 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 417 __asm volatile("msync;isync"); 418} 419 420static psize_t 421memprobe(vaddr_t endkernel) 422{ 423 phys_ram_seg_t *mr; 424 paddr_t boot_page = cpu_read_4(GUR_BPTR); 425 printf(" bptr=%"PRIxPADDR, boot_page); 426 if (boot_page & BPTR_EN) { 427 /* 428 * shift it to an address 429 */ 430 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 431 } else { 432 boot_page = ~(paddr_t)0; 433 } 434 435 /* 436 * First we need to find out how much physical memory we have. 437 * We could let our bootloader tell us, but it's almost as easy 438 * to ask the DDR memory controller. 439 */ 440 mr = physmemr; 441 for (u_int i = 0; i < 4; i++) { 442 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 443 if (v & CS_CONFIG_EN) { 444 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 445 if (v == 0) 446 continue; 447 mr->start = BNDS_SA_GET(v); 448 mr->size = BNDS_SIZE_GET(v); 449#ifdef MEMSIZE 450 if (mr->start >= MEMSIZE) 451 continue; 452 if (mr->start + mr->size > MEMSIZE) 453 mr->size = MEMSIZE - mr->start; 454#endif 455#if 0 456 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 457 mr - physmemr, mr->size, mr->start); 458#endif 459 mr++; 460 } 461 } 462 463 if (mr == physmemr) 464 panic("no memory configured!"); 465 466 /* 467 * Sort memory regions from low to high and coalesce adjacent regions 468 */ 469 u_int cnt = mr - physmemr; 470 if (cnt > 1) { 471 for (u_int i = 0; i < cnt - 1; i++) { 472 for (u_int j = i + 1; j < cnt; j++) { 473 if (physmemr[j].start < physmemr[i].start) { 474 phys_ram_seg_t tmp = physmemr[i]; 475 physmemr[i] = physmemr[j]; 476 physmemr[j] = tmp; 477 } 478 } 479 } 480 mr = physmemr; 481 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 482 if (mr->start + mr->size == mr[1].start) { 483 mr->size += mr[1].size; 484 for (u_int j = 1; i + j + 1 < cnt; j++) 485 mr[j] = mr[j+1]; 486 cnt--; 487 } 488 } 489 } else if (cnt == 0) { 490 panic("%s: no memory found", __func__); 491 } 492 493 /* 494 * Copy physical memory to available memory. 495 */ 496 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 497 498 /* 499 * Adjust available memory to skip kernel at start of memory. 500 */ 501 availmemr[0].size -= endkernel - availmemr[0].start; 502 availmemr[0].start = endkernel; 503 504 mr = availmemr; 505 for (u_int i = 0; i < cnt; i++, mr++) { 506 /* 507 * U-boot reserves a boot-page on multi-core chips. 508 * We need to make sure that we never disturb it. 509 */ 510 const paddr_t mr_end = mr->start + mr->size; 511 if (mr_end > boot_page && boot_page >= mr->start) { 512 /* 513 * Normally u-boot will put in at the end 514 * of memory. But in case it doesn't, deal 515 * with all possibilities. 516 */ 517 if (boot_page + PAGE_SIZE == mr_end) { 518 mr->size -= PAGE_SIZE; 519 } else if (boot_page == mr->start) { 520 mr->start += PAGE_SIZE; 521 mr->size -= PAGE_SIZE; 522 } else { 523 mr->size = boot_page - mr->start; 524 mr++; 525 for (u_int j = cnt; j > i + 1; j--) { 526 availmemr[j] = availmemr[j-1]; 527 } 528 cnt++; 529 mr->start = boot_page + PAGE_SIZE; 530 mr->size = mr_end - mr->start; 531 } 532 break; 533 } 534 } 535 536 /* 537 * Steal pages at the end of memory for the kernel message buffer. 538 */ 539 mr = availmemr + cnt - 1; 540 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 541 mr->size -= round_page(MSGBUFSIZE); 542 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 543 544 /* 545 * Calculate physmem. 546 */ 547 for (u_int i = 0; i < cnt; i++) 548 physmem += atop(physmemr[i].size); 549 550 nmemr = cnt; 551 return physmemr[cnt-1].start + physmemr[cnt-1].size; 552} 553 554void 555consinit(void) 556{ 557 static bool attached = false; 558 559 if (attached) 560 return; 561 attached = true; 562 563 if (comcnfreq == -1) { 564 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 565 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 566 comcnfreq = e500_sys_clk * plat_ratio; 567 printf(" comcnfreq=%u", comcnfreq); 568 } 569 570 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 571 COM_TYPE_NORMAL, comcnmode); 572} 573 574void 575cpu_probe_cache(void) 576{ 577 struct cpu_info * const ci = curcpu(); 578 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 579 580 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 581 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 582 583 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 584 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 585 586 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 587 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 588 } else { 589 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 590 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 591 } 592 593#ifdef DEBUG 594 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 595 if ((L1CSR_CE & l1csr0) == 0) 596 printf(" DC=off"); 597 598 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 599 if ((L1CSR_CE & l1csr1) == 0) 600 printf(" IC=off"); 601#endif 602} 603 604static uint16_t 605getsvr(void) 606{ 607 uint16_t svr = mfspr(SPR_SVR) >> 16; 608 609 svr &= ~0x8; /* clear security bit */ 610 switch (svr) { 611 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 612 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 613 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 614 default: return svr; 615 } 616} 617 618static const char * 619socname(uint32_t svr) 620{ 621 svr &= ~0x80000; /* clear security bit */ 622 switch (svr >> 8) { 623 case SVR_MPC8533 >> 8: return "MPC8533"; 624 case SVR_MPC8536v1 >> 8: return "MPC8536"; 625 case SVR_MPC8541v1 >> 8: return "MPC8541"; 626 case SVR_MPC8543v2 >> 8: return "MPC8543"; 627 case SVR_MPC8544v1 >> 8: return "MPC8544"; 628 case SVR_MPC8545v2 >> 8: return "MPC8545"; 629 case SVR_MPC8547v2 >> 8: return "MPC8547"; 630 case SVR_MPC8548v2 >> 8: return "MPC8548"; 631 case SVR_MPC8555v1 >> 8: return "MPC8555"; 632 case SVR_MPC8568v1 >> 8: return "MPC8568"; 633 case SVR_MPC8567v1 >> 8: return "MPC8567"; 634 case SVR_MPC8572v1 >> 8: return "MPC8572"; 635 case SVR_P2020v2 >> 8: return "P2020"; 636 case SVR_P2010v2 >> 8: return "P2010"; 637 default: 638 panic("%s: unknown SVR %#x", __func__, svr); 639 } 640} 641 642static void 643e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 644{ 645 static const char units[16] = "KKKKKMMMMMGGGGGT"; 646 647 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 648 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 649 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 650 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 651 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 652 653 aprint_normal_dev(self, "%s:", name); 654 655 aprint_normal(" %u", nentries); 656 if (TLBCFG_AVAIL_P(tlbcfg)) { 657 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 658 minsize, maxsize, units[maxsize_log4k]); 659 } else { 660 aprint_normal(" fixed-size (%uKB)", minsize); 661 } 662 if (assoc == 0 || assoc == nentries) 663 aprint_normal(" fully"); 664 else 665 aprint_normal(" %u-way set", assoc); 666 aprint_normal(" associative entries\n"); 667} 668 669static void 670cpu_print_info(struct cpu_info *ci) 671{ 672 uint64_t freq = board_info_get_number("processor-frequency"); 673 device_t self = ci->ci_dev; 674 675 char freqbuf[10]; 676 if (freq >= 999500000) { 677 const uint32_t freq32 = (freq + 500000) / 10000000; 678 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 679 freq32 / 100, freq32 % 100); 680 } else { 681 const uint32_t freq32 = (freq + 500000) / 1000000; 682 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 683 } 684 685 const uint32_t pvr = mfpvr(); 686 const uint32_t svr = mfspr(SPR_SVR); 687 const uint32_t pir = mfspr(SPR_PIR); 688 689 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 690 "ID %u%s\n", 691 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 692 (svr >> 4) & 15, svr & 15, 693 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 694 (pvr >> 4) & 15, pvr & 15, 695 pir, (pir == 0 ? " (Primary)" : "")); 696 697 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 698 aprint_normal_dev(self, 699 "%uKB/%uB %u-way L1 %s cache\n", 700 L1CFG_CSIZE_GET(l1cfg0) >> 10, 701 32 << L1CFG_CBSIZE_GET(l1cfg0), 702 L1CFG_CNWAY_GET(l1cfg0), 703 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 704 ? "data" : "unified"); 705 706 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 707 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 708 aprint_normal_dev(self, 709 "%uKB/%uB %u-way L1 %s cache\n", 710 L1CFG_CSIZE_GET(l1cfg1) >> 10, 711 32 << L1CFG_CBSIZE_GET(l1cfg1), 712 L1CFG_CNWAY_GET(l1cfg1), 713 "instruction"); 714 } 715 716 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 717 aprint_normal_dev(self, 718 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 719 MMUCFG_NTLBS_GET(mmucfg) + 1, 720 MMUCFG_NPIDS_GET(mmucfg), 721 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 722 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 723 724 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 725 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 726} 727 728#ifdef MULTIPROCESSOR 729static void 730e500_cpu_spinup(device_t self, struct cpu_info *ci) 731{ 732 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 733 struct pglist splist; 734 735 if (spinup_table_addr == 0) { 736 aprint_error_dev(self, "hatch failed (no spin-up table)"); 737 return; 738 } 739 740 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 741 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 742 const size_t id = cpu_index(ci); 743 volatile __cpuset_t * const hatchlings = &cpuset_info.cpus_hatched; 744 745 if (h->hatch_sp == 0) { 746 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 747 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 748 if (error) { 749 aprint_error_dev(self, 750 "unable to allocate hatch stack\n"); 751 return; 752 } 753 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 754 + PAGE_SIZE - CALLFRAMELEN; 755 } 756 757 758 for (size_t i = 1; e[i].entry_pir != 0; i++) { 759 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 760 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 761 if (e[i].entry_pir == ci->ci_cpuid) { 762 763 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 764 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 765 ci->ci_curpm = pmap_kernel(); 766 ci->ci_lasttb = cpu_info[0].ci_lasttb; 767 ci->ci_data.cpu_cc_freq = 768 cpu_info[0].ci_data.cpu_cc_freq; 769 770 h->hatch_self = self; 771 h->hatch_ci = ci; 772 h->hatch_running = -1; 773 h->hatch_pir = e[i].entry_pir; 774 h->hatch_hid0 = mfspr(SPR_HID0); 775 KASSERT(h->hatch_sp != 0); 776 /* 777 * Get new timebase. We don't want to deal with 778 * timebase crossing a 32-bit boundary so make sure 779 * that we have enough headroom to do the timebase 780 * synchronization. 781 */ 782#define TBSYNC_SLOP 2000 783 uint32_t tbl; 784 uint32_t tbu; 785 do { 786 tbu = mfspr(SPR_RTBU); 787 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 788 } while (tbl < TBSYNC_SLOP); 789 790 h->hatch_tbu = tbu; 791 h->hatch_tbl = tbl; 792 __asm("sync;isync"); 793 dcache_wbinv((vaddr_t)h, sizeof(*h)); 794 795#if 1 796 /* 797 * And here we go... 798 */ 799 e[i].entry_addr_lower = 800 (uint32_t)e500_spinup_trampoline; 801 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 802 __asm __volatile("sync;isync"); 803 __insn_barrier(); 804 805 for (u_int timo = 0; timo++ < 10000; ) { 806 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 807 if (e[i].entry_addr_lower == 3) { 808 printf( 809 "%s: cpu%u started in %u spins\n", 810 __func__, cpu_index(ci), timo); 811 break; 812 } 813 } 814 for (u_int timo = 0; timo++ < 10000; ) { 815 dcache_inv((vaddr_t)h, sizeof(*h)); 816 if (h->hatch_running == 0) { 817 printf( 818 "%s: cpu%u cracked in %u spins: (running=%d)\n", 819 __func__, cpu_index(ci), 820 timo, h->hatch_running); 821 break; 822 } 823 } 824 if (h->hatch_running == -1) { 825 aprint_error_dev(self, 826 "hatch failed (timeout): running=%d" 827 ", entry=%#x\n", 828 h->hatch_running, e[i].entry_addr_lower); 829 goto out; 830 } 831#endif 832 833 /* 834 * First then we do is to synchronize timebases. 835 * TBSYNC_SLOP*16 should be more than enough 836 * instructions. 837 */ 838 while (tbl != mftbl()) 839 continue; 840 h->hatch_running = 1; 841 dcache_wbinv((vaddr_t)h, sizeof(*h)); 842 __asm("sync;isync"); 843 __insn_barrier(); 844 845 for (u_int timo = 10000; timo-- > 0; ) { 846 dcache_inv((vaddr_t)h, sizeof(*h)); 847 if (h->hatch_running > 1) 848 break; 849 } 850 if (h->hatch_running == 1) { 851 printf( 852 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 853 __func__, 854 ((int64_t)tbu << 32) + tbl, 855 (int64_t) 856 (((uint64_t)h->hatch_tbu << 32) 857 + (uint64_t)h->hatch_tbl), 858 h->hatch_running); 859 goto out; 860 } 861 printf( 862 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 863 __func__, 864 (int64_t) 865 (((uint64_t)h->hatch_tbu << 32) 866 + (uint64_t)h->hatch_tbl), 867 h->hatch_running); 868 /* 869 * Now we wait for the hatching to complete. 10ms 870 * should be long enough. 871 */ 872 for (u_int timo = 10000; timo-- > 0; ) { 873 if (CPUSET_HAS_P(*hatchlings, id)) { 874 aprint_normal_dev(self, 875 "hatch successful (%u spins, " 876 "timebase adjusted by %"PRId64")\n", 877 10000 - timo, 878 (int64_t) 879 (((uint64_t)h->hatch_tbu << 32) 880 + (uint64_t)h->hatch_tbl)); 881 goto out; 882 } 883 DELAY(1); 884 } 885 886 aprint_error_dev(self, 887 "hatch failed (timeout): running=%u\n", 888 h->hatch_running); 889 goto out; 890 } 891 } 892 893 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 894 ci->ci_cpuid); 895out: 896 if (h->hatch_sp == 0) 897 uvm_pglistfree(&splist); 898} 899#endif 900 901void 902e500_cpu_hatch(struct cpu_info *ci) 903{ 904 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 905 906 /* 907 * Make sure interrupts are blocked. 908 */ 909 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 910 911 intr_cpu_hatch(ci); 912 913 cpu_print_info(ci); 914 915/* 916 */ 917} 918 919static void 920e500_cpu_attach(device_t self, u_int instance) 921{ 922 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 923 924 if (instance > 1) { 925#if defined(MULTIPROCESSOR) 926 ci->ci_idepth = -1; 927 self->dv_private = ci; 928 929 ci->ci_cpuid = instance - (instance > 0); 930 ci->ci_dev = self; 931 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 932 933 mi_cpu_attach(ci); 934 935 intr_cpu_attach(ci); 936 cpu_evcnt_attach(ci); 937 938 e500_cpu_spinup(self, ci); 939 return; 940#else 941 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 942 return; 943#endif 944 } 945 946 self->dv_private = ci; 947 948 ci->ci_cpuid = instance - (instance > 0); 949 ci->ci_dev = self; 950 951 intr_cpu_attach(ci); 952 cpu_evcnt_attach(ci); 953 954 KASSERT(ci == curcpu()); 955 intr_cpu_hatch(ci); 956 957 cpu_print_info(ci); 958} 959 960void 961e500_ipi_halt(void) 962{ 963 register_t msr, hid0; 964 965 msr = wrtee(0); 966 967 hid0 = mfspr(SPR_HID0); 968 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 969 mtspr(SPR_HID0, hid0); 970 971 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 972 mtmsr(msr); 973 for (;;); /* loop forever */ 974} 975 976 977static void 978calltozero(void) 979{ 980 panic("call to 0 from %p", __builtin_return_address(0)); 981} 982 983void 984initppc(vaddr_t startkernel, vaddr_t endkernel, 985 void *a0, void *a1, void *a2, void *a3) 986{ 987 struct cpu_info * const ci = curcpu(); 988 struct cpu_softc * const cpu = ci->ci_softc; 989 990 cn_tab = &e500_earlycons; 991 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 992 startkernel, endkernel, a0, a1, a2, a3); 993 994 /* 995 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 996 * DOZE is ok. 997 */ 998 const register_t hid0 = mfspr(SPR_HID0); 999 mtspr(SPR_HID0, 1000 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1001#ifdef CADMUS 1002 /* 1003 * Need to cache this from cadmus since we need to unmap cadmus since 1004 * it falls in the middle of kernel address space. 1005 */ 1006 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1007 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1008 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1009 printf(" cadmus_pci=%#x", cadmus_pci); 1010 printf(" cadmus_csr=%#x", cadmus_csr); 1011 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1012 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1013 e500_sys_clk *= 2; 1014 } 1015#endif 1016#ifdef PIXIS 1017 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1018 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1019 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1020#ifndef SYS_CLK 1021 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1022#else 1023 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1024#endif 1025#endif 1026 printf(" porpllsr=0x%08x", 1027 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1028 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1029 1030 /* 1031 * Make sure arguments are page aligned. 1032 */ 1033 startkernel = trunc_page(startkernel); 1034 endkernel = round_page(endkernel); 1035 1036 /* 1037 * Initialize the bus space tag used to access the 85xx general 1038 * utility registers. It doesn't need to be extent protected. 1039 * We know the GUR is mapped via a TLB1 entry so we add a limited 1040 * mapiodev which allows mappings in GUR space. 1041 */ 1042 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1043 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1044 bus_space_init(&gur_bst, NULL, NULL, 0); 1045 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1046 cpu->cpu_bst = &gur_bst; 1047 cpu->cpu_le_bst = &gur_le_bst; 1048 cpu->cpu_bsh = gur_bsh; 1049 1050 /* 1051 * Attach the console early, really early. 1052 */ 1053 consinit(); 1054 1055 /* 1056 * Reset the PIC to a known state. 1057 */ 1058 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1059 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1060 ; 1061#if 0 1062 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1063#endif 1064 printf(" openpic-reset(ctpr=%u)", 1065 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1066 1067 /* 1068 * fill in with an absolute branch to a routine that will panic. 1069 */ 1070 *(int *)0 = 0x48000002 | (int) calltozero; 1071 1072 /* 1073 * Get the cache sizes. 1074 */ 1075 cpu_probe_cache(); 1076 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1077 ci->ci_ci.dcache_size >> 10, 1078 ci->ci_ci.dcache_line_size, 1079 ci->ci_ci.icache_size >> 10, 1080 ci->ci_ci.icache_line_size); 1081 1082 /* 1083 * Now find out how much memory is attached 1084 */ 1085 pmemsize = memprobe(endkernel); 1086 cpu->cpu_highmem = pmemsize; 1087 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1088 1089 /* 1090 * Now we need cleanout the TLB of stuff that we don't need. 1091 */ 1092 e500_tlb_init(endkernel, pmemsize); 1093 printf(" e500_tlbinit(%#lx,%zuMB)", 1094 endkernel, (size_t) (pmemsize >> 20)); 1095 1096 /* 1097 * 1098 */ 1099 printf(" hid0=%#lx/%#lx", hid0, mfspr(SPR_HID0)); 1100 printf(" hid1=%#lx", mfspr(SPR_HID1)); 1101 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1102 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1103 1104 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1105 1106 /* 1107 * Initialize the message buffer. 1108 */ 1109 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1110 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1111 1112 /* 1113 * Initialize exception vectors and interrupts 1114 */ 1115 exception_init(&e500_intrsw); 1116 1117 printf(" exception_init=%p", &e500_intrsw); 1118 1119 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1120 1121 /* 1122 * Set the page size. 1123 */ 1124 uvm_setpagesize(); 1125 1126 /* 1127 * Initialize the pmap. 1128 */ 1129 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1130 1131 /* 1132 * Let's take all the indirect calls via our stubs and patch 1133 * them to be direct calls. 1134 */ 1135 cpu_fixup_stubs(); 1136 1137 /* 1138 * As a debug measure we can change the TLB entry that maps all of 1139 * memory to one that encompasses the 64KB with the kernel vectors. 1140 * All other pages will be soft faulted into the TLB as needed. 1141 */ 1142 e500_tlb_minimize(endkernel); 1143 1144 /* 1145 * Set some more MD helpers 1146 */ 1147 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1148 cpu_md_ops.md_device_register = e500_device_register; 1149 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1150 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1151#if NGPIO > 0 1152 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1153#endif 1154 1155 printf(" initppc done!\n"); 1156 1157 /* 1158 * Look for the Book-E modules in the right place. 1159 */ 1160 module_machine = module_machine_booke; 1161} 1162 1163#ifdef MPC8548 1164static const char * const mpc8548cds_extirq_names[] = { 1165 [0] = "pci inta", 1166 [1] = "pci intb", 1167 [2] = "pci intc", 1168 [3] = "pci intd", 1169 [4] = "irq4", 1170 [5] = "gige phy", 1171 [6] = "atm phy", 1172 [7] = "cpld", 1173 [8] = "irq8", 1174 [9] = "nvram", 1175 [10] = "debug", 1176 [11] = "pci2 inta", 1177}; 1178#endif 1179 1180static const char * const mpc85xx_extirq_names[] = { 1181 [0] = "extirq 0", 1182 [1] = "extirq 1", 1183 [2] = "extirq 2", 1184 [3] = "extirq 3", 1185 [4] = "extirq 4", 1186 [5] = "extirq 5", 1187 [6] = "extirq 6", 1188 [7] = "extirq 7", 1189 [8] = "extirq 8", 1190 [9] = "extirq 9", 1191 [10] = "extirq 10", 1192 [11] = "extirq 11", 1193}; 1194 1195static void 1196mpc85xx_extirq_setup(void) 1197{ 1198#ifdef MPC8548 1199 const char * const * names = mpc8548cds_extirq_names; 1200 const size_t n = __arraycount(mpc8548cds_extirq_names); 1201#else 1202 const char * const * names = mpc85xx_extirq_names; 1203 const size_t n = __arraycount(mpc85xx_extirq_names); 1204#endif 1205 prop_array_t extirqs = prop_array_create_with_capacity(n); 1206 for (u_int i = 0; i < n; i++) { 1207 prop_string_t ps = prop_string_create_cstring_nocopy(names[i]); 1208 prop_array_set(extirqs, i, ps); 1209 prop_object_release(ps); 1210 } 1211 board_info_add_object("external-irqs", extirqs); 1212 prop_object_release(extirqs); 1213} 1214 1215static void 1216mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1217{ 1218 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1219 KASSERT(pci_intmap != NULL); 1220 prop_number_t mask = prop_number_create_unsigned_integer(intmask); 1221 KASSERT(mask != NULL); 1222 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1223 prop_object_release(mask); 1224 prop_number_t pn_ist = prop_number_create_unsigned_integer(ist); 1225 KASSERT(pn_ist != NULL); 1226 prop_number_t pn_intr = prop_number_create_unsigned_integer(inta); 1227 KASSERT(pn_intr != NULL); 1228 prop_dictionary_t entry = prop_dictionary_create(); 1229 KASSERT(entry != NULL); 1230 prop_dictionary_set(entry, "interrupt", pn_intr); 1231 prop_dictionary_set(entry, "type", pn_ist); 1232 prop_dictionary_set(pci_intmap, "000000", entry); 1233 prop_object_release(pn_intr); 1234 prop_object_release(entry); 1235 va_list ap; 1236 va_start(ap, inta); 1237 u_int intrinc = __LOWEST_SET_BIT(intmask); 1238 for (u_int i = 0; i < intmask; i += intrinc) { 1239 char prop_name[12]; 1240 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1241 entry = prop_dictionary_create(); 1242 KASSERT(entry != NULL); 1243 pn_intr = prop_number_create_unsigned_integer(va_arg(ap, u_int)); 1244 KASSERT(pn_intr != NULL); 1245 prop_dictionary_set(entry, "interrupt", pn_intr); 1246 prop_dictionary_set(entry, "type", pn_ist); 1247 prop_dictionary_set(pci_intmap, prop_name, entry); 1248 prop_object_release(pn_intr); 1249 prop_object_release(entry); 1250 } 1251 va_end(ap); 1252 prop_object_release(pn_ist); 1253 board_info_add_object(name, pci_intmap); 1254 prop_object_release(pci_intmap); 1255} 1256 1257void 1258cpu_startup(void) 1259{ 1260 struct cpu_info * const ci = curcpu(); 1261 const uint16_t svr = getsvr(); 1262 1263 powersave = 0; /* we can do it but turn it on by default */ 1264 1265 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1266 1267 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1268 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1269 uint32_t e500_ratio = E500_RATIO_GET(v); 1270 1271 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1272 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1273 1274 ci->ci_khz = (cpu_freq + 500) / 1000; 1275 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1276 1277 board_info_add_number("my-id", svr); 1278 board_info_add_bool("pq3"); 1279 board_info_add_number("mem-size", pmemsize); 1280 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1281 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1282 uint32_t l2banks = l2siz >> 16; 1283#ifdef MPC85555 1284 if (svr == (MPC8555v1 >> 16)) { 1285 l2siz >>= 1; 1286 l2banks >>= 1; 1287 } 1288#endif 1289 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1290 if (boot_page & BPTR_EN) { 1291 bool found = false; 1292 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1293 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1294 * const bp = (void *)boot_page; 1295 bp <= dp; dp--) { 1296 if (*dp == boot_page) { 1297 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1298 spinup_table_addr = 1299 roundup2(spinup_table_addr, 32); 1300 board_info_add_number("mp-boot-page", 1301 boot_page); 1302 board_info_add_number("mp-spin-up-table", 1303 spinup_table_addr); 1304 printf("Found MP boot page @ %#"PRIxPADDR". " 1305 "Spin-up table @ %#"PRIxPTR"\n", 1306 boot_page, spinup_table_addr); 1307 found = true; 1308 break; 1309 } 1310 } 1311 if (!found) { 1312 printf("Found MP boot page @ %#"PRIxPADDR 1313 " with missing U-boot signature!\n", boot_page); 1314 board_info_add_number("mp-spin-up-table", 0); 1315 } 1316 } 1317 board_info_add_number("l2-cache-size", l2siz); 1318 board_info_add_number("l2-cache-line-size", 32); 1319 board_info_add_number("l2-cache-banks", l2banks); 1320 board_info_add_number("l2-cache-ways", 8); 1321 1322 board_info_add_number("processor-frequency", cpu_freq); 1323 board_info_add_number("bus-frequency", ccb_freq); 1324 board_info_add_number("pci-frequency", e500_sys_clk); 1325 board_info_add_number("timebase-frequency", ccb_freq / 8); 1326 1327#ifdef CADMUS 1328 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1329 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1330 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1331 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1332 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1333#else 1334 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1335 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1336 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1337 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1338#endif 1339 1340 uint64_t macstnaddr = 1341 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1342 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1343 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1344 1345#if NPCI > 0 && defined(PCI_MEMBASE) 1346 pcimem_ex = extent_create("pcimem", 1347 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1348 NULL, 0, EX_WAITOK); 1349#endif 1350#if NPCI > 0 && defined(PCI_IOBASE) 1351 pciio_ex = extent_create("pciio", 1352 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1353 NULL, 0, EX_WAITOK); 1354#endif 1355 mpc85xx_extirq_setup(); 1356 /* 1357 * PCI-Express virtual wire interrupts on combined with 1358 * External IRQ0/1/2/3. 1359 */ 1360 switch (svr) { 1361#if defined(MPC8548) 1362 case SVR_MPC8548v1 >> 16: 1363 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1364 IST_LEVEL, 0, 1, 2, 3); 1365 break; 1366#endif 1367#if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) || defined(P2020) 1368 case SVR_MPC8536v1 >> 16: 1369 case SVR_MPC8544v1 >> 16: 1370 case SVR_MPC8572v1 >> 16: 1371 case SVR_P2010v2 >> 16: 1372 case SVR_P2020v2 >> 16: 1373 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1374 0, 1, 2, 3); 1375 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1376 4, 5, 6, 7); 1377 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1378 8, 9, 10, 11); 1379 break; 1380#endif 1381 } 1382 switch (svr) { 1383#if defined(MPC8536) 1384 case SVR_MPC8536v1 >> 16: 1385 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1386 1, 2, 3, 4); 1387 break; 1388#endif 1389#if defined(MPC8544) 1390 case SVR_MPC8544v1 >> 16: 1391 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1392 0, 1, 2, 3); 1393 break; 1394#endif 1395#if defined(MPC8548) 1396 case SVR_MPC8548v1 >> 16: 1397 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1398 0, 1, 2, 3); 1399 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1400 11, 1, 2, 3); 1401 break; 1402#endif 1403 } 1404} 1405