1/*	$NetBSD: ifpgavar.h,v 1.5 2009/07/21 16:04:16 dyoung Exp $ */
2
3/*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 *    products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#ifndef _IFPGAVAR_H_
33#define _IFPGAVAR_H_
34
35#include <sys/bus.h>
36
37/* We statically map the UARTS at boot so that we can access the console
38   before we've probed for the IFPGA. */
39#define UART0_BOOT_BASE		0xfde00000
40#define UART1_BOOT_BASE		0xfdf00000
41
42#define IFPGA_UART0		0x06000000	/* Uart 0 */
43#define IFPGA_UART1		0x07000000	/* Uart 1 */
44
45typedef paddr_t ifpga_addr_t;
46
47struct ifpga_softc {
48	bus_space_tag_t		sc_iot;		/* Bus tag */
49	bus_space_handle_t	sc_sc_ioh;	/* System Controller handle */
50	bus_space_handle_t	sc_cm_ioh;	/* Core Module handle */
51	bus_space_handle_t	sc_tmr_ioh;	/* Timers handle */
52	bus_space_handle_t	sc_irq_ioh;	/* IRQ controller handle */
53
54	/* Clock variables.  */
55	int			sc_statclock_count;
56	int			sc_clock_count;
57	int			sc_clock_ticks_per_256us;
58	void *			sc_clockintr;
59	void *			sc_statclockintr;
60};
61
62#define cf_iobase			cf_loc[IFPGACF_OFFSET]
63#define cf_irq				cf_loc[IFPGACF_IRQ]
64
65#define IRQUNK		IFPGACF_IRQ_DEFAULT
66
67struct ifpga_attach_args {
68	char *ifa_name;			/* Device name */
69	bus_space_tag_t    ifa_iot;	/* Bus space tag for io */
70	bus_space_handle_t ifa_sc_ioh;	/* System controller handle */
71
72	ifpga_addr_t	   ifa_addr;	/* Address of device.  */
73	int		   ifa_irq;	/* IRQ to use.  */
74	/*
75	 * Other data extracted from the system should go here.  Eg UART clock
76	 * rates.
77	 */
78};
79
80/* There are roughly 32 interrupt sources.  */
81#define NIRQ		32
82struct intrhand {
83	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
84	int (*ih_func)(void *);		/* handler */
85	void *ih_arg;			/* arg for handler */
86	int ih_ipl;			/* IPL_* */
87	int ih_irq;			/* IRQ number */
88};
89
90#define IRQNAMESIZE	sizeof("tmr 0 hard")
91
92struct intrq {
93	TAILQ_HEAD(, intrhand) iq_list;	/* handler list */
94	struct evcnt iq_ev;		/* event counter */
95	int iq_mask;			/* IRQs to mask while handling */
96	int iq_levels;			/* IPL_*'s this IRQ has */
97	int iq_ist;			/* share type */
98};
99
100
101void ifpga_intr_init(void);
102void ifpga_intr_postinit(void);
103void *ifpga_intr_establish(int, int, int (*)(void *), void *);
104void ifpga_intr_disestablish(void *);
105
106void ifpga_create_io_bs_tag(struct bus_space *, void *);
107void ifpga_create_mem_bs_tag(struct bus_space *, void *);
108
109void ifpga_reset(void);
110
111#endif /* _IFPGAVAR_H */
112