1/*	$NetBSD: hdlgreg.h,v 1.2 2006/06/08 23:27:47 nonaka Exp $	*/
2
3/*-
4 * Copyright (C) 2005, 2006 NONAKA Kimihiro <nonaka@netbsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef _HDLGREG_H_
29#define	_HDLGREG_H_
30
31/*
32 * Memory map and register definitions for I-O DATA HDL-G
33 */
34
35/*
36 * The memory map of I/O-DATA HDL-G looks like so:
37 *
38 *           ------------------------------
39 *		Intel 80321 IOP Reserved
40 * FFFF E900 ------------------------------
41 *		Peripheral Memory Mapped
42 *		    Registers
43 * FFFF E000 ------------------------------
44 *		On-board devices
45 * FE80 0000 ------------------------------
46 *		SDRAM
47 * A000 0000 ------------------------------
48 *		Reserved
49 * 9100 0000 ------------------------------
50 * 		Flash
51 * 9080 0000 ------------------------------
52 *		Reserved
53 * 9002 0000 ------------------------------
54 *		ATU Outbound Transaction
55 *		    Windows
56 * 8000 0000 ------------------------------
57 *		ATU Outbound Direct
58 *		    Addressing Windows
59 * 0000 1000 ------------------------------
60 *		Initialization Boot Code
61 *		    from Flash
62 * 0000 0000 ------------------------------
63 */
64
65/*
66 * We allocate a page table for VA 0xfe400000 (4MB) and map the
67 * PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
68 */
69#define	HDLG_IOPXS_VBASE	0xfe400000UL
70#define	HDLG_IOW_VBASE		HDLG_IOPXS_VBASE
71#define	HDLG_80321_VBASE	(HDLG_IOW_VBASE + \
72				 VERDE_OUT_XLATE_IO_WIN_SIZE)
73
74/*
75 * The GIGALANDISK on-board devices are mapped VA==PA during bootstrap.
76 * Conveniently, the size of the on-board register space is 1 section
77 * mapping.
78 */
79#define	HDLG_OBIO_BASE	0xfe800000UL
80#define	HDLG_OBIO_SIZE	0x00100000UL	/* 1MB */
81
82#define	HDLG_UART1	0xfe800000UL	/* TI 16550 */
83#define	HDLG_PLD	0xfe8d0000UL	/* CPLD */
84
85/*
86 * CPLD
87 */
88#define	HDLG_LEDCTRL		(HDLG_PLD + 0x00)
89#define		LEDCTRL_STAT_GREEN	0x01
90#define		LEDCTRL_STAT_RED	0x02
91#define		LEDCTRL_USB1		0x04
92#define		LEDCTRL_USB2		0x08
93#define		LEDCTRL_USB3		0x10
94#define		LEDCTRL_USB4		0x20
95#define		LEDCTRL_HDD		0x40
96#define		LEDCTRL_BUZZER		0x80
97#define	HDLG_PWRLEDCTRL		(HDLG_PLD + 0x01)
98#define		PWRLEDCTRL_0		0x01
99#define		PWRLEDCTRL_1		0x02
100#define		PWRLEDCTRL_2		0x04
101#define		PWRLEDCTRL_3		0x08
102#define	HDLG_BTNSTAT		(HDLG_PLD + 0x02)
103#define		BTNSTAT_POWER		0x01
104#define		BTNSTAT_SELECT		0x02
105#define		BTNSTAT_COPY		0x04
106#define		BTNSTAT_REMOVE		0x08
107#define		BTNSTAT_RESET		0x10
108#define	HDLG_INTEN		(HDLG_PLD + 0x03)
109#define		INTEN_PWRSW		0x01
110#define		INTEN_BUTTON		0x02
111#define		INTEN_RTC		0x40
112#define	HDLG_PWRMNG		(HDLG_PLD + 0x04)
113#define		PWRMNG_POWOFF		0x01
114#define		PWRMNG_RESET		0x02
115#define	HDLG_FANCTRL		(HDLG_PLD + 0x06)
116#define		FANCTRL_OFF		0x00
117#define		FANCTRL_ON		0x01
118
119#define	hdlg_enable_pldintr(bit) \
120do { \
121	*(volatile uint8_t *)HDLG_INTEN |= (bit); \
122} while (/*CONSTCOND*/0)
123
124#define	hdlg_disable_pldintr(bit) \
125do { \
126	*(volatile uint8_t *)HDLG_INTEN &= ~(bit); \
127} while (/*CONSTCOND*/0)
128
129#endif /* _HDLGREG_H_ */
130