1/*	$NetBSD: zs.c,v 1.2 2008/03/29 19:15:34 tsutsui Exp $	*/
2
3/*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 */
38
39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.2 2008/03/29 19:15:34 tsutsui Exp $");
41
42#include "opt_ddb.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/conf.h>
47#include <sys/device.h>
48#include <sys/tty.h>
49#include <sys/intr.h>
50
51#include <dev/cons.h>
52#include <dev/ic/z8530reg.h>
53
54#include <machine/autoconf.h>
55#include <machine/z8530var.h>
56
57#include <cobalt/cobalt/console.h>
58
59#include "ioconf.h"
60
61/*
62 * Some warts needed by z8530tty.c -
63 * The default parity REALLY needs to be the same as the PROM uses,
64 * or you can not see messages done with printf during boot-up...
65 */
66int zs_def_cflag = (CREAD | CS8 | HUPCL);
67
68#define ZS_DEFSPEED	115200
69#define PCLK		(115200 * 96)	/*  11.0592MHz */
70
71#define ZS_DELAY()	delay(2)
72
73/* The layout of this is hardware-dependent (padding, order). */
74/* A/~B (Channel A/Channel B) pin is connected to DAdr0 */
75#define ZS_CHAN_A	0x01
76#define ZS_CHAN_B	0x00
77
78/* D/~C (Data/Control) pin is connected to DAdr1 */
79#define ZS_CSR		0x00		/* ctrl, status, and indirect access */
80#define ZS_DATA		0x02		/* data */
81
82
83/* Definition of the driver for autoconfig. */
84static int  zs_match(device_t, cfdata_t, void *);
85static void zs_attach(device_t, device_t, void *);
86static int  zs_print(void *, const char *name);
87
88CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
89    zs_match, zs_attach, NULL, NULL);
90
91static int zshard(void *);
92#if 0
93static int zs_get_speed(struct zs_chanstate *);
94#endif
95static int  zs_getc(void *);
96static void zs_putc(void *, int);
97
98/* console status from cninit */
99static struct zs_chanstate zs_conschan_store;
100static struct zs_chanstate *zs_conschan;
101static uint8_t *zs_cons;
102
103/* default speed for all channels */
104static int zs_defspeed = ZS_DEFSPEED;
105
106static uint8_t zs_init_reg[16] = {
107	0,					/* 0: CMD (reset, etc.) */
108	0,					/* 1: No interrupts yet. */
109	0,					/* 2: no IVECT */
110	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,		/* 3: RX params and ctrl */
111	ZSWR4_CLK_X16 | ZSWR4_ONESB,		/* 4: TX/RX misc params */
112	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,		/* 5: TX params and ctrl */
113	0,					/* 6: TXSYNC/SYNCLO */
114	0,					/* 7: RXSYNC/SYNCHI */
115	0,					/* 8: alias for data port */
116	ZSWR9_MASTER_IE,			/* 9: Master interrupt ctrl */
117	0,					/*10: Misc TX/RX ctrl */
118	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,	/*11: Clock Mode ctrl */
119	BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED),	/*12: BAUDLO */
120	0,					/*13: BAUDHI */
121	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, /*14: Misc ctrl */
122	ZSWR15_BREAK_IE,			/*15: Ext/Status intr ctrl */
123};
124
125/* register address offset for each channel */
126static const int chanoff[] = { ZS_CHAN_A, ZS_CHAN_B };
127
128
129static int
130zs_match(device_t parent, cfdata_t cf, void *aux)
131{
132	static int matched;
133
134	/* only one zs */
135	if (matched)
136		return 0;
137
138	/* only Qube 2700 could have Z85C30 serial */
139	if (cobalt_id != COBALT_ID_QUBE2700)
140		return 0;
141
142	if (!console_present)
143		return 0;
144
145	matched = 1;
146	return 1;
147}
148
149/*
150 * Attach a found zs.
151 */
152static void
153zs_attach(device_t parent, device_t self, void *aux)
154{
155	struct zsc_softc *zsc = device_private(self);
156	struct mainbus_attach_args *maa = aux;
157	struct zsc_attach_args zsc_args;
158	uint8_t *zs_base;
159	struct zs_chanstate *cs;
160	int s, channel;
161
162	zsc->zsc_dev = self;
163
164	/* XXX: MI z8530 doesn't use bus_space(9) yet */
165	zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr);
166
167	aprint_normal(": optional Z85C30 serial port\n");
168
169	/*
170	 * Initialize software state for each channel.
171	 */
172	for (channel = 0; channel < 2; channel++) {
173		zsc_args.channel = channel;
174		cs = &zsc->zsc_cs_store[channel];
175
176		zsc->zsc_cs[channel] = cs;
177
178		zs_init_reg[2] = 0;
179
180		if ((zs_base + chanoff[channel]) == zs_cons) {
181			memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
182			zs_conschan = cs;
183			zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
184		} else {
185			cs->cs_reg_csr  = zs_base + chanoff[channel] + ZS_CSR;
186			cs->cs_reg_data = zs_base + chanoff[channel] + ZS_DATA;
187			memcpy(cs->cs_creg, zs_init_reg, 16);
188			memcpy(cs->cs_preg, zs_init_reg, 16);
189			cs->cs_defspeed = zs_defspeed;
190			zsc_args.hwflags = 0;
191		}
192
193		zs_lock_init(cs);
194		cs->cs_defcflag = zs_def_cflag;
195
196		cs->cs_channel = channel;
197		cs->cs_private = NULL;
198		cs->cs_ops = &zsops_null;
199		cs->cs_brg_clk = PCLK / 16;
200
201		/* Make these correspond to cs_defcflag (-crtscts) */
202		cs->cs_rr0_dcd = ZSRR0_DCD;
203		cs->cs_rr0_cts = 0;
204		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
205		cs->cs_wr5_rts = 0;
206
207		/*
208		 * Clear the master interrupt enable.
209		 * The INTENA is common to both channels,
210		 * so just do it on the A channel.
211		 */
212		if (channel == 0) {
213			s = splhigh();
214			zs_write_reg(cs, 9, 0);
215			splx(s);
216		}
217
218		/*
219		 * Look for a child driver for this channel.
220		 * The child attach will setup the hardware.
221		 */
222		if (!config_found(self, (void *)&zsc_args, zs_print)) {
223			/* No sub-driver.  Just reset it. */
224			uint8_t reset = (channel == 0) ?
225			    ZSWR9_A_RESET : ZSWR9_B_RESET;
226			s = splhigh();
227			zs_write_reg(cs,  9, reset);
228			splx(s);
229		}
230	}
231
232	/*
233	 * Now safe to install interrupt handlers.
234	 */
235	icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc);
236	zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
237	    (void (*)(void *))zsc_intr_soft, zsc);
238
239	/*
240	 * Set the master interrupt enable and interrupt vector.
241	 * (common to both channels, do it on A)
242	 */
243	cs = zsc->zsc_cs[0];
244	s = splhigh();
245	/* interrupt vector */
246	zs_write_reg(cs, 2, 0);
247	/* master interrupt control (enable) */
248	zs_write_reg(cs, 9, zs_init_reg[9]);
249	splx(s);
250}
251
252static int
253zs_print(void *aux, const char *name)
254{
255	struct zsc_attach_args *args = aux;
256
257	if (name != NULL)
258		aprint_normal("%s: ", name);
259
260	if (args->channel != -1)
261		aprint_normal(" channel %d", args->channel);
262
263	return UNCONF;
264}
265
266static int
267zshard(void *arg)
268{
269	struct zsc_softc *zsc = arg;
270	int rval;
271
272	rval = zsc_intr_hard(zsc);
273
274#if 1
275	/* XXX: there is some race condition? */
276	if (rval)
277		while (zsc_intr_hard(zsc))
278			;
279#endif
280
281	/* We are at splzs here, so no need to lock. */
282	if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
283		softint_schedule(zsc->zsc_softintr_cookie);
284
285	return rval;
286}
287
288/*
289 * Compute the current baud rate given a ZS channel.
290 */
291#if 0
292static int
293zs_get_speed(struct zs_chanstate *cs)
294{
295	int tconst;
296
297	tconst =  zs_read_reg(cs, 12);
298	tconst |= zs_read_reg(cs, 13) << 8;
299	return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
300}
301#endif
302
303/*
304 * MD functions for setting the baud rate and control modes.
305 */
306int
307zs_set_speed(struct zs_chanstate *cs, int bps)
308{
309	int tconst, real_bps;
310
311	if (bps == 0)
312		return 0;
313
314#ifdef	DIAGNOSTIC
315	if (cs->cs_brg_clk == 0)
316		panic("zs_set_speed");
317#endif
318
319	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
320	if (tconst < 0)
321		return EINVAL;
322
323	/* Convert back to make sure we can do it. */
324	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
325
326	/* Allow ~4% tolerance here */
327	if (abs(real_bps - bps) >= bps * 4 / 100)
328		return EINVAL;
329
330	cs->cs_preg[12] = tconst;
331	cs->cs_preg[13] = tconst >> 8;
332
333	/* Caller will stuff the pending registers. */
334	return 0;
335}
336
337int
338zs_set_modes(struct zs_chanstate *cs, int cflag)
339{
340	int s;
341
342	/*
343	 * Output hardware flow control on the chip is horrendous:
344	 * if carrier detect drops, the receiver is disabled, and if
345	 * CTS drops, the transmitter is stoped IN MID CHARACTER!
346	 * Therefore, NEVER set the HFC bit, and instead use the
347	 * status interrupt to detect CTS changes.
348	 */
349	s = splzs();
350	cs->cs_rr0_pps = 0;
351	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
352		cs->cs_rr0_dcd = 0;
353		if ((cflag & MDMBUF) == 0)
354			cs->cs_rr0_pps = ZSRR0_DCD;
355	} else
356		cs->cs_rr0_dcd = ZSRR0_DCD;
357	if ((cflag & CRTSCTS) != 0) {
358		cs->cs_wr5_dtr = ZSWR5_DTR;
359		cs->cs_wr5_rts = ZSWR5_RTS;
360		cs->cs_rr0_cts = ZSRR0_CTS;
361	} else if ((cflag & MDMBUF) != 0) {
362		cs->cs_wr5_dtr = 0;
363		cs->cs_wr5_rts = ZSWR5_DTR;
364		cs->cs_rr0_cts = ZSRR0_DCD;
365	} else {
366		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
367		cs->cs_wr5_rts = 0;
368		cs->cs_rr0_cts = 0;
369	}
370	splx(s);
371
372	/* Caller will stuff the pending registers. */
373	return 0;
374}
375
376
377/*
378 * Read or write the chip with suitable delays.
379 */
380
381uint8_t
382zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
383{
384	uint8_t val;
385
386	*cs->cs_reg_csr = reg;
387	ZS_DELAY();
388	val = *cs->cs_reg_csr;
389	ZS_DELAY();
390	return val;
391}
392
393void
394zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
395{
396
397	*cs->cs_reg_csr = reg;
398	ZS_DELAY();
399	*cs->cs_reg_csr = val;
400	ZS_DELAY();
401}
402
403uint8_t
404zs_read_csr(struct zs_chanstate *cs)
405{
406	uint8_t val;
407
408	val = *cs->cs_reg_csr;
409	ZS_DELAY();
410	return val;
411}
412
413void
414zs_write_csr(struct zs_chanstate *cs, uint8_t val)
415{
416
417	*cs->cs_reg_csr = val;
418	ZS_DELAY();
419}
420
421uint8_t
422zs_read_data(struct zs_chanstate *cs)
423{
424	uint8_t val;
425
426	val = *cs->cs_reg_data;
427	ZS_DELAY();
428	return val;
429}
430
431void
432zs_write_data(struct zs_chanstate *cs, uint8_t val)
433{
434
435	*cs->cs_reg_data = val;
436	ZS_DELAY();
437}
438
439void
440zs_abort(struct zs_chanstate *cs)
441{
442
443#ifdef DDB
444	Debugger();
445#endif
446}
447
448/*
449 * Polled input char.
450 */
451int
452zs_getc(void *arg)
453{
454	struct zs_chanstate *cs = arg;
455	int s, c;
456	uint8_t rr0;
457
458	s = splhigh();
459	/* Wait for a character to arrive. */
460	do {
461		rr0 = *cs->cs_reg_csr;
462		ZS_DELAY();
463	} while ((rr0 & ZSRR0_RX_READY) == 0);
464
465	c = *cs->cs_reg_data;
466	ZS_DELAY();
467	splx(s);
468
469	return c;
470}
471
472/*
473 * Polled output char.
474 */
475void
476zs_putc(void *arg, int c)
477{
478	struct zs_chanstate *cs = arg;
479	int s;
480	uint8_t rr0;
481
482	s = splhigh();
483	/* Wait for transmitter to become ready. */
484	do {
485		rr0 = *cs->cs_reg_csr;
486		ZS_DELAY();
487	} while ((rr0 & ZSRR0_TX_READY) == 0);
488
489	*cs->cs_reg_data = c;
490	ZS_DELAY();
491	splx(s);
492}
493
494void
495zscnprobe(struct consdev *cn)
496{
497
498	cn->cn_pri = (console_present != 0 && cobalt_id == COBALT_ID_QUBE2700)
499	    ? CN_NORMAL : CN_DEAD;
500}
501
502void
503zscninit(struct consdev *cn)
504{
505	struct zs_chanstate *cs;
506
507	extern const struct cdevsw zstty_cdevsw;
508
509	cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
510
511	zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
512
513	zs_conschan = cs = &zs_conschan_store;
514
515	/* Setup temporary chanstate. */
516	cs->cs_reg_csr  = zs_cons + ZS_CSR;
517	cs->cs_reg_data = zs_cons + ZS_DATA;
518
519	/* Initialize the pending registers. */
520	memcpy(cs->cs_preg, zs_init_reg, 16);
521	cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
522
523	cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
524	cs->cs_preg[13] = 0;
525	cs->cs_defspeed = ZS_DEFSPEED;
526
527	/* Clear the master interrupt enable. */
528	zs_write_reg(cs, 9, 0);
529
530	/* Reset the whole SCC chip. */
531	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
532
533	/* Copy "pending" to "current" and H/W */
534	zs_loadchannelregs(cs);
535}
536
537int
538zscngetc(dev_t dev)
539{
540
541	return zs_getc((void *)zs_conschan);
542}
543
544void
545zscnputc(dev_t dev, int c)
546{
547
548	zs_putc((void *)zs_conschan, c);
549}
550