1/*	$NetBSD: i80321_pci.c,v 1.11 2012/01/27 18:52:51 para Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for i80321 I/O Processor chip.
40 */
41
42#include <sys/cdefs.h>
43__KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.11 2012/01/27 18:52:51 para Exp $");
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/device.h>
48#include <sys/extent.h>
49#include <sys/malloc.h>
50
51#include <uvm/uvm_extern.h>
52
53#include <sys/bus.h>
54
55#include <arm/xscale/i80321reg.h>
56#include <arm/xscale/i80321var.h>
57
58#include <dev/pci/ppbreg.h>
59#include <dev/pci/pciconf.h>
60
61#include "opt_pci.h"
62#include "opt_i80321.h"
63#include "pci.h"
64
65void		i80321_pci_attach_hook(struct device *, struct device *,
66		    struct pcibus_attach_args *);
67int		i80321_pci_bus_maxdevs(void *, int);
68pcitag_t	i80321_pci_make_tag(void *, int, int, int);
69void		i80321_pci_decompose_tag(void *, pcitag_t, int *, int *,
70		    int *);
71pcireg_t	i80321_pci_conf_read(void *, pcitag_t, int);
72void		i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t);
73
74#define	PCI_CONF_LOCK(s)	(s) = disable_interrupts(I32_bit)
75#define	PCI_CONF_UNLOCK(s)	restore_interrupts((s))
76
77void
78i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
79{
80#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
81	struct i80321_softc *sc = cookie;
82	struct extent *ioext, *memext;
83	uint32_t busno;
84#endif
85
86	pc->pc_conf_v = cookie;
87	pc->pc_attach_hook = i80321_pci_attach_hook;
88	pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs;
89	pc->pc_make_tag = i80321_pci_make_tag;
90	pc->pc_decompose_tag = i80321_pci_decompose_tag;
91	pc->pc_conf_read = i80321_pci_conf_read;
92	pc->pc_conf_write = i80321_pci_conf_write;
93
94#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
95	/*
96	 * Configure the PCI bus.
97	 *
98	 * XXX We need to revisit this.  We only configure the Secondary
99	 * bus (and its children).  The bus configure code needs changes
100	 * to support how the busses are arranged on this chip.  We also
101	 * need to only configure devices in the private device space on
102	 * the Secondary bus.
103	 */
104
105	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
106	busno = PCIXSR_BUSNO(busno);
107	if (busno == 0xff)
108		busno = 0;
109
110	ioext  = extent_create("pciio",
111	    sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
112	    sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1,
113	    NULL, 0, EX_NOWAIT);
114
115#ifdef I80321_USE_DIRECT_WIN
116	memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
117	    VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1,
118	    NULL, 0, EX_NOWAIT);
119#else
120	memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo,
121	    sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1,
122	    NULL, 0, EX_NOWAIT);
123#endif
124
125	aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
126	pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align);
127
128	extent_destroy(ioext);
129	extent_destroy(memext);
130#endif
131}
132
133void
134pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
135{
136}
137
138void
139i80321_pci_attach_hook(struct device *parent, struct device *self,
140    struct pcibus_attach_args *pba)
141{
142
143	/* Nothing to do. */
144}
145
146int
147i80321_pci_bus_maxdevs(void *v, int busno)
148{
149
150	return (32);
151}
152
153pcitag_t
154i80321_pci_make_tag(void *v, int b, int d, int f)
155{
156
157	return ((b << 16) | (d << 11) | (f << 8));
158}
159
160void
161i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
162{
163
164	if (bp != NULL)
165		*bp = (tag >> 16) & 0xff;
166	if (dp != NULL)
167		*dp = (tag >> 11) & 0x1f;
168	if (fp != NULL)
169		*fp = (tag >> 8) & 0x7;
170}
171
172struct pciconf_state {
173	uint32_t ps_addr_val;
174
175	int ps_b, ps_d, ps_f;
176};
177
178static int
179i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset,
180    struct pciconf_state *ps)
181{
182	uint32_t busno;
183
184	i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
185
186	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
187	busno = PCIXSR_BUSNO(busno);
188	if (busno == 0xff)
189		busno = 0;
190
191	/*
192	 * If the bus # is the same as our own, then use Type 0 cycles,
193	 * else use Type 1.
194	 *
195	 * XXX We should filter out all non-private devices here!
196	 * XXX How does private space interact with PCI-PCI bridges?
197	 */
198	if (ps->ps_b == busno) {
199		if (ps->ps_d > (31 - 16))
200			return (1);
201		/*
202		 * NOTE: PCI-X requires that that devices updated their
203		 * PCIXSR on every config write with the device number
204		 * specified in AD[15:11].  If we don't set this field,
205		 * each device could end of thinking it is at device 0,
206		 * which can cause a number of problems.  Doing this
207		 * unconditionally should be OK when only PCI devices
208		 * are present.
209		 */
210		ps->ps_addr_val = (1U << (ps->ps_d + 16)) |
211		    (ps->ps_d << 11) | (ps->ps_f << 8) | offset;
212	} else {
213		/* The tag is already in the correct format. */
214		ps->ps_addr_val = tag | offset | 1;
215	}
216
217	return (0);
218}
219
220pcireg_t
221i80321_pci_conf_read(void *v, pcitag_t tag, int offset)
222{
223	struct i80321_softc *sc = v;
224	struct pciconf_state ps;
225	vaddr_t va;
226	uint32_t isr;
227	pcireg_t rv;
228	u_int s;
229
230	if (i80321_pci_conf_setup(sc, tag, offset, &ps))
231		return ((pcireg_t) -1);
232
233	PCI_CONF_LOCK(s);
234
235	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
236	    ps.ps_addr_val);
237
238	va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
239	if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) {
240		isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
241		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
242		    isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
243			   ATUISR_PTAT|ATUISR_PMPE));
244#if 0
245		printf("conf_read: %d/%d/%d bad address\n",
246		    ps.ps_b, ps.ps_d, ps.ps_f);
247#endif
248		rv = (pcireg_t) -1;
249	}
250
251	PCI_CONF_UNLOCK(s);
252
253	return (rv);
254}
255
256void
257i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
258{
259	struct i80321_softc *sc = v;
260	struct pciconf_state ps;
261	u_int s;
262
263	if (i80321_pci_conf_setup(sc, tag, offset, &ps))
264		return;
265
266	PCI_CONF_LOCK(s);
267
268	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
269	    ps.ps_addr_val);
270	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val);
271
272	PCI_CONF_UNLOCK(s);
273}
274