1/* 2 * adapted/extracted from omap_wdt.c 3 * 4 * Copyright (c) 2007 Microsoft 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Microsoft 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#ifndef _OMAP_WDTREG_H 33#define _OMAP_WDTREG_H 34 35#define PTV 1 /* prescaler ratio: clock is divided by 2 */ 36#define PRE 1 /* enable divided input clock */ 37#define TCLK 32768 /* timer clock period in normal mode */ 38 39#define WIDR 0x00 /* watchdog ID reg offset */ 40#define WD_REV 0xff /* WIDR rev field mask */ 41 42#define WD_SYSCONFIG 0x10 /* WD System Configuration register */ 43#define WD_SYSCONFIG_AUTOIDLE 0x0 /* interface clock autogating */ 44 45#define WCLR 0x24 /* watchdog control register */ 46#define WCLR_PRE(PRE) ((PRE & 0x1)<<5) 47#define WCLR_PTV(PTV) ((PTV & 0x7)<<2) 48 49#define WCRR 0x28 /* watchdog counter register */ 50#define WLDR 0x2c /* watchdog load register */ 51#define WTGR 0x30 /* watchdog trigger register */ 52 53#define WWPS 0x34 /* watchdog write pending register */ 54#define W_PEND_WSPR (1<<4) 55#define W_PEND_WTGR (1<<3) 56#define W_PEND_WLDR (1<<2) 57#define W_PEND_WCRR (1<<1) 58#define W_PEND_WCLR (1<<0) 59 60#define WSPR 0x48 /* watchdog start/stop register */ 61#define WD_ENABLE_WORD1 0x0000BBBB 62#define WD_ENABLE_WORD2 0x00004444 63#define WD_DISABLE_WORD1 0x0000AAAA 64#define WD_DISABLE_WORD2 0x00005555 65 66 67/* compute number of ticks corresponding to timeout seconds */ 68#define WATCHDOG_COUNT(timeout) (~((timeout) * TCLK / (1<<PTV) -1)) 69 70 71#endif /* _OMAP_WDTREG_H */ 72