1/* $NetBSD: omap2430_intr.h,v 1.2 2008/04/27 18:58:45 matt Exp $ */ 2 3/* 4 * Define the SDP2430 specific information and then include the generic OMAP 5 * interrupt header. 6 */ 7 8/* 9 * Copyright (c) 2007 Microsoft 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Microsoft 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37#ifndef _ARM_OMAP_SDP2430_INTR_H_ 38#define _ARM_OMAP_SDP2430_INTR_H_ 39 40#define ARM_IRQ_HANDLER _C_LABEL(omap_irq_handler) 41 42#ifndef _LOCORE 43 44#define OMAP_INTC_DEVICE "omap2430intc" 45 46#include <arm/cpu.h> 47#include <arm/armreg.h> 48#include <arm/cpufunc.h> 49 50uint32_t omap_microtimer_read(void); 51uint32_t omap_microtimer_interval(uint32_t start, uint32_t end); 52 53#define EMUINT_IRQ 0 /* MPU emulation (1) */ 54#define COMMRX_IRQ 1 /* MPU emulation (1) */ 55#define COMMTX_IRQ 2 /* MPU emulation (1) */ 56#define BENCH_IRQ 3 /* MPU emulation (1) */ 57#define XTI_IRQ 4 /* (2430) XTI module (2) (3) */ 58#define XTI_WKUP_IRQ 5 /* (2430) XTI module (3) */ 59#define SSM_ABORT_IRQ 6 /* (2430) MPU subsystem secure state-machine abort */ 60#define SYS_nIRQ0 7 /* External interrupt (active low) */ 61#define D2D_FW_STACKED 8 /* (2430) Occurs when modem does a security violation and has been automatically put DEVICE_SECURITY [0] under reset. */ 62#define M_IRQ_9 9 /* Reserved */ 63#define L3_IRQ 10 /* (2420) L2 interconnect (transaction error) */ 64#define SMX_APE_IA_ARM1136 10 /* (2430) Error flag for reporting application and unknown errors from SMX-APE (4) rd_wrSError_o */ 65#define PRCM_MPU_IRQ 11 /* PRCM */ 66#define SDMA_IRQ0 12 /* System DMA interrupt request 0 (5) */ 67#define SDMA_IRQ1 13 /* System DMA interrupt request 1 (5) */ 68#define SDMA_IRQ2 14 /* System DMA interrupt request 2 */ 69#define SDMA_IRQ3 15 /* System DMA interrupt request 3 */ 70#define McBSP2_COMMON_IRQ 16 /* (2430) McBSP2 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ 71#define McBSP3_COMMON_IRQ 17 /* (2430) McBSP3 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ 72#define McBSP4_COMMON_IRQ 18 /* (2430) McBSP4 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ 73#define McBSP5_COMMON_IRQ 19 /* (2430) McBSP5 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */ 74#define GPMC_IRQ 20 /* General-purpose memory controller module */ 75#define GFX_IRQ 21 /* (2430) 2D/3D graphics module */ 76#define M_IRQ_22 22 /* Reserved */ 77#define EAC_IRQ 23 /* Audio Controller (2420) */ 78#define CAM_IRQ0 24 /* Camera interface interrupt request 0 */ 79#define DSS_IRQ 25 /* Display subsystem module (5) */ 80#define MAIL_U0_MPU_IRQ 26 /* Mailbox user 0 interrupt request */ 81#define DSP_UMA_IRQ 27 /* (2420) DSP UMA core s/w interrupt */ 82#define DSP_MMU_IRQ 28 /* (2420) DSP MMU interrupt */ 83#define IVA2_MMU_IRQ 28 /* (2430) IVA2 MMU interrupt */ 84#define GPIO1_MPU_IRQ 29 /* GPIO module 1 (5) (3) */ 85#define GPIO2_MPU_IRQ 30 /* GPIO module 2 (5) (3) */ 86#define GPIO3_MPU_IRQ 31 /* GPIO module 3 (5) (3) */ 87#define GPIO4_MPU_IRQ 32 /* GPIO module 4 (5) (3) */ 88#define GPIO5_MPU_IRQ 33 /* (2430) GPIO module 5 */ 89#define MAIL_U2_MPU_IRQ 34 /* (2420) Mailbox user 2 */ 90#define WDT3_IRQ 35 /* (2420) Watchdog timer module 3 overflow */ 91#define WDT4_IRQ 36 /* (2420) Watchdog timer module 4 overflow */ 92#define IVA2WDT_IRQ 36 /* (2430) IVA2 watchdog timer interrupt */ 93#define GPT1_IRQ 37 /* General-purpose timer module 1 */ 94#define GPT2_IRQ 38 /* General-purpose timer module 2 */ 95#define GPT3_IRQ 39 /* General-purpose timer module 3 */ 96#define GPT4_IRQ 40 /* General-purpose timer module 4 */ 97#define GPT5_IRQ 41 /* General-purpose timer module 5 (5) */ 98#define GPT6_IRQ 42 /* General-purpose timer module 6 (5) (3) */ 99#define GPT7_IRQ 43 /* General-purpose timer module 7 (5) (3) */ 100#define GPT8_IRQ 44 /* General-purpose timer module 8 (5) (3) */ 101#define GPT9_IRQ 45 /* General-purpose timer module 9 (3) */ 102#define GPT10_IRQ 46 /* General-purpose timer module 10 */ 103#define GPT11_IRQ 47 /* General-purpose timer module 11 (PWM) */ 104#define GPT12_IRQ 48 /* General-purpose timer module 12 (PWM) */ 105#define M_IRQ_49 49 /* Reserved */ 106#define PKA_IRQ 50 /* (2430) PKA crypto-accelerator */ 107#define SHA1MD5_IRQ 51 /* (2430) SHA-1/MD5 crypto-accelerator */ 108#define RNG_IRQ 52 /* (2430) RNG module */ 109#define MG_IRQ 53 /* (2430) MG function (5) */ 110#define MCBSP4_IRQ_TX 54 /* (2430) McBSP module 4 transmit (5) */ 111#define MCBSP4_IRQ_RX 55 /* (2430) McBSP module 4 receive (5) */ 112#define I2C1_IRQ 56 /* I2C module 1 */ 113#define I2C2_IRQ 57 /* I2C module 2 */ 114#define HDQ_IRQ 58 /* HDQ/1-wire */ 115#define McBSP1_IRQ_TX 59 /* McBSP module 1 transmit (5) */ 116#define McBSP1_IRQ_RX 60 /* McBSP module 1 receive (5) */ 117#define MCBSP1_IRQ_OVR 61 /* (2430) McBSP module 1 overflow interrupt (5) */ 118#define McBSP2_IRQ_TX 62 /* McBSP module 2 transmit (5) */ 119#define McBSP2_IRQ_RX 63 /* McBSP module 2 receive (5) */ 120#define McBSP1_COMMON_IRQ 64 /* (2430) McBSP1 common IRQ. This IRQ regroups all the interrupt sources of the McBSPLP. Not backward compatible with previous McBSP. */ 121#define SPI1_IRQ 65 /* McSPI module 1 */ 122#define SPI2_IRQ 66 /* McSPI module 2 */ 123#define SSI_P1_MPU_IRQ0 67 /* (2430) Dual SSI port 1 interrupt request 0 (5) */ 124#define SSI_P1_MPU_IRQ1 68 /* (2430) Dual SSI port 1 interrupt request 1 (5) */ 125#define SSI_P2_MPU_IRQ0 69 /* (2430) Dual SSI port 2 interrupt request 0 (5) */ 126#define SSI_P2_MPU_IRQ1 70 /* (2430) Dual SSI port 2 interrupt request 1 (5) */ 127#define SSI_GDD_MPU_IRQ 71 /* (2430) Dual SSI GDD (5) */ 128#define UART1_IRQ 72 /* UART module 1 (3) */ 129#define UART2_IRQ 73 /* UART module 2 (3) */ 130#define UART3_IRQ 74 /* UART module 3 (also infrared) (5) (3) */ 131#define USB_IRQ_GEN 75 /* USB device general interrupt (3) */ 132#define USB_IRQ_NISO 76 /* USB device non-ISO (3) */ 133#define USB_IRQ_ISO 77 /* USB device ISO (3) */ 134#define USB_IRQ_HGEN 78 /* USB host general interrupt (3) */ 135#define USB_IRQ_HSOF 79 /* USB host start-of-frame (3) */ 136#define USB_IRQ_OTG 80 /* USB OTG */ 137#define MCBSP5_IRQ_TX 81 /* (2430) McBSP module 5 transmit (5) */ 138#define MCBSP5_IRQ_RX 82 /* (2430) McBSP module 5 receive (5) */ 139#define MMC1_IRQ 83 /* (2430) MMC/SD module 1 (3) */ 140#define MS_IRQ 84 /* (2430) MS-PRO module */ 141#define FAC_IRQ 85 /* (2430) FAC module */ 142#define MMC2_IRQ 86 /* (2430) MMC/SD module 2 */ 143#define ARM11_ICR_IRQ 87 /* (2430) ARM11 ICR interrupt */ 144#define D2DFRINT 88 /* (2430) From 3G coprocessor hardware when used in chassis mode */ 145#define MCBSP3_IRQ_TX 89 /* (2430) McBSP module 3 transmit (5) */ 146#define MCBSP3_IRQ_RX 90 /* (2430) McBSP module 3 receive (5) */ 147#define SPI3_IRQ 91 /* (2430) Module McSPI 3 */ 148#define HS_USB_MC_NINT 92 /* (2430) Module HS USB OTG controller (3) */ 149#define HS_USB_DMA_NINT 93 /* (2430) Module HS USB OTG DMA controller interrupt (3) */ 150#define Carkit_IRQ 94 /* (2430) Carkit interrupt when the external HS USB transceiver is used in carkit mode (2) */ 151#define M_IRQ_95 95 /* Reserved */ 152 153int _splraise(int); 154int _spllower(int); 155void splx(int); 156 157#define omap_splx splx 158#define omap_splrasise _splrasise 159#define omap_spllower _spllower 160 161void omap_irq_handler(void *); 162void *omap_intr_establish(int, int, const char *, int (*)(void *), void *); 163void omap_intr_disestablish(void *); 164int omapintc_match(struct device *, struct cfdata *, void *); 165void omapintc_attach(struct device *, struct device *, void *); 166 167#endif /* ! _LOCORE */ 168 169#endif /* _ARM_OMAP_SDP2430_INTR_H_ */ 170